Changeset 455 for branches/v5/modules/vci_mem_cache/caba/source/include

Timestamp:

Jul 19, 2013, 10:16:17 AM (11 years ago)

Author:

cfuguet

Message:

Merged

/trunk/modules/vci_mem_cache:449 with
/branches/v5/modules/vci_mem_cache:446.

This merge introduces into the branch the last modifications concerning
the VCI memory cache configuration interface

Location:

branches/v5/modules/vci_mem_cache

Files:

• . (modified) (1 prop)
• caba/source/include/mem_cache_directory.h (modified) (6 diffs)
• caba/source/include/vci_mem_cache.h (modified) (4 diffs)

branches/v5/modules/vci_mem_cache/caba/source/include/mem_cache_directory.h

@@ -12 +12 @@
 // to behave in an unpredicted way.
 // TODO Either remove the mechanism from the mem cache or update its behaviour.
+
 #define L1_MULTI_CACHE 0
 
@@ -247 +248 @@
     // The function returns a copy of a (valid or invalid) entry  
     /////////////////////////////////////////////////////////////////////
-    DirectoryEntry read(const addr_t &address,size_t &way)
+    DirectoryEntry read(const addr_t &address, size_t &way)
     {
 
@@ -277 +278 @@
     // way arguments. 
     /////////////////////////////////////////////////////////////////////
-    void inval( const size_t &set, const size_t &way )
+    void inval( const size_t &way, const size_t &set )
     {
         m_dir_tab[set][way].init();
@@ -289 +290 @@
     // The function returns a copy of a (valid or invalid) entry  
     /////////////////////////////////////////////////////////////////////
-    DirectoryEntry read_neutral(const addr_t &address)
+    DirectoryEntry read_neutral( const addr_t &address, 
+                                 size_t*      ret_way,
+                                 size_t*      ret_set )
     {
 
 #define L2 soclib::common::uint32_log2
-      const size_t set = (size_t)(address >> (L2(m_words) + 2)) & (m_sets - 1);
-      const tag_t  tag = (tag_t)(address >> (L2(m_sets) + L2(m_words) + 2));
+        size_t set = (size_t)(address >> (L2(m_words) + 2)) & (m_sets - 1);
+        tag_t  tag = (tag_t)(address >> (L2(m_sets) + L2(m_words) + 2));
 #undef L2
 
-      bool hit       = false;
-      for ( size_t i=0 ; i<m_ways ; i++ ) {
-        bool equal = ( m_dir_tab[set][i].tag == tag );
-        bool valid = m_dir_tab[set][i].valid;
-        hit = equal && valid;
-        if ( hit ) {                    
-          return DirectoryEntry(m_dir_tab[set][i]);
+        for ( size_t way = 0 ; way < m_ways ; way++ ) 
+        {
+            bool equal = ( m_dir_tab[set][way].tag == tag );
+            bool valid = m_dir_tab[set][way].valid;
+            if ( equal and valid )
+            {
+                *ret_set = set;
+                *ret_way = way; 
+                return DirectoryEntry(m_dir_tab[set][way]);
+            }
         } 
-      }
-      return DirectoryEntry();
+        return DirectoryEntry();
     } // end read_neutral()
 
@@ -406 +411 @@
     void init()
     {
-      for ( size_t set=0 ; set<m_sets ; set++ ) {
-        for ( size_t way=0 ; way<m_ways ; way++ ) {
+      for ( size_t set=0 ; set<m_sets ; set++ ) 
+      {
+        for ( size_t way=0 ; way<m_ways ; way++ ) 
+        {
           m_dir_tab[set][way].init();
           m_lru_tab[set][way].init();
@@ -688 +695 @@
         assert((set < m_sets ) && "Cache data error: Trying to read a wrong set" );
         assert((way < m_ways ) && "Cache data error: Trying to read a wrong way" );
-      
+
         for (uint32_t word=0; word<m_words; word++)
           cache_line[word].write(m_cache_data[way][set][word]);

branches/v5/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h

@@ -69 +69 @@
     {
       typedef typename vci_param_int::fast_addr_t  addr_t;
-
       typedef typename sc_dt::sc_uint<64>          wide_data_t;
-
-      typedef uint32_t data_t;
-      typedef uint32_t tag_t;
-      typedef uint32_t be_t;
-      typedef uint32_t copy_t;
+      typedef uint32_t                             data_t;
+      typedef uint32_t                             tag_t;
+      typedef uint32_t                             be_t;
+      typedef uint32_t                             copy_t;
 
       /* States of the TGT_CMD fsm */
@@ -396 +394 @@
 
       // debug variables (for each FSM)
-      bool         m_debug;
-      bool         m_debug_previous_hit;
-      size_t       m_debug_previous_count;
+      bool                 m_debug;
+      bool                 m_debug_previous_valid;
+      size_t               m_debug_previous_count;
+      bool                 m_debug_previous_dirty;
+      sc_signal<data_t>*   m_debug_previous_data;
+      sc_signal<data_t>*   m_debug_data;
 
       bool         m_monitor_ok;
@@ -482 +483 @@
       void print_stats();
       void print_trace();
-      void copies_monitor(addr_t addr);
+      void cache_monitor(addr_t addr);
       void start_monitor(addr_t addr, addr_t length);
       void stop_monitor();
@@ -490 +491 @@
       void transition();
       void genMoore();
-      void check_monitor( const char *buf, addr_t addr, data_t data, bool read);
+      void check_monitor(addr_t addr, data_t data, bool read);
 
       // Component attributes