Changeset 455 for branches/v5/modules/vci_mem_cache/caba/source/src
- Timestamp:
- Jul 19, 2013, 10:16:17 AM (11 years ago)
- Location:
- branches/v5/modules/vci_mem_cache
- Files:
-
- 2 edited
-
. (modified) (1 prop)
-
caba/source/src/vci_mem_cache.cpp (modified) (32 diffs)
Legend:
- Unmodified
- Added
- Removed
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branches/v5/modules/vci_mem_cache
- Property svn:mergeinfo changed
/trunk/modules/vci_mem_cache merged: 449
- Property svn:mergeinfo changed
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branches/v5/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp
r445 r455 527 527 r_cas_rdata = new sc_signal<data_t>[2]; 528 528 529 // Allocation for debug 530 m_debug_previous_data = new sc_signal<data_t>[nwords]; 531 m_debug_data = new sc_signal<data_t>[nwords]; 529 532 530 533 SC_METHOD(transition); … … 554 557 555 558 //////////////////////////////////////////////// 556 tmpl(void) ::check_monitor( const char *buf, 557 addr_t addr, 559 tmpl(void) ::check_monitor( addr_t addr, 558 560 data_t data, 559 561 bool read ) … … 563 565 (addr < m_monitor_base + m_monitor_length)) 564 566 { 565 if ( read ) std::cout << " Monitor MEMC Read "; 566 else std::cout << " Monitor MEMC Write "; 567 std::cout << buf 568 << " / Address = " << std::hex << addr 567 if ( read ) std::cout << " Monitor MEMC Read "; 568 else std::cout << " Monitor MEMC Write"; 569 std::cout << " / Address = " << std::hex << addr 569 570 << " / Data = " << data 570 571 << " at cycle " << std::dec << m_cpt_cycles << std::endl; … … 573 574 574 575 ///////////////////////////////////////////////////// 575 tmpl(void) ::c opies_monitor(addr_t addr)576 tmpl(void) ::cache_monitor(addr_t addr) 576 577 ///////////////////////////////////////////////////// 577 578 { 578 DirectoryEntry entry = m_cache_directory.read_neutral(addr); 579 580 if((entry.count != m_debug_previous_count) or 581 (entry.valid != m_debug_previous_hit)) 582 { 583 std::cout << "Monitor MEMC " << name() 584 << " at cycle " << std::dec << m_cpt_cycles 585 << " for address " << std::hex << addr 586 << " / HIT = " << entry.valid 587 << " / COUNT = " << std::dec << entry.count << std::endl; 588 } 589 m_debug_previous_count = entry.count; 590 m_debug_previous_hit = entry.valid; 579 size_t way = 0; 580 size_t set = 0; 581 DirectoryEntry entry = m_cache_directory.read_neutral(addr, &way, &set ); 582 583 bool data_change = false; 584 585 if ( entry.valid ) 586 { 587 m_cache_data.read_line( way, set, m_debug_data ); 588 589 for ( size_t i = 0 ; i<m_words ; i++ ) 590 { 591 if ( m_debug_previous_valid and 592 (m_debug_data[i].read() != m_debug_previous_data[i].read()) ) 593 data_change = true; 594 m_debug_previous_data[i] = m_debug_data[i].read(); 595 } 596 } 597 598 if ( (entry.valid != m_debug_previous_valid) or 599 (entry.valid and (entry.count != m_debug_previous_count)) or 600 (entry.valid and (entry.dirty != m_debug_previous_dirty)) or data_change ) 601 { 602 std::cout << "Monitor MEMC " << name() 603 << " at cycle " << std::dec << m_cpt_cycles 604 << " for address " << std::hex << addr 605 << " / HIT = " << std::dec << entry.valid 606 << " / WAY = " << way 607 << " / COUNT = " << entry.count 608 << " / DIRTY = " << entry.dirty 609 << " / DATA_CHANGE = " << entry.count 610 << std::endl; 611 } 612 m_debug_previous_count = entry.count; 613 m_debug_previous_valid = entry.valid; 614 m_debug_previous_dirty = entry.dirty; 591 615 } 592 616 … … 694 718 695 719 m_debug = false; 696 m_debug_previous_hit = false; 720 m_debug_previous_valid = false; 721 m_debug_previous_dirty = false; 697 722 m_debug_previous_count = 0; 698 723 … … 1440 1465 // 1441 1466 // From the software point of view, a configuration request is a sequence 1442 // of 6 atomic accesses :1467 // of 6 atomic accesses in an uncached segment: 1443 1468 // - Read MEMC_LOCK : Get the lock 1444 1469 // - Write MEMC_ADDR_LO : Set the buffer address LSB … … 1595 1620 nb_copies, 1596 1621 index); 1622 1597 1623 if ( wok ) // IVT success => inval DIR slot 1598 1624 { … … 1837 1863 case READ_IDLE: // waiting a read request 1838 1864 { 1839 if(m_cmd_read_addr_fifo.rok())1840 {1865 if(m_cmd_read_addr_fifo.rok()) 1866 { 1841 1867 1842 1868 #if DEBUG_MEMC_READ 1843 if(m_debug)1844 std::cout << " <MEMC " << name() << " READ_IDLE> Read request"1845 << " : address = " << std::hex << m_cmd_read_addr_fifo.read()1846 << " / srcid = " << m_cmd_read_srcid_fifo.read()1847 << " / trdid = " << m_cmd_read_trdid_fifo.read()1848 << " / pktid = " << m_cmd_read_pktid_fifo.read()1849 << " / nwords = " << std::dec << m_cmd_read_length_fifo.read() << std::endl;1850 #endif 1851 r_read_fsm = READ_DIR_REQ;1852 }1869 if(m_debug) 1870 std::cout << " <MEMC " << name() << " READ_IDLE> Read request" 1871 << " : address = " << std::hex << m_cmd_read_addr_fifo.read() 1872 << " / srcid = " << m_cmd_read_srcid_fifo.read() 1873 << " / trdid = " << m_cmd_read_trdid_fifo.read() 1874 << " / pktid = " << m_cmd_read_pktid_fifo.read() 1875 << " / nwords = " << std::dec << m_cmd_read_length_fifo.read() << std::endl; 1876 #endif 1877 r_read_fsm = READ_DIR_REQ; 1878 } 1853 1879 break; 1854 1880 } … … 1877 1903 DirectoryEntry entry = 1878 1904 m_cache_directory.read(m_cmd_read_addr_fifo.read(), way); 1879 if((m_cmd_read_pktid_fifo.read() & 0x7) == TYPE_LL) // access the global table ONLY when we have an LL cmd 1905 // access the global table ONLY when we have an LL cmd 1906 if((m_cmd_read_pktid_fifo.read() & 0x7) == TYPE_LL) 1880 1907 { 1881 1908 r_read_ll_key = m_llsc_table.ll(m_cmd_read_addr_fifo.read()); … … 1939 1966 1940 1967 ////////////////// 1941 case READ_DIR_HIT: 1942 { 1943 // read data in cache & update the directory 1944 // we enter this state in 3 cases: 1945 // - the read request is uncachable 1946 // - the cache line is in counter mode 1947 // - the cache line is valid but not replcated 1948 1968 case READ_DIR_HIT: // read data in cache & update the directory 1969 // we enter this state in 3 cases: 1970 // - the read request is uncachable 1971 // - the cache line is in counter mode 1972 // - the cache line is valid but not replicated 1973 1974 { 1949 1975 if(r_alloc_dir_fsm.read() == ALLOC_DIR_READ) 1950 1976 { … … 1965 1991 m_cache_data.read_line(way, set, r_read_data); 1966 1992 1993 if(m_monitor_ok) check_monitor( m_cmd_read_addr_fifo.read(), r_read_data[0], true); 1994 1967 1995 // update the cache directory 1968 1996 DirectoryEntry entry; … … 1973 2001 entry.lock = r_read_lock.read(); 1974 2002 entry.ptr = r_read_ptr.read(); 2003 1975 2004 if(cached_read) // Cached read => we must update the copies 1976 2005 { … … 1994 2023 } 1995 2024 } 1996 else // Uncached read2025 else // Uncached read 1997 2026 { 1998 2027 entry.owner.srcid = r_read_copy.read(); … … 2005 2034 2006 2035 #if DEBUG_MEMC_READ 2007 if(m_debug) 2008 std::cout << " <MEMC " << name() << " READ_DIR_HIT> Update directory entry:" 2009 << " addr = " << std::hex << m_cmd_read_addr_fifo.read() 2010 << " / set = " << std::dec << set 2011 << " / way = " << way 2012 << " / owner_id = " << std::hex << entry.owner.srcid 2013 << " / owner_ins = " << std::dec << entry.owner.inst 2014 << " / count = " << entry.count 2015 << " / is_cnt = " << entry.is_cnt << std::endl; 2016 #endif 2017 2018 if(m_monitor_ok) 2019 { 2020 char buf[80]; 2021 snprintf(buf, 80, "READ_DIR_HIT srcid %d, ins %d", 2022 (int)m_cmd_read_srcid_fifo.read(), 2023 (int)((m_cmd_read_pktid_fifo.read()&0x2)!=0)); 2024 check_monitor(buf, m_cmd_read_addr_fifo.read(), r_read_data[0], true); 2025 } 2026 2036 if(m_debug) 2037 std::cout << " <MEMC " << name() << " READ_DIR_HIT> Update directory entry:" 2038 << " addr = " << std::hex << m_cmd_read_addr_fifo.read() 2039 << " / set = " << std::dec << set 2040 << " / way = " << way 2041 << " / owner_id = " << std::hex << entry.owner.srcid 2042 << " / owner_ins = " << std::dec << entry.owner.inst 2043 << " / count = " << entry.count 2044 << " / is_cnt = " << entry.is_cnt << std::endl; 2045 #endif 2027 2046 2028 2047 m_cache_directory.write(set, way, entry); … … 2031 2050 break; 2032 2051 } 2033 2034 2052 /////////////////// 2035 2053 case READ_HEAP_REQ: // Get the lock to the HEAP directory … … 2062 2080 2063 2081 m_cache_data.read_line(way, set, r_read_data); 2082 2083 if(m_monitor_ok) check_monitor( m_cmd_read_addr_fifo.read(), r_read_data[0], true); 2064 2084 2065 2085 // update the cache directory … … 2429 2449 2430 2450 #if DEBUG_MEMC_WRITE 2431 if(m_debug) 2432 { 2433 std::cout << " <MEMC " << name() << " WRITE_IDLE> Write request " 2434 << " srcid = " << std::dec << m_cmd_write_srcid_fifo.read() 2435 << " / address = " << std::hex << m_cmd_write_addr_fifo.read() 2436 << " / data = " << m_cmd_write_data_fifo.read() << std::endl; 2437 } 2451 if(m_debug) 2452 std::cout << " <MEMC " << name() << " WRITE_IDLE> Write request " 2453 << " srcid = " << std::hex << m_cmd_write_srcid_fifo.read() 2454 << " / address = " << std::hex << m_cmd_write_addr_fifo.read() 2455 << " / data = " << m_cmd_write_data_fifo.read() << std::endl; 2438 2456 #endif 2439 2457 } … … 2448 2466 2449 2467 #if DEBUG_MEMC_WRITE 2450 if(m_debug) 2451 { 2452 std::cout << " <MEMC " << name() 2453 << " WRITE_NEXT> Write another word in local buffer" 2454 << std::endl; 2455 } 2468 if(m_debug) 2469 std::cout << " <MEMC " << name() 2470 << " WRITE_NEXT> Write another word in local buffer" 2471 << std::endl; 2456 2472 #endif 2457 2473 m_cpt_write_cells++; … … 2532 2548 2533 2549 #if DEBUG_MEMC_WRITE 2534 if(m_debug) 2535 { 2536 std::cout 2537 << " <MEMC " << name() << " WRITE_DIR_REQ> Requesting DIR lock " 2538 << std::endl; 2539 } 2550 if(m_debug) 2551 std::cout << " <MEMC " << name() << " WRITE_DIR_REQ> Requesting DIR lock " 2552 << std::endl; 2540 2553 #endif 2541 2554 … … 2544 2557 2545 2558 //////////////////// 2546 case WRITE_DIR_LOCK: 2547 // access directory to check hit/miss 2559 case WRITE_DIR_LOCK: // access directory to check hit/miss 2548 2560 { 2549 2561 if(r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE) … … 2582 2594 2583 2595 #if DEBUG_MEMC_WRITE 2584 2585 2586 2587 2588 << "hit = " << std::dec << entry.valid2589 << "count = " << entry.count2590 << " is_cnt = " << entry.is_cnt << std::endl;2591 2592 std::cout << " <MEMC " << name() << " WRITE_DIR_LOCK> global_llsc_tableSC access" << std::endl;2593 2594 std::cout << " <MEMC " << name() << " WRITE_DIR_LOCK> global_llsc_tableSW access" << std::endl;2595 2596 if(m_debug) 2597 { 2598 std::cout << " <MEMC " << name() << " WRITE_DIR_LOCK> Check the directory: " 2599 << " address = " << std::hex << r_write_address.read() 2600 << " / hit = " << std::dec << entry.valid 2601 << " / count = " << entry.count 2602 << " / is_cnt = " << entry.is_cnt ; 2603 if((r_write_pktid.read() & 0x7) == TYPE_SC) 2604 std::cout << " / SC access" << std::endl; 2605 else 2606 std::cout << " / SW access" << std::endl; 2607 } 2596 2608 #endif 2597 2609 } … … 2604 2616 exit(0); 2605 2617 } 2606 2607 break; 2608 } 2609 2618 break; 2619 } 2610 2620 //////////////////// 2611 2621 case WRITE_DIR_READ: // read the cache and complete the buffer when be!=0xF … … 2632 2642 2633 2643 #if DEBUG_MEMC_WRITE 2634 if(m_debug) 2635 { 2636 std::cout << " <MEMC " << name() << " WRITE_DIR_READ> Read the cache to complete local buffer" << std::endl; 2637 } 2644 if(m_debug) 2645 std::cout << " <MEMC " << name() << " WRITE_DIR_READ>" 2646 << " Read the cache to complete local buffer" << std::endl; 2638 2647 #endif 2639 2648 break; … … 2648 2657 entry.valid = true; 2649 2658 entry.dirty = true; 2650 entry.tag = r_write_tag.read();2659 entry.tag = r_write_tag.read(); 2651 2660 entry.is_cnt = r_write_is_cnt.read(); 2652 2661 entry.lock = r_write_lock.read(); … … 2675 2684 // (tests for sc requests) 2676 2685 bool no_update = ( (r_write_count.read() == 0) or 2677 (owner and (r_write_count.read() ==1) and (r_write_pktid.read() != TYPE_SC))); 2686 (owner and (r_write_count.read() ==1) and 2687 (r_write_pktid.read() != TYPE_SC))); 2678 2688 2679 2689 // write data in the cache if no coherence transaction … … 2687 2697 { 2688 2698 addr_t address = (r_write_address.read() & ~(addr_t) 0x3F) | word<<2; 2689 char buf[80]; 2690 snprintf(buf, 80, "WRITE_DIR_HIT srcid %d", 2691 (int)r_write_srcid.read()); 2692 check_monitor(buf, address, r_write_data[word].read(), false); 2699 check_monitor( address, r_write_data[word].read(), false); 2693 2700 } 2694 2701 } … … 2739 2746 break; 2740 2747 } 2741 2742 2748 //////////////////// 2743 2749 case WRITE_UPT_LOCK: // Try to register the update request in UPT … … 2778 2784 { 2779 2785 addr_t address = (r_write_address.read() & ~(addr_t) 0x3F) | word<<2; 2780 char buf[80]; 2781 snprintf(buf, 80, "WRITE_UPT_LOCK srcid %d", (int)srcid); 2782 check_monitor(buf, address, r_write_data[word].read(), false); 2786 check_monitor( address, r_write_data[word].read(), false); 2783 2787 } 2784 2788 } … … 3880 3884 { 3881 3885 addr_t address = r_xram_rsp_trt_buf.nline<<6 | word<<2; 3882 check_monitor( "XRAM_RSP_DIR_UPDT",address, r_xram_rsp_trt_buf.wdata[word], false);3886 check_monitor( address, r_xram_rsp_trt_buf.wdata[word], false); 3883 3887 } 3884 3888 } … … 5270 5274 { 5271 5275 addr_t address = m_cmd_cas_addr_fifo.read(); 5272 char buf[80]; 5273 snprintf(buf, 80, "CAS_DIR_HIT_WRITE srcid %d", 5274 (int)m_cmd_cas_srcid_fifo.read()); 5275 check_monitor(buf, address, r_cas_wdata.read(), false); 5276 check_monitor( address, r_cas_wdata.read(), false); 5276 5277 5277 5278 if(r_cas_cpt.read() == 4) 5278 check_monitor( buf,address+4, m_cmd_cas_wdata_fifo.read(), false);5279 check_monitor( address+4, m_cmd_cas_wdata_fifo.read(), false); 5279 5280 } 5280 5281 … … 5335 5336 { 5336 5337 addr_t address = m_cmd_cas_addr_fifo.read(); 5337 char buf[80]; 5338 snprintf(buf, 80, "CAS_DIR_HIT_WRITE srcid %d", 5339 (int)m_cmd_cas_srcid_fifo.read()); 5340 check_monitor(buf, address, r_cas_wdata.read(), false); 5338 check_monitor( address, r_cas_wdata.read(), false); 5341 5339 5342 5340 if(r_cas_cpt.read() ==4) 5343 check_monitor( buf,address+4, m_cmd_cas_wdata_fifo.read(), false);5341 check_monitor( address+4, m_cmd_cas_wdata_fifo.read(), false); 5344 5342 } 5345 5343 } … … 5572 5570 { 5573 5571 addr_t address = m_cmd_cas_addr_fifo.read(); 5574 char buf[80]; 5575 snprintf(buf, 80, "CAS_DIR_HIT_WRITE srcid %d", 5576 (int)m_cmd_cas_srcid_fifo.read()); 5577 check_monitor(buf, address, r_cas_wdata.read(), false); 5572 check_monitor( address, r_cas_wdata.read(), false); 5573 5578 5574 if(r_cas_cpt.read() ==4) 5579 check_monitor( buf,address+4, m_cmd_cas_wdata_fifo.read(), false);5575 check_monitor( address+4, m_cmd_cas_wdata_fifo.read(), false); 5580 5576 } 5581 5577 r_cas_upt_index = index;
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