Index: branches/v5/modules/vci_mem_cache/caba/source/include/mem_cache_directory.h =================================================================== --- branches/v5/modules/vci_mem_cache/caba/source/include/mem_cache_directory.h (revision 454) +++ branches/v5/modules/vci_mem_cache/caba/source/include/mem_cache_directory.h (revision 455) @@ -12,4 +12,5 @@ // to behave in an unpredicted way. // TODO Either remove the mechanism from the mem cache or update its behaviour. + #define L1_MULTI_CACHE 0 @@ -247,5 +248,5 @@ // The function returns a copy of a (valid or invalid) entry ///////////////////////////////////////////////////////////////////// - DirectoryEntry read(const addr_t &address,size_t &way) + DirectoryEntry read(const addr_t &address, size_t &way) { @@ -277,5 +278,5 @@ // way arguments. ///////////////////////////////////////////////////////////////////// - void inval( const size_t &set, const size_t &way ) + void inval( const size_t &way, const size_t &set ) { m_dir_tab[set][way].init(); @@ -289,22 +290,26 @@ // The function returns a copy of a (valid or invalid) entry ///////////////////////////////////////////////////////////////////// - DirectoryEntry read_neutral(const addr_t &address) + DirectoryEntry read_neutral( const addr_t &address, + size_t* ret_way, + size_t* ret_set ) { #define L2 soclib::common::uint32_log2 - const size_t set = (size_t)(address >> (L2(m_words) + 2)) & (m_sets - 1); - const tag_t tag = (tag_t)(address >> (L2(m_sets) + L2(m_words) + 2)); + size_t set = (size_t)(address >> (L2(m_words) + 2)) & (m_sets - 1); + tag_t tag = (tag_t)(address >> (L2(m_sets) + L2(m_words) + 2)); #undef L2 - bool hit = false; - for ( size_t i=0 ; i wide_data_t; - - typedef uint32_t data_t; - typedef uint32_t tag_t; - typedef uint32_t be_t; - typedef uint32_t copy_t; + typedef uint32_t data_t; + typedef uint32_t tag_t; + typedef uint32_t be_t; + typedef uint32_t copy_t; /* States of the TGT_CMD fsm */ @@ -396,7 +394,10 @@ // debug variables (for each FSM) - bool m_debug; - bool m_debug_previous_hit; - size_t m_debug_previous_count; + bool m_debug; + bool m_debug_previous_valid; + size_t m_debug_previous_count; + bool m_debug_previous_dirty; + sc_signal* m_debug_previous_data; + sc_signal* m_debug_data; bool m_monitor_ok; @@ -482,5 +483,5 @@ void print_stats(); void print_trace(); - void copies_monitor(addr_t addr); + void cache_monitor(addr_t addr); void start_monitor(addr_t addr, addr_t length); void stop_monitor(); @@ -490,5 +491,5 @@ void transition(); void genMoore(); - void check_monitor( const char *buf, addr_t addr, data_t data, bool read); + void check_monitor(addr_t addr, data_t data, bool read); // Component attributes Index: branches/v5/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp =================================================================== --- branches/v5/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp (revision 454) +++ branches/v5/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp (revision 455) @@ -527,4 +527,7 @@ r_cas_rdata = new sc_signal[2]; + // Allocation for debug + m_debug_previous_data = new sc_signal[nwords]; + m_debug_data = new sc_signal[nwords]; SC_METHOD(transition); @@ -554,6 +557,5 @@ //////////////////////////////////////////////// -tmpl(void) ::check_monitor( const char *buf, - addr_t addr, +tmpl(void) ::check_monitor( addr_t addr, data_t data, bool read ) @@ -563,8 +565,7 @@ (addr < m_monitor_base + m_monitor_length)) { - if ( read ) std::cout << " Monitor MEMC Read "; - else std::cout << " Monitor MEMC Write "; - std::cout << buf - << " / Address = " << std::hex << addr + if ( read ) std::cout << " Monitor MEMC Read "; + else std::cout << " Monitor MEMC Write"; + std::cout << " / Address = " << std::hex << addr << " / Data = " << data << " at cycle " << std::dec << m_cpt_cycles << std::endl; @@ -573,20 +574,43 @@ ///////////////////////////////////////////////////// -tmpl(void) ::copies_monitor(addr_t addr) +tmpl(void) ::cache_monitor(addr_t addr) ///////////////////////////////////////////////////// { - DirectoryEntry entry = m_cache_directory.read_neutral(addr); - - if((entry.count != m_debug_previous_count) or - (entry.valid != m_debug_previous_hit)) - { - std::cout << "Monitor MEMC " << name() - << " at cycle " << std::dec << m_cpt_cycles - << " for address " << std::hex << addr - << " / HIT = " << entry.valid - << " / COUNT = " << std::dec << entry.count << std::endl; - } - m_debug_previous_count = entry.count; - m_debug_previous_hit = entry.valid; + size_t way = 0; + size_t set = 0; + DirectoryEntry entry = m_cache_directory.read_neutral(addr, &way, &set ); + + bool data_change = false; + + if ( entry.valid ) + { + m_cache_data.read_line( way, set, m_debug_data ); + + for ( size_t i = 0 ; i Read request" - << " : address = " << std::hex << m_cmd_read_addr_fifo.read() - << " / srcid = " << m_cmd_read_srcid_fifo.read() - << " / trdid = " << m_cmd_read_trdid_fifo.read() - << " / pktid = " << m_cmd_read_pktid_fifo.read() - << " / nwords = " << std::dec << m_cmd_read_length_fifo.read() << std::endl; -#endif - r_read_fsm = READ_DIR_REQ; - } + if(m_debug) + std::cout << " Read request" + << " : address = " << std::hex << m_cmd_read_addr_fifo.read() + << " / srcid = " << m_cmd_read_srcid_fifo.read() + << " / trdid = " << m_cmd_read_trdid_fifo.read() + << " / pktid = " << m_cmd_read_pktid_fifo.read() + << " / nwords = " << std::dec << m_cmd_read_length_fifo.read() << std::endl; +#endif + r_read_fsm = READ_DIR_REQ; + } break; } @@ -1877,5 +1903,6 @@ DirectoryEntry entry = m_cache_directory.read(m_cmd_read_addr_fifo.read(), way); - if((m_cmd_read_pktid_fifo.read() & 0x7) == TYPE_LL) // access the global table ONLY when we have an LL cmd + // access the global table ONLY when we have an LL cmd + if((m_cmd_read_pktid_fifo.read() & 0x7) == TYPE_LL) { r_read_ll_key = m_llsc_table.ll(m_cmd_read_addr_fifo.read()); @@ -1939,12 +1966,11 @@ ////////////////// - case READ_DIR_HIT: - { - // read data in cache & update the directory - // we enter this state in 3 cases: - // - the read request is uncachable - // - the cache line is in counter mode - // - the cache line is valid but not replcated - + case READ_DIR_HIT: // read data in cache & update the directory + // we enter this state in 3 cases: + // - the read request is uncachable + // - the cache line is in counter mode + // - the cache line is valid but not replicated + + { if(r_alloc_dir_fsm.read() == ALLOC_DIR_READ) { @@ -1965,4 +1991,6 @@ m_cache_data.read_line(way, set, r_read_data); + if(m_monitor_ok) check_monitor( m_cmd_read_addr_fifo.read(), r_read_data[0], true); + // update the cache directory DirectoryEntry entry; @@ -1973,4 +2001,5 @@ entry.lock = r_read_lock.read(); entry.ptr = r_read_ptr.read(); + if(cached_read) // Cached read => we must update the copies { @@ -1994,5 +2023,5 @@ } } - else // Uncached read + else // Uncached read { entry.owner.srcid = r_read_copy.read(); @@ -2005,24 +2034,14 @@ #if DEBUG_MEMC_READ -if(m_debug) -std::cout << " Update directory entry:" - << " addr = " << std::hex << m_cmd_read_addr_fifo.read() - << " / set = " << std::dec << set - << " / way = " << way - << " / owner_id = " << std::hex << entry.owner.srcid - << " / owner_ins = " << std::dec << entry.owner.inst - << " / count = " << entry.count - << " / is_cnt = " << entry.is_cnt << std::endl; -#endif - - if(m_monitor_ok) - { - char buf[80]; - snprintf(buf, 80, "READ_DIR_HIT srcid %d, ins %d", - (int)m_cmd_read_srcid_fifo.read(), - (int)((m_cmd_read_pktid_fifo.read()&0x2)!=0)); - check_monitor(buf, m_cmd_read_addr_fifo.read(), r_read_data[0], true); - } - + if(m_debug) + std::cout << " Update directory entry:" + << " addr = " << std::hex << m_cmd_read_addr_fifo.read() + << " / set = " << std::dec << set + << " / way = " << way + << " / owner_id = " << std::hex << entry.owner.srcid + << " / owner_ins = " << std::dec << entry.owner.inst + << " / count = " << entry.count + << " / is_cnt = " << entry.is_cnt << std::endl; +#endif m_cache_directory.write(set, way, entry); @@ -2031,5 +2050,4 @@ break; } - /////////////////// case READ_HEAP_REQ: // Get the lock to the HEAP directory @@ -2062,4 +2080,6 @@ m_cache_data.read_line(way, set, r_read_data); + + if(m_monitor_ok) check_monitor( m_cmd_read_addr_fifo.read(), r_read_data[0], true); // update the cache directory @@ -2429,11 +2449,9 @@ #if DEBUG_MEMC_WRITE - if(m_debug) - { - std::cout << " Write request " - << " srcid = " << std::dec << m_cmd_write_srcid_fifo.read() - << " / address = " << std::hex << m_cmd_write_addr_fifo.read() - << " / data = " << m_cmd_write_data_fifo.read() << std::endl; - } +if(m_debug) +std::cout << " Write request " + << " srcid = " << std::hex << m_cmd_write_srcid_fifo.read() + << " / address = " << std::hex << m_cmd_write_addr_fifo.read() + << " / data = " << m_cmd_write_data_fifo.read() << std::endl; #endif } @@ -2448,10 +2466,8 @@ #if DEBUG_MEMC_WRITE - if(m_debug) - { - std::cout << " Write another word in local buffer" - << std::endl; - } +if(m_debug) +std::cout << " Write another word in local buffer" + << std::endl; #endif m_cpt_write_cells++; @@ -2532,10 +2548,7 @@ #if DEBUG_MEMC_WRITE - if(m_debug) - { - std::cout - << " Requesting DIR lock " - << std::endl; - } +if(m_debug) +std::cout << " Requesting DIR lock " + << std::endl; #endif @@ -2544,6 +2557,5 @@ //////////////////// - case WRITE_DIR_LOCK: - // access directory to check hit/miss + case WRITE_DIR_LOCK: // access directory to check hit/miss { if(r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE) @@ -2582,16 +2594,16 @@ #if DEBUG_MEMC_WRITE - if(m_debug) - { - std::cout << " Check the directory: " - << " address = " << std::hex << r_write_address.read() - << " hit = " << std::dec << entry.valid - << " count = " << entry.count - << " is_cnt = " << entry.is_cnt << std::endl; - if((r_write_pktid.read() & 0x7) == TYPE_SC) - std::cout << " global_llsc_table SC access" << std::endl; - else - std::cout << " global_llsc_table SW access" << std::endl; - } +if(m_debug) +{ +std::cout << " Check the directory: " + << " address = " << std::hex << r_write_address.read() + << " / hit = " << std::dec << entry.valid + << " / count = " << entry.count + << " / is_cnt = " << entry.is_cnt ; +if((r_write_pktid.read() & 0x7) == TYPE_SC) +std::cout << " / SC access" << std::endl; +else +std::cout << " / SW access" << std::endl; +} #endif } @@ -2604,8 +2616,6 @@ exit(0); } - - break; - } - + break; + } //////////////////// case WRITE_DIR_READ: // read the cache and complete the buffer when be!=0xF @@ -2632,8 +2642,7 @@ #if DEBUG_MEMC_WRITE - if(m_debug) - { - std::cout << " Read the cache to complete local buffer" << std::endl; - } +if(m_debug) +std::cout << " " + << " Read the cache to complete local buffer" << std::endl; #endif break; @@ -2648,5 +2657,5 @@ entry.valid = true; entry.dirty = true; - entry.tag = r_write_tag.read(); + entry.tag = r_write_tag.read(); entry.is_cnt = r_write_is_cnt.read(); entry.lock = r_write_lock.read(); @@ -2675,5 +2684,6 @@ // (tests for sc requests) bool no_update = ( (r_write_count.read() == 0) or - (owner and (r_write_count.read() ==1) and (r_write_pktid.read() != TYPE_SC))); + (owner and (r_write_count.read() ==1) and + (r_write_pktid.read() != TYPE_SC))); // write data in the cache if no coherence transaction @@ -2687,8 +2697,5 @@ { addr_t address = (r_write_address.read() & ~(addr_t) 0x3F) | word<<2; - char buf[80]; - snprintf(buf, 80, "WRITE_DIR_HIT srcid %d", - (int)r_write_srcid.read()); - check_monitor(buf, address, r_write_data[word].read(), false); + check_monitor( address, r_write_data[word].read(), false); } } @@ -2739,5 +2746,4 @@ break; } - //////////////////// case WRITE_UPT_LOCK: // Try to register the update request in UPT @@ -2778,7 +2784,5 @@ { addr_t address = (r_write_address.read() & ~(addr_t) 0x3F) | word<<2; - char buf[80]; - snprintf(buf, 80, "WRITE_UPT_LOCK srcid %d", (int)srcid); - check_monitor(buf, address, r_write_data[word].read(), false); + check_monitor( address, r_write_data[word].read(), false); } } @@ -3880,5 +3884,5 @@ { addr_t address = r_xram_rsp_trt_buf.nline<<6 | word<<2; - check_monitor("XRAM_RSP_DIR_UPDT", address, r_xram_rsp_trt_buf.wdata[word], false); + check_monitor( address, r_xram_rsp_trt_buf.wdata[word], false); } } @@ -5270,11 +5274,8 @@ { addr_t address = m_cmd_cas_addr_fifo.read(); - char buf[80]; - snprintf(buf, 80, "CAS_DIR_HIT_WRITE srcid %d", - (int)m_cmd_cas_srcid_fifo.read()); - check_monitor(buf, address, r_cas_wdata.read(), false); + check_monitor( address, r_cas_wdata.read(), false); if(r_cas_cpt.read() == 4) - check_monitor(buf, address+4, m_cmd_cas_wdata_fifo.read(), false); + check_monitor( address+4, m_cmd_cas_wdata_fifo.read(), false); } @@ -5335,11 +5336,8 @@ { addr_t address = m_cmd_cas_addr_fifo.read(); - char buf[80]; - snprintf(buf, 80, "CAS_DIR_HIT_WRITE srcid %d", - (int)m_cmd_cas_srcid_fifo.read()); - check_monitor(buf, address, r_cas_wdata.read(), false); + check_monitor( address, r_cas_wdata.read(), false); if(r_cas_cpt.read() ==4) - check_monitor(buf, address+4, m_cmd_cas_wdata_fifo.read(), false); + check_monitor( address+4, m_cmd_cas_wdata_fifo.read(), false); } } @@ -5572,10 +5570,8 @@ { addr_t address = m_cmd_cas_addr_fifo.read(); - char buf[80]; - snprintf(buf, 80, "CAS_DIR_HIT_WRITE srcid %d", - (int)m_cmd_cas_srcid_fifo.read()); - check_monitor(buf, address, r_cas_wdata.read(), false); + check_monitor( address, r_cas_wdata.read(), false); + if(r_cas_cpt.read() ==4) - check_monitor(buf, address+4, m_cmd_cas_wdata_fifo.read(), false); + check_monitor( address+4, m_cmd_cas_wdata_fifo.read(), false); } r_cas_upt_index = index;