Index: branches/ODCCP/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h
===================================================================
--- trunk/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h	(revision 432)
+++ branches/ODCCP/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h	(revision 460)
@@ -117,4 +117,5 @@
         DCACHE_XTN_IT_INVAL,
         DCACHE_XTN_DC_FLUSH,
+        DCACHE_XTN_DC_FLUSH_DATA,
         DCACHE_XTN_DC_FLUSH_GO,
         DCACHE_XTN_DC_INVAL_VA,
@@ -122,4 +123,5 @@
         DCACHE_XTN_DC_INVAL_END,
         DCACHE_XTN_DC_INVAL_GO,
+        DCACHE_XTN_DC_INVAL_DATA,
         DCACHE_XTN_DT_INVAL,
         //handling dirty bit update
@@ -129,4 +131,5 @@
         DCACHE_MISS_SELECT,
         DCACHE_MISS_CLEAN,
+        DCACHE_MISS_DATA,
         DCACHE_MISS_WAIT,
         DCACHE_MISS_DATA_UPDT,
@@ -138,4 +141,5 @@
         // handling coherence requests
         DCACHE_CC_CHECK,
+        DCACHE_CC_INVAL_DATA,
         DCACHE_CC_INVAL,
         DCACHE_CC_UPDT,
@@ -188,4 +192,5 @@
         CC_SEND_CLEANUP_1,
         CC_SEND_CLEANUP_2,
+        CC_SEND_CLEANUP_DATA_UPDT,
         CC_SEND_MULTI_ACK,
     };
@@ -194,5 +199,5 @@
     enum transaction_type_e
     {
-        // b3 unused
+        // b3 ODCCP/RWT : COHERENT/NO COHERENT
         // b2 READ / NOT READ
         // if READ
@@ -202,12 +207,13 @@
         //  b1 accÃšs table llsc type SW / other
         //  b2 WRITE/CAS/LL/SC
-        TYPE_READ_DATA_UNC          = 0x0,
-        TYPE_READ_DATA_MISS         = 0x1,
-        TYPE_READ_INS_UNC           = 0x2,
-        TYPE_READ_INS_MISS          = 0x3,
-        TYPE_WRITE                  = 0x4,
-        TYPE_CAS                    = 0x5,
-        TYPE_LL                     = 0x6,
-        TYPE_SC                     = 0x7
+        TYPE_READ_DATA_UNC                      = 0x0,
+        TYPE_READ_DATA_MISS                     = 0x1,
+        TYPE_READ_INS_UNC                       = 0x2,
+        TYPE_READ_INS_MISS                      = 0x3,
+        TYPE_WRITE                              = 0x4,
+        TYPE_CAS                                = 0x5,
+        TYPE_LL                                 = 0x6,
+        TYPE_SC                                 = 0x7,
+        TYPE_READ_DATA_MISS_NO_COHERENT         = 0x9
     };
 
@@ -283,4 +289,14 @@
         TYPE_INS_MISS     = 0x3,
     };
+
+    //////////////////MODIFIED////////////////
+    enum content_line_cache_status_e
+    {
+        LINE_CACHE_DATA_NOT_DIRTY,
+        LINE_CACHE_DATA_DIRTY,
+        LINE_CACHE_IN_TLB,
+        LINE_CACHE_CONTAINS_PTD,
+    };
+    //////////////////////////////////////////
 
 public:
@@ -384,5 +400,5 @@
     // communication between ICACHE FSM and CC_SEND FSM
     sc_signal<bool>         r_icache_cc_send_req;           // ICACHE cc_send request
-    sc_signal<cc_send_t>    r_icache_cc_send_type;          // ICACHE cc_send request type
+    sc_signal<int>          r_icache_cc_send_type;          // ICACHE cc_send request type
     sc_signal<paddr_t>      r_icache_cc_send_nline;         // ICACHE cc_send nline
     sc_signal<size_t>       r_icache_cc_send_way;           // ICACHE cc_send way
@@ -472,12 +488,44 @@
     // communication between DCACHE FSM and CC_SEND FSM
     sc_signal<bool>         r_dcache_cc_send_req;           // DCACHE cc_send request
-    sc_signal<cc_send_t>    r_dcache_cc_send_type;          // DCACHE cc_send request type
+    sc_signal<int>          r_dcache_cc_send_type;          // DCACHE cc_send request type
     sc_signal<paddr_t>      r_dcache_cc_send_nline;         // DCACHE cc_send nline
     sc_signal<size_t>       r_dcache_cc_send_way;           // DCACHE cc_send way
     sc_signal<size_t>       r_dcache_cc_send_updt_tab_idx;  // DCACHE cc_send update table index
-
+    
+    // special registers for ODCCP/RWT
+    sc_signal<bool>         r_dcache_cc_cleanup_updt_data;          // Register for cleanup with data (wb updt)
+    sc_signal<bool>         r_dcache_cleanup_ncc;                   // Register for cleanup no coherent 
+    sc_signal<bool>         r_dcache_miss_victim_no_coherence;      // Register for victim in no coherence mode
+    sc_signal<bool>         r_dcache_line_no_coherence;             // Register for line current in no coherence mode
+    sc_signal<bool>         r_dcache_miss_no_coherent;              // Register for miss on NCC line 
+    sc_signal<bool>         r_vci_rsp_read_data_miss_no_coherent;   // Read miss rsp on line NCC
+    sc_signal<uint32_t>     r_cc_send_cpt_word;
+
+    sc_signal<uint32_t>     r_dcache_miss_data_cpt;                 // Cpt a word to read for sending Cleanup with data (MISS STATE)
+    sc_signal<paddr_t>      r_dcache_miss_data_addr;                // Addr for read word for sending Cleanup with data (MISS STATE)
+    
+    sc_signal<int>          r_dcache_xtn_state;
+    sc_signal<paddr_t>      r_dcache_xtn_data_addr;                 // Cpt a word to read for sending Cleanup with data (XTN DC INVAL STATE)
+    sc_signal<uint32_t>     r_dcache_xtn_data_cpt;                  // Addr for read word for sending Cleanup with data (XTN DC INVAL STATE)
+    
+    sc_signal<paddr_t>      r_dcache_cc_inval_addr;                 // Cpt a word to read for sending Cleanup with data (CC INVAL STATE)
+    sc_signal<uint32_t>     r_dcache_cc_inval_data_cpt;             // Addr for read word for sending Cleanup with data (CC INVAL STATE)
+    sc_signal<int>          r_dcache_cc_state;
+    
+    sc_signal<paddr_t>      r_dcache_xtn_flush_addr_data;           // Cpt a word to read for sending Cleanup with data (XTN DC FLUSH STATE)
+    sc_signal<uint32_t>     r_dcache_xtn_flush_data_cpt;            // Addr for read word for sending Cleanup with data (XTN DC FLUSH STATE)
+    
+    /*STATS DIRTY*/
+    bool *dirty_stats;
+    uint32_t m_cpt_words_dirty;     // total number of words dirty when we send a cleanup with data
+    
+    //////////////
+    GenericFifo<uint32_t>   r_cc_send_data_fifo;                    // Fifo for save data value (before sending cleanup with data)
     // dcache directory extension
-    bool                    *r_dcache_in_tlb;               // copy exist in dtlb or itlb
-    bool                    *r_dcache_contains_ptd;         // cache line contains a PTD
+    ///////////////////////////MODIFIED///////////////////////////////////////////////////
+    //bool                    *r_dcache_in_tlb;           // copy exist in dtlb or itlb
+    //bool                    *r_dcache_contains_ptd;     // cache line contains a PTD
+    int                     *r_dcache_content_state;    // content state of one cache line
+    //////////////////////////////////////////////////////////////////////////////////////
 
     // Physical address extension for data access
@@ -502,4 +550,5 @@
     GenericFifo<uint32_t>   r_vci_rsp_fifo_icache;	        // response FIFO to ICACHE FSM
     GenericFifo<uint32_t>   r_vci_rsp_fifo_dcache;	        // response FIFO to DCACHE FSM
+    
 
     ///////////////////////////////////
@@ -523,5 +572,5 @@
     // communication between CC_RECEIVE FSM and ICACHE FSM
     sc_signal<bool>         r_cc_receive_icache_req;        // cc_receive to icache request
-    sc_signal<cc_receive_t> r_cc_receive_icache_type;       // cc_receive type of request
+    sc_signal<int>          r_cc_receive_icache_type;       // cc_receive type of request
     sc_signal<size_t>       r_cc_receive_icache_way;        // cc_receive to icache way
     sc_signal<size_t>       r_cc_receive_icache_set;        // cc_receive to icache set
@@ -531,5 +580,5 @@
     // communication between CC_RECEIVE FSM and DCACHE FSM
     sc_signal<bool>         r_cc_receive_dcache_req;        // cc_receive to dcache request
-    sc_signal<cc_receive_t> r_cc_receive_dcache_type;       // cc_receive type of request
+    sc_signal<int>          r_cc_receive_dcache_type;       // cc_receive type of request
     sc_signal<size_t>       r_cc_receive_dcache_way;        // cc_receive to dcache way
     sc_signal<size_t>       r_cc_receive_dcache_set;        // cc_receive to dcache set
@@ -576,4 +625,9 @@
     uint32_t m_cpt_data_read;               // total number of read data
     uint32_t m_cpt_data_write;              // total number of write data
+    uint32_t m_cpt_data_write_back;         // total number of write NCC
+    uint32_t m_cpt_data_cleanup;            // total number of flits cleanup data 
+    uint32_t m_cpt_data_cleanup_dirty;      // total number of cleanup data dirty
+    uint32_t m_cpt_data_sc;
+    uint32_t m_cpt_data_write_miss_ncc;     // total number of write NCC miss
     uint32_t m_cpt_data_miss;               // number of read miss
     uint32_t m_cpt_ins_miss;                // number of instruction miss
