Changeset 460 for branches/ODCCP/modules/vci_mem_cache/caba/source/include
- Timestamp:
- Jul 19, 2013, 2:34:03 PM (11 years ago)
- Location:
- branches/ODCCP/modules/vci_mem_cache
- Files:
-
- 3 edited
- 1 copied
-
. (copied) (copied from trunk/modules/vci_mem_cache)
-
caba/source/include/mem_cache_directory.h (modified) (5 diffs)
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caba/source/include/vci_mem_cache.h (modified) (9 diffs)
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caba/source/include/xram_transaction.h (modified) (1 diff)
Legend:
- Unmodified
- Added
- Removed
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branches/ODCCP/modules/vci_mem_cache/caba/source/include/mem_cache_directory.h
r449 r460 99 99 bool dirty; // entry dirty 100 100 bool lock; // entry locked 101 bool coherent; // entry coherent or not 101 102 tag_t tag; // tag of the entry 102 103 size_t count; // number of copies … … 110 111 dirty = false; 111 112 lock = false; 113 coherent = true; 112 114 tag = 0; 113 115 count = 0; … … 126 128 dirty = source.dirty; 127 129 lock = source.lock; 130 coherent = source.coherent; 128 131 tag = source.tag; 129 132 count = source.count; … … 141 144 dirty = false; 142 145 lock = false; 146 coherent = true; 143 147 count = 0; 144 148 } … … 153 157 dirty = source.dirty; 154 158 lock = source.lock; 159 coherent = source.coherent; 155 160 tag = source.tag; 156 161 count = source.count; -
branches/ODCCP/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h
r449 r460 254 254 IXR_CMD_CAS_IDLE, 255 255 IXR_CMD_XRAM_IDLE, 256 IXR_CMD_CLEANUP_IDLE, 256 257 IXR_CMD_READ, 257 258 IXR_CMD_WRITE, 258 259 IXR_CMD_CAS, 259 IXR_CMD_XRAM 260 IXR_CMD_XRAM, 261 IXR_CMD_CLEANUP_DATA 260 262 }; 261 263 … … 291 293 CLEANUP_IDLE, 292 294 CLEANUP_GET_NLINE, 295 CLEANUP_GET_DATA, 293 296 CLEANUP_DIR_REQ, 294 297 CLEANUP_DIR_LOCK, … … 304 307 CLEANUP_WRITE_RSP, 305 308 CLEANUP_CONFIG_ACK, 309 CLEANUP_IXR_REQ, 310 CLEANUP_WAIT, 306 311 CLEANUP_SEND_CLACK 307 312 }; … … 326 331 ALLOC_TRT_CAS, 327 332 ALLOC_TRT_XRAM_RSP, 328 ALLOC_TRT_IXR_RSP 333 ALLOC_TRT_IXR_RSP, 334 ALLOC_TRT_CLEANUP 329 335 }; 330 336 … … 425 431 uint32_t m_cpt_inval_brdcast; // Number of BROADCAST INVAL 426 432 uint32_t m_cpt_cleanup; // Number of CLEANUP transactions 433 uint32_t m_cpt_cleanup_data; // Number of CLEANUP WITH DATA transactions 427 434 uint32_t m_cpt_ll; // Number of LL transactions 428 435 uint32_t m_cpt_sc; // Number of SC transactions 429 436 uint32_t m_cpt_cas; // Number of CAS transactions 437 438 uint32_t m_cpt_read_fsm_dir_lock; // wait DIR LOCK 439 uint32_t m_cpt_read_fsm_n_dir_lock; // NB DIR LOCK 440 uint32_t m_cpt_write_fsm_dir_lock; // wait DIR LOCK 441 uint32_t m_cpt_write_fsm_n_dir_lock; // NB DIR LOCK 442 uint32_t m_cpt_xram_rsp_fsm_dir_lock; // wait DIR LOCK 443 uint32_t m_cpt_xram_rsp_fsm_n_dir_lock; // NB DIR LOCK 444 uint32_t m_cpt_cas_fsm_dir_lock; // wait DIR LOCK 445 uint32_t m_cpt_cas_fsm_n_dir_lock; // NB DIR LOCK 446 uint32_t m_cpt_cleanup_fsm_dir_lock; // wait DIR LOCK 447 uint32_t m_cpt_cleanup_fsm_n_dir_lock; // NB DIR LOCK 448 449 uint32_t m_cpt_dir_unused; // NB cycles DIR LOCK unused 450 uint32_t m_cpt_read_fsm_dir_used; // NB cycles DIR LOCK used 451 uint32_t m_cpt_write_fsm_dir_used; // NB cycles DIR LOCK used 452 uint32_t m_cpt_cas_fsm_dir_used; // NB cycles DIR LOCK used 453 uint32_t m_cpt_xram_rsp_fsm_dir_used; // NB cycles DIR LOCK used 454 uint32_t m_cpt_cleanup_fsm_dir_used; // NB cycles DIR LOCK used 455 456 uint32_t m_cpt_read_fsm_trt_lock; // wait TRT LOCK 457 uint32_t m_cpt_write_fsm_trt_lock; // wait TRT LOCK 458 uint32_t m_cpt_cas_fsm_trt_lock; // wait TRT LOCK 459 uint32_t m_cpt_xram_rsp_fsm_trt_lock; // wait TRT LOCK 460 uint32_t m_cpt_ixr_fsm_trt_lock; // wait TRT LOCK 461 462 uint32_t m_cpt_read_fsm_n_trt_lock; // NB TRT LOCK 463 uint32_t m_cpt_write_fsm_n_trt_lock; // NB TRT LOCK 464 uint32_t m_cpt_cas_fsm_n_trt_lock; // NB TRT LOCK 465 uint32_t m_cpt_xram_rsp_fsm_n_trt_lock; // NB TRT LOCK 466 uint32_t m_cpt_ixr_fsm_n_trt_lock; // NB TRT LOCK 467 468 uint32_t m_cpt_read_fsm_trt_used; // NB cycles TRT LOCK used 469 uint32_t m_cpt_write_fsm_trt_used; // NB cycles TRT LOCK used 470 uint32_t m_cpt_cas_fsm_trt_used; // NB cycles TRT LOCK used 471 uint32_t m_cpt_xram_rsp_fsm_trt_used; // NB cycles TRT LOCK used 472 uint32_t m_cpt_ixr_fsm_trt_used; // NB cycles TRT LOCK used 473 474 uint32_t m_cpt_trt_unused; // NB cycles TRT LOCK unused 475 476 uint32_t m_cpt_write_fsm_upt_lock; // wait UPT LOCK 477 uint32_t m_cpt_xram_rsp_fsm_upt_lock; // wait UPT LOCK 478 uint32_t m_cpt_multi_ack_fsm_upt_lock; // wait UPT LOCK 479 uint32_t m_cpt_cleanup_fsm_upt_lock; // wait UPT LOCK 480 uint32_t m_cpt_cas_fsm_upt_lock; // wait UPT LOCK 481 482 uint32_t m_cpt_write_fsm_n_upt_lock; // NB UPT LOCK 483 uint32_t m_cpt_xram_rsp_fsm_n_upt_lock; // NB UPT LOCK 484 uint32_t m_cpt_multi_ack_fsm_n_upt_lock; // NB UPT LOCK 485 uint32_t m_cpt_cleanup_fsm_n_upt_lock; // NB UPT LOCK 486 uint32_t m_cpt_cas_fsm_n_upt_lock; // NB UPT LOCK 487 488 uint32_t m_cpt_write_fsm_upt_used; // NB cycles UPT LOCK used 489 uint32_t m_cpt_xram_rsp_fsm_upt_used; // NB cycles UPT LOCK used 490 uint32_t m_cpt_multi_ack_fsm_upt_used; // NB cycles UPT LOCK used 491 uint32_t m_cpt_cleanup_fsm_upt_used; // NB cycles UPT LOCK used 492 uint32_t m_cpt_cas_fsm_upt_used; // NB cycles UPT LOCK used 493 494 uint32_t m_cpt_upt_unused; // NB cycles UPT LOCK unused 495 496 uint32_t m_cpt_read_fsm_heap_lock; // wait HEAP LOCK 497 uint32_t m_cpt_write_fsm_heap_lock; // wait HEAP LOCK 498 uint32_t m_cpt_cas_fsm_heap_lock; // wait HEAP LOCK 499 uint32_t m_cpt_cleanup_fsm_heap_lock; // wait HEAP LOCK 500 uint32_t m_cpt_xram_rsp_fsm_heap_lock; // wait HEAP LOCK 501 502 uint32_t m_cpt_read_fsm_n_heap_lock; // NB HEAP LOCK 503 uint32_t m_cpt_write_fsm_n_heap_lock; // NB HEAP LOCK 504 uint32_t m_cpt_cas_fsm_n_heap_lock; // NB HEAP LOCK 505 uint32_t m_cpt_cleanup_fsm_n_heap_lock; // NB HEAP LOCK 506 uint32_t m_cpt_xram_rsp_fsm_n_heap_lock; // NB HEAP LOCK 507 508 uint32_t m_cpt_read_fsm_heap_used; // NB cycles HEAP LOCK used 509 uint32_t m_cpt_write_fsm_heap_used; // NB cycles HEAP LOCK used 510 uint32_t m_cpt_cas_fsm_heap_used; // NB cycles HEAP LOCK used 511 uint32_t m_cpt_cleanup_fsm_heap_used; // NB cycles HEAP LOCK used 512 uint32_t m_cpt_xram_rsp_fsm_heap_used; // NB cycles HEAP LOCK used 513 514 uint32_t m_cpt_heap_unused; // NB cycles HEAP LOCK unused 430 515 431 516 uint32_t m_cpt_cleanup_cost; // Number of (flits * distance) for CLEANUPs … … 473 558 ~VciMemCache(); 474 559 560 void clear_stats(); 475 561 void print_stats(); 476 562 void print_trace(); … … 852 938 // Buffer between IXR_RSP fsm and XRAM_RSP fsm (response from the XRAM) 853 939 sc_signal<bool> * r_ixr_rsp_to_xram_rsp_rok; // A xram response is ready 940 sc_signal<bool> * r_ixr_rsp_to_xram_rsp_no_coherent; // A xram response is ready and no coherent (ODCCP) 854 941 855 942 //////////////////////////////////////////////////// … … 861 948 TransactionTabEntry r_xram_rsp_trt_buf; // TRT entry local buffer 862 949 sc_signal<bool> r_xram_rsp_victim_inval; // victim line invalidate 950 sc_signal<bool> r_xram_rsp_victim_coherent; // victim line coherent 863 951 sc_signal<bool> r_xram_rsp_victim_is_cnt; // victim line inst bit 864 952 sc_signal<bool> r_xram_rsp_victim_dirty; // victim line dirty bit … … 958 1046 sc_signal<int> r_alloc_heap_fsm; 959 1047 sc_signal<unsigned> r_alloc_heap_reset_cpt; 1048 1049 1050 //////////////////////////////////////////////////// 1051 // REGISTERS FOR ODCCP 1052 //////////////////////////////////////////////////// 1053 1054 sc_signal<uint32_t> r_cleanup_data_index; 1055 sc_signal<uint32_t> r_cleanup_trdid; 1056 sc_signal<uint32_t> r_cleanup_pktid; 1057 sc_signal<data_t> *r_cleanup_data; // buffer for saving data from cleanup 1058 sc_signal<bool> r_cleanup_contains_data; 1059 sc_signal<bool> r_cleanup_ncc; 1060 1061 sc_signal<bool> r_xram_rsp_to_ixr_cmd_inval_ncc_pending; 1062 1063 sc_signal<bool> r_cleanup_to_ixr_cmd_req; 1064 sc_signal<data_t> *r_cleanup_to_ixr_cmd_data; 1065 sc_signal<uint32_t> r_cleanup_to_ixr_cmd_srcid; 1066 sc_signal<bool> r_cleanup_to_ixr_cmd_l1_dirty_ncc; // this cleanup was dirty in L1 1067 sc_signal<uint32_t> r_cleanup_to_ixr_cmd_trdid; 1068 sc_signal<uint32_t> r_cleanup_to_ixr_cmd_pktid; 1069 sc_signal<addr_t> r_cleanup_to_ixr_cmd_nline; 960 1070 }; // end class VciMemCache 961 1071 -
branches/ODCCP/modules/vci_mem_cache/caba/source/include/xram_transaction.h
r422 r460 293 293 return false; 294 294 } 295 296 /////////////////////////////////////////////////////////////////////// 297 // The hit_write() function looks if an XRAM write transaction exists 298 // for a given line. 299 // Arguments : 300 // - nline : the index (zy) of the requested line 301 // The function returns true if a write request has already been sent 302 /////////////////////////////////////////////////////////////////////// 303 bool hit_write(const addr_t nline, size_t *index) 304 { 305 for(size_t i=0; i<size_tab; i++){ 306 if(tab[i].valid && (nline==tab[i].nline) && !(tab[i].xram_read)) { 307 *index = i; 308 return true; 309 } 310 } 311 return false; 312 } 295 313 296 314 /////////////////////////////////////////////////////////////////////
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