Changeset 461
- Timestamp:
- Jul 19, 2013, 3:49:43 PM (11 years ago)
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
branches/v5/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp
r454 r461 1819 1819 paddr_t mask = ~((m_icache_words<<2)-1); 1820 1820 1821 // CLACK handler 1822 // We switch the directory slot to EMPTY state 1823 // and reset r_icache_miss_clack if the cleanup ack 1824 // is matching a pending miss. 1821 1825 if ( r_icache_clack_req.read() ) 1822 // We switch the directory slot to EMPTY state1823 // and reset r_icache_miss_clack if the cleanup ack1824 // is matching a pending miss1825 1826 { 1826 1827 … … 1837 1838 if ( (r_icache_miss_set.read() == r_icache_clack_set.read()) and 1838 1839 (r_icache_miss_way.read() == r_icache_clack_way.read()) ) 1839 r_icache_miss_clack = false; 1840 { 1841 r_icache_miss_clack = false; 1842 } 1840 1843 1841 1844 r_icache_clack_req = false; 1845 1846 // return to cc_save state if no pending CC request 1847 if ( not r_cc_receive_icache_req.read() ) 1848 r_icache_fsm = r_icache_fsm_save.read(); 1842 1849 1843 1850 #if DEBUG_ICACHE … … 1845 1852 { 1846 1853 std::cout << " <PROC " << name() 1847 << " ICACHE_CC_CHECK> CC_TYPE_CLACK slot returns to empty state"1848 << " set = " << r_icache_clack_set.read()1849 << " / way = " << r_icache_clack_way.read() << std::endl;1854 << " ICACHE_CC_CHECK> CC_TYPE_CLACK slot returns to empty state" 1855 << " set = " << r_icache_clack_set.read() 1856 << " / way = " << r_icache_clack_way.read() << std::endl; 1850 1857 } 1851 1858 #endif 1852 // we should handle the clack request first, 1853 // if the cc request is arrived simultaneously, 1854 // we stay here in next cycle for treating the cc request. 1855 if ( not r_cc_receive_icache_req.read() ) 1856 r_icache_fsm = r_icache_fsm_save.read(); 1857 1858 break; 1859 } 1860 else if( r_cc_receive_icache_req.read() and 1861 ((r_icache_fsm_save.read() == ICACHE_MISS_SELECT) or 1862 (r_icache_fsm_save.read() == ICACHE_MISS_WAIT) or 1863 (r_icache_fsm_save.read() == ICACHE_MISS_DIR_UPDT)) and 1864 ((r_icache_vci_paddr.read() & mask) == (paddr & mask)) ) // matching 1859 1860 break; 1861 } 1862 1863 // Match between MISS address and CC address 1864 if (r_cc_receive_icache_req.read() and 1865 ((r_icache_fsm_save.read() == ICACHE_MISS_SELECT ) or 1866 (r_icache_fsm_save.read() == ICACHE_MISS_WAIT ) or 1867 (r_icache_fsm_save.read() == ICACHE_MISS_DIR_UPDT)) and 1868 ((r_icache_vci_paddr.read() & mask) == (paddr & mask)) ) // matching 1865 1869 { 1866 1870 // signaling the matching … … 1873 1877 r_icache_fsm = ICACHE_CC_UPDT; 1874 1878 r_icache_cc_word = r_cc_receive_word_idx.read(); 1879 1875 1880 // just pop the fifo , don't write in icache 1876 1881 r_icache_cc_need_write = false; … … 1890 1895 } 1891 1896 #endif 1892 } 1893 else // no match 1894 { 1895 int state = 0; 1896 size_t way = 0; 1897 size_t set = 0; 1898 size_t word = 0; 1897 break; 1898 } 1899 1900 // CC request handler 1901 1902 int state = 0; 1903 size_t way = 0; 1904 size_t set = 0; 1905 size_t word = 0; 1899 1906 1900 1907 #ifdef INSTRUMENTATION 1901 1908 m_cpt_icache_dir_read++; 1902 1909 #endif 1903 1904 1905 1906 1907 1908 1909 1910 1911 1912 1913 1914 1915 1916 1917 1918 r_icache_fsm= ICACHE_CC_UPDT;1919 r_icache_cc_word= r_cc_receive_word_idx.read();1920 1921 1922 1923 r_icache_fsm= ICACHE_CC_INVAL;1924 1925 1926 1927 1928 1929 1930 1931 r_icache_fsm= ICACHE_CC_UPDT;1932 r_icache_cc_word= r_cc_receive_word_idx.read();1933 // just pop the fifo , don't write in icache 1934 r_icache_cc_need_write = false;1935 }1936 else // No response needed1937 {1938 r_cc_receive_icache_req = false;1939 r_icache_fsm = r_icache_fsm_save.read();1940 }1910 r_icache.read_dir(paddr, 1911 &state, 1912 &way, 1913 &set, 1914 &word); 1915 1916 r_icache_cc_way = way; 1917 r_icache_cc_set = set; 1918 1919 if ( state == CACHE_SLOT_STATE_VALID) // hit 1920 { 1921 // need to update the cache state 1922 if (r_cc_receive_icache_type.read() == CC_TYPE_UPDT) // hit update 1923 { 1924 r_icache_cc_need_write = true; 1925 r_icache_fsm = ICACHE_CC_UPDT; 1926 r_icache_cc_word = r_cc_receive_word_idx.read(); 1927 } 1928 else if ( r_cc_receive_icache_type.read() == CC_TYPE_INVAL ) // hit inval 1929 { 1930 r_icache_fsm = ICACHE_CC_INVAL; 1931 } 1932 } 1933 else // miss 1934 { 1935 // multicast acknowledgement required in case of update 1936 if(r_cc_receive_icache_type.read() == CC_TYPE_UPDT) 1937 { 1938 r_icache_fsm = ICACHE_CC_UPDT; 1939 r_icache_cc_word = r_cc_receive_word_idx.read(); 1940 1941 // just pop the fifo , don't write in icache 1942 r_icache_cc_need_write = false; 1943 } 1944 else // No response needed 1945 { 1946 r_cc_receive_icache_req = false; 1947 r_icache_fsm = r_icache_fsm_save.read(); 1941 1948 } 1942 1949 } … … 1946 1953 case ICACHE_CC_INVAL: // hit inval : switch slot to ZOMBI state 1947 1954 { 1955 // return to CC_CHECK if pending request to CC_SEND 1956 // to handle possible pending CLACK and avoid deadlock 1957 if (r_icache_cc_send_req.read()) 1958 { 1959 r_icache_fsm = ICACHE_CC_CHECK; 1960 break; 1961 } 1962 1963 #ifdef INSTRUMENTATION 1964 m_cpt_icache_dir_read++; 1965 #endif 1966 1967 // Switch slot state to ZOMBI and send CLEANUP command 1968 r_icache.write_dir( 0, 1969 r_icache_cc_way.read(), 1970 r_icache_cc_set.read(), 1971 CACHE_SLOT_STATE_ZOMBI ); 1972 1973 // coherence request completed 1974 r_icache_cc_send_req = true; 1975 r_icache_cc_send_nline = r_cc_receive_icache_nline.read(); 1976 r_icache_cc_send_way = r_icache_cc_way.read(); 1977 r_icache_cc_send_type = CC_TYPE_CLEANUP; 1978 1979 r_icache_fsm = r_icache_fsm_save.read(); 1948 1980 1949 1981 #if DEBUG_ICACHE 1950 1982 if ( m_debug_activated ) 1951 1983 { 1952 1953 << " ICACHE_CC_INVAL> slot returns to zombistate"1954 1955 1984 std::cout << " <PROC " << name() 1985 << " ICACHE_CC_INVAL> slot returns to ZOMBI state" 1986 << " set = " << r_icache_cc_set.read() 1987 << " / way = " << r_icache_cc_way.read() << std::endl; 1956 1988 } 1957 1989 #endif 1958 1990 1959 #ifdef INSTRUMENTATION1960 m_cpt_icache_dir_read++;1961 #endif1962 // send a cleanup request to cc_send_fsm1963 if(not r_icache_cc_send_req.read()) // cc_send is available1964 {1965 r_icache.write_dir( 0,1966 r_icache_cc_way.read(),1967 r_icache_cc_set.read(),1968 CACHE_SLOT_STATE_ZOMBI );1969 // coherence request completed1970 r_icache_cc_send_req = true;1971 r_icache_cc_send_nline = r_cc_receive_icache_nline.read();1972 r_icache_cc_send_way = r_icache_cc_way.read();1973 r_icache_cc_send_type = CC_TYPE_CLEANUP;1974 1975 r_icache_fsm = r_icache_fsm_save.read();1976 }1977 //else go to CC_CHECK1978 else1979 r_icache_fsm = ICACHE_CC_CHECK;1980 1991 break; 1981 1982 1992 } 1983 1993 //////////////////// 1984 1994 case ICACHE_CC_UPDT: // hit update : write one word per cycle 1985 1995 { 1996 1997 // if pending request to CC_SEND or if the CC_UPDT data is not ready to 1998 // handle possible pending CLACK and avoid deadlock 1999 if ( r_icache_cc_send_req.read() ) 2000 { 2001 r_icache_fsm = ICACHE_CC_CHECK; 2002 break; 2003 } 2004 2005 if ( not r_cc_receive_updt_fifo_be.rok() ) break; 2006 2007 2008 size_t word = r_icache_cc_word.read(); 2009 size_t way = r_icache_cc_way.read(); 2010 size_t set = r_icache_cc_set.read(); 2011 2012 if (r_icache_cc_need_write.read()) 2013 { 2014 r_icache.write( way, 2015 set, 2016 word, 2017 r_cc_receive_updt_fifo_data.read(), 2018 r_cc_receive_updt_fifo_be.read() ); 2019 2020 r_icache_cc_word = word+1; 2021 2022 #ifdef INSTRUMENTATION 2023 m_cpt_icache_data_write++; 2024 #endif 1986 2025 1987 2026 #if DEBUG_ICACHE … … 1995 2034 } 1996 2035 #endif 1997 1998 #ifdef INSTRUMENTATION 1999 m_cpt_icache_data_write++; 2000 #endif 2001 size_t word = r_icache_cc_word.read(); 2002 size_t way = r_icache_cc_way.read(); 2003 size_t set = r_icache_cc_set.read(); 2004 2005 if( (not r_icache_cc_send_req.read()) and r_cc_receive_updt_fifo_be.rok() ) // cc_send is available 2006 { 2007 if (r_icache_cc_need_write.read()) 2008 { 2009 r_icache.write( way, 2010 set, 2011 word, 2012 r_cc_receive_updt_fifo_data.read(), 2013 r_cc_receive_updt_fifo_be.read() ); 2014 2015 r_icache_cc_word = word+1; 2016 } 2017 if ( r_cc_receive_updt_fifo_eop.read() ) // last word 2018 { 2019 // no need to write in the cache anymore 2020 r_icache_cc_need_write = false; 2021 // coherence request completed 2022 r_cc_receive_icache_req = false; 2023 // request multicast acknowledgement 2024 r_icache_cc_send_req = true; 2025 r_icache_cc_send_nline = r_cc_receive_icache_nline.read(); 2026 r_icache_cc_send_updt_tab_idx = r_cc_receive_icache_updt_tab_idx.read(); 2027 r_icache_cc_send_type = CC_TYPE_MULTI_ACK; 2028 2029 r_icache_fsm = r_icache_fsm_save.read(); 2030 } 2031 //consume fifo if not eop 2032 cc_receive_updt_fifo_get = true; 2033 } 2034 else 2035 r_icache_fsm = ICACHE_CC_CHECK; 2036 } 2037 2038 if ( r_cc_receive_updt_fifo_eop.read() ) // last word 2039 { 2040 // no need to write in the cache anymore 2041 r_icache_cc_need_write = false; 2042 2043 // coherence request completed 2044 r_cc_receive_icache_req = false; 2045 2046 // request multicast acknowledgement 2047 r_icache_cc_send_req = true; 2048 r_icache_cc_send_nline = r_cc_receive_icache_nline.read(); 2049 r_icache_cc_send_updt_tab_idx = r_cc_receive_icache_updt_tab_idx.read(); 2050 r_icache_cc_send_type = CC_TYPE_MULTI_ACK; 2051 2052 r_icache_fsm = r_icache_fsm_save.read(); 2053 } 2054 //consume fifo if not eop 2055 cc_receive_updt_fifo_get = true; 2036 2056 2037 2057 break; … … 4435 4455 size_t way; 4436 4456 size_t set; 4437 size_t word; 4457 size_t word; // unused 4438 4458 int state; 4439 4459 … … 4504 4524 } 4505 4525 4506 if ( r_vci_rsp_data_error.read() ) 4526 if ( r_vci_rsp_data_error.read() ) // bus error 4507 4527 { 4508 4528 std::cout << "BUS ERROR in DCACHE_DIRTY_WAIT state" << std::endl; … … 4510 4530 exit(0); 4511 4531 } 4512 else if ( r_vci_rsp_fifo_dcache.rok() ) 4532 else if ( r_vci_rsp_fifo_dcache.rok() ) // response available 4513 4533 { 4514 4534 vci_rsp_fifo_dcache_get = true; … … 4554 4574 #endif 4555 4575 4576 // CLACK handler 4577 // We switch the directory slot to EMPTY state 4578 // and reset r_dcache_miss_clack if the cleanup ack 4579 // is matching a pending miss. 4556 4580 if ( r_dcache_clack_req.read() ) 4557 // We switch the directory slot to EMPTY state 4558 // and reset r_icache_miss_clack if the cleanup ack 4559 // is matching a pending miss. 4560 { 4561 4581 { 4562 4582 if ( m_dreq.valid ) m_cost_data_miss_frz++; 4563 4583 … … 4572 4592 if ( (r_dcache_miss_set.read() == r_dcache_clack_set.read()) and 4573 4593 (r_dcache_miss_way.read() == r_dcache_clack_way.read()) ) 4594 { 4574 4595 r_dcache_miss_clack = false; 4596 } 4575 4597 4576 4598 r_dcache_clack_req = false; 4599 4600 // return to cc_save state if no pending CC request 4601 if ( not r_cc_receive_dcache_req.read() ) 4602 r_dcache_fsm = r_dcache_fsm_cc_save.read() ; 4603 4577 4604 #if DEBUG_DCACHE 4578 4605 if ( m_debug_activated ) … … 4584 4611 } 4585 4612 #endif 4586 if ( not r_cc_receive_dcache_req.read() ) 4587 r_dcache_fsm = r_dcache_fsm_cc_save.read() ; 4588 4589 break; 4590 } 4591 else if( r_cc_receive_dcache_req.read() and 4592 ((r_dcache_fsm_cc_save == DCACHE_MISS_SELECT) or 4593 (r_dcache_fsm_cc_save == DCACHE_MISS_WAIT) or 4594 (r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT)) and 4595 ((r_dcache_vci_paddr.read() & mask) == (paddr & mask)) ) // matching 4613 break; 4614 } 4615 4616 // Match between MISS address and CC address 4617 if (r_cc_receive_dcache_req.read() and 4618 ((r_dcache_fsm_cc_save == DCACHE_MISS_SELECT ) or 4619 (r_dcache_fsm_cc_save == DCACHE_MISS_WAIT ) or 4620 (r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT)) and 4621 ((r_dcache_vci_paddr.read() & mask) == (paddr & mask))) // matching 4596 4622 { 4597 4623 // signaling matching … … 4604 4630 r_dcache_fsm = DCACHE_CC_UPDT; 4605 4631 r_dcache_cc_word = r_cc_receive_word_idx.read(); 4632 4606 4633 // just pop the fifo , don't write in icache 4607 4634 r_dcache_cc_need_write = false; … … 4623 4650 #endif 4624 4651 4625 } 4626 else // no match 4627 { 4628 int state = 0; 4629 size_t way = 0; 4630 size_t set = 0; 4631 size_t word = 0; 4652 break; 4653 } 4654 4655 // CC request handler 4656 4657 int state = 0; 4658 size_t way = 0; 4659 size_t set = 0; 4660 size_t word = 0; 4632 4661 4633 4662 #ifdef INSTRUMENTATION 4634 4663 m_cpt_dcache_dir_read++; 4635 4664 #endif 4636 r_dcache.read_dir( paddr, 4637 &state, 4638 &way, 4639 &set, 4640 &word ); // unused 4641 4642 r_dcache_cc_way = way; 4643 r_dcache_cc_set = set; 4644 4645 if ( state == CACHE_SLOT_STATE_VALID) // hit 4646 { 4647 // need to update the cache state 4648 if (r_cc_receive_dcache_type.read() == CC_TYPE_UPDT) // hit update 4649 { 4650 r_dcache_cc_need_write = true; 4651 r_dcache_fsm = DCACHE_CC_UPDT; 4652 r_dcache_cc_word = r_cc_receive_word_idx.read(); 4653 } 4654 else if ( r_cc_receive_dcache_type.read() == CC_TYPE_INVAL ) // hit inval 4655 { 4656 r_dcache_fsm = DCACHE_CC_INVAL; 4657 } 4658 } 4659 else // miss 4660 { 4661 // multicast acknowledgement required in case of update 4662 if(r_cc_receive_dcache_type.read() == CC_TYPE_UPDT) 4663 { 4664 r_dcache_fsm = DCACHE_CC_UPDT; 4665 r_dcache_cc_word = r_cc_receive_word_idx.read(); 4666 // just pop the fifo , don't write in icache 4667 r_dcache_cc_need_write = false; 4668 } 4669 else // No response needed 4670 { 4671 r_cc_receive_dcache_req = false; 4672 r_dcache_fsm = r_dcache_fsm_cc_save.read(); 4673 } 4674 } 4665 r_dcache.read_dir( paddr, 4666 &state, 4667 &way, 4668 &set, 4669 &word ); // unused 4670 4671 r_dcache_cc_way = way; 4672 r_dcache_cc_set = set; 4673 4674 if ( state == CACHE_SLOT_STATE_VALID) // hit 4675 { 4676 // need to update the cache state 4677 if (r_cc_receive_dcache_type.read() == CC_TYPE_UPDT) // hit update 4678 { 4679 r_dcache_cc_need_write = true; 4680 r_dcache_fsm = DCACHE_CC_UPDT; 4681 r_dcache_cc_word = r_cc_receive_word_idx.read(); 4682 } 4683 else if ( r_cc_receive_dcache_type.read() == CC_TYPE_INVAL ) // hit inval 4684 { 4685 r_dcache_fsm = DCACHE_CC_INVAL; 4686 } 4687 } 4688 else // miss 4689 { 4690 // multicast acknowledgement required in case of update 4691 if(r_cc_receive_dcache_type.read() == CC_TYPE_UPDT) 4692 { 4693 r_dcache_fsm = DCACHE_CC_UPDT; 4694 r_dcache_cc_word = r_cc_receive_word_idx.read(); 4695 4696 // just pop the fifo , don't write in icache 4697 r_dcache_cc_need_write = false; 4698 } 4699 else // No response needed 4700 { 4701 r_cc_receive_dcache_req = false; 4702 r_dcache_fsm = r_dcache_fsm_cc_save.read(); 4703 } 4704 } 4675 4705 4676 4706 #if DEBUG_DCACHE … … 4684 4714 } 4685 4715 #endif 4686 } 4716 4687 4717 break; 4688 4718 } 4689 4719 ///////////////////// 4690 case DCACHE_CC_INVAL: // hit inval: switch slot to EMPTY state, 4691 // after possible invalidation of copies in TLBs 4692 { 4693 size_t way = r_dcache_cc_way.read(); 4694 size_t set = r_dcache_cc_set.read(); 4695 4696 if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) // selective TLB inval 4720 case DCACHE_CC_INVAL: // hit inval: switch slot to ZOMBI state and send a 4721 // CLEANUP after possible invalidation of copies in 4722 // TLBs 4723 { 4724 size_t way = r_dcache_cc_way.read(); 4725 size_t set = r_dcache_cc_set.read(); 4726 4727 if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) // selective TLB inval 4697 4728 { 4698 4729 r_dcache_in_tlb[way*m_dcache_sets+set] = false; … … 4704 4735 } 4705 4736 4706 if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) 4737 if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) // TLB flush 4707 4738 { 4708 4739 r_itlb.reset(); … … 4718 4749 #endif 4719 4750 } 4720 4721 if ( not r_dcache_cc_send_req.read() ) // cc_send is available 4722 { 4723 r_dcache.write_dir( 0, 4724 way, 4725 set, 4726 CACHE_SLOT_STATE_ZOMBI ); 4751 4752 // return to CC_CHECK if pending request to CC_SEND 4753 // to handle possible pending CLACK and avoid deadlock 4754 if ( r_dcache_cc_send_req.read() ) 4755 { 4756 r_dcache_fsm = DCACHE_CC_CHECK; 4757 break; 4758 } 4759 4760 // Switch slot state to ZOMBI and send CLEANUP command 4761 r_dcache.write_dir( 0, 4762 way, 4763 set, 4764 CACHE_SLOT_STATE_ZOMBI ); 4765 4766 // coherence request completed 4767 r_cc_receive_dcache_req = false; 4768 r_dcache_cc_send_req = true; 4769 r_dcache_cc_send_nline = r_cc_receive_dcache_nline.read(); 4770 r_dcache_cc_send_way = r_dcache_cc_way.read(); 4771 r_dcache_cc_send_type = CC_TYPE_CLEANUP; 4772 r_dcache_fsm = r_dcache_fsm_cc_save.read(); 4727 4773 4728 4774 #if DEBUG_DCACHE … … 4730 4776 { 4731 4777 std::cout << " <PROC " << name() 4732 4733 4734 4778 << " DCACHE_CC_INVAL> Switch slot to EMPTY state:" << std::dec 4779 << " / WAY = " << way 4780 << " / SET = " << set << std::endl; 4735 4781 } 4736 4782 #endif 4737 // coherence request completed4738 r_cc_receive_dcache_req = false;4739 r_dcache_cc_send_req = true;4740 r_dcache_cc_send_nline = r_cc_receive_dcache_nline.read();4741 r_dcache_cc_send_way = r_dcache_cc_way.read();4742 r_dcache_cc_send_type = CC_TYPE_CLEANUP;4743 4744 r_dcache_fsm = r_dcache_fsm_cc_save.read();4745 }4746 //else go to DCACHE_CC_CHECK4747 else4748 r_dcache_fsm = DCACHE_CC_CHECK;4749 4750 4783 break; 4751 4784 } 4752 4785 /////////////////// 4753 case DCACHE_CC_UPDT: 4786 case DCACHE_CC_UPDT: // hit update: write one word per cycle, 4754 4787 // after possible invalidation of copies in TLBs 4755 4788 { 4756 size_t 4757 size_t 4758 size_t 4759 4760 if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) 4789 size_t word = r_dcache_cc_word.read(); 4790 size_t way = r_dcache_cc_way.read(); 4791 size_t set = r_dcache_cc_set.read(); 4792 4793 if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) // selective TLB inval 4761 4794 { 4762 4795 r_dcache_in_tlb[way*m_dcache_sets+set] = false; 4763 r_dcache_tlb_inval_line = r_cc_receive_dcache_nline.read(); 4764 r_dcache_tlb_inval_set = 0; 4765 r_dcache_fsm_scan_save = r_dcache_fsm.read(); 4766 r_dcache_fsm = DCACHE_INVAL_TLB_SCAN; 4767 break; 4768 } 4769 4770 if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) // TLB flush 4796 r_dcache_tlb_inval_line = r_cc_receive_dcache_nline.read(); 4797 r_dcache_tlb_inval_set = 0; 4798 r_dcache_fsm_scan_save = r_dcache_fsm.read(); 4799 r_dcache_fsm = DCACHE_INVAL_TLB_SCAN; 4800 4801 break; 4802 } 4803 4804 if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) // TLB flush 4771 4805 { 4772 4806 r_itlb.reset(); … … 4783 4817 } 4784 4818 4785 if ( (not r_dcache_cc_send_req.read()) and r_cc_receive_updt_fifo_be.rok()) 4786 { 4787 if (r_dcache_cc_need_write.read()) 4788 { 4789 4819 // if pending request to CC_SEND or if the CC_UPDT data is not ready to 4820 // handle possible pending CLACK and avoid deadlock 4821 if ( r_dcache_cc_send_req.read() ) 4822 { 4823 r_dcache_fsm = DCACHE_CC_CHECK; 4824 break; 4825 } 4826 4827 if ( not r_cc_receive_updt_fifo_be.rok() ) break; 4828 4829 if (r_dcache_cc_need_write.read()) 4830 { 4831 4790 4832 #ifdef INSTRUMENTATION 4791 4833 m_cpt_dcache_data_write++; 4792 4834 #endif 4793 4794 4795 4796 4797 4798 4799 4835 r_dcache.write( way, 4836 set, 4837 word, 4838 r_cc_receive_updt_fifo_data.read(), 4839 r_cc_receive_updt_fifo_be.read() ); 4840 4841 r_dcache_cc_word = word + 1; 4800 4842 4801 4843 #if DEBUG_DCACHE … … 4810 4852 } 4811 4853 #endif 4812 } 4813 4814 if ( r_cc_receive_updt_fifo_eop.read() ) // last word 4815 { 4816 // no need to write in the cache anymore 4817 r_dcache_cc_need_write = false; 4818 4819 // coherence request completed 4820 r_cc_receive_dcache_req = false; 4821 4822 // request multicast acknowledgement 4823 r_dcache_cc_send_req = true; 4824 r_dcache_cc_send_nline = r_cc_receive_dcache_nline.read(); 4825 r_dcache_cc_send_updt_tab_idx = r_cc_receive_dcache_updt_tab_idx.read(); 4826 r_dcache_cc_send_type = CC_TYPE_MULTI_ACK; 4827 4828 r_dcache_fsm = r_dcache_fsm_cc_save.read(); 4829 } 4830 4831 //consume fifo if not eop 4832 cc_receive_updt_fifo_get = true; 4833 } 4834 else 4835 r_dcache_fsm = DCACHE_CC_CHECK; 4854 } 4855 4856 if ( r_cc_receive_updt_fifo_eop.read() ) // last word 4857 { 4858 // no need to write in the cache anymore 4859 r_dcache_cc_need_write = false; 4860 4861 // coherence request completed 4862 r_cc_receive_dcache_req = false; 4863 4864 // request multicast acknowledgement 4865 r_dcache_cc_send_req = true; 4866 r_dcache_cc_send_nline = r_cc_receive_dcache_nline.read(); 4867 r_dcache_cc_send_updt_tab_idx = r_cc_receive_dcache_updt_tab_idx.read(); 4868 r_dcache_cc_send_type = CC_TYPE_MULTI_ACK; 4869 4870 r_dcache_fsm = r_dcache_fsm_cc_save.read(); 4871 } 4872 4873 //consume fifo if not eop 4874 cc_receive_updt_fifo_get = true; 4836 4875 4837 4876 break;
Note: See TracChangeset
for help on using the changeset viewer.
