Changeset 462 for branches/v5

Timestamp:

Jul 19, 2013, 4:26:26 PM (11 years ago)

Author:

cfuguet

Message:

Modification in vci_cc_vcache_wrapper:

• Optimization in DCACHE/ICACHE CC_CHECK state. We can handle a CLACK and a CC request if the latter does a MISS match. This is because the CC request doing MISS match does not need to access the directory

File:

• branches/v5/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp (modified) (5 diffs)

branches/v5/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp

@@ -1819 +1819 @@
         paddr_t  mask  = ~((m_icache_words<<2)-1);
 
+
+        // Match between MISS address and CC address
+        // note: In the same cycle we can handle a CLACK and a MISS match
+        // because the CLACK access the directory but the MISS match dont.
+        if (r_cc_receive_icache_req.read() and
+          ((r_icache_fsm_save.read() == ICACHE_MISS_SELECT  )  or
+           (r_icache_fsm_save.read() == ICACHE_MISS_WAIT    )  or
+           (r_icache_fsm_save.read() == ICACHE_MISS_DIR_UPDT)) and
+          ((r_icache_vci_paddr.read() & mask) == (paddr & mask)) ) // matching
+        {
+            // signaling the matching
+            r_icache_miss_inval     = true;
+
+            // in case of update, go to CC_UPDT
+            // JUST TO POP THE FIFO
+            if (r_cc_receive_icache_type.read() == CC_TYPE_UPDT)
+            {
+                r_icache_fsm        = ICACHE_CC_UPDT;
+                r_icache_cc_word    = r_cc_receive_word_idx.read();
+
+                // just pop the fifo , don't write in icache
+                r_icache_cc_need_write = false;
+            }
+            // the request is dealt with
+            else
+            {
+                r_cc_receive_icache_req = false;
+                r_icache_fsm          = r_icache_fsm_save.read();
+            }
+#if DEBUG_ICACHE
+if ( m_debug_activated )
+{
+    std::cout << "  <PROC " << name()
+              << " ICACHE_CC_CHECK> Coherence request matching a pending miss:"
+              << " PADDR = " << std::hex << paddr << std::endl;
+}
+#endif
+        }
+
         // CLACK handler
         // We switch the directory slot to EMPTY state
@@ -1858 +1897 @@
 #endif
 
-            break;
-        }
-
-        // Match between MISS address and CC address
-        if (r_cc_receive_icache_req.read() and
-          ((r_icache_fsm_save.read() == ICACHE_MISS_SELECT  )  or
-           (r_icache_fsm_save.read() == ICACHE_MISS_WAIT    )  or
-           (r_icache_fsm_save.read() == ICACHE_MISS_DIR_UPDT)) and
-          ((r_icache_vci_paddr.read() & mask) == (paddr & mask)) ) // matching
-        {
-            // signaling the matching
-            r_icache_miss_inval     = true;
-
-            // in case of update, go to CC_UPDT
-            // JUST TO POP THE FIFO
-            if (r_cc_receive_icache_type.read() == CC_TYPE_UPDT)
-            {
-                r_icache_fsm        = ICACHE_CC_UPDT;
-                r_icache_cc_word    = r_cc_receive_word_idx.read();
-
-                // just pop the fifo , don't write in icache
-                r_icache_cc_need_write = false;
-            }
-            // the request is dealt with
-            else
-            {
-                r_cc_receive_icache_req = false;
-                r_icache_fsm          = r_icache_fsm_save.read();
-            }
-#if DEBUG_ICACHE
-if ( m_debug_activated )
-{
-    std::cout << "  <PROC " << name()
-              << " ICACHE_CC_CHECK> Coherence request matching a pending miss:"
-              << " PADDR = " << std::hex << paddr << std::endl;
-}
-#endif
             break;
         }
@@ -4574 +4576 @@
 #endif
 
+        
+        // Match between MISS address and CC address
+        // note: In the same cycle we can handle a CLACK and a MISS match
+        // because the CLACK access the directory but the MISS match dont.
+        if (r_cc_receive_dcache_req.read() and 
+          ((r_dcache_fsm_cc_save == DCACHE_MISS_SELECT  )  or
+           (r_dcache_fsm_cc_save == DCACHE_MISS_WAIT    )  or
+           (r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT)) and
+          ((r_dcache_vci_paddr.read() & mask) == (paddr & mask))) // matching
+        {
+            // signaling matching
+            r_dcache_miss_inval = true;
+
+            // in case of update, go to CC_UPDT
+            // JUST TO POP THE FIFO
+            if (r_cc_receive_dcache_type.read() == CC_TYPE_UPDT)
+            {
+                r_dcache_fsm        = DCACHE_CC_UPDT;
+                r_dcache_cc_word    = r_cc_receive_word_idx.read();
+
+                // just pop the fifo , don't write in icache
+                r_dcache_cc_need_write = false;
+            }
+            // the request is dealt with
+            else
+            {
+                r_cc_receive_dcache_req = false;
+                r_dcache_fsm            = r_dcache_fsm_cc_save.read();
+            }
+
+#if DEBUG_DCACHE
+if ( m_debug_activated )
+{
+    std::cout << "  <PROC " << name()
+              << " DCACHE_CC_CHECK> Coherence request matching a pending miss:"
+              << " PADDR = " << std::hex << paddr << std::endl;
+}
+#endif
+        }
+
         // CLACK handler
-        // We switch the directory slot to EMPTY state
-        // and reset r_dcache_miss_clack if the cleanup ack
-        // is matching a pending miss.
+        // We switch the directory slot to EMPTY state and reset
+        // r_dcache_miss_clack if the cleanup ack is matching a pending miss.
         if ( r_dcache_clack_req.read() )
         {
@@ -4600 +4641 @@
             // return to cc_save state if no pending CC request
             if ( not r_cc_receive_dcache_req.read() )
+            {
                 r_dcache_fsm = r_dcache_fsm_cc_save.read() ;
+            }
 
 #if DEBUG_DCACHE
@@ -4611 +4654 @@
 }
 #endif
-            break;
-        }
-        
-        // Match between MISS address and CC address
-        if (r_cc_receive_dcache_req.read() and 
-          ((r_dcache_fsm_cc_save == DCACHE_MISS_SELECT  )  or
-           (r_dcache_fsm_cc_save == DCACHE_MISS_WAIT    )  or
-           (r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT)) and
-          ((r_dcache_vci_paddr.read() & mask) == (paddr & mask))) // matching
-        {
-            // signaling matching
-            r_dcache_miss_inval = true;
-
-            // in case of update, go to CC_UPDT
-            // JUST TO POP THE FIFO
-            if (r_cc_receive_dcache_type.read() == CC_TYPE_UPDT)
-            {
-                r_dcache_fsm        = DCACHE_CC_UPDT;
-                r_dcache_cc_word    = r_cc_receive_word_idx.read();
-
-                // just pop the fifo , don't write in icache
-                r_dcache_cc_need_write = false;
-            }
-            // the request is dealt with
-            else
-            {
-                r_cc_receive_dcache_req = false;
-                r_dcache_fsm          = r_dcache_fsm_cc_save.read();
-            }
-
-#if DEBUG_DCACHE
-if ( m_debug_activated )
-{
-    std::cout << "  <PROC " << name()
-              << " DCACHE_CC_CHECK> Coherence request matching a pending miss:"
-              << " PADDR = " << std::hex << paddr << std::endl;
-}
-#endif
-
             break;
         }