Index: /branches/v5/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp =================================================================== --- /branches/v5/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp (revision 461) +++ /branches/v5/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp (revision 462) @@ -1819,4 +1819,43 @@ paddr_t mask = ~((m_icache_words<<2)-1); + + // Match between MISS address and CC address + // note: In the same cycle we can handle a CLACK and a MISS match + // because the CLACK access the directory but the MISS match dont. + if (r_cc_receive_icache_req.read() and + ((r_icache_fsm_save.read() == ICACHE_MISS_SELECT ) or + (r_icache_fsm_save.read() == ICACHE_MISS_WAIT ) or + (r_icache_fsm_save.read() == ICACHE_MISS_DIR_UPDT)) and + ((r_icache_vci_paddr.read() & mask) == (paddr & mask)) ) // matching + { + // signaling the matching + r_icache_miss_inval = true; + + // in case of update, go to CC_UPDT + // JUST TO POP THE FIFO + if (r_cc_receive_icache_type.read() == CC_TYPE_UPDT) + { + r_icache_fsm = ICACHE_CC_UPDT; + r_icache_cc_word = r_cc_receive_word_idx.read(); + + // just pop the fifo , don't write in icache + r_icache_cc_need_write = false; + } + // the request is dealt with + else + { + r_cc_receive_icache_req = false; + r_icache_fsm = r_icache_fsm_save.read(); + } +#if DEBUG_ICACHE +if ( m_debug_activated ) +{ + std::cout << " Coherence request matching a pending miss:" + << " PADDR = " << std::hex << paddr << std::endl; +} +#endif + } + // CLACK handler // We switch the directory slot to EMPTY state @@ -1858,41 +1897,4 @@ #endif - break; - } - - // Match between MISS address and CC address - if (r_cc_receive_icache_req.read() and - ((r_icache_fsm_save.read() == ICACHE_MISS_SELECT ) or - (r_icache_fsm_save.read() == ICACHE_MISS_WAIT ) or - (r_icache_fsm_save.read() == ICACHE_MISS_DIR_UPDT)) and - ((r_icache_vci_paddr.read() & mask) == (paddr & mask)) ) // matching - { - // signaling the matching - r_icache_miss_inval = true; - - // in case of update, go to CC_UPDT - // JUST TO POP THE FIFO - if (r_cc_receive_icache_type.read() == CC_TYPE_UPDT) - { - r_icache_fsm = ICACHE_CC_UPDT; - r_icache_cc_word = r_cc_receive_word_idx.read(); - - // just pop the fifo , don't write in icache - r_icache_cc_need_write = false; - } - // the request is dealt with - else - { - r_cc_receive_icache_req = false; - r_icache_fsm = r_icache_fsm_save.read(); - } -#if DEBUG_ICACHE -if ( m_debug_activated ) -{ - std::cout << " Coherence request matching a pending miss:" - << " PADDR = " << std::hex << paddr << std::endl; -} -#endif break; } @@ -4574,8 +4576,47 @@ #endif + + // Match between MISS address and CC address + // note: In the same cycle we can handle a CLACK and a MISS match + // because the CLACK access the directory but the MISS match dont. + if (r_cc_receive_dcache_req.read() and + ((r_dcache_fsm_cc_save == DCACHE_MISS_SELECT ) or + (r_dcache_fsm_cc_save == DCACHE_MISS_WAIT ) or + (r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT)) and + ((r_dcache_vci_paddr.read() & mask) == (paddr & mask))) // matching + { + // signaling matching + r_dcache_miss_inval = true; + + // in case of update, go to CC_UPDT + // JUST TO POP THE FIFO + if (r_cc_receive_dcache_type.read() == CC_TYPE_UPDT) + { + r_dcache_fsm = DCACHE_CC_UPDT; + r_dcache_cc_word = r_cc_receive_word_idx.read(); + + // just pop the fifo , don't write in icache + r_dcache_cc_need_write = false; + } + // the request is dealt with + else + { + r_cc_receive_dcache_req = false; + r_dcache_fsm = r_dcache_fsm_cc_save.read(); + } + +#if DEBUG_DCACHE +if ( m_debug_activated ) +{ + std::cout << " Coherence request matching a pending miss:" + << " PADDR = " << std::hex << paddr << std::endl; +} +#endif + } + // CLACK handler - // We switch the directory slot to EMPTY state - // and reset r_dcache_miss_clack if the cleanup ack - // is matching a pending miss. + // We switch the directory slot to EMPTY state and reset + // r_dcache_miss_clack if the cleanup ack is matching a pending miss. if ( r_dcache_clack_req.read() ) { @@ -4600,5 +4641,7 @@ // return to cc_save state if no pending CC request if ( not r_cc_receive_dcache_req.read() ) + { r_dcache_fsm = r_dcache_fsm_cc_save.read() ; + } #if DEBUG_DCACHE @@ -4611,43 +4654,4 @@ } #endif - break; - } - - // Match between MISS address and CC address - if (r_cc_receive_dcache_req.read() and - ((r_dcache_fsm_cc_save == DCACHE_MISS_SELECT ) or - (r_dcache_fsm_cc_save == DCACHE_MISS_WAIT ) or - (r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT)) and - ((r_dcache_vci_paddr.read() & mask) == (paddr & mask))) // matching - { - // signaling matching - r_dcache_miss_inval = true; - - // in case of update, go to CC_UPDT - // JUST TO POP THE FIFO - if (r_cc_receive_dcache_type.read() == CC_TYPE_UPDT) - { - r_dcache_fsm = DCACHE_CC_UPDT; - r_dcache_cc_word = r_cc_receive_word_idx.read(); - - // just pop the fifo , don't write in icache - r_dcache_cc_need_write = false; - } - // the request is dealt with - else - { - r_cc_receive_dcache_req = false; - r_dcache_fsm = r_dcache_fsm_cc_save.read(); - } - -#if DEBUG_DCACHE -if ( m_debug_activated ) -{ - std::cout << " Coherence request matching a pending miss:" - << " PADDR = " << std::hex << paddr << std::endl; -} -#endif - break; }