Changeset 466
- Timestamp:
- Jul 23, 2013, 5:01:49 PM (11 years ago)
- Location:
- branches/v5/platforms/tsar_generic_xbar
- Files:
-
- 3 edited
Legend:
- Unmodified
- Added
- Removed
-
branches/v5/platforms/tsar_generic_xbar/top.cpp
r448 r466 350 350 "The NB_NIC_CHANNELS parameter must be smaller than 9" ); 351 351 352 assert( (vci_address_width == vci_address_width) and353 "address widths must be equal on internal & external networks" );354 355 352 assert( (vci_address_width == 40) and 356 353 "VCI address width must be 40 bits" ); … … 498 495 // Horizontal inter-clusters DSPIN signals 499 496 DspinSignals<dspin_cmd_width>*** signal_dspin_h_cmd_inc = 500 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cmd_inc", XMAX-1, YMAX, 2);497 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cmd_inc", XMAX-1, YMAX, 3); 501 498 DspinSignals<dspin_cmd_width>*** signal_dspin_h_cmd_dec = 502 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cmd_dec", XMAX-1, YMAX, 2);499 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cmd_dec", XMAX-1, YMAX, 3); 503 500 DspinSignals<dspin_rsp_width>*** signal_dspin_h_rsp_inc = 504 501 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_rsp_inc", XMAX-1, YMAX, 2); 505 502 DspinSignals<dspin_rsp_width>*** signal_dspin_h_rsp_dec = 506 503 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_rsp_dec", XMAX-1, YMAX, 2); 507 DspinSignals<dspin_cmd_width>** signal_dspin_h_clack_inc =508 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_clack_inc", XMAX-1, YMAX);509 DspinSignals<dspin_cmd_width>** signal_dspin_h_clack_dec =510 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_clack_dec", XMAX-1, YMAX);511 504 512 505 // Vertical inter-clusters DSPIN signals 513 506 DspinSignals<dspin_cmd_width>*** signal_dspin_v_cmd_inc = 514 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cmd_inc", XMAX, YMAX-1, 2);507 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cmd_inc", XMAX, YMAX-1, 3); 515 508 DspinSignals<dspin_cmd_width>*** signal_dspin_v_cmd_dec = 516 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cmd_dec", XMAX, YMAX-1, 2);509 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cmd_dec", XMAX, YMAX-1, 3); 517 510 DspinSignals<dspin_rsp_width>*** signal_dspin_v_rsp_inc = 518 511 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_rsp_inc", XMAX, YMAX-1, 2); 519 512 DspinSignals<dspin_rsp_width>*** signal_dspin_v_rsp_dec = 520 513 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_rsp_dec", XMAX, YMAX-1, 2); 521 DspinSignals<dspin_cmd_width>** signal_dspin_v_clack_inc =522 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_clack_inc", XMAX, YMAX-1);523 DspinSignals<dspin_cmd_width>** signal_dspin_v_clack_dec =524 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_clack_dec", XMAX, YMAX-1);525 514 526 515 // Mesh boundaries DSPIN signals 527 516 DspinSignals<dspin_cmd_width>**** signal_dspin_false_cmd_in = 528 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_false_cmd_in" , XMAX, YMAX, 2, 4);517 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_false_cmd_in" , XMAX, YMAX, 4, 3); 529 518 DspinSignals<dspin_cmd_width>**** signal_dspin_false_cmd_out = 530 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_false_cmd_out", XMAX, YMAX, 2, 4);519 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_false_cmd_out", XMAX, YMAX, 4, 3); 531 520 DspinSignals<dspin_rsp_width>**** signal_dspin_false_rsp_in = 532 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_false_rsp_in" , XMAX, YMAX, 2, 4);521 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_false_rsp_in" , XMAX, YMAX, 4, 2); 533 522 DspinSignals<dspin_rsp_width>**** signal_dspin_false_rsp_out = 534 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_false_rsp_out", XMAX, YMAX, 2, 4); 535 DspinSignals<dspin_cmd_width>*** signal_dspin_false_clack_in = 536 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_false_clack_in", XMAX, YMAX, 4); 537 DspinSignals<dspin_cmd_width>*** signal_dspin_false_clack_out = 538 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_false_clack_out", XMAX, YMAX, 4); 523 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_false_rsp_out", XMAX, YMAX, 4, 2); 539 524 540 525 … … 655 640 for (size_t x = 0; x < (XMAX-1); x++){ 656 641 for (size_t y = 0; y < YMAX; y++){ 642 for (size_t k = 0; k < 3; k++){ 643 clusters[x][y]->p_cmd_out[EAST][k] (signal_dspin_h_cmd_inc[x][y][k]); 644 clusters[x+1][y]->p_cmd_in[WEST][k] (signal_dspin_h_cmd_inc[x][y][k]); 645 clusters[x][y]->p_cmd_in[EAST][k] (signal_dspin_h_cmd_dec[x][y][k]); 646 clusters[x+1][y]->p_cmd_out[WEST][k] (signal_dspin_h_cmd_dec[x][y][k]); 647 } 648 657 649 for (size_t k = 0; k < 2; k++){ 658 clusters[x][y]->p_cmd_out[k][EAST] (signal_dspin_h_cmd_inc[x][y][k]); 659 clusters[x+1][y]->p_cmd_in[k][WEST] (signal_dspin_h_cmd_inc[x][y][k]); 660 clusters[x][y]->p_cmd_in[k][EAST] (signal_dspin_h_cmd_dec[x][y][k]); 661 clusters[x+1][y]->p_cmd_out[k][WEST] (signal_dspin_h_cmd_dec[x][y][k]); 662 clusters[x][y]->p_rsp_out[k][EAST] (signal_dspin_h_rsp_inc[x][y][k]); 663 clusters[x+1][y]->p_rsp_in[k][WEST] (signal_dspin_h_rsp_inc[x][y][k]); 664 clusters[x][y]->p_rsp_in[k][EAST] (signal_dspin_h_rsp_dec[x][y][k]); 665 clusters[x+1][y]->p_rsp_out[k][WEST] (signal_dspin_h_rsp_dec[x][y][k]); 650 clusters[x][y]->p_rsp_out[EAST][k] (signal_dspin_h_rsp_inc[x][y][k]); 651 clusters[x+1][y]->p_rsp_in[WEST][k] (signal_dspin_h_rsp_inc[x][y][k]); 652 clusters[x][y]->p_rsp_in[EAST][k] (signal_dspin_h_rsp_dec[x][y][k]); 653 clusters[x+1][y]->p_rsp_out[WEST][k] (signal_dspin_h_rsp_dec[x][y][k]); 666 654 } 667 clusters[x][y]->p_clack_out[EAST] (signal_dspin_h_clack_inc[x][y]);668 clusters[x+1][y]->p_clack_in[WEST] (signal_dspin_h_clack_inc[x][y]);669 clusters[x][y]->p_clack_in[EAST] (signal_dspin_h_clack_dec[x][y]);670 clusters[x+1][y]->p_clack_out[WEST] (signal_dspin_h_clack_dec[x][y]);671 655 } 672 656 } … … 678 662 for (size_t y = 0; y < (YMAX-1); y++){ 679 663 for (size_t x = 0; x < XMAX; x++){ 664 for (size_t k = 0; k < 3; k++){ 665 clusters[x][y]->p_cmd_out[NORTH][k] (signal_dspin_v_cmd_inc[x][y][k]); 666 clusters[x][y+1]->p_cmd_in[SOUTH][k] (signal_dspin_v_cmd_inc[x][y][k]); 667 clusters[x][y]->p_cmd_in[NORTH][k] (signal_dspin_v_cmd_dec[x][y][k]); 668 clusters[x][y+1]->p_cmd_out[SOUTH][k] (signal_dspin_v_cmd_dec[x][y][k]); 669 } 670 680 671 for (size_t k = 0; k < 2; k++){ 681 clusters[x][y]->p_cmd_out[k][NORTH] (signal_dspin_v_cmd_inc[x][y][k]); 682 clusters[x][y+1]->p_cmd_in[k][SOUTH] (signal_dspin_v_cmd_inc[x][y][k]); 683 clusters[x][y]->p_cmd_in[k][NORTH] (signal_dspin_v_cmd_dec[x][y][k]); 684 clusters[x][y+1]->p_cmd_out[k][SOUTH] (signal_dspin_v_cmd_dec[x][y][k]); 685 clusters[x][y]->p_rsp_out[k][NORTH] (signal_dspin_v_rsp_inc[x][y][k]); 686 clusters[x][y+1]->p_rsp_in[k][SOUTH] (signal_dspin_v_rsp_inc[x][y][k]); 687 clusters[x][y]->p_rsp_in[k][NORTH] (signal_dspin_v_rsp_dec[x][y][k]); 688 clusters[x][y+1]->p_rsp_out[k][SOUTH] (signal_dspin_v_rsp_dec[x][y][k]); 672 clusters[x][y]->p_rsp_out[NORTH][k] (signal_dspin_v_rsp_inc[x][y][k]); 673 clusters[x][y+1]->p_rsp_in[SOUTH][k] (signal_dspin_v_rsp_inc[x][y][k]); 674 clusters[x][y]->p_rsp_in[NORTH][k] (signal_dspin_v_rsp_dec[x][y][k]); 675 clusters[x][y+1]->p_rsp_out[SOUTH][k] (signal_dspin_v_rsp_dec[x][y][k]); 689 676 } 690 clusters[x][y]->p_clack_out[NORTH] (signal_dspin_v_clack_inc[x][y]);691 clusters[x][y+1]->p_clack_in[SOUTH] (signal_dspin_v_clack_inc[x][y]);692 clusters[x][y]->p_clack_in[NORTH] (signal_dspin_v_clack_dec[x][y]);693 clusters[x][y+1]->p_clack_out[SOUTH] (signal_dspin_v_clack_dec[x][y]);694 677 } 695 678 } … … 700 683 for (size_t y = 0; y < YMAX; y++) 701 684 { 685 for (size_t k = 0; k < 3; k++) 686 { 687 clusters[0][y]->p_cmd_in[WEST][k] (signal_dspin_false_cmd_in[0][y][WEST][k]); 688 clusters[0][y]->p_cmd_out[WEST][k] (signal_dspin_false_cmd_out[0][y][WEST][k]); 689 clusters[XMAX-1][y]->p_cmd_in[EAST][k] (signal_dspin_false_cmd_in[XMAX-1][y][EAST][k]); 690 clusters[XMAX-1][y]->p_cmd_out[EAST][k] (signal_dspin_false_cmd_out[XMAX-1][y][EAST][k]); 691 } 692 702 693 for (size_t k = 0; k < 2; k++) 703 694 { 704 clusters[0][y]->p_cmd_in[k][WEST] (signal_dspin_false_cmd_in[0][y][k][WEST]); 705 clusters[0][y]->p_cmd_out[k][WEST] (signal_dspin_false_cmd_out[0][y][k][WEST]); 706 clusters[0][y]->p_rsp_in[k][WEST] (signal_dspin_false_rsp_in[0][y][k][WEST]); 707 clusters[0][y]->p_rsp_out[k][WEST] (signal_dspin_false_rsp_out[0][y][k][WEST]); 708 709 clusters[XMAX-1][y]->p_cmd_in[k][EAST] (signal_dspin_false_cmd_in[XMAX-1][y][k][EAST]); 710 clusters[XMAX-1][y]->p_cmd_out[k][EAST] (signal_dspin_false_cmd_out[XMAX-1][y][k][EAST]); 711 clusters[XMAX-1][y]->p_rsp_in[k][EAST] (signal_dspin_false_rsp_in[XMAX-1][y][k][EAST]); 712 clusters[XMAX-1][y]->p_rsp_out[k][EAST] (signal_dspin_false_rsp_out[XMAX-1][y][k][EAST]); 713 } 714 715 clusters[0][y]->p_clack_in[WEST] (signal_dspin_false_clack_in[0][y][WEST]); 716 clusters[0][y]->p_clack_out[WEST] (signal_dspin_false_clack_out[0][y][WEST]); 717 718 clusters[XMAX-1][y]->p_clack_in[EAST] (signal_dspin_false_clack_in[XMAX-1][y][EAST]); 719 clusters[XMAX-1][y]->p_clack_out[EAST] (signal_dspin_false_clack_out[XMAX-1][y][EAST]); 695 clusters[0][y]->p_rsp_in[WEST][k] (signal_dspin_false_rsp_in[0][y][WEST][k]); 696 clusters[0][y]->p_rsp_out[WEST][k] (signal_dspin_false_rsp_out[0][y][WEST][k]); 697 clusters[XMAX-1][y]->p_rsp_in[EAST][k] (signal_dspin_false_rsp_in[XMAX-1][y][EAST][k]); 698 clusters[XMAX-1][y]->p_rsp_out[EAST][k] (signal_dspin_false_rsp_out[XMAX-1][y][EAST][k]); 699 } 720 700 } 721 701 … … 723 703 for (size_t x = 0; x < XMAX; x++) 724 704 { 705 for (size_t k = 0; k < 3; k++) 706 { 707 clusters[x][0]->p_cmd_in[SOUTH][k] (signal_dspin_false_cmd_in[x][0][SOUTH][k]); 708 clusters[x][0]->p_cmd_out[SOUTH][k] (signal_dspin_false_cmd_out[x][0][SOUTH][k]); 709 clusters[x][YMAX-1]->p_cmd_in[NORTH][k] (signal_dspin_false_cmd_in[x][YMAX-1][NORTH][k]); 710 clusters[x][YMAX-1]->p_cmd_out[NORTH][k] (signal_dspin_false_cmd_out[x][YMAX-1][NORTH][k]); 711 } 712 725 713 for (size_t k = 0; k < 2; k++) 726 714 { 727 clusters[x][0]->p_cmd_in[k][SOUTH] (signal_dspin_false_cmd_in[x][0][k][SOUTH]); 728 clusters[x][0]->p_cmd_out[k][SOUTH] (signal_dspin_false_cmd_out[x][0][k][SOUTH]); 729 clusters[x][0]->p_rsp_in[k][SOUTH] (signal_dspin_false_rsp_in[x][0][k][SOUTH]); 730 clusters[x][0]->p_rsp_out[k][SOUTH] (signal_dspin_false_rsp_out[x][0][k][SOUTH]); 731 732 clusters[x][YMAX-1]->p_cmd_in[k][NORTH] (signal_dspin_false_cmd_in[x][YMAX-1][k][NORTH]); 733 clusters[x][YMAX-1]->p_cmd_out[k][NORTH] (signal_dspin_false_cmd_out[x][YMAX-1][k][NORTH]); 734 clusters[x][YMAX-1]->p_rsp_in[k][NORTH] (signal_dspin_false_rsp_in[x][YMAX-1][k][NORTH]); 735 clusters[x][YMAX-1]->p_rsp_out[k][NORTH] (signal_dspin_false_rsp_out[x][YMAX-1][k][NORTH]); 736 } 737 738 clusters[x][0]->p_clack_in[SOUTH] (signal_dspin_false_clack_in[x][0][SOUTH]); 739 clusters[x][0]->p_clack_out[SOUTH] (signal_dspin_false_clack_out[x][0][SOUTH]); 740 741 clusters[x][YMAX-1]->p_clack_in[NORTH] (signal_dspin_false_clack_in[x][YMAX-1][NORTH]); 742 clusters[x][YMAX-1]->p_clack_out[NORTH] (signal_dspin_false_clack_out[x][YMAX-1][NORTH]); 715 clusters[x][0]->p_rsp_in[SOUTH][k] (signal_dspin_false_rsp_in[x][0][SOUTH][k]); 716 clusters[x][0]->p_rsp_out[SOUTH][k] (signal_dspin_false_rsp_out[x][0][SOUTH][k]); 717 clusters[x][YMAX-1]->p_rsp_in[NORTH][k] (signal_dspin_false_rsp_in[x][YMAX-1][NORTH][k]); 718 clusters[x][YMAX-1]->p_rsp_out[NORTH][k] (signal_dspin_false_rsp_out[x][YMAX-1][NORTH][k]); 719 } 743 720 } 744 721 std::cout << "North, South, West, East connections established" << std::endl; … … 756 733 for (size_t x = 0; x < XMAX ; x++){ 757 734 for (size_t y = 0; y < YMAX ; y++){ 758 for (size_t k = 0; k < 2; k++){ 759 for (size_t a = 0; a < 4; a++){ 760 signal_dspin_false_cmd_in [x][y][k][a].write = false; 761 signal_dspin_false_cmd_in [x][y][k][a].read = true; 762 signal_dspin_false_cmd_out[x][y][k][a].write = false; 763 signal_dspin_false_cmd_out[x][y][k][a].read = true; 764 765 signal_dspin_false_rsp_in [x][y][k][a].write = false; 766 signal_dspin_false_rsp_in [x][y][k][a].read = true; 767 signal_dspin_false_rsp_out[x][y][k][a].write = false; 768 signal_dspin_false_rsp_out[x][y][k][a].read = true; 735 for (size_t a = 0; a < 4; a++){ 736 for (size_t k = 0; k < 3; k++){ 737 signal_dspin_false_cmd_in [x][y][a][k].write = false; 738 signal_dspin_false_cmd_in [x][y][a][k].read = true; 739 signal_dspin_false_cmd_out[x][y][a][k].write = false; 740 signal_dspin_false_cmd_out[x][y][a][k].read = true; 769 741 } 770 } 771 } 772 } 773 // clack network boundaries signals 774 for (size_t x = 0; x < XMAX ; x++){ 775 for (size_t y = 0; y < YMAX ; y++){ 776 for (size_t k = 0; k < 4; k++){ 777 signal_dspin_false_clack_in [x][y][k].write = false; 778 signal_dspin_false_clack_in [x][y][k].read = true; 779 signal_dspin_false_clack_out[x][y][k].write = false; 780 signal_dspin_false_clack_out[x][y][k].read = true; 742 743 for (size_t k = 0; k < 2; k++){ 744 signal_dspin_false_rsp_in [x][y][a][k].write = false; 745 signal_dspin_false_rsp_in [x][y][a][k].read = true; 746 signal_dspin_false_rsp_out[x][y][a][k].write = false; 747 signal_dspin_false_rsp_out[x][y][a][k].read = true; 748 } 781 749 } 782 750 } -
branches/v5/platforms/tsar_generic_xbar/tsar_xbar_cluster/caba/source/include/tsar_xbar_cluster.h
r448 r466 55 55 soclib::caba::DspinOutput<dspin_rsp_width> **p_rsp_out; 56 56 soclib::caba::DspinInput<dspin_rsp_width> **p_rsp_in; 57 soclib::caba::DspinOutput<dspin_cmd_width> *p_clack_out;58 soclib::caba::DspinInput<dspin_cmd_width> *p_clack_in;59 57 60 58 // interrupt signals … … 209 207 VirtualDspinRouter<dspin_cmd_width>* router_cmd; 210 208 VirtualDspinRouter<dspin_rsp_width>* router_rsp; 211 DspinRouter<dspin_cmd_width>* router_clack;212 209 213 210 TsarXbarCluster( sc_module_name insname, -
branches/v5/platforms/tsar_generic_xbar/tsar_xbar_cluster/caba/source/src/tsar_xbar_cluster.cpp
r448 r466 85 85 { 86 86 // Vectors of ports definition 87 p_cmd_in = alloc_elems<DspinInput<dspin_cmd_width> >("p_cmd_in", 2, 4); 88 p_cmd_out = alloc_elems<DspinOutput<dspin_cmd_width> >("p_cmd_out", 2, 4); 89 p_rsp_in = alloc_elems<DspinInput<dspin_rsp_width> >("p_rsp_in", 2, 4); 90 p_rsp_out = alloc_elems<DspinOutput<dspin_rsp_width> >("p_rsp_out", 2, 4); 91 p_clack_in = alloc_elems<DspinInput<dspin_cmd_width> >("p_clack_in", 4); 92 p_clack_out = alloc_elems<DspinOutput<dspin_cmd_width> >("p_clack_out", 4); 87 p_cmd_in = alloc_elems<DspinInput<dspin_cmd_width> >("p_cmd_in", 4, 3); 88 p_cmd_out = alloc_elems<DspinOutput<dspin_cmd_width> >("p_cmd_out", 4, 3); 89 p_rsp_in = alloc_elems<DspinInput<dspin_rsp_width> >("p_rsp_in", 4, 2); 90 p_rsp_out = alloc_elems<DspinOutput<dspin_rsp_width> >("p_rsp_out", 4, 2); 93 91 94 92 ///////////////////////////////////////////////////////////////////////////// … … 289 287 x_id,y_id, // coordinate in the mesh 290 288 x_width, y_width, // x & y fields width 289 3, // nb virtual channels 291 290 4,4); // input & output fifo depths 292 291 … … 296 295 x_id,y_id, // coordinates in mesh 297 296 x_width, y_width, // x & y fields width 298 4,4); // input & output fifo depths 299 300 ///////////////////////////////////////////////////////////////////////////// 301 router_clack = new DspinRouter<dspin_cmd_width>( 302 "router_clack", 303 x_id,y_id, // coordinates in mesh 304 x_width, y_width, // x & y fields width 297 2, // nb virtual channels 305 298 4,4); // input & output fifo depths 306 299 … … 403 396 router_rsp->p_clk (this->p_clk); 404 397 router_rsp->p_resetn (this->p_resetn); 405 router_clack->p_clk (this->p_clk); 406 router_clack->p_resetn (this->p_resetn); 407 408 for (int x = 0; x < 2; x++) 409 { 410 for(int y = 0; y < 4; y++) 398 399 for(int i = 0; i < 4; i++) 400 { 401 for (int k = 0; k < 3; k++) 411 402 { 412 router_cmd->p_out[x][y] (this->p_cmd_out[x][y]); 413 router_cmd->p_in[x][y] (this->p_cmd_in[x][y]); 414 router_rsp->p_out[x][y] (this->p_rsp_out[x][y]); 415 router_rsp->p_in[x][y] (this->p_rsp_in[x][y]); 403 router_cmd->p_out[i][k] (this->p_cmd_out[i][k]); 404 router_cmd->p_in[i][k] (this->p_cmd_in[i][k]); 416 405 } 417 } 418 419 for(int x = 0; x < 4; x++) 420 { 421 router_clack->p_out[x] (this->p_clack_out[x]); 422 router_clack->p_in[x] (this->p_clack_in[x]); 423 } 424 425 router_cmd->p_out[0][4] (signal_dspin_cmd_g2l_d); 426 router_cmd->p_out[1][4] (signal_dspin_m2p_g2l_c); 427 router_cmd->p_in[0][4] (signal_dspin_cmd_l2g_d); 428 router_cmd->p_in[1][4] (signal_dspin_m2p_l2g_c); 429 430 router_rsp->p_out[0][4] (signal_dspin_rsp_g2l_d); 431 router_rsp->p_out[1][4] (signal_dspin_p2m_g2l_c); 432 router_rsp->p_in[0][4] (signal_dspin_rsp_l2g_d); 433 router_rsp->p_in[1][4] (signal_dspin_p2m_l2g_c); 434 435 router_clack->p_out[4] (signal_dspin_clack_g2l_c); 436 router_clack->p_in[4] (signal_dspin_clack_l2g_c); 406 407 for (int k = 0; k < 2; k++) 408 { 409 router_rsp->p_out[i][k] (this->p_rsp_out[i][k]); 410 router_rsp->p_in[i][k] (this->p_rsp_in[i][k]); 411 } 412 } 413 414 router_cmd->p_out[4][0] (signal_dspin_cmd_g2l_d); 415 router_cmd->p_out[4][1] (signal_dspin_m2p_g2l_c); 416 router_cmd->p_out[4][2] (signal_dspin_clack_g2l_c); 417 router_cmd->p_in[4][0] (signal_dspin_cmd_l2g_d); 418 router_cmd->p_in[4][1] (signal_dspin_m2p_l2g_c); 419 router_cmd->p_in[4][2] (signal_dspin_clack_l2g_c); 420 421 router_rsp->p_out[4][0] (signal_dspin_rsp_g2l_d); 422 router_rsp->p_out[4][1] (signal_dspin_p2m_g2l_c); 423 router_rsp->p_in[4][0] (signal_dspin_rsp_l2g_d); 424 router_rsp->p_in[4][1] (signal_dspin_p2m_l2g_c); 437 425 438 426
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