Index: trunk/modules/vci_mem_cache/caba/metadata/vci_mem_cache.sd =================================================================== --- trunk/modules/vci_mem_cache/caba/metadata/vci_mem_cache.sd (revision 449) +++ trunk/modules/vci_mem_cache/caba/metadata/vci_mem_cache.sd (revision 468) @@ -49,9 +49,13 @@ Port('caba:vci_initiator', 'p_vci_ixr'), Port('caba:dspin_input', - 'p_dspin_in', + 'p_dspin_p2m', dspin_data_size = parameter.Reference('dspin_in_width') ), Port('caba:dspin_output', - 'p_dspin_out', + 'p_dspin_m2p', + dspin_data_size = parameter.Reference('dspin_out_width') + ), + Port('caba:dspin_output', + 'p_dspin_clack', dspin_data_size = parameter.Reference('dspin_out_width') ), Index: trunk/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h =================================================================== --- trunk/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h (revision 449) +++ trunk/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h (revision 468) @@ -54,4 +54,5 @@ #define TRT_ENTRIES 4 // Number of entries in TRT #define UPT_ENTRIES 4 // Number of entries in UPT +#define IVT_ENTRIES 4 // Number of entries in IVT #define HEAP_ENTRIES 1024 // Number of entries in HEAP @@ -122,10 +123,8 @@ CC_SEND_WRITE_IDLE, CC_SEND_CAS_IDLE, - CC_SEND_CLEANUP_IDLE, CC_SEND_CONFIG_INVAL_HEADER, CC_SEND_CONFIG_INVAL_NLINE, CC_SEND_CONFIG_BRDCAST_HEADER, CC_SEND_CONFIG_BRDCAST_NLINE, - CC_SEND_CLEANUP_ACK, CC_SEND_XRAM_RSP_BRDCAST_HEADER, CC_SEND_XRAM_RSP_BRDCAST_NLINE, @@ -163,5 +162,5 @@ CONFIG_DIR_REQ, CONFIG_DIR_ACCESS, - CONFIG_DIR_UPT_LOCK, + CONFIG_DIR_IVT_LOCK, CONFIG_BC_SEND, CONFIG_BC_WAIT, @@ -211,5 +210,5 @@ WRITE_MISS_XRAM_REQ, WRITE_BC_TRT_LOCK, - WRITE_BC_UPT_LOCK, + WRITE_BC_IVT_LOCK, WRITE_BC_DIR_INVAL, WRITE_BC_CC_SEND, @@ -274,5 +273,5 @@ CAS_UPT_NEXT, CAS_BC_TRT_LOCK, - CAS_BC_UPT_LOCK, + CAS_BC_IVT_LOCK, CAS_BC_DIR_INVAL, CAS_BC_CC_SEND, @@ -299,7 +298,7 @@ CLEANUP_HEAP_CLEAN, CLEANUP_HEAP_FREE, - CLEANUP_UPT_LOCK, - CLEANUP_UPT_DECREMENT, - CLEANUP_UPT_CLEAR, + CLEANUP_IVT_LOCK, + CLEANUP_IVT_DECREMENT, + CLEANUP_IVT_CLEAR, CLEANUP_WRITE_RSP, CLEANUP_CONFIG_ACK, @@ -332,10 +331,17 @@ enum alloc_upt_fsm_state_e { - ALLOC_UPT_CONFIG, ALLOC_UPT_WRITE, - ALLOC_UPT_XRAM_RSP, - ALLOC_UPT_MULTI_ACK, - ALLOC_UPT_CLEANUP, - ALLOC_UPT_CAS + ALLOC_UPT_CAS, + ALLOC_UPT_MULTI_ACK + }; + + /* States of the ALLOC_IVT fsm */ + enum alloc_ivt_fsm_state_e + { + ALLOC_IVT_WRITE, + ALLOC_IVT_XRAM_RSP, + ALLOC_IVT_CLEANUP, + ALLOC_IVT_CAS, + ALLOC_IVT_CONFIG }; @@ -451,6 +457,7 @@ soclib::caba::VciTarget p_vci_tgt; soclib::caba::VciInitiator p_vci_ixr; - soclib::caba::DspinInput p_dspin_in; - soclib::caba::DspinOutput p_dspin_out; + soclib::caba::DspinInput p_dspin_p2m; + soclib::caba::DspinOutput p_dspin_m2p; + soclib::caba::DspinOutput p_dspin_clack; VciMemCache( @@ -468,4 +475,5 @@ const size_t trt_lines=TRT_ENTRIES, const size_t upt_lines=UPT_ENTRIES, + const size_t ivt_lines=IVT_ENTRIES, const size_t debug_start_cycle=0, const bool debug_ok=false ); @@ -502,5 +510,6 @@ TransactionTab m_trt; // xram transaction table uint32_t m_upt_lines; - UpdateTab m_upt; // pending update & invalidate + UpdateTab m_upt; // pending update + UpdateTab m_ivt; // pending invalidate CacheDirectory m_cache_directory; // data cache directory CacheData m_cache_data; // data array[set][way][word] @@ -591,5 +600,5 @@ sc_signal r_config_heap_next; // current pointer to scan HEAP - sc_signal r_config_upt_index; // UPT index + sc_signal r_config_ivt_index; // IVT index // Buffer between CONFIG fsm and TGT_RSP fsm (send a done response to L1 cache) @@ -780,11 +789,4 @@ sc_signal r_cleanup_to_tgt_rsp_pktid; // transaction pktid - // Buffer between CLEANUP fsm and CC_SEND fsm (acknowledge a cleanup command from L1) - sc_signal r_cleanup_to_cc_send_req; // valid request - sc_signal r_cleanup_to_cc_send_srcid; // L1 srcid - sc_signal r_cleanup_to_cc_send_set_index; // L1 set index - sc_signal r_cleanup_to_cc_send_way_index; // L1 way index - sc_signal r_cleanup_to_cc_send_inst; // Instruction Cleanup Ack - /////////////////////////////////////////////////////// // Registers controlled by CAS fsm @@ -872,5 +874,5 @@ sc_signal r_xram_rsp_victim_ptr; // victim line pointer to the heap sc_signal * r_xram_rsp_victim_data; // victim line data - sc_signal r_xram_rsp_upt_index; // UPT entry index + sc_signal r_xram_rsp_ivt_index; // IVT entry index sc_signal r_xram_rsp_next_ptr; // Next pointer to the heap @@ -953,4 +955,10 @@ //////////////////////////////////////////////////// + // Registers controlled by ALLOC_IVT fsm + //////////////////////////////////////////////////// + + sc_signal r_alloc_ivt_fsm; + + //////////////////////////////////////////////////// // Registers controlled by ALLOC_HEAP fsm //////////////////////////////////////////////////// Index: trunk/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp =================================================================== --- trunk/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp (revision 449) +++ trunk/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp (revision 468) @@ -99,10 +99,8 @@ "CC_SEND_WRITE_IDLE", "CC_SEND_CAS_IDLE", - "CC_SEND_CLEANUP_IDLE", "CC_SEND_CONFIG_INVAL_HEADER", "CC_SEND_CONFIG_INVAL_NLINE", "CC_SEND_CONFIG_BRDCAST_HEADER", "CC_SEND_CONFIG_BRDCAST_NLINE", - "CC_SEND_CLEANUP_ACK", "CC_SEND_XRAM_RSP_BRDCAST_HEADER", "CC_SEND_XRAM_RSP_BRDCAST_NLINE", @@ -136,5 +134,5 @@ "CONFIG_DIR_REQ", "CONFIG_DIR_ACCESS", - "CONFIG_DIR_UPT_LOCK", + "CONFIG_DIR_IVT_LOCK", "CONFIG_BC_SEND", "CONFIG_BC_WAIT", @@ -180,5 +178,5 @@ "WRITE_MISS_XRAM_REQ", "WRITE_BC_TRT_LOCK", - "WRITE_BC_UPT_LOCK", + "WRITE_BC_IVT_LOCK", "WRITE_BC_DIR_INVAL", "WRITE_BC_CC_SEND", @@ -235,5 +233,5 @@ "CAS_UPT_NEXT", "CAS_BC_TRT_LOCK", - "CAS_BC_UPT_LOCK", + "CAS_BC_IVT_LOCK", "CAS_BC_DIR_INVAL", "CAS_BC_CC_SEND", @@ -258,7 +256,7 @@ "CLEANUP_HEAP_CLEAN", "CLEANUP_HEAP_FREE", - "CLEANUP_UPT_LOCK", - "CLEANUP_UPT_DECREMENT", - "CLEANUP_UPT_CLEAR", + "CLEANUP_IVT_LOCK", + "CLEANUP_IVT_DECREMENT", + "CLEANUP_IVT_CLEAR", "CLEANUP_WRITE_RSP", "CLEANUP_CONFIG_ACK", @@ -268,4 +266,5 @@ { "ALLOC_DIR_RESET", + "ALLOC_DIR_CONFIG", "ALLOC_DIR_READ", "ALLOC_DIR_WRITE", @@ -285,8 +284,14 @@ { "ALLOC_UPT_WRITE", - "ALLOC_UPT_XRAM_RSP", - "ALLOC_UPT_MULTI_ACK", - "ALLOC_UPT_CLEANUP", - "ALLOC_UPT_CAS" + "ALLOC_UPT_CAS", + "ALLOC_UPT_MULTI_ACK" +}; +const char *alloc_ivt_fsm_str[] = +{ + "ALLOC_IVT_WRITE", + "ALLOC_IVT_XRAM_RSP", + "ALLOC_IVT_CLEANUP", + "ALLOC_IVT_CAS", + "ALLOC_IVT_CONFIG" }; const char *alloc_heap_fsm_str[] = @@ -328,4 +333,5 @@ const size_t trt_lines, // number of TRT entries const size_t upt_lines, // number of UPT entries + const size_t ivt_lines, // number of IVT entries const size_t debug_start_cycle, const bool debug_ok) @@ -337,6 +343,7 @@ p_vci_tgt( "p_vci_tgt" ), p_vci_ixr( "p_vci_ixr" ), - p_dspin_in( "p_dspin_in" ), - p_dspin_out( "p_dspin_out" ), + p_dspin_p2m( "p_dspin_p2m" ), + p_dspin_m2p( "p_dspin_m2p" ), + p_dspin_clack( "p_dspin_clack" ), m_seglist( mtp.getSegmentList(tgtid_d) ), @@ -355,4 +362,5 @@ m_upt_lines(upt_lines), m_upt(upt_lines), + m_ivt(ivt_lines), m_cache_directory(nways, nsets, nwords, vci_param_int::N), m_cache_data(nways, nsets, nwords), @@ -446,4 +454,5 @@ r_alloc_trt_fsm("r_alloc_trt_fsm"), r_alloc_upt_fsm("r_alloc_upt_fsm"), + r_alloc_ivt_fsm("r_alloc_ivt_fsm"), r_alloc_heap_fsm("r_alloc_heap_fsm"), r_alloc_heap_reset_cpt("r_alloc_heap_reset_cpt") @@ -623,8 +632,9 @@ << " | " << ixr_cmd_fsm_str[r_ixr_cmd_fsm.read()] << " | " << ixr_rsp_fsm_str[r_ixr_rsp_fsm.read()] - << " | " << xram_rsp_fsm_str[r_xram_rsp_fsm] << std::endl; + << " | " << xram_rsp_fsm_str[r_xram_rsp_fsm.read()] << std::endl; std::cout << " " << alloc_dir_fsm_str[r_alloc_dir_fsm.read()] << " | " << alloc_trt_fsm_str[r_alloc_trt_fsm.read()] << " | " << alloc_upt_fsm_str[r_alloc_upt_fsm.read()] + << " | " << alloc_ivt_fsm_str[r_alloc_ivt_fsm.read()] << " | " << alloc_heap_fsm_str[r_alloc_heap_fsm.read()] << std::endl; } @@ -702,4 +712,5 @@ r_alloc_trt_fsm = ALLOC_TRT_READ; r_alloc_upt_fsm = ALLOC_UPT_WRITE; + r_alloc_ivt_fsm = ALLOC_IVT_XRAM_RSP; r_ixr_rsp_fsm = IXR_RSP_IDLE; r_xram_rsp_fsm = XRAM_RSP_IDLE; @@ -714,4 +725,5 @@ m_trt.init(); m_upt.init(); + m_ivt.init(); m_llsc_table.init(); @@ -1534,5 +1546,5 @@ r_config_dir_next_ptr = entry.ptr; - r_config_fsm = CONFIG_DIR_UPT_LOCK; + r_config_fsm = CONFIG_DIR_IVT_LOCK; } else if ( entry.valid and // hit & sync command @@ -1563,11 +1575,11 @@ } ///////////////////////// - case CONFIG_DIR_UPT_LOCK: // enter this state in case of INVAL command - // Try to get both DIR & UPT locks, and return - // to LOOP state if UPT full. - // Register inval in UPT, and invalidate the - // directory if UPT not full. - { - if ( r_alloc_upt_fsm.read() == ALLOC_UPT_CONFIG ) + case CONFIG_DIR_IVT_LOCK: // enter this state in case of INVAL command + // Try to get both DIR & IVT locks, and return + // to LOOP state if IVT full. + // Register inval in IVT, and invalidate the + // directory if IVT not full. + { + if ( r_alloc_ivt_fsm.read() == ALLOC_IVT_CONFIG ) { size_t set = m_y[(addr_t)(r_config_address.read())]; @@ -1583,9 +1595,9 @@ #if DEBUG_MEMC_CONFIG if(m_debug) -std::cout << " " +std::cout << " " << " No copies in L1 : inval DIR entry" << std::endl; #endif } - else // try to register inval in UPT + else // try to register inval in IVT { bool wok = false; @@ -1598,5 +1610,5 @@ size_t nb_copies = r_config_dir_count.read(); - wok = m_upt.set(false, // it's an inval transaction + wok = m_ivt.set(false, // it's an inval transaction broadcast, false, // no response required @@ -1609,8 +1621,8 @@ index); - if ( wok ) // UPT success => inval DIR slot + if ( wok ) // IVT success => inval DIR slot { m_cache_directory.inval( way, set ); - r_config_upt_index = index; + r_config_ivt_index = index; if ( broadcast ) r_config_fsm = CONFIG_BC_SEND; else r_config_fsm = CONFIG_INV_SEND; @@ -1618,11 +1630,11 @@ #if DEBUG_MEMC_CONFIG if(m_debug) -std::cout << " " - << " Inval DIR entry and register inval in UPT" +std::cout << " " + << " Inval DIR entry and register inval in IVT" << " : index = " << std::dec << index << " / broadcast = " << broadcast << std::endl; #endif } - else // UPT full => release both DIR and UPT locks + else // IVT full => release both DIR and IVT locks { r_config_fsm = CONFIG_LOOP; @@ -1630,6 +1642,6 @@ #if DEBUG_MEMC_CONFIG if(m_debug) -std::cout << " " - << " UPT full : release DIR & UPT locks and retry" << std::endl; +std::cout << " " + << " IVT full : release DIR & IVT locks and retry" << std::endl; #endif } @@ -1646,5 +1658,5 @@ r_config_to_cc_send_multi_req = false; r_config_to_cc_send_brdcast_req = true; - r_config_to_cc_send_trdid = r_config_upt_index.read(); + r_config_to_cc_send_trdid = r_config_ivt_index.read(); r_config_to_cc_send_nline = m_nline[(addr_t)(r_config_address.read())]; r_cleanup_to_config_ack = false; @@ -1686,5 +1698,5 @@ r_config_to_cc_send_multi_req = true; r_config_to_cc_send_brdcast_req = false; - r_config_to_cc_send_trdid = r_config_upt_index.read(); + r_config_to_cc_send_trdid = r_config_ivt_index.read(); r_config_to_cc_send_nline = m_nline[(addr_t)(r_config_address.read())]; r_multi_ack_to_config_ack = false; @@ -1848,18 +1860,18 @@ switch(r_read_fsm.read()) { - /////////////// - case READ_IDLE: // waiting a read request - { + /////////////// + case READ_IDLE: // waiting a read request + { if(m_cmd_read_addr_fifo.rok()) { #if DEBUG_MEMC_READ -if(m_debug) -std::cout << " Read request" - << " : address = " << std::hex << m_cmd_read_addr_fifo.read() - << " / srcid = " << m_cmd_read_srcid_fifo.read() - << " / trdid = " << m_cmd_read_trdid_fifo.read() - << " / pktid = " << m_cmd_read_pktid_fifo.read() - << " / nwords = " << std::dec << m_cmd_read_length_fifo.read() << std::endl; + if(m_debug) + std::cout << " Read request" + << " : address = " << std::hex << m_cmd_read_addr_fifo.read() + << " / srcid = " << m_cmd_read_srcid_fifo.read() + << " / trdid = " << m_cmd_read_trdid_fifo.read() + << " / pktid = " << m_cmd_read_pktid_fifo.read() + << " / nwords = " << std::dec << m_cmd_read_length_fifo.read() << std::endl; #endif r_read_fsm = READ_DIR_REQ; @@ -1961,80 +1973,80 @@ { - if(r_alloc_dir_fsm.read() == ALLOC_DIR_READ) - { - // check if this is an instruction read, this means pktid is either - // TYPE_READ_INS_UNC 0bX010 with TSAR encoding - // TYPE_READ_INS_MISS 0bX011 with TSAR encoding - bool inst_read = ((m_cmd_read_pktid_fifo.read() & 0x2) != 0); - // check if this is a cached read, this means pktid is either - // TYPE_READ_DATA_MISS 0bX001 with TSAR encoding - // TYPE_READ_INS_MISS 0bX011 with TSAR encoding - bool cached_read = (m_cmd_read_pktid_fifo.read() & 0x1); - bool is_cnt = r_read_is_cnt.read(); - - // read data in the cache - size_t set = m_y[(addr_t)(m_cmd_read_addr_fifo.read())]; - size_t way = r_read_way.read(); - - m_cache_data.read_line(way, set, r_read_data); - - if(m_monitor_ok) check_monitor( m_cmd_read_addr_fifo.read(), r_read_data[0], true); - - // update the cache directory - DirectoryEntry entry; - entry.valid = true; - entry.is_cnt = is_cnt; - entry.dirty = r_read_dirty.read(); - entry.tag = r_read_tag.read(); - entry.lock = r_read_lock.read(); - entry.ptr = r_read_ptr.read(); - - if(cached_read) // Cached read => we must update the copies - { - if(!is_cnt) // Not counter mode - { - entry.owner.srcid = m_cmd_read_srcid_fifo.read(); + if(r_alloc_dir_fsm.read() == ALLOC_DIR_READ) + { + // check if this is an instruction read, this means pktid is either + // TYPE_READ_INS_UNC 0bX010 with TSAR encoding + // TYPE_READ_INS_MISS 0bX011 with TSAR encoding + bool inst_read = ((m_cmd_read_pktid_fifo.read() & 0x2) != 0); + // check if this is a cached read, this means pktid is either + // TYPE_READ_DATA_MISS 0bX001 with TSAR encoding + // TYPE_READ_INS_MISS 0bX011 with TSAR encoding + bool cached_read = (m_cmd_read_pktid_fifo.read() & 0x1); + bool is_cnt = r_read_is_cnt.read(); + + // read data in the cache + size_t set = m_y[(addr_t)(m_cmd_read_addr_fifo.read())]; + size_t way = r_read_way.read(); + + m_cache_data.read_line(way, set, r_read_data); + + if(m_monitor_ok) check_monitor( m_cmd_read_addr_fifo.read(), r_read_data[0], true); + + // update the cache directory + DirectoryEntry entry; + entry.valid = true; + entry.is_cnt = is_cnt; + entry.dirty = r_read_dirty.read(); + entry.tag = r_read_tag.read(); + entry.lock = r_read_lock.read(); + entry.ptr = r_read_ptr.read(); + + if(cached_read) // Cached read => we must update the copies + { + if(!is_cnt) // Not counter mode + { + entry.owner.srcid = m_cmd_read_srcid_fifo.read(); #if L1_MULTI_CACHE - entry.owner.cache_id = m_cmd_read_pktid_fifo.read(); -#endif - entry.owner.inst = inst_read; - entry.count = r_read_count.read() + 1; - } - else // Counter mode - { - entry.owner.srcid = 0; + entry.owner.cache_id = m_cmd_read_pktid_fifo.read(); +#endif + entry.owner.inst = inst_read; + entry.count = r_read_count.read() + 1; + } + else // Counter mode + { + entry.owner.srcid = 0; #if L1_MULTI_CACHE - entry.owner.cache_id = 0; -#endif - entry.owner.inst = false; - entry.count = r_read_count.read() + 1; - } - } - else // Uncached read - { - entry.owner.srcid = r_read_copy.read(); + entry.owner.cache_id = 0; +#endif + entry.owner.inst = false; + entry.count = r_read_count.read() + 1; + } + } + else // Uncached read + { + entry.owner.srcid = r_read_copy.read(); #if L1_MULTI_CACHE - entry.owner.cache_id = r_read_copy_cache.read(); -#endif - entry.owner.inst = r_read_copy_inst.read(); - entry.count = r_read_count.read(); - } + entry.owner.cache_id = r_read_copy_cache.read(); +#endif + entry.owner.inst = r_read_copy_inst.read(); + entry.count = r_read_count.read(); + } #if DEBUG_MEMC_READ -if(m_debug) -std::cout << " Update directory entry:" - << " addr = " << std::hex << m_cmd_read_addr_fifo.read() - << " / set = " << std::dec << set - << " / way = " << way - << " / owner_id = " << std::hex << entry.owner.srcid - << " / owner_ins = " << std::dec << entry.owner.inst - << " / count = " << entry.count - << " / is_cnt = " << entry.is_cnt << std::endl; -#endif - - m_cache_directory.write(set, way, entry); - r_read_fsm = READ_RSP; - } - break; + if(m_debug) + std::cout << " Update directory entry:" + << " addr = " << std::hex << m_cmd_read_addr_fifo.read() + << " / set = " << std::dec << set + << " / way = " << way + << " / owner_id = " << std::hex << entry.owner.srcid + << " / owner_ins = " << std::dec << entry.owner.inst + << " / count = " << entry.count + << " / is_cnt = " << entry.is_cnt << std::endl; +#endif + + m_cache_directory.write(set, way, entry); + r_read_fsm = READ_RSP; + } + break; } /////////////////// @@ -2750,7 +2762,7 @@ wok = m_upt.set(true, // it's an update transaction - false, // it's not a broadcast - true, // response required - false, // no acknowledge required + false, // it's not a broadcast + true, // response required + false, // no acknowledge required srcid, trdid, @@ -2904,5 +2916,5 @@ entry.owner.inst) // put the next srcid in the fifo { - dec_upt_counter = false; + dec_upt_counter = false; write_to_cc_send_fifo_put = true; write_to_cc_send_fifo_inst = entry.owner.inst; @@ -2957,5 +2969,5 @@ { r_write_to_cc_send_multi_req = true; - if(r_write_to_dec.read() or dec_upt_counter) r_write_fsm = WRITE_UPT_DEC; + if(r_write_to_dec.read() or dec_upt_counter) r_write_fsm = WRITE_UPT_DEC; else r_write_fsm = WRITE_IDLE; } @@ -3200,5 +3212,5 @@ { r_write_trt_index = wok_index; - r_write_fsm = WRITE_BC_UPT_LOCK; + r_write_fsm = WRITE_BC_IVT_LOCK; } else // wait an empty entry in TRT @@ -3217,7 +3229,7 @@ ////////////////////// - case WRITE_BC_UPT_LOCK: // register BC transaction in UPT - { - if(r_alloc_upt_fsm.read() == ALLOC_UPT_WRITE) + case WRITE_BC_IVT_LOCK: // register BC transaction in IVT + { + if(r_alloc_ivt_fsm.read() == ALLOC_IVT_WRITE) { bool wok = false; @@ -3229,8 +3241,8 @@ size_t nb_copies = r_write_count.read(); - wok = m_upt.set(false, // it's an inval transaction - true, // it's a broadcast - true, // response required - false, // no acknowledge required + wok = m_ivt.set(false, // it's an inval transaction + true, // it's a broadcast + true, // response required + false, // no acknowledge required srcid, trdid, @@ -3242,5 +3254,5 @@ #if DEBUG_MEMC_WRITE if( m_debug and wok ) -std::cout << " Register broadcast inval in UPT" +std::cout << " Register broadcast inval in IVT" << " / nb_copies = " << r_write_count.read() << std::endl; #endif @@ -3248,5 +3260,5 @@ if(wok) r_write_fsm = WRITE_BC_DIR_INVAL; - else r_write_fsm = WRITE_WAIT; + else r_write_fsm = WRITE_WAIT; } break; @@ -3259,9 +3271,9 @@ // and invalidate the line in directory if((r_alloc_trt_fsm.read() != ALLOC_TRT_WRITE) or - (r_alloc_upt_fsm.read() != ALLOC_UPT_WRITE) or - (r_alloc_dir_fsm.read() != ALLOC_DIR_WRITE)) + (r_alloc_ivt_fsm.read() != ALLOC_IVT_WRITE) or + (r_alloc_dir_fsm.read() != ALLOC_DIR_WRITE)) { std::cout << "VCI_MEM_CACHE ERROR " << name() << " WRITE_BC_DIR_INVAL state" << std::endl; - std::cout << "bad TRT, DIR, or UPT allocation" << std::endl; + std::cout << "bad TRT, DIR, or IVT allocation" << std::endl; exit(0); } @@ -3791,10 +3803,10 @@ } ///////////////////////// - case XRAM_RSP_INVAL_LOCK: // Take the UPT lock to check a possible pending inval - { - if(r_alloc_upt_fsm == ALLOC_UPT_XRAM_RSP) + case XRAM_RSP_INVAL_LOCK: // Take the IVT lock to check a possible pending inval + { + if(r_alloc_ivt_fsm == ALLOC_IVT_XRAM_RSP) { size_t index = 0; - if(m_upt.search_inval(r_xram_rsp_trt_buf.nline, index)) // pending inval + if(m_ivt.search_inval(r_xram_rsp_trt_buf.nline, index)) // pending inval { r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT; @@ -3803,5 +3815,5 @@ if(m_debug) std::cout << " " - << " Get acces to UPT, but line invalidation registered" + << " Get acces to IVT, but line invalidation registered" << " / nline = " << std::hex << r_xram_rsp_trt_buf.nline << " / index = " << std::dec << index << std::endl; @@ -3809,5 +3821,5 @@ } - else if(m_upt.is_full() and r_xram_rsp_victim_inval.read()) // UPT full + else if(m_ivt.is_full() and r_xram_rsp_victim_inval.read()) // IVT full { r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT; @@ -3816,5 +3828,5 @@ if(m_debug) std::cout << " " - << " Get acces to UPT, but inval required and UPT full" << std::endl; + << " Get acces to IVT, but inval required and IVT full" << std::endl; #endif } @@ -3826,5 +3838,5 @@ if(m_debug) std::cout << " " - << " Get acces to UPT" << std::endl; + << " Get acces to IVT" << std::endl; #endif } @@ -3846,5 +3858,5 @@ /////////////////////// case XRAM_RSP_DIR_UPDT: // updates the cache (both data & directory) - // and possibly set an inval request in UPT + // and possibly set an inval request in IVT { // check if this is an instruction read, this means pktid is either @@ -3904,5 +3916,5 @@ m_cache_directory.write(set, way, entry); - // request an invalidattion request in UPT for victim line + // request an invalidattion request in IVT for victim line if(r_xram_rsp_victim_inval.read()) { @@ -3911,5 +3923,5 @@ size_t count_copies = r_xram_rsp_victim_count.read(); - bool wok = m_upt.set(false, // it's an inval transaction + bool wok = m_ivt.set(false, // it's an inval transaction broadcast, // set broadcast bit false, // no response required @@ -3922,10 +3934,10 @@ index); - r_xram_rsp_upt_index = index; + r_xram_rsp_ivt_index = index; if(!wok) { std::cout << "VCI_MEM_CACHE ERROR " << name() << " XRAM_RSP_DIR_UPDT" - << " update_tab entry free but write unsuccessful" << std::endl; + << " invalidate_tab entry free but write unsuccessful" << std::endl; exit(0); } @@ -4036,5 +4048,5 @@ r_xram_rsp_to_cc_send_brdcast_req = r_xram_rsp_victim_is_cnt.read(); r_xram_rsp_to_cc_send_nline = r_xram_rsp_victim_nline.read(); - r_xram_rsp_to_cc_send_trdid = r_xram_rsp_upt_index; + r_xram_rsp_to_cc_send_trdid = r_xram_rsp_ivt_index; xram_rsp_to_cc_send_fifo_srcid = r_xram_rsp_victim_copy.read(); xram_rsp_to_cc_send_fifo_inst = r_xram_rsp_victim_copy_inst.read(); @@ -4252,5 +4264,5 @@ DspinDhccpParam::dspin_get( flit, - DspinDhccpParam::FROM_L1_TYPE); + DspinDhccpParam::P2M_TYPE); r_cleanup_way_index = @@ -4381,5 +4393,5 @@ else // miss : check UPT for a pending invalidation transaction { - r_cleanup_fsm = CLEANUP_UPT_LOCK; + r_cleanup_fsm = CLEANUP_IVT_LOCK; } @@ -4839,13 +4851,13 @@ } ////////////////////// - case CLEANUP_UPT_LOCK: // get the lock protecting the UPT to search a pending + case CLEANUP_IVT_LOCK: // get the lock protecting the IVT to search a pending // invalidate transaction matching the cleanup { - if(r_alloc_upt_fsm.read() != ALLOC_UPT_CLEANUP) break; + if(r_alloc_ivt_fsm.read() != ALLOC_IVT_CLEANUP) break; size_t index = 0; bool match_inval; - match_inval = m_upt.search_inval(r_cleanup_nline.read(), index); + match_inval = m_ivt.search_inval(r_cleanup_nline.read(), index); if ( not match_inval ) // no pending inval @@ -4856,6 +4868,6 @@ if(m_debug) std::cout << " Unexpected cleanup" - << " with no corresponding UPT entry:" + << " CLEANUP_IVT_LOCK> Unexpected cleanup" + << " with no corresponding IVT entry:" << " address = " << std::hex << (r_cleanup_nline.read() *4*m_words) @@ -4866,32 +4878,32 @@ // pending inval - r_cleanup_write_srcid = m_upt.srcid(index); - r_cleanup_write_trdid = m_upt.trdid(index); - r_cleanup_write_pktid = m_upt.pktid(index); - r_cleanup_need_rsp = m_upt.need_rsp(index); - r_cleanup_need_ack = m_upt.need_ack(index); + r_cleanup_write_srcid = m_ivt.srcid(index); + r_cleanup_write_trdid = m_ivt.trdid(index); + r_cleanup_write_pktid = m_ivt.pktid(index); + r_cleanup_need_rsp = m_ivt.need_rsp(index); + r_cleanup_need_ack = m_ivt.need_ack(index); r_cleanup_index = index; - r_cleanup_fsm = CLEANUP_UPT_DECREMENT; + r_cleanup_fsm = CLEANUP_IVT_DECREMENT; #if DEBUG_MEMC_CLEANUP if(m_debug) std::cout << " Cleanup matching pending" - << " invalidate transaction on UPT:" + << " CLEANUP_IVT_LOCK> Cleanup matching pending" + << " invalidate transaction on IVT:" << " address = " << std::hex << r_cleanup_nline.read() * m_words * 4 - << " / upt_entry = " << index << std::endl; + << " / ivt_entry = " << index << std::endl; #endif break; } /////////////////////////// - case CLEANUP_UPT_DECREMENT: // decrement response counter in UPT matching entry - { - if(r_alloc_upt_fsm.read() != ALLOC_UPT_CLEANUP) + case CLEANUP_IVT_DECREMENT: // decrement response counter in IVT matching entry + { + if(r_alloc_ivt_fsm.read() != ALLOC_IVT_CLEANUP) { std::cout << "VCI_MEM_CACHE ERROR " << name() - << " CLEANUP_UPT_DECREMENT state" << std::endl - << "Bad UPT allocation" + << " CLEANUP_IVT_DECREMENT state" << std::endl + << "Bad IVT allocation" << std::endl; @@ -4900,9 +4912,9 @@ size_t count = 0; - m_upt.decrement(r_cleanup_index.read(), count); + m_ivt.decrement(r_cleanup_index.read(), count); if(count == 0) // multi inval transaction completed { - r_cleanup_fsm = CLEANUP_UPT_CLEAR; + r_cleanup_fsm = CLEANUP_IVT_CLEAR; } else // multi inval transaction not completed @@ -4913,7 +4925,7 @@ #if DEBUG_MEMC_CLEANUP if(m_debug) -std::cout << " " - << " Decrement response counter in UPT:" - << " UPT_index = " << r_cleanup_index.read() +std::cout << " " + << " Decrement response counter in IVT:" + << " IVT_index = " << r_cleanup_index.read() << " / rsp_count = " << count << std::endl; #endif @@ -4921,12 +4933,12 @@ } /////////////////////// - case CLEANUP_UPT_CLEAR: // Clear UPT entry - { - if(r_alloc_upt_fsm.read() != ALLOC_UPT_CLEANUP) + case CLEANUP_IVT_CLEAR: // Clear IVT entry + { + if(r_alloc_ivt_fsm.read() != ALLOC_IVT_CLEANUP) { std::cout << "VCI_MEM_CACHE ERROR " << name() - << " CLEANUP_UPT_CLEAR state" << std::endl - << "Bad UPT allocation" + << " CLEANUP_IVT_CLEAR state" << std::endl + << "Bad IVT allocation" << std::endl; @@ -4934,5 +4946,5 @@ } - m_upt.clear(r_cleanup_index.read()); + m_ivt.clear(r_cleanup_index.read()); if ( r_cleanup_need_rsp.read() ) r_cleanup_fsm = CLEANUP_WRITE_RSP; @@ -4943,6 +4955,6 @@ if(m_debug) std::cout << " Clear entry in UPT:" - << " UPT_index = " << r_cleanup_index.read() << std::endl; + << " CLEANUP_IVT_CLEAR> Clear entry in IVT:" + << " IVT_index = " << r_cleanup_index.read() << std::endl; #endif break; @@ -4989,15 +5001,8 @@ } //////////////////////// - case CLEANUP_SEND_CLACK: // acknowledgement to a cleanup command - // on the coherence network (request to the CC_SEND FSM). - // wait if pending request to the CC_SEND FSM - { - if(r_cleanup_to_cc_send_req.read()) break; - - r_cleanup_to_cc_send_req = true; - r_cleanup_to_cc_send_set_index = r_cleanup_nline.read() & 0xFFFF; - r_cleanup_to_cc_send_way_index = r_cleanup_way_index.read(); - r_cleanup_to_cc_send_srcid = r_cleanup_srcid.read(); - r_cleanup_to_cc_send_inst = r_cleanup_inst.read(); + case CLEANUP_SEND_CLACK: // acknowledgement to a cleanup command + // on the coherence CLACK network. + { + if(not p_dspin_clack.read) break; r_cleanup_fsm = CLEANUP_IDLE; @@ -5007,5 +5012,8 @@ std::cout << " Send the response to a cleanup request:" - << " srcid = " << std::dec << r_cleanup_srcid.read() << std::endl; + << " nline = " << std::hex << r_cleanup_nline.read() + << " / way = " << std::dec << r_cleanup_way.read() + << " / srcid = " << std::dec << r_cleanup_srcid.read() + << std::endl; #endif break; @@ -5242,5 +5250,5 @@ !r_cas_to_cc_send_brdcast_req.read()) { - r_cas_fsm = CAS_UPT_LOCK; // multi update required + r_cas_fsm = CAS_UPT_LOCK; // multi update required } else @@ -5507,5 +5515,5 @@ { r_cas_trt_index = wok_index; - r_cas_fsm = CAS_BC_UPT_LOCK; + r_cas_fsm = CAS_BC_IVT_LOCK; } else @@ -5522,8 +5530,8 @@ } ///////////////////// - case CAS_BC_UPT_LOCK: // register a broadcast inval transaction in UPT + case CAS_BC_IVT_LOCK: // register a broadcast inval transaction in IVT // write data in cache in case of successful registration { - if(r_alloc_upt_fsm.read() == ALLOC_UPT_CAS) + if(r_alloc_ivt_fsm.read() == ALLOC_IVT_CAS) { bool wok = false; @@ -5535,9 +5543,9 @@ size_t nb_copies = r_cas_count.read(); - // register a broadcast inval transaction in UPT - wok = m_upt.set(false, // it's an inval transaction - true, // it's a broadcast - true, // response required - false, // no acknowledge required + // register a broadcast inval transaction in IVT + wok = m_ivt.set(false, // it's an inval transaction + true, // it's a broadcast + true, // response required + false, // no acknowledge required srcid, trdid, @@ -5547,5 +5555,5 @@ index); - if(wok) // UPT not full + if(wok) // IVT not full { // cache update @@ -5573,11 +5581,11 @@ if(m_debug) std::cout << " Register a broadcast inval transaction in UPT" + << " CAS_BC_IVT_LOCK> Register a broadcast inval transaction in IVT" << " / nline = " << std::hex << nline << " / count = " << std::dec << nb_copies - << " / upt_index = " << index << std::endl; -#endif - } - else // releases the lock protecting UPT + << " / ivt_index = " << index << std::endl; +#endif + } + else // releases the lock protecting IVT { r_cas_fsm = CAS_WAIT; @@ -5590,6 +5598,6 @@ { if((r_alloc_trt_fsm.read() == ALLOC_TRT_CAS) and - (r_alloc_upt_fsm.read() == ALLOC_UPT_CAS) and - (r_alloc_dir_fsm.read() == ALLOC_DIR_CAS)) + (r_alloc_ivt_fsm.read() == ALLOC_IVT_CAS) and + (r_alloc_dir_fsm.read() == ALLOC_DIR_CAS)) { // set TRT @@ -5834,9 +5842,6 @@ // network, used to update or invalidate cache lines in L1 caches. // - // This fsm is used also to acknowledge CLEANUP a command after request from - // the CLEANUP fsm. - // - // It implements a round-robin priority between the five possible client FSMs - // XRAM_RSP > CAS > CLEANUP > WRITE > CONFIG + // It implements a round-robin priority between the four possible client FSMs + // XRAM_RSP > CAS > WRITE > CONFIG // // Each FSM can request the next services: @@ -5850,6 +5855,4 @@ // r_config_to_cc_send_brdcast_req : broadcast-inval // - // - r_cleanup_to_cc_send_req : cleanup acknowledgement - // // An inval request is a double DSPIN flit command containing: // 1. the index of the line to be invalidated. @@ -5894,10 +5897,4 @@ break; } - // CLEANUP - if (r_cleanup_to_cc_send_req.read()) - { - r_cc_send_fsm = CC_SEND_CLEANUP_ACK; - break; - } // WRITE if(m_write_to_cc_send_inst_fifo.rok() or @@ -5973,10 +5970,4 @@ break; } - // CLEANUP - if (r_cleanup_to_cc_send_req.read()) - { - r_cc_send_fsm = CC_SEND_CLEANUP_ACK; - break; - } // WRITE if(m_write_to_cc_send_inst_fifo.rok() or @@ -6012,10 +6003,4 @@ break; } - // CLEANUP - if(r_cleanup_to_cc_send_req.read()) - { - r_cc_send_fsm = CC_SEND_CLEANUP_ACK; - break; - } // WRITE if(m_write_to_cc_send_inst_fifo.rok() or @@ -6065,9 +6050,4 @@ case CC_SEND_CAS_IDLE: // CLEANUP FSM has highest priority { - if(r_cleanup_to_cc_send_req.read()) - { - r_cc_send_fsm = CC_SEND_CLEANUP_ACK; - break; - } if(m_write_to_cc_send_inst_fifo.rok() or r_write_to_cc_send_multi_req.read()) @@ -6124,70 +6104,4 @@ break; } - ////////////////////////// - case CC_SEND_CLEANUP_IDLE: // WRITE FSM has highest priority - { - // WRITE - if(m_write_to_cc_send_inst_fifo.rok() or - r_write_to_cc_send_multi_req.read()) - { - r_cc_send_fsm = CC_SEND_WRITE_UPDT_HEADER; - m_cpt_update++; - break; - } - if(r_write_to_cc_send_brdcast_req.read()) - { - r_cc_send_fsm = CC_SEND_WRITE_BRDCAST_HEADER; - m_cpt_inval++; - break; - } - // CONFIG - if(r_config_to_cc_send_multi_req.read()) - { - r_cc_send_fsm = CC_SEND_CONFIG_INVAL_HEADER; - m_cpt_inval++; - break; - } - if(r_config_to_cc_send_brdcast_req.read()) - { - r_cc_send_fsm = CC_SEND_CONFIG_BRDCAST_HEADER; - m_cpt_inval++; - break; - } - // XRAM_RSP - if(m_xram_rsp_to_cc_send_inst_fifo.rok() or - r_xram_rsp_to_cc_send_multi_req.read()) - { - r_cc_send_fsm = CC_SEND_XRAM_RSP_INVAL_HEADER; - m_cpt_inval++; - break; - } - if(r_xram_rsp_to_cc_send_brdcast_req.read()) - { - r_cc_send_fsm = CC_SEND_XRAM_RSP_BRDCAST_HEADER; - m_cpt_inval++; - break; - } - // CAS - if(m_cas_to_cc_send_inst_fifo.rok() or - r_cas_to_cc_send_multi_req.read()) - { - r_cc_send_fsm = CC_SEND_CAS_UPDT_HEADER; - m_cpt_update++; - break; - } - if(r_cas_to_cc_send_brdcast_req.read()) - { - r_cc_send_fsm = CC_SEND_CAS_BRDCAST_HEADER; - m_cpt_inval++; - break; - } - // CLEANUP - if(r_cleanup_to_cc_send_req.read()) - { - r_cc_send_fsm = CC_SEND_CLEANUP_ACK; - break; - } - break; - } ///////////////////////////////// case CC_SEND_CONFIG_INVAL_HEADER: // send first flit multi-inval (from CONFIG FSM) @@ -6195,5 +6109,5 @@ if(m_config_to_cc_send_inst_fifo.rok()) { - if(not p_dspin_out.read) break; + if(not p_dspin_m2p.read) break; r_cc_send_fsm = CC_SEND_CONFIG_INVAL_NLINE; break; @@ -6206,5 +6120,5 @@ case CC_SEND_CONFIG_INVAL_NLINE: // send second flit multi-inval (from CONFIG FSM) { - if(not p_dspin_out.read) break; + if(not p_dspin_m2p.read) break; m_cpt_inval_mult++; config_to_cc_send_fifo_get = true; @@ -6222,5 +6136,5 @@ case CC_SEND_CONFIG_BRDCAST_HEADER: // send first flit BC-inval (from CONFIG FSM) { - if(not p_dspin_out.read) break; + if(not p_dspin_m2p.read) break; r_cc_send_fsm = CC_SEND_CONFIG_BRDCAST_NLINE; break; @@ -6229,5 +6143,5 @@ case CC_SEND_CONFIG_BRDCAST_NLINE: // send second flit BC-inval (from CONFIG FSM) { - if(not p_dspin_out.read) break; + if(not p_dspin_m2p.read) break; m_cpt_inval_brdcast++; r_config_to_cc_send_brdcast_req = false; @@ -6242,20 +6156,4 @@ break; } - ///////////////////////// - case CC_SEND_CLEANUP_ACK: // send one flit for a cleanup acknowledgement - { - if(not p_dspin_out.read) break; - - r_cleanup_to_cc_send_req = false; - r_cc_send_fsm = CC_SEND_CLEANUP_IDLE; - -#if DEBUG_MEMC_CC_SEND -if(m_debug) -std::cout << " Cleanup Ack for srcid " - << std::hex << r_cleanup_to_cc_send_srcid.read() << std::endl; -#endif - break; - } /////////////////////////////////// case CC_SEND_XRAM_RSP_INVAL_HEADER: // send first flit multi-inval (from XRAM_RSP FSM) @@ -6263,5 +6161,5 @@ if(m_xram_rsp_to_cc_send_inst_fifo.rok()) { - if(not p_dspin_out.read) break; + if(not p_dspin_m2p.read) break; r_cc_send_fsm = CC_SEND_XRAM_RSP_INVAL_NLINE; break; @@ -6274,5 +6172,5 @@ case CC_SEND_XRAM_RSP_INVAL_NLINE: // send second flit multi-inval (from XRAM_RSP FSM) { - if(not p_dspin_out.read) break; + if(not p_dspin_m2p.read) break; m_cpt_inval_mult++; xram_rsp_to_cc_send_fifo_get = true; @@ -6282,5 +6180,5 @@ if(m_debug) std::cout << " BC-Inval for line " + << " CC_SEND_XRAM_RSP_INVAL_NLINE> Multicast-Inval for line " << std::hex << r_xram_rsp_to_cc_send_nline.read() << std::endl; #endif @@ -6290,5 +6188,5 @@ case CC_SEND_XRAM_RSP_BRDCAST_HEADER: // send first flit broadcast-inval (from XRAM_RSP FSM) { - if(not p_dspin_out.read) break; + if(not p_dspin_m2p.read) break; r_cc_send_fsm = CC_SEND_XRAM_RSP_BRDCAST_NLINE; break; @@ -6297,5 +6195,5 @@ case CC_SEND_XRAM_RSP_BRDCAST_NLINE: // send second flit broadcast-inval (from XRAM_RSP FSM) { - if(not p_dspin_out.read) break; + if(not p_dspin_m2p.read) break; m_cpt_inval_brdcast++; r_xram_rsp_to_cc_send_brdcast_req = false; @@ -6313,5 +6211,5 @@ case CC_SEND_WRITE_BRDCAST_HEADER: // send first flit broadcast-inval (from WRITE FSM) { - if(not p_dspin_out.read) break; + if(not p_dspin_m2p.read) break; r_cc_send_fsm = CC_SEND_WRITE_BRDCAST_NLINE; break; @@ -6320,5 +6218,5 @@ case CC_SEND_WRITE_BRDCAST_NLINE: // send second flit broadcast-inval (from WRITE FSM) { - if(not p_dspin_out.read) break; + if(not p_dspin_m2p.read) break; m_cpt_inval_brdcast++; @@ -6340,5 +6238,5 @@ if(m_write_to_cc_send_inst_fifo.rok()) { - if(not p_dspin_out.read) break; + if(not p_dspin_m2p.read) break; r_cc_send_fsm = CC_SEND_WRITE_UPDT_NLINE; @@ -6357,5 +6255,5 @@ case CC_SEND_WRITE_UPDT_NLINE: // send second flit for a multi-update (from WRITE FSM) { - if(not p_dspin_out.read) break; + if(not p_dspin_m2p.read) break; m_cpt_update_mult++; @@ -6374,5 +6272,5 @@ case CC_SEND_WRITE_UPDT_DATA: // send N data flits for a multi-update (from WRITE FSM) { - if(not p_dspin_out.read) break; + if(not p_dspin_m2p.read) break; if(r_cc_send_cpt.read() == (r_write_to_cc_send_count.read()-1)) { @@ -6388,5 +6286,5 @@ case CC_SEND_CAS_BRDCAST_HEADER: // send first flit broadcast-inval (from CAS FSM) { - if(not p_dspin_out.read) break; + if(not p_dspin_m2p.read) break; r_cc_send_fsm = CC_SEND_CAS_BRDCAST_NLINE; break; @@ -6395,5 +6293,5 @@ case CC_SEND_CAS_BRDCAST_NLINE: // send second flit broadcast-inval (from CAS FSM) { - if(not p_dspin_out.read) break; + if(not p_dspin_m2p.read) break; m_cpt_inval_brdcast++; @@ -6414,5 +6312,5 @@ if(m_cas_to_cc_send_inst_fifo.rok()) { - if(not p_dspin_out.read) break; + if(not p_dspin_m2p.read) break; r_cc_send_fsm = CC_SEND_CAS_UPDT_NLINE; @@ -6432,5 +6330,5 @@ case CC_SEND_CAS_UPDT_NLINE: // send second flit for a multi-update (from CAS FSM) { - if(not p_dspin_out.read) break; + if(not p_dspin_m2p.read) break; m_cpt_update_mult++; @@ -6450,5 +6348,5 @@ case CC_SEND_CAS_UPDT_DATA: // send first data for a multi-update (from CAS FSM) { - if(not p_dspin_out.read) break; + if(not p_dspin_m2p.read) break; if(r_cas_to_cc_send_is_long.read()) @@ -6465,5 +6363,5 @@ case CC_SEND_CAS_UPDT_DATA_HIGH: // send second data for a multi-update (from CAS FSM) { - if(not p_dspin_out.read) break; + if(not p_dspin_m2p.read) break; cas_to_cc_send_fifo_get = true; r_cc_send_fsm = CC_SEND_CAS_UPDT_HEADER; @@ -6485,10 +6383,10 @@ case CC_RECEIVE_IDLE: { - if(not p_dspin_in.write) break; + if(not p_dspin_p2m.write) break; uint8_t type = DspinDhccpParam::dspin_get( - p_dspin_in.data.read(), - DspinDhccpParam::FROM_L1_TYPE); + p_dspin_p2m.data.read(), + DspinDhccpParam::P2M_TYPE); if((type == DspinDhccpParam::TYPE_CLEANUP_DATA) or @@ -6516,8 +6414,8 @@ // write first CLEANUP flit in CC_RECEIVE to CLEANUP fifo - if(not p_dspin_in.write or not m_cc_receive_to_cleanup_fifo.wok()) + if(not p_dspin_p2m.write or not m_cc_receive_to_cleanup_fifo.wok()) break; - assert(not p_dspin_in.eop.read() and + assert(not p_dspin_p2m.eop.read() and "VCI_MEM_CACHE ERROR in CC_RECEIVE : " "CLEANUP command must have two flits"); @@ -6533,8 +6431,8 @@ // write second CLEANUP flit in CC_RECEIVE to CLEANUP fifo - if(not p_dspin_in.write or not m_cc_receive_to_cleanup_fifo.wok()) + if(not p_dspin_p2m.write or not m_cc_receive_to_cleanup_fifo.wok()) break; - assert(p_dspin_in.eop.read() and + assert(p_dspin_p2m.eop.read() and "VCI_MEM_CACHE ERROR in CC_RECEIVE : " "CLEANUP command must have two flits"); @@ -6552,8 +6450,8 @@ // wait for a WOK in the CC_RECEIVE to MULTI_ACK fifo - if(not p_dspin_in.write or not m_cc_receive_to_multi_ack_fifo.wok()) + if(not p_dspin_p2m.write or not m_cc_receive_to_multi_ack_fifo.wok()) break; - assert(p_dspin_in.eop.read() and + assert(p_dspin_p2m.eop.read() and "VCI_MEM_CACHE ERROR in CC_RECEIVE : " "MULTI_ACK command must have one flit"); @@ -6965,159 +6863,161 @@ // ALLOC_UPT FSM //////////////////////////////////////////////////////////////////////////////////// - // The ALLOC_UPT FSM allocates the access to the Update/Inval Table (UPT), - // with a round robin priority between six FSMs, with the following order: - // CONFIG > MULTI_ACK > WRITE > XRAM_RSP > CLEANUP > CAS - // - The CONFIG FSM initiates an inval transaction and sets a new entry in UPT. + // The ALLOC_UPT FSM allocates the access to the Update Table (UPT), + // with a round robin priority between three FSMs, with the following order: + // WRITE -> CAS -> MULTI_ACK + // - The WRITE FSM initiates update transaction and sets a new entry in UPT. + // - The CAS FSM does the same thing as the WRITE FSM. // - The MULTI_ACK FSM complete those trasactions and erase the UPT entry. - // - The WRITE FSM initiates update transaction and sets a new entry in UPT. - // - The XRAM_RSP FSM initiates an inval transactions and sets a new entry in UPT. - // - The CLEANUP FSM decrement an entry in UPT. - // - The CAS FSM does the same thing as the WRITE FSM. // The resource is always allocated. ///////////////////////////////////////////////////////////////////////////////////// - switch(r_alloc_upt_fsm.read()) { - ////////////////////// - case ALLOC_UPT_CONFIG: // allocated to CONFIG FSM - if (r_config_fsm.read() != CONFIG_DIR_UPT_LOCK) - { - if(r_multi_ack_fsm.read() == MULTI_ACK_UPT_LOCK) - r_alloc_upt_fsm = ALLOC_UPT_MULTI_ACK; - - else if((r_write_fsm.read() == WRITE_UPT_LOCK) or - (r_write_fsm.read() == WRITE_BC_UPT_LOCK)) - r_alloc_upt_fsm = ALLOC_UPT_WRITE; - - else if(r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK) - r_alloc_upt_fsm = ALLOC_UPT_XRAM_RSP; - - else if(r_cleanup_fsm.read() == CLEANUP_UPT_LOCK) - r_alloc_upt_fsm = ALLOC_UPT_CLEANUP; - - else if((r_cas_fsm.read() == CAS_UPT_LOCK) or - (r_cas_fsm.read() == CAS_BC_UPT_LOCK)) - r_alloc_upt_fsm = ALLOC_UPT_CAS; - } - break; - ///////////////////////// - case ALLOC_UPT_MULTI_ACK: // allocated to MULTI_ACK FSM - if( (r_multi_ack_fsm.read() != MULTI_ACK_UPT_LOCK) and - (r_multi_ack_fsm.read() != MULTI_ACK_UPT_CLEAR)) - { - if((r_write_fsm.read() == WRITE_UPT_LOCK) or - (r_write_fsm.read() == WRITE_BC_UPT_LOCK)) - r_alloc_upt_fsm = ALLOC_UPT_WRITE; - - else if(r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK) - r_alloc_upt_fsm = ALLOC_UPT_XRAM_RSP; - - else if(r_cleanup_fsm.read() == CLEANUP_UPT_LOCK) - r_alloc_upt_fsm = ALLOC_UPT_CLEANUP; - - else if((r_cas_fsm.read() == CAS_UPT_LOCK) or - (r_cas_fsm.read() == CAS_BC_UPT_LOCK)) - r_alloc_upt_fsm = ALLOC_UPT_CAS; - - else if(r_config_fsm.read() == CONFIG_DIR_UPT_LOCK) - r_alloc_upt_fsm = ALLOC_UPT_CONFIG; - } - break; - - ///////////////////// - case ALLOC_UPT_WRITE: // allocated to WRITE FSM - if((r_write_fsm.read() != WRITE_UPT_LOCK) and - (r_write_fsm.read() != WRITE_BC_UPT_LOCK)) - { - if(r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK) - r_alloc_upt_fsm = ALLOC_UPT_XRAM_RSP; - - else if(r_cleanup_fsm.read() == CLEANUP_UPT_LOCK) - r_alloc_upt_fsm = ALLOC_UPT_CLEANUP; - - else if((r_cas_fsm.read() == CAS_UPT_LOCK) or - (r_cas_fsm.read() == CAS_BC_UPT_LOCK)) - r_alloc_upt_fsm = ALLOC_UPT_CAS; - - else if(r_config_fsm.read() == CONFIG_DIR_UPT_LOCK) - r_alloc_upt_fsm = ALLOC_UPT_CONFIG; - - else if(r_multi_ack_fsm.read() == MULTI_ACK_UPT_LOCK) - r_alloc_upt_fsm = ALLOC_UPT_MULTI_ACK; - } - break; - - //////////////////////// - case ALLOC_UPT_XRAM_RSP: - if(r_xram_rsp_fsm.read() != XRAM_RSP_INVAL_LOCK) - { - if(r_cleanup_fsm.read() == CLEANUP_UPT_LOCK) - r_alloc_upt_fsm = ALLOC_UPT_CLEANUP; - - else if((r_cas_fsm.read() == CAS_UPT_LOCK) or - (r_cas_fsm.read() == CAS_BC_UPT_LOCK)) - r_alloc_upt_fsm = ALLOC_UPT_CAS; - - else if(r_config_fsm.read() == CONFIG_DIR_UPT_LOCK) - r_alloc_upt_fsm = ALLOC_UPT_CONFIG; - - else if(r_multi_ack_fsm.read() == MULTI_ACK_UPT_LOCK) - r_alloc_upt_fsm = ALLOC_UPT_MULTI_ACK; - - else if((r_write_fsm.read() == WRITE_UPT_LOCK) or - (r_write_fsm.read() == WRITE_BC_UPT_LOCK)) - r_alloc_upt_fsm = ALLOC_UPT_WRITE; - } - break; - + case ALLOC_UPT_WRITE: // allocated to WRITE FSM + if (r_write_fsm.read() != WRITE_UPT_LOCK) + { + if (r_cas_fsm.read() == CAS_UPT_LOCK) + r_alloc_upt_fsm = ALLOC_UPT_CAS; + + else if (r_multi_ack_fsm.read() == MULTI_ACK_UPT_LOCK) + r_alloc_upt_fsm = ALLOC_UPT_MULTI_ACK; + } + break; + + ///////////////////////// + case ALLOC_UPT_CAS: // allocated to CAS FSM + if (r_cas_fsm.read() != CAS_UPT_LOCK) + { + if (r_multi_ack_fsm.read() == MULTI_ACK_UPT_LOCK) + r_alloc_upt_fsm = ALLOC_UPT_MULTI_ACK; + + else if (r_write_fsm.read() == WRITE_UPT_LOCK) + r_alloc_upt_fsm = ALLOC_UPT_WRITE; + } + break; + + ///////////////////////// + case ALLOC_UPT_MULTI_ACK: // allocated to MULTI_ACK FSM + if ((r_multi_ack_fsm.read() != MULTI_ACK_UPT_LOCK ) and + (r_multi_ack_fsm.read() != MULTI_ACK_UPT_CLEAR)) + { + if (r_write_fsm.read() == WRITE_UPT_LOCK) + r_alloc_upt_fsm = ALLOC_UPT_WRITE; + + else if (r_cas_fsm.read() == CAS_UPT_LOCK) + r_alloc_upt_fsm = ALLOC_UPT_CAS; + } + break; + } // end switch r_alloc_upt_fsm + + //////////////////////////////////////////////////////////////////////////////////// + // ALLOC_IVT FSM + //////////////////////////////////////////////////////////////////////////////////// + // The ALLOC_IVT FSM allocates the access to the Invalidate Table (IVT), + // with a round robin priority between five FSMs, with the following order: + // WRITE -> XRAM_RSP -> CLEANUP -> CAS -> CONFIG + // - The WRITE FSM initiates broadcast invalidate transactions and sets a new entry + // in IVT. + // - The CAS FSM does the same thing as the WRITE FSM. + // - The XRAM_RSP FSM initiates broadcast/multicast invalidate transaction and sets + // a new entry in the IVT + // - The CONFIG FSM does the same thing as the XRAM_RSP FSM + // - The CLEANUP FSM complete those trasactions and erase the IVT entry. + // The resource is always allocated. + ///////////////////////////////////////////////////////////////////////////////////// + switch(r_alloc_ivt_fsm.read()) + { ////////////////////////// - case ALLOC_UPT_CLEANUP: - if((r_cleanup_fsm.read() != CLEANUP_UPT_LOCK ) and - (r_cleanup_fsm.read() != CLEANUP_UPT_DECREMENT)) - { - if((r_cas_fsm.read() == CAS_UPT_LOCK) or - (r_cas_fsm.read() == CAS_BC_UPT_LOCK)) - r_alloc_upt_fsm = ALLOC_UPT_CAS; - - else if(r_config_fsm.read() == CONFIG_DIR_UPT_LOCK) - r_alloc_upt_fsm = ALLOC_UPT_CONFIG; - - else if(r_multi_ack_fsm.read() == MULTI_ACK_UPT_LOCK) - r_alloc_upt_fsm = ALLOC_UPT_MULTI_ACK; - - else if((r_write_fsm.read() == WRITE_UPT_LOCK) or - (r_write_fsm.read() == WRITE_BC_UPT_LOCK)) - r_alloc_upt_fsm = ALLOC_UPT_WRITE; - - else if(r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK) - r_alloc_upt_fsm = ALLOC_UPT_XRAM_RSP; - } - break; + case ALLOC_IVT_WRITE: // allocated to WRITE FSM + if (r_write_fsm.read() != WRITE_BC_IVT_LOCK) + { + if (r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_XRAM_RSP; + + else if (r_cleanup_fsm.read() == CLEANUP_IVT_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_CLEANUP; + + else if (r_cas_fsm.read() == CAS_BC_IVT_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_CAS; + + else if (r_config_fsm.read() == CONFIG_DIR_IVT_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_CONFIG; + } + break; ////////////////////////// - case ALLOC_UPT_CAS: - if((r_cas_fsm.read() != CAS_UPT_LOCK) and - (r_cas_fsm.read() != CAS_BC_UPT_LOCK)) - { - if(r_config_fsm.read() == CONFIG_DIR_UPT_LOCK) - r_alloc_upt_fsm = ALLOC_UPT_CONFIG; - - else if(r_multi_ack_fsm.read() == MULTI_ACK_UPT_LOCK) - r_alloc_upt_fsm = ALLOC_UPT_MULTI_ACK; - - else if((r_write_fsm.read() == WRITE_UPT_LOCK) or - (r_write_fsm.read() == WRITE_BC_UPT_LOCK)) - r_alloc_upt_fsm = ALLOC_UPT_WRITE; - - else if(r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK) - r_alloc_upt_fsm = ALLOC_UPT_XRAM_RSP; - - else if(r_cleanup_fsm.read() == CLEANUP_UPT_LOCK) - r_alloc_upt_fsm = ALLOC_UPT_CLEANUP; - } - break; - - } // end switch r_alloc_upt_fsm + case ALLOC_IVT_XRAM_RSP: // allocated to XRAM_RSP FSM + if(r_xram_rsp_fsm.read() != XRAM_RSP_INVAL_LOCK) + { + if(r_cleanup_fsm.read() == CLEANUP_IVT_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_CLEANUP; + + else if (r_cas_fsm.read() == CAS_BC_IVT_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_CAS; + + else if (r_config_fsm.read() == CONFIG_DIR_IVT_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_CONFIG; + + else if (r_write_fsm.read() == WRITE_BC_IVT_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_WRITE; + } + break; + + ////////////////////////// + case ALLOC_IVT_CLEANUP: // allocated to CLEANUP FSM + if ((r_cleanup_fsm.read() != CLEANUP_IVT_LOCK ) and + (r_cleanup_fsm.read() != CLEANUP_IVT_DECREMENT)) + { + if (r_cas_fsm.read() == CAS_BC_IVT_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_CAS; + + else if (r_config_fsm.read() == CONFIG_DIR_IVT_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_CONFIG; + + else if (r_write_fsm.read() == WRITE_BC_IVT_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_WRITE; + + else if (r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_XRAM_RSP; + } + break; + + ////////////////////////// + case ALLOC_IVT_CAS: // allocated to CAS FSM + if (r_cas_fsm.read() != CAS_BC_IVT_LOCK) + { + if (r_config_fsm.read() == CONFIG_DIR_IVT_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_CONFIG; + + else if (r_write_fsm.read() == WRITE_BC_IVT_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_WRITE; + + else if (r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_XRAM_RSP; + + else if (r_cleanup_fsm.read() == CLEANUP_IVT_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_CLEANUP; + } + break; + + ////////////////////////// + case ALLOC_IVT_CONFIG: // allocated to CONFIG FSM + if (r_config_fsm.read() != CONFIG_DIR_IVT_LOCK) + { + if (r_write_fsm.read() == WRITE_BC_IVT_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_WRITE; + + else if (r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_XRAM_RSP; + + else if (r_cleanup_fsm.read() == CLEANUP_IVT_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_CLEANUP; + + else if (r_cas_fsm.read() == CAS_BC_IVT_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_CAS; + } + break; + + } // end switch r_alloc_ivt_fsm //////////////////////////////////////////////////////////////////////////////////// @@ -7149,5 +7049,5 @@ if ( (r_config_fsm.read() != CONFIG_DIR_REQ) and (r_config_fsm.read() != CONFIG_DIR_ACCESS) and - (r_config_fsm.read() != CONFIG_DIR_UPT_LOCK) ) + (r_config_fsm.read() != CONFIG_DIR_IVT_LOCK) ) { if(r_read_fsm.read() == READ_DIR_REQ) @@ -7202,5 +7102,5 @@ (r_write_fsm.read() != WRITE_DIR_HIT) and (r_write_fsm.read() != WRITE_BC_TRT_LOCK) and - (r_write_fsm.read() != WRITE_BC_UPT_LOCK) and + (r_write_fsm.read() != WRITE_BC_IVT_LOCK) and (r_write_fsm.read() != WRITE_MISS_TRT_LOCK) and (r_write_fsm.read() != WRITE_UPT_LOCK) and @@ -7238,5 +7138,5 @@ (r_cas_fsm.read() != CAS_DIR_HIT_WRITE) and (r_cas_fsm.read() != CAS_BC_TRT_LOCK) and - (r_cas_fsm.read() != CAS_BC_UPT_LOCK) and + (r_cas_fsm.read() != CAS_BC_IVT_LOCK) and (r_cas_fsm.read() != CAS_MISS_TRT_LOCK) and (r_cas_fsm.read() != CAS_UPT_LOCK) and @@ -7352,5 +7252,5 @@ if((r_write_fsm.read() != WRITE_MISS_TRT_LOCK) and (r_write_fsm.read() != WRITE_BC_TRT_LOCK) and - (r_write_fsm.read() != WRITE_BC_UPT_LOCK)) + (r_write_fsm.read() != WRITE_BC_IVT_LOCK)) { if((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) or @@ -7375,5 +7275,5 @@ if((r_cas_fsm.read() != CAS_MISS_TRT_LOCK) and (r_cas_fsm.read() != CAS_BC_TRT_LOCK) and - (r_cas_fsm.read() != CAS_BC_UPT_LOCK)) + (r_cas_fsm.read() != CAS_BC_IVT_LOCK)) { if((r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) and @@ -7665,5 +7565,5 @@ m_cc_receive_to_cleanup_fifo.update( cc_receive_to_cleanup_fifo_get, cc_receive_to_cleanup_fifo_put, - p_dspin_in.data.read() ); + p_dspin_p2m.data.read() ); //////////////////////////////////////////////////////////////////////////////////// @@ -7673,5 +7573,5 @@ m_cc_receive_to_multi_ack_fifo.update( cc_receive_to_multi_ack_fifo_get, cc_receive_to_multi_ack_fifo_put, - p_dspin_in.data.read() ); + p_dspin_p2m.data.read() ); //////////////////////////////////////////////////////////////////////////////////// @@ -8015,10 +7915,10 @@ //////////////////////////////////////////////////////////////////// - // p_dspin_out port (CC_SEND FSM) + // p_dspin_m2p port (CC_SEND FSM) //////////////////////////////////////////////////////////////////// - p_dspin_out.write = false; - p_dspin_out.eop = false; - p_dspin_out.data = 0; + p_dspin_m2p.write = false; + p_dspin_m2p.eop = false; + p_dspin_m2p.data = 0; switch(r_cc_send_fsm.read()) @@ -8029,5 +7929,4 @@ case CC_SEND_WRITE_IDLE: case CC_SEND_CAS_IDLE: - case CC_SEND_CLEANUP_IDLE: { break; @@ -8064,7 +7963,7 @@ DspinDhccpParam::dspin_set( flit, multi_inval_type, - DspinDhccpParam::FROM_MC_TYPE); - p_dspin_out.write = true; - p_dspin_out.data = flit; + DspinDhccpParam::M2P_TYPE); + p_dspin_m2p.write = true; + p_dspin_m2p.data = flit; break; } @@ -8076,54 +7975,9 @@ r_config_to_cc_send_nline.read(), DspinDhccpParam::MULTI_INVAL_NLINE); - p_dspin_out.eop = true; - p_dspin_out.write = true; - p_dspin_out.data = flit; + p_dspin_m2p.eop = true; + p_dspin_m2p.write = true; + p_dspin_m2p.data = flit; break; } - //////////////////////// - case CC_SEND_CLEANUP_ACK: - { - uint8_t cleanup_ack_type; - if(r_cleanup_to_cc_send_inst.read()) - { - cleanup_ack_type = DspinDhccpParam::TYPE_CLEANUP_ACK_INST; - } - else - { - cleanup_ack_type = DspinDhccpParam::TYPE_CLEANUP_ACK_DATA; - } - - uint64_t flit = 0; - uint64_t dest = - r_cleanup_to_cc_send_srcid.read() << - (DspinDhccpParam::SRCID_WIDTH - vci_param_int::S); - - DspinDhccpParam::dspin_set( - flit, - dest, - DspinDhccpParam::CLEANUP_ACK_DEST); - - DspinDhccpParam::dspin_set( - flit, - r_cleanup_to_cc_send_set_index.read(), - DspinDhccpParam::CLEANUP_ACK_SET); - - DspinDhccpParam::dspin_set( - flit, - r_cleanup_to_cc_send_way_index.read(), - DspinDhccpParam::CLEANUP_ACK_WAY); - - DspinDhccpParam::dspin_set( - flit, - cleanup_ack_type, - DspinDhccpParam::FROM_MC_TYPE); - - p_dspin_out.eop = true; - p_dspin_out.write = true; - p_dspin_out.data = flit; - - break; - } - /////////////////////////////////// case CC_SEND_XRAM_RSP_INVAL_HEADER: @@ -8159,7 +8013,7 @@ DspinDhccpParam::dspin_set( flit, multi_inval_type, - DspinDhccpParam::FROM_MC_TYPE); - p_dspin_out.write = true; - p_dspin_out.data = flit; + DspinDhccpParam::M2P_TYPE); + p_dspin_m2p.write = true; + p_dspin_m2p.data = flit; break; } @@ -8173,7 +8027,7 @@ r_xram_rsp_to_cc_send_nline.read(), DspinDhccpParam::MULTI_INVAL_NLINE); - p_dspin_out.eop = true; - p_dspin_out.write = true; - p_dspin_out.data = flit; + p_dspin_m2p.eop = true; + p_dspin_m2p.write = true; + p_dspin_m2p.data = flit; break; } @@ -8197,7 +8051,7 @@ DspinDhccpParam::dspin_set( flit, 1ULL, - DspinDhccpParam::FROM_MC_BC); - p_dspin_out.write = true; - p_dspin_out.data = flit; + DspinDhccpParam::M2P_BC); + p_dspin_m2p.write = true; + p_dspin_m2p.data = flit; break; } @@ -8209,7 +8063,7 @@ r_xram_rsp_to_cc_send_nline.read(), DspinDhccpParam::BROADCAST_NLINE); - p_dspin_out.write = true; - p_dspin_out.eop = true; - p_dspin_out.data = flit; + p_dspin_m2p.write = true; + p_dspin_m2p.eop = true; + p_dspin_m2p.data = flit; break; } @@ -8221,7 +8075,7 @@ r_config_to_cc_send_nline.read(), DspinDhccpParam::BROADCAST_NLINE); - p_dspin_out.write = true; - p_dspin_out.eop = true; - p_dspin_out.data = flit; + p_dspin_m2p.write = true; + p_dspin_m2p.eop = true; + p_dspin_m2p.data = flit; break; } @@ -8233,7 +8087,7 @@ r_write_to_cc_send_nline.read(), DspinDhccpParam::BROADCAST_NLINE); - p_dspin_out.write = true; - p_dspin_out.eop = true; - p_dspin_out.data = flit; + p_dspin_m2p.write = true; + p_dspin_m2p.eop = true; + p_dspin_m2p.data = flit; break; } @@ -8245,7 +8099,7 @@ r_cas_to_cc_send_nline.read(), DspinDhccpParam::BROADCAST_NLINE); - p_dspin_out.write = true; - p_dspin_out.eop = true; - p_dspin_out.data = flit; + p_dspin_m2p.write = true; + p_dspin_m2p.eop = true; + p_dspin_m2p.data = flit; break; } @@ -8288,8 +8142,8 @@ flit, multi_updt_type, - DspinDhccpParam::FROM_MC_TYPE); - - p_dspin_out.write = true; - p_dspin_out.data = flit; + DspinDhccpParam::M2P_TYPE); + + p_dspin_m2p.write = true; + p_dspin_m2p.data = flit; break; @@ -8310,6 +8164,6 @@ DspinDhccpParam::MULTI_UPDT_NLINE); - p_dspin_out.write = true; - p_dspin_out.data = flit; + p_dspin_m2p.write = true; + p_dspin_m2p.data = flit; break; @@ -8337,7 +8191,7 @@ DspinDhccpParam::MULTI_UPDT_DATA); - p_dspin_out.write = true; - p_dspin_out.eop = (r_cc_send_cpt.read() == (r_write_to_cc_send_count.read()-1)); - p_dspin_out.data = flit; + p_dspin_m2p.write = true; + p_dspin_m2p.eop = (r_cc_send_cpt.read() == (r_write_to_cc_send_count.read()-1)); + p_dspin_m2p.data = flit; break; @@ -8381,8 +8235,8 @@ flit, multi_updt_type, - DspinDhccpParam::FROM_MC_TYPE); - - p_dspin_out.write = true; - p_dspin_out.data = flit; + DspinDhccpParam::M2P_TYPE); + + p_dspin_m2p.write = true; + p_dspin_m2p.data = flit; break; @@ -8403,6 +8257,6 @@ DspinDhccpParam::MULTI_UPDT_NLINE); - p_dspin_out.write = true; - p_dspin_out.data = flit; + p_dspin_m2p.write = true; + p_dspin_m2p.data = flit; break; @@ -8423,7 +8277,7 @@ DspinDhccpParam::MULTI_UPDT_DATA); - p_dspin_out.write = true; - p_dspin_out.eop = not r_cas_to_cc_send_is_long.read(); - p_dspin_out.data = flit; + p_dspin_m2p.write = true; + p_dspin_m2p.eop = not r_cas_to_cc_send_is_long.read(); + p_dspin_m2p.data = flit; break; @@ -8444,7 +8298,7 @@ DspinDhccpParam::MULTI_UPDT_DATA); - p_dspin_out.write = true; - p_dspin_out.eop = true; - p_dspin_out.data = flit; + p_dspin_m2p.write = true; + p_dspin_m2p.eop = true; + p_dspin_m2p.data = flit; break; @@ -8452,12 +8306,84 @@ } + //////////////////////////////////////////////////////////////////// + // p_dspin_clack port (CLEANUP FSM) + //////////////////////////////////////////////////////////////////// + + switch(r_cleanup_fsm.read()) + { + case CLEANUP_IDLE: + case CLEANUP_GET_NLINE: + case CLEANUP_DIR_REQ: + case CLEANUP_DIR_LOCK: + case CLEANUP_DIR_WRITE: + case CLEANUP_HEAP_REQ: + case CLEANUP_HEAP_LOCK: + case CLEANUP_HEAP_SEARCH: + case CLEANUP_HEAP_CLEAN: + case CLEANUP_HEAP_FREE: + case CLEANUP_IVT_LOCK: + case CLEANUP_IVT_DECREMENT: + case CLEANUP_IVT_CLEAR: + case CLEANUP_WRITE_RSP: + case CLEANUP_CONFIG_ACK: + p_dspin_clack.write = false; + p_dspin_clack.eop = false; + p_dspin_clack.data = 0; + + break; + + case CLEANUP_SEND_CLACK: + { + uint8_t cleanup_ack_type; + if(r_cleanup_inst.read()) + { + cleanup_ack_type = DspinDhccpParam::TYPE_CLACK_INST; + } + else + { + cleanup_ack_type = DspinDhccpParam::TYPE_CLACK_DATA; + } + + uint64_t flit = 0; + uint64_t dest = + r_cleanup_srcid.read() << + (DspinDhccpParam::SRCID_WIDTH - vci_param_int::S); + + DspinDhccpParam::dspin_set( + flit, + dest, + DspinDhccpParam::CLACK_DEST); + + DspinDhccpParam::dspin_set( + flit, + r_cleanup_nline.read() & 0xFFFF, + DspinDhccpParam::CLACK_SET); + + DspinDhccpParam::dspin_set( + flit, + r_cleanup_way_index.read(), + DspinDhccpParam::CLACK_WAY); + + DspinDhccpParam::dspin_set( + flit, + cleanup_ack_type, + DspinDhccpParam::CLACK_TYPE); + + p_dspin_clack.eop = true; + p_dspin_clack.write = true; + p_dspin_clack.data = flit; + } + break; + } + /////////////////////////////////////////////////////////////////// - // p_dspin_in port (CC_RECEIVE FSM) + // p_dspin_p2m port (CC_RECEIVE FSM) /////////////////////////////////////////////////////////////////// - p_dspin_in.read = false; + // switch(r_cc_receive_fsm.read()) { case CC_RECEIVE_IDLE: { + p_dspin_p2m.read = false; break; } @@ -8465,10 +8391,10 @@ case CC_RECEIVE_CLEANUP_EOP: { - p_dspin_in.read = m_cc_receive_to_cleanup_fifo.wok(); + p_dspin_p2m.read = m_cc_receive_to_cleanup_fifo.wok(); break; } case CC_RECEIVE_MULTI_ACK: { - p_dspin_in.read = m_cc_receive_to_multi_ack_fifo.wok(); + p_dspin_p2m.read = m_cc_receive_to_multi_ack_fifo.wok(); break; }