Changeset 472


Ignore:
Timestamp:
Jul 24, 2013, 3:06:05 PM (11 years ago)
Author:
alain
Message:

Fixing the IRQs wiring to support the "4c_1p_iob" mapping.

File:
1 edited

Legend:

Unmodified
Added
Removed

  • trunk/platforms/tsar_generic_iob/top.cpp

    r468 r472  
    66// This program is released under the GNU public license
    77///////////////////////////////////////////////////////////////////////////////
    8 // This file define a generic TSAR architecture using an IO network emulating
     8// This file define a generic TSAR architecture with an IO network emulating
    99// an external bus (i.e. Hypertransport) to access external peripherals:
    1010//
    11 // - boot rom (BROM)
    12 // - disk controller (BDEV)
    13 // - multi-channel network controller (MNIC)
    14 // - multi-channel chbuf dma controller (CDMA)
    15 // - multi-channel tty controller (MTTY)
    16 // - frame buffer controller (FBUF)
     11// - BROM : boot ROM
     12// - FBUF : Frame Buffer
     13// - MTTY : multi TTY (up to 15 channels)
     14// - MNIC : Network controller (up to 2 channels)
     15// - CDMA : Chained Buffer controller (up to 4 channels)
     16// - BDEV : Dlock Device controler (1 channel)
    1717//
    1818// The internal physical address space is 40 bits.
    1919//
    20 // It contains a 2D mesh of clusters communicating through 3 networks:
     20// It contains a 2D mesh of XMAX*YMAX clusters, and 3 networks:
    2121//
    2222// 1) the INT network supports Read/Write transactions
    … …  
    2525//    It supports also coherence transactions between L1 & L2 caches.
    2626// 3) the RAM network is emulating the 3D network between L2 caches
    27 //    and L3 caches, and is implemented as a 2D network between L2 caches,
    28 //    the two IO bridges and physical RAMs disributed in all clusters.
     27//    and L3 caches, and is implemented as a 2D mesh between the L2 caches,
     28//    the two IO bridges and the physical RAMs disributed in all clusters.
    2929//    (VCI ADDRESS = 40 bits / VCI DATA = 64 bits)
    3030// 4) the IOX network connects the two IO bridge components to the
    … …  
    3232//    (VCI ADDDRESS = 40 bits / VCI DATA width = 64 bits)
    3333//
    34 // The top-cell contains XMAX * YMAX clusters, plus a VGMN component
    35 // implementing the IO network, plus 6 external peripherals :
     34// The external peripherals IRQs are connected to the XICU component
     35// in cluster(0,0): therefore, the number of channels for the external
     36// peripherals (MTTY, MNIC, CDMA) is limited by the number of IRQ ports...
    3637//
     38// In all clusters, the IRQs are connected to XICU as follow:
     39// - IRQ_IN[0]  to IRQ_IN[3] not connected (reserved  for context switch)
     40// - IRQ_IN[4]  to IRQ_IN[7] are connected to 4 MDMA channels
     41//
     42// In external peripheral IRQs are connected in cluster(0,0) only:
     43// - IRQ_IN[8]  to IRQ_IN[9]  are connected to 2 NIC_RX channels.
     44// - IRQ_IN[10] to IRQ_IN[11] are connected to 2 NIC_TX channels.
     45// - IRQ_IN[12] to IRQ_IN[15] are connected to 4 CDMA channels
     46// - IRQ_IN[16] to IRQ_IN[30] are connected to 15 TTY channels
     47// - IRQ_IN[31]               is connected to BDEV
     48//
    3749// All clusters are identical, but cluster(0,0) and cluster(XMAX-1,YMAX-1)
    3850// contain an extra IO bridge component. These IOB0 & IOB1 components are
    3951// connected to the three networks (INT, RAM, IOX).
    4052// The number of clusters cannot be larger than 256.
    41 // The number of processors per cluster cannot be larger than 8.
     53// The number of processors per cluster cannot be larger than 4.
    4254//
    4355// - It uses two dspin_local_crossbar per cluster to implement the
    … …  
    5668// tsar_iob_cluster.* (with * = cpp, h, sd)
    5769//
    58 // In all clusters, the IRQs are connected to XICU as follow:
    59 // - IRQ_IN[0]  to IRQ_IN[3] are connected to 4 MDMA channels
    60 //
    61 // In cluster(0,0), the IRQs are connected to XICUs as follow:
    62 // - IRQ_IN[0]  to IRQ_IN[3]  are connected to 4 MDMA channels.
    63 // - IRQ_IN[4]  to IRQ_IN[5]  are connected to 2 NIC_RX channels.
    64 // - IRQ_IN[6]  to IRQ_IN[7]  are connected to 2 NIC_TX channels.
    65 // - IRQ_IN[8]  to IRQ_IN[11] are connected to 4 CDMA channels
    66 // - IRQ_IN[12] to IRQ_IN[30] are connected to 19 TTY channels
    67 // - IRQ_IN[31]               is connected to BDEV
    68 //
    6970// The main hardware parameters must be defined in the hard_config.h file :
    7071// - XMAX        : number of clusters in a row (power of 2)
    … …  
    449450           "The NB_DMA_CHANNELS parameter must be 4" );
    450451
    451    assert( (NB_TTY_CHANNELS < 20) and
    452            "The NB_TTY_CHANNELS parameter must be smaller than 20" );
     452   assert( (NB_TTY_CHANNELS < 16) and
     453           "The NB_TTY_CHANNELS parameter must be smaller than 16" );
    453454
    454455   assert( (NB_NIC_CHANNELS == 2) and
    … …  
    11151116
    11161117    // IRQ connexions (for cluster_iob0 only)
    1117     size_t mx = 12 + NB_TTY_CHANNELS;
     1118    size_t mx = 16 + NB_TTY_CHANNELS;
    11181119    for ( size_t n=0 ; n<32 ; n++ )
    11191120    {
    1120         if      ( n < 4  ) clusters[0][0]->p_irq[n]->bind    (signal_unused_irq[n]);
    1121         else if ( n < 6  ) clusters[0][0]->p_irq[n]->bind    (signal_irq_mnic_rx[n-4]);
    1122         else if ( n < 8  ) clusters[0][0]->p_irq[n]->bind    (signal_irq_mnic_tx[n-6]);
    1123         else if ( n < 12 ) clusters[0][0]->p_irq[n]->bind    (signal_irq_cdma[n-8]);
    1124         else if ( n < mx ) clusters[0][0]->p_irq[n]->bind    (signal_irq_mtty[n-12]);
     1121        if      ( n < 8  ) clusters[0][0]->p_irq[n]->bind    (signal_unused_irq[n]);
     1122        else if ( n < 10 ) clusters[0][0]->p_irq[n]->bind    (signal_irq_mnic_rx[n-8]);
     1123        else if ( n < 12 ) clusters[0][0]->p_irq[n]->bind    (signal_irq_mnic_tx[n-10]);
     1124        else if ( n < 16 ) clusters[0][0]->p_irq[n]->bind    (signal_irq_cdma[n-12]);
     1125        else if ( n < mx ) clusters[0][0]->p_irq[n]->bind    (signal_irq_mtty[n-16]);
    11251126        else if ( n < 31 ) clusters[0][0]->p_irq[n]->bind    (signal_unused_irq[n]);
    11261127        else               clusters[0][0]->p_irq[n]->bind    (signal_irq_bdev);
    … …  
    13321333   {
    13331334      // Monitor a specific address for L1 & L2 caches
    1334       clusters[1][1]->proc[0]->cache_monitor(0xC000039FC0ULL);
    1335       clusters[1][1]->memc->cache_monitor(   0xC000039FC0ULL);
     1335//    clusters[1][1]->proc[0]->cache_monitor(0xC000039FC0ULL);
     1336//    clusters[1][1]->memc->cache_monitor(   0xC000039FC0ULL);
    13361337
    13371338      if (debug_ok and (n > debug_from) and (n % debug_period == 0))
    … …  
    13411342
    13421343        // trace proc[debug_proc_id]
    1343         if ( debug_proc_id < XMAX*YMAX*NB_PROCS_MAX )
     1344//      if ( debug_proc_id < XMAX*YMAX*NB_PROCS_MAX )
     1345
     1346        for ( debug_proc_id = 0 ; debug_proc_id < 4 ; debug_proc_id++ )
    13441347        {
    13451348
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