Changeset 474 for branches/ODCCP/modules/vci_mem_cache
- Timestamp:
- Jul 25, 2013, 10:07:40 AM (11 years ago)
- File:
-
- 1 edited
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branches/ODCCP/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp
r460 r474 55 55 56 56 #define RANDOMIZE_CAS 1 57 58 #define ODCCP_NON_INCLUSIVE 1 59 57 60 58 61 namespace soclib { namespace caba { … … 273 276 { 274 277 "ALLOC_DIR_RESET", 278 "ALLOC_DIR_CONFIG", 275 279 "ALLOC_DIR_READ", 276 280 "ALLOC_DIR_WRITE", … … 290 294 const char *alloc_upt_fsm_str[] = 291 295 { 296 "ALLOC_UPT_CONFIG", 292 297 "ALLOC_UPT_WRITE", 293 298 "ALLOC_UPT_XRAM_RSP", … … 2494 2499 addr_t addr = (addr_t) m_cmd_read_addr_fifo.read(); 2495 2500 bool hit_read = m_trt.hit_read(m_nline[addr], index); 2501 #if ODCCP_NON_INCLUSIVE 2502 bool hit_write = (m_trt.hit_write(m_nline[addr], &index_write) or 2503 ((r_cleanup_to_ixr_cmd_nline.read() == m_nline[addr]) and r_cleanup_to_ixr_cmd_req.read())); 2504 #else 2496 2505 bool hit_write = m_trt.hit_write(m_nline[addr], &index_write); 2506 #endif 2497 2507 bool wok = !m_trt.full(index); 2498 2508 … … 3296 3306 size_t hit_index = 0; 3297 3307 size_t wok_index = 0; 3298 addr_t addr = (addr_t) r_write_address.read();3308 addr_t addr = (addr_t) r_write_address.read(); 3299 3309 bool hit_read = m_trt.hit_read(m_nline[addr], hit_index); 3310 #if ODCCP_NON_INCLUSIVE 3311 bool hit_write = (m_trt.hit_write(m_nline[addr]) or 3312 ((r_cleanup_to_ixr_cmd_nline.read() == m_nline[addr]) and r_cleanup_to_ixr_cmd_req.read())); 3313 #else 3300 3314 bool hit_write = m_trt.hit_write(m_nline[addr]); 3315 #endif 3301 3316 bool wok = !m_trt.full(wok_index); 3302 3317 … … 3863 3878 case IXR_RSP_ACK: // Aknowledge the VCI response for a PUT 3864 3879 { 3880 #if ODCCP_NON_INCLUSIVE 3881 if(p_vci_ixr.rspval.read()) 3882 { 3883 if (r_ixr_rsp_trt_index.read() == m_trt_lines) 3884 r_ixr_rsp_fsm = IXR_RSP_IDLE; 3885 else 3886 r_ixr_rsp_fsm = IXR_RSP_TRT_ERASE; 3887 } 3888 #else 3865 3889 if(p_vci_ixr.rspval.read()) r_ixr_rsp_fsm = IXR_RSP_TRT_ERASE; 3890 #endif 3866 3891 3867 3892 #if DEBUG_MEMC_IXR_RSP … … 4023 4048 DirectoryEntry victim(m_cache_directory.select(set, way)); 4024 4049 4050 #if ODCCP_NON_INCLUSIVE 4051 bool inval = (victim.count and victim.valid and victim.coherent) ; 4052 #else 4025 4053 bool inval = (victim.count and victim.valid) ; 4054 #endif 4026 4055 4027 4056 // copy the victim line in a local buffer … … 4048 4077 if(!r_xram_rsp_trt_buf.rerror) 4049 4078 { 4079 #if ODCCP_NON_INCLUSIVE 4080 r_xram_rsp_fsm = XRAM_RSP_INVAL_LOCK; 4081 #else 4050 4082 /*ODCCP*/ //if victim is no coherent and there is an inval no coherent pending we wait 4051 4083 if(!victim.coherent and r_xram_rsp_to_ixr_cmd_inval_ncc_pending.read()) … … 4057 4089 r_xram_rsp_fsm = XRAM_RSP_INVAL_LOCK; 4058 4090 } 4091 #endif 4059 4092 } 4060 4093 else … … 4208 4241 m_cache_directory.write(set, way, entry); 4209 4242 4210 // request an invalidat tion request in UPT for victim line4243 // request an invalidation request in UPT for victim line 4211 4244 if(r_xram_rsp_victim_inval.read()) 4212 4245 { … … 4254 4287 #endif 4255 4288 4289 #if ODCCP_NON_INCLUSIVE 4290 if (!r_xram_rsp_victim_dirty.read()) m_trt.erase(r_xram_rsp_trt_index.read()); 4291 4292 if (r_xram_rsp_victim_dirty.read()) r_xram_rsp_fsm = XRAM_RSP_TRT_DIRTY; 4293 else if(r_xram_rsp_trt_buf.proc_read) r_xram_rsp_fsm = XRAM_RSP_DIR_RSP; 4294 else if(r_xram_rsp_victim_inval.read()) r_xram_rsp_fsm = XRAM_RSP_INVAL; 4295 else r_xram_rsp_fsm = XRAM_RSP_IDLE; 4296 #else 4256 4297 // If the victim is not dirty and coherent or victim's count egal 0 , we don't need another XRAM put transaction, 4257 4298 // and we can erase the TRT entry … … 4259 4300 4260 4301 // Next state 4261 if(r_xram_rsp_victim_dirty.read() or (!r_xram_rsp_victim_coherent.read() and (r_xram_rsp_victim_count.read() == 1))) r_xram_rsp_fsm = XRAM_RSP_TRT_DIRTY; 4302 if(r_xram_rsp_victim_dirty.read() or (!r_xram_rsp_victim_coherent.read() and (r_xram_rsp_victim_count.read() == 1))) 4303 r_xram_rsp_fsm = XRAM_RSP_TRT_DIRTY; 4262 4304 else if(r_xram_rsp_trt_buf.proc_read) r_xram_rsp_fsm = XRAM_RSP_DIR_RSP; 4263 4305 else if(r_xram_rsp_victim_inval.read()) r_xram_rsp_fsm = XRAM_RSP_INVAL; 4264 4306 else r_xram_rsp_fsm = XRAM_RSP_IDLE; 4307 #endif 4265 4308 break; 4266 4309 } … … 4316 4359 r_xram_rsp_to_tgt_rsp_req = true; 4317 4360 4318 if(r_xram_rsp_victim_inval) r_xram_rsp_fsm = XRAM_RSP_INVAL; 4319 else if(r_xram_rsp_victim_dirty or (!r_xram_rsp_victim_coherent.read() and (r_xram_rsp_victim_count.read() == 1))) r_xram_rsp_fsm = XRAM_RSP_WRITE_DIRTY; 4320 else r_xram_rsp_fsm = XRAM_RSP_IDLE; 4361 #if ODCCP_NON_INCLUSIVE 4362 if (r_xram_rsp_victim_inval.read()) r_xram_rsp_fsm = XRAM_RSP_INVAL; 4363 else if(r_xram_rsp_victim_dirty.read()) r_xram_rsp_fsm = XRAM_RSP_WRITE_DIRTY; 4364 else r_xram_rsp_fsm = XRAM_RSP_IDLE; 4365 #else 4366 if(r_xram_rsp_victim_inval.read()) r_xram_rsp_fsm = XRAM_RSP_INVAL; 4367 else if(r_xram_rsp_victim_dirty.read() or 4368 (!r_xram_rsp_victim_coherent.read() and (r_xram_rsp_victim_count.read() == 1))) 4369 r_xram_rsp_fsm = XRAM_RSP_WRITE_DIRTY; 4370 else r_xram_rsp_fsm = XRAM_RSP_IDLE; 4371 #endif 4321 4372 4322 4373 #if DEBUG_MEMC_XRAM_RSP … … 4353 4404 r_xram_rsp_next_ptr = r_xram_rsp_victim_ptr.read(); 4354 4405 4355 if(r_xram_rsp_victim_dirty or (!r_xram_rsp_victim_coherent.read() and (r_xram_rsp_victim_count.read() == 1))) r_xram_rsp_fsm = XRAM_RSP_WRITE_DIRTY; 4406 #if ODCCP_NON_INCLUSIVE 4407 if(r_xram_rsp_victim_dirty.read()) r_xram_rsp_fsm = XRAM_RSP_WRITE_DIRTY; 4408 else if(not_last_multi_req) r_xram_rsp_fsm = XRAM_RSP_HEAP_REQ; 4409 else r_xram_rsp_fsm = XRAM_RSP_IDLE; 4410 #else 4411 if(r_xram_rsp_victim_dirty or (!r_xram_rsp_victim_coherent.read() and (r_xram_rsp_victim_count.read() == 1))) 4412 r_xram_rsp_fsm = XRAM_RSP_WRITE_DIRTY; 4356 4413 else if(not_last_multi_req) r_xram_rsp_fsm = XRAM_RSP_HEAP_REQ; 4357 4414 else r_xram_rsp_fsm = XRAM_RSP_IDLE; 4415 #endif 4358 4416 4359 4417 #if DEBUG_MEMC_XRAM_RSP … … 4380 4438 } 4381 4439 m_cpt_write_dirty++; 4382 4440 4441 #if (ODCCP_NON_INCLUSIVE == 0) 4383 4442 // if victim is no coherent, we dont request a ixr command 4384 4443 if( (!r_xram_rsp_victim_coherent.read()) and (r_xram_rsp_victim_count.read() == 1) ) … … 4389 4448 break; 4390 4449 } 4450 #endif 4391 4451 4392 4452 bool multi_req = !r_xram_rsp_victim_is_cnt.read() and r_xram_rsp_victim_inval.read(); … … 5415 5475 { 5416 5476 size_t index = 0; 5417 bool hit = m_trt.hit_write(r_cleanup_nline.read(), &index); // we save the index of the matching entry in TRT 5477 bool hit = m_trt.hit_write(r_cleanup_nline.read(), &index); // we save the index of the matching entry in TRT 5478 #if ODCCP_NON_INCLUSIVE 5479 if (!hit) 5480 { 5481 for(size_t i = 0; i < m_words; i++){ 5482 r_cleanup_to_ixr_cmd_data[i] = r_cleanup_data[i]; 5483 } 5484 r_cleanup_to_ixr_cmd_req = r_cleanup_contains_data.read(); 5485 r_cleanup_to_ixr_cmd_srcid = r_cleanup_srcid.read(); 5486 r_cleanup_to_ixr_cmd_trdid = m_trt_lines; 5487 r_cleanup_to_ixr_cmd_pktid = r_cleanup_pktid.read(); 5488 r_cleanup_to_ixr_cmd_nline = r_cleanup_nline.read(); 5489 r_cleanup_to_ixr_cmd_l1_dirty_ncc = true; 5490 r_cleanup_fsm = CLEANUP_SEND_CLACK; 5491 } 5492 else // wait until inval done 5493 { 5494 r_cleanup_fsm = CLEANUP_WAIT; 5495 } 5496 5497 #else 5418 5498 if (!hit) 5419 5499 { 5420 5500 std::cout << "assert on line " << r_cleanup_nline.read() << " | at cycle " << std::dec <<m_cpt_cycles << std::endl; 5421 for ( int i=0; i<4; i++) m_trt.print(i);5501 for (size_t i = 0; i < m_trt_lines; i++) m_trt.print(i); 5422 5502 } 5423 5503 assert (hit and "CLEANUP_IXR_REQ found no matching entry in TRT"); … … 5435 5515 r_cleanup_to_ixr_cmd_l1_dirty_ncc = r_cleanup_contains_data.read(); 5436 5516 r_cleanup_fsm = CLEANUP_SEND_CLACK; 5517 #endif 5518 5437 5519 #if DEBUG_MEMC_CLEANUP 5438 5520 if(m_debug)
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