Index: branches/ODCCP/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp =================================================================== --- branches/ODCCP/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp (revision 460) +++ branches/ODCCP/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp (revision 474) @@ -55,4 +55,7 @@ #define RANDOMIZE_CAS 1 + +#define ODCCP_NON_INCLUSIVE 1 + namespace soclib { namespace caba { @@ -273,4 +276,5 @@ { "ALLOC_DIR_RESET", + "ALLOC_DIR_CONFIG", "ALLOC_DIR_READ", "ALLOC_DIR_WRITE", @@ -290,4 +294,5 @@ const char *alloc_upt_fsm_str[] = { + "ALLOC_UPT_CONFIG", "ALLOC_UPT_WRITE", "ALLOC_UPT_XRAM_RSP", @@ -2494,5 +2499,10 @@ addr_t addr = (addr_t) m_cmd_read_addr_fifo.read(); bool hit_read = m_trt.hit_read(m_nline[addr], index); +#if ODCCP_NON_INCLUSIVE + bool hit_write = (m_trt.hit_write(m_nline[addr], &index_write) or + ((r_cleanup_to_ixr_cmd_nline.read() == m_nline[addr]) and r_cleanup_to_ixr_cmd_req.read())); +#else bool hit_write = m_trt.hit_write(m_nline[addr], &index_write); +#endif bool wok = !m_trt.full(index); @@ -3296,7 +3306,12 @@ size_t hit_index = 0; size_t wok_index = 0; - addr_t addr = (addr_t) r_write_address.read(); + addr_t addr = (addr_t) r_write_address.read(); bool hit_read = m_trt.hit_read(m_nline[addr], hit_index); +#if ODCCP_NON_INCLUSIVE + bool hit_write = (m_trt.hit_write(m_nline[addr]) or + ((r_cleanup_to_ixr_cmd_nline.read() == m_nline[addr]) and r_cleanup_to_ixr_cmd_req.read())); +#else bool hit_write = m_trt.hit_write(m_nline[addr]); +#endif bool wok = !m_trt.full(wok_index); @@ -3863,5 +3878,15 @@ case IXR_RSP_ACK: // Aknowledge the VCI response for a PUT { +#if ODCCP_NON_INCLUSIVE + if(p_vci_ixr.rspval.read()) + { + if (r_ixr_rsp_trt_index.read() == m_trt_lines) + r_ixr_rsp_fsm = IXR_RSP_IDLE; + else + r_ixr_rsp_fsm = IXR_RSP_TRT_ERASE; + } +#else if(p_vci_ixr.rspval.read()) r_ixr_rsp_fsm = IXR_RSP_TRT_ERASE; +#endif #if DEBUG_MEMC_IXR_RSP @@ -4023,5 +4048,9 @@ DirectoryEntry victim(m_cache_directory.select(set, way)); +#if ODCCP_NON_INCLUSIVE + bool inval = (victim.count and victim.valid and victim.coherent) ; +#else bool inval = (victim.count and victim.valid) ; +#endif // copy the victim line in a local buffer @@ -4048,4 +4077,7 @@ if(!r_xram_rsp_trt_buf.rerror) { +#if ODCCP_NON_INCLUSIVE + r_xram_rsp_fsm = XRAM_RSP_INVAL_LOCK; +#else /*ODCCP*/ //if victim is no coherent and there is an inval no coherent pending we wait if(!victim.coherent and r_xram_rsp_to_ixr_cmd_inval_ncc_pending.read()) @@ -4057,4 +4089,5 @@ r_xram_rsp_fsm = XRAM_RSP_INVAL_LOCK; } +#endif } else @@ -4208,5 +4241,5 @@ m_cache_directory.write(set, way, entry); - // request an invalidattion request in UPT for victim line + // request an invalidation request in UPT for victim line if(r_xram_rsp_victim_inval.read()) { @@ -4254,4 +4287,12 @@ #endif +#if ODCCP_NON_INCLUSIVE + if (!r_xram_rsp_victim_dirty.read()) m_trt.erase(r_xram_rsp_trt_index.read()); + + if (r_xram_rsp_victim_dirty.read()) r_xram_rsp_fsm = XRAM_RSP_TRT_DIRTY; + else if(r_xram_rsp_trt_buf.proc_read) r_xram_rsp_fsm = XRAM_RSP_DIR_RSP; + else if(r_xram_rsp_victim_inval.read()) r_xram_rsp_fsm = XRAM_RSP_INVAL; + else r_xram_rsp_fsm = XRAM_RSP_IDLE; +#else // If the victim is not dirty and coherent or victim's count egal 0 , we don't need another XRAM put transaction, // and we can erase the TRT entry @@ -4259,8 +4300,10 @@ // Next state - if(r_xram_rsp_victim_dirty.read() or (!r_xram_rsp_victim_coherent.read() and (r_xram_rsp_victim_count.read() == 1))) r_xram_rsp_fsm = XRAM_RSP_TRT_DIRTY; + if(r_xram_rsp_victim_dirty.read() or (!r_xram_rsp_victim_coherent.read() and (r_xram_rsp_victim_count.read() == 1))) + r_xram_rsp_fsm = XRAM_RSP_TRT_DIRTY; else if(r_xram_rsp_trt_buf.proc_read) r_xram_rsp_fsm = XRAM_RSP_DIR_RSP; else if(r_xram_rsp_victim_inval.read()) r_xram_rsp_fsm = XRAM_RSP_INVAL; else r_xram_rsp_fsm = XRAM_RSP_IDLE; +#endif break; } @@ -4316,7 +4359,15 @@ r_xram_rsp_to_tgt_rsp_req = true; - if(r_xram_rsp_victim_inval) r_xram_rsp_fsm = XRAM_RSP_INVAL; - else if(r_xram_rsp_victim_dirty or (!r_xram_rsp_victim_coherent.read() and (r_xram_rsp_victim_count.read() == 1))) r_xram_rsp_fsm = XRAM_RSP_WRITE_DIRTY; - else r_xram_rsp_fsm = XRAM_RSP_IDLE; +#if ODCCP_NON_INCLUSIVE + if (r_xram_rsp_victim_inval.read()) r_xram_rsp_fsm = XRAM_RSP_INVAL; + else if(r_xram_rsp_victim_dirty.read()) r_xram_rsp_fsm = XRAM_RSP_WRITE_DIRTY; + else r_xram_rsp_fsm = XRAM_RSP_IDLE; +#else + if(r_xram_rsp_victim_inval.read()) r_xram_rsp_fsm = XRAM_RSP_INVAL; + else if(r_xram_rsp_victim_dirty.read() or + (!r_xram_rsp_victim_coherent.read() and (r_xram_rsp_victim_count.read() == 1))) + r_xram_rsp_fsm = XRAM_RSP_WRITE_DIRTY; + else r_xram_rsp_fsm = XRAM_RSP_IDLE; +#endif #if DEBUG_MEMC_XRAM_RSP @@ -4353,7 +4404,14 @@ r_xram_rsp_next_ptr = r_xram_rsp_victim_ptr.read(); - if(r_xram_rsp_victim_dirty or (!r_xram_rsp_victim_coherent.read() and (r_xram_rsp_victim_count.read() == 1))) r_xram_rsp_fsm = XRAM_RSP_WRITE_DIRTY; +#if ODCCP_NON_INCLUSIVE + if(r_xram_rsp_victim_dirty.read()) r_xram_rsp_fsm = XRAM_RSP_WRITE_DIRTY; + else if(not_last_multi_req) r_xram_rsp_fsm = XRAM_RSP_HEAP_REQ; + else r_xram_rsp_fsm = XRAM_RSP_IDLE; +#else + if(r_xram_rsp_victim_dirty or (!r_xram_rsp_victim_coherent.read() and (r_xram_rsp_victim_count.read() == 1))) + r_xram_rsp_fsm = XRAM_RSP_WRITE_DIRTY; else if(not_last_multi_req) r_xram_rsp_fsm = XRAM_RSP_HEAP_REQ; else r_xram_rsp_fsm = XRAM_RSP_IDLE; +#endif #if DEBUG_MEMC_XRAM_RSP @@ -4380,5 +4438,6 @@ } m_cpt_write_dirty++; - + +#if (ODCCP_NON_INCLUSIVE == 0) // if victim is no coherent, we dont request a ixr command if( (!r_xram_rsp_victim_coherent.read()) and (r_xram_rsp_victim_count.read() == 1) ) @@ -4389,4 +4448,5 @@ break; } +#endif bool multi_req = !r_xram_rsp_victim_is_cnt.read() and r_xram_rsp_victim_inval.read(); @@ -5415,9 +5475,29 @@ { size_t index = 0; - bool hit = m_trt.hit_write(r_cleanup_nline.read(), &index); // we save the index of the matching entry in TRT + bool hit = m_trt.hit_write(r_cleanup_nline.read(), &index); // we save the index of the matching entry in TRT +#if ODCCP_NON_INCLUSIVE + if (!hit) + { + for(size_t i = 0; i < m_words; i++){ + r_cleanup_to_ixr_cmd_data[i] = r_cleanup_data[i]; + } + r_cleanup_to_ixr_cmd_req = r_cleanup_contains_data.read(); + r_cleanup_to_ixr_cmd_srcid = r_cleanup_srcid.read(); + r_cleanup_to_ixr_cmd_trdid = m_trt_lines; + r_cleanup_to_ixr_cmd_pktid = r_cleanup_pktid.read(); + r_cleanup_to_ixr_cmd_nline = r_cleanup_nline.read(); + r_cleanup_to_ixr_cmd_l1_dirty_ncc = true; + r_cleanup_fsm = CLEANUP_SEND_CLACK; + } + else // wait until inval done + { + r_cleanup_fsm = CLEANUP_WAIT; + } + +#else if (!hit) { std::cout << "assert on line " << r_cleanup_nline.read() << " | at cycle " << std::dec <