- Timestamp:
- Jul 29, 2013, 11:31:38 AM (11 years ago)
- Location:
- branches/ODCCP
- Files:
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- 10 edited
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branches/ODCCP/communication/dspin_dhccp_param
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/trunk/communication/dspin_dhccp_param merged eligible /branches/v5/communication/dspin_dhccp_param 377-467
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branches/ODCCP/communication/dspin_dhccp_param/caba/source/include/dspin_dhccp_param.h
r460 r479 66 66 67 67 /* 68 * Memory Cache to L1 cache command packets 69 * 70 * CLEANUP ACKNOWLEDGEMENT 71 * 72 * flit 1 73 * ---------------------------------------------------------------------------------------------- 74 * EOP:1 | DEST(14 bits) | X(3 bits) | SET_INDEX(16 bits) | WAY_INDEX(2 bits) | TYPE:0b10X | BC:0 75 * ---------------------------------------------------------------------------------------------- 76 * | X: 0 DATA | 77 * | 1 INST | 68 * M2P command packets 78 69 * 79 70 * MULTICAST UPDATE … … 81 72 * flit 1 82 73 * ---------------------------------------------------------------------------------------------- 83 * EOP:0 | DEST(14 bits) | X( 3 bits) | MEMC_ID(14 bits) | UPDT_INDEX(4 bits) | TYPE:0b00X| BC:074 * EOP:0 | DEST(14 bits) | X(4 bits) | MEMC_ID(14 bits) | UPDT_INDEX(4 bits) | TYPE:0b0X | BC:0 84 75 * ---------------------------------------------------------------------------------------------- 85 76 * | X: 0 DATA | … … 104 95 * flit 1 105 96 * ---------------------------------------------------------------------------------------------- 106 * EOP:0 | DEST(14 bits) | X( 3 bits) | MEMC_ID(14 bits) | UPDT_INDEX(4 bits) | TYPE:0b01X| BC:097 * EOP:0 | DEST(14 bits) | X(4 bits) | MEMC_ID(14 bits) | UPDT_INDEX(4 bits) | TYPE:0b1X | BC:0 107 98 * ---------------------------------------------------------------------------------------------- 108 99 * | X: 0 DATA | … … 125 116 * EOP:1 | X(5 bits) | NLINE (34 bits) 126 117 * ---------------------------------------------------------------------------------------------- 118 * 119 * M2P clack commands 120 * 121 * CLEANUP ACKNOWLEDGEMENT 122 * 123 * flit 1 124 * ---------------------------------------------------------------------------------------------- 125 * EOP:1 | DEST(14 bits) | X(5 bits) | SET_INDEX(16 bits) | WAY_INDEX(2 bits) | TYPE:0bX | BC:0 126 * ---------------------------------------------------------------------------------------------- 127 * | X: 0 CLACK | 128 * | DATA | 129 * | 1 CLACK | 130 * | INST | 131 * 127 132 */ 128 133 … … 140 145 public: 141 146 142 static const uint8_t from_memc_flit_width = 40; 143 static const uint8_t from_l1_flit_width = 33; 144 145 static const uint8_t UPDT_INDEX_WIDTH = 4; 146 static const uint8_t NLINE_WIDTH = 34; 147 static const uint8_t SRCID_WIDTH = 14; 148 static const uint8_t GLOBALID_WIDTH = 10; 149 static const uint8_t WORD_INDEX_WIDTH = 4; 150 static const uint8_t BE_WIDTH = 4; 151 static const uint8_t DATA_WIDTH = 32; 152 static const uint8_t SET_INDEX_WIDTH = 16; 153 static const uint8_t WAY_INDEX_WIDTH = 2; 154 static const uint8_t BROADCAST_BOX_WIDTH = 20; 155 static const uint8_t MC_TYPE_WIDTH = 3; 156 static const uint8_t L1_TYPE_WIDTH = 2; 157 158 static const uint8_t FROM_L1_TYPE_SHIFT = 1; 159 static const uint64_t FROM_L1_TYPE_MASK = ((1ULL<<L1_TYPE_WIDTH)-1); 160 static const uint8_t FROM_L1_EOP_SHIFT = 32; 161 static const uint64_t FROM_L1_EOP_MASK = 1; 162 static const uint8_t FROM_L1_BC_SHIFT = 0; 163 static const uint64_t FROM_L1_BC_MASK = 1; 147 static const uint8_t m2p_flit_width = 40; 148 static const uint8_t p2m_flit_width = 33; 149 static const uint8_t clack_flit_width = 40; 150 151 static const uint8_t UPDT_INDEX_WIDTH = 4; 152 static const uint8_t NLINE_WIDTH = 34; 153 static const uint8_t SRCID_WIDTH = 14; 154 static const uint8_t GLOBALID_WIDTH = 10; 155 static const uint8_t WORD_INDEX_WIDTH = 4; 156 static const uint8_t BE_WIDTH = 4; 157 static const uint8_t DATA_WIDTH = 32; 158 static const uint8_t SET_INDEX_WIDTH = 16; 159 static const uint8_t WAY_INDEX_WIDTH = 2; 160 static const uint8_t BROADCAST_BOX_WIDTH = 20; 161 static const uint8_t M2P_TYPE_WIDTH = 2; 162 static const uint8_t P2M_TYPE_WIDTH = 2; 163 static const uint8_t CLACK_TYPE_WIDTH = 1; 164 165 static const uint8_t P2M_TYPE_SHIFT = 1; 166 static const uint64_t P2M_TYPE_MASK = ((1ULL<<P2M_TYPE_WIDTH)-1); 167 static const uint8_t P2M_EOP_SHIFT = 32; 168 static const uint64_t P2M_EOP_MASK = 1; 169 static const uint8_t P2M_BC_SHIFT = 0; 170 static const uint64_t P2M_BC_MASK = 1; 164 171 165 172 static const uint8_t CLEANUP_NCC_SHIFT = 5; … … 183 190 static const uint64_t MULTI_ACK_UPDT_INDEX_MASK = ((1ULL<<UPDT_INDEX_WIDTH)-1); 184 191 185 static const uint8_t FROM_MC_TYPE_SHIFT= 1;186 static const uint64_t FROM_MC_TYPE_MASK = ((1ULL<<MC_TYPE_WIDTH)-1);187 static const uint8_t FROM_MC_EOP_SHIFT= 39;188 static const uint64_t FROM_MC_EOP_MASK= 1;189 static const uint8_t FROM_MC_BC_SHIFT= 0;190 static const uint64_t FROM_MC_BC_MASK= 1;192 static const uint8_t M2P_TYPE_SHIFT = 1; 193 static const uint64_t M2P_TYPE_MASK = ((1ULL<<M2P_TYPE_WIDTH)-1); 194 static const uint8_t M2P_EOP_SHIFT = 39; 195 static const uint64_t M2P_EOP_MASK = 1; 196 static const uint8_t M2P_BC_SHIFT = 0; 197 static const uint64_t M2P_BC_MASK = 1; 191 198 192 199 static const uint8_t MULTI_INVAL_DEST_SHIFT = 25; … … 214 221 static const uint64_t MULTI_UPDT_DATA_MASK = ((1ULL<<DATA_WIDTH)-1); 215 222 216 static const uint8_t CLEANUP_ACK_DEST_SHIFT = MULTI_INVAL_DEST_SHIFT;217 static const uint64_t CLEANUP_ACK_DEST_MASK = MULTI_INVAL_DEST_MASK;218 static const uint8_t CLEANUP_ACK_SET_SHIFT = 6;219 static const uint64_t CLEANUP_ACK_SET_MASK = ((1ULL<<SET_INDEX_WIDTH)-1);220 static const uint8_t CLEANUP_ACK_WAY_SHIFT = 4;221 static const uint64_t CLEANUP_ACK_WAY_MASK = ((1ULL<<WAY_INDEX_WIDTH)-1);222 223 223 static const uint8_t BROADCAST_BOX_SHIFT = 19; 224 224 static const uint64_t BROADCAST_BOX_MASK = ((1ULL<<BROADCAST_BOX_WIDTH)-1); … … 228 228 static const uint64_t BROADCAST_NLINE_MASK = MULTI_INVAL_NLINE_MASK; 229 229 230 static const uint8_t CLACK_TYPE_SHIFT = 1; 231 static const uint64_t CLACK_TYPE_MASK = ((1ULL<<CLACK_TYPE_WIDTH)-1); 232 static const uint8_t CLACK_EOP_SHIFT = 39; 233 static const uint64_t CLACK_EOP_MASK = 1; 234 static const uint8_t CLACK_BC_SHIFT = 0; 235 static const uint64_t CLACK_BC_MASK = 1; 236 static const uint8_t CLACK_DEST_SHIFT = 25; 237 static const uint64_t CLACK_DEST_MASK = ((1ULL<<SRCID_WIDTH)-1); 238 static const uint8_t CLACK_SET_SHIFT = 6; 239 static const uint64_t CLACK_SET_MASK = ((1ULL<<SET_INDEX_WIDTH)-1); 240 static const uint8_t CLACK_WAY_SHIFT = 4; 241 static const uint64_t CLACK_WAY_MASK = ((1ULL<<WAY_INDEX_WIDTH)-1); 242 230 243 /* 231 * L1 cache to Memory Cachecommand types244 * P2M command types 232 245 */ 233 246 enum … … 240 253 241 254 /* 242 * M emory Cache to L1 cachecommand types255 * M2P command types 243 256 */ 244 257 enum … … 249 262 TYPE_MULTI_INVAL = 2, 250 263 TYPE_MULTI_INVAL_DATA = TYPE_MULTI_INVAL, 251 TYPE_MULTI_INVAL_INST = 3, 252 TYPE_CLEANUP_ACK = 4, 253 TYPE_CLEANUP_ACK_DATA = TYPE_CLEANUP_ACK, 254 TYPE_CLEANUP_ACK_INST = 5 264 TYPE_MULTI_INVAL_INST = 3 255 265 }; 256 266 267 /* 268 * CLACK command types 269 */ 270 enum 271 { 272 TYPE_CLACK = 0, 273 TYPE_CLACK_DATA = TYPE_CLACK, 274 TYPE_CLACK_INST = 1 275 }; 276 257 277 enum flit_field_e 258 278 { 259 FROM_L1_TYPE,260 FROM_L1_EOP,261 FROM_L1_BC,279 P2M_TYPE, 280 P2M_EOP, 281 P2M_BC, 262 282 263 283 CLEANUP_NCC, … … 272 292 MULTI_ACK_UPDT_INDEX, 273 293 274 FROM_MC_TYPE,275 FROM_MC_EOP,276 FROM_MC_BC,294 M2P_TYPE, 295 M2P_EOP, 296 M2P_BC, 277 297 278 298 MULTI_INVAL_DEST, … … 289 309 MULTI_UPDT_DATA, 290 310 291 CLEANUP_ACK_DEST, 292 CLEANUP_ACK_SET, 293 CLEANUP_ACK_WAY, 311 CLACK_TYPE, 312 313 CLACK_DEST, 314 CLACK_SET, 315 CLACK_WAY, 294 316 295 317 BROADCAST_BOX, … … 302 324 switch(field) 303 325 { 304 GET_FIELD(flit, FROM_L1_TYPE);305 GET_FIELD(flit, FROM_L1_EOP);306 GET_FIELD(flit, FROM_L1_BC);326 GET_FIELD(flit,P2M_TYPE); 327 GET_FIELD(flit,P2M_EOP); 328 GET_FIELD(flit,P2M_BC); 307 329 GET_FIELD(flit,CLEANUP_NCC); 308 330 GET_FIELD(flit,CLEANUP_DEST); … … 314 336 GET_FIELD(flit,MULTI_ACK_DEST); 315 337 GET_FIELD(flit,MULTI_ACK_UPDT_INDEX); 316 GET_FIELD(flit, FROM_MC_TYPE);317 GET_FIELD(flit, FROM_MC_EOP);318 GET_FIELD(flit, FROM_MC_BC);338 GET_FIELD(flit,M2P_TYPE); 339 GET_FIELD(flit,M2P_EOP); 340 GET_FIELD(flit,M2P_BC); 319 341 GET_FIELD(flit,MULTI_INVAL_DEST); 320 342 GET_FIELD(flit,MULTI_INVAL_SRCID); … … 328 350 GET_FIELD(flit,MULTI_UPDT_BE); 329 351 GET_FIELD(flit,MULTI_UPDT_DATA); 330 GET_FIELD(flit,CLEANUP_ACK_DEST); 331 GET_FIELD(flit,CLEANUP_ACK_SET); 332 GET_FIELD(flit,CLEANUP_ACK_WAY); 352 GET_FIELD(flit,CLACK_TYPE); 353 GET_FIELD(flit,CLACK_DEST); 354 GET_FIELD(flit,CLACK_SET); 355 GET_FIELD(flit,CLACK_WAY); 333 356 GET_FIELD(flit,BROADCAST_BOX); 334 357 GET_FIELD(flit,BROADCAST_SRCID); … … 343 366 switch(field) 344 367 { 345 SET_FIELD(flit,value, FROM_L1_TYPE);346 SET_FIELD(flit,value, FROM_L1_EOP);347 SET_FIELD(flit,value, FROM_L1_BC);368 SET_FIELD(flit,value,P2M_TYPE); 369 SET_FIELD(flit,value,P2M_EOP); 370 SET_FIELD(flit,value,P2M_BC); 348 371 SET_FIELD(flit,value,CLEANUP_NCC); 349 372 SET_FIELD(flit,value,CLEANUP_DEST); … … 355 378 SET_FIELD(flit,value,MULTI_ACK_DEST); 356 379 SET_FIELD(flit,value,MULTI_ACK_UPDT_INDEX); 357 SET_FIELD(flit,value, FROM_MC_TYPE);358 SET_FIELD(flit,value, FROM_MC_EOP);359 SET_FIELD(flit,value, FROM_MC_BC);380 SET_FIELD(flit,value,M2P_TYPE); 381 SET_FIELD(flit,value,M2P_EOP); 382 SET_FIELD(flit,value,M2P_BC); 360 383 SET_FIELD(flit,value,MULTI_INVAL_DEST); 361 384 SET_FIELD(flit,value,MULTI_INVAL_SRCID); … … 369 392 SET_FIELD(flit,value,MULTI_UPDT_BE); 370 393 SET_FIELD(flit,value,MULTI_UPDT_DATA); 371 SET_FIELD(flit,value,CLEANUP_ACK_DEST); 372 SET_FIELD(flit,value,CLEANUP_ACK_SET); 373 SET_FIELD(flit,value,CLEANUP_ACK_WAY); 394 SET_FIELD(flit,value,CLACK_TYPE); 395 SET_FIELD(flit,value,CLACK_DEST); 396 SET_FIELD(flit,value,CLACK_SET); 397 SET_FIELD(flit,value,CLACK_WAY); 374 398 SET_FIELD(flit,value,BROADCAST_BOX); 375 399 SET_FIELD(flit,value,BROADCAST_SRCID); -
branches/ODCCP/modules/vci_cc_vcache_wrapper
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/trunk/modules/vci_cc_vcache_wrapper merged eligible /branches/v5/modules/vci_cc_vcache_wrapper 444-467
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branches/ODCCP/modules/vci_cc_vcache_wrapper/caba/metadata/vci_cc_vcache_wrapper.sd
r421 r479 37 37 ports = [ 38 38 Port('caba:vci_initiator', 'p_vci'), 39 Port('caba:dspin_input', 'p_dspin_ in',39 Port('caba:dspin_input', 'p_dspin_m2p', 40 40 dspin_data_size = parameter.Reference('dspin_in_width')), 41 Port('caba:dspin_output', 'p_dspin_ out',41 Port('caba:dspin_output', 'p_dspin_p2m', 42 42 dspin_data_size = parameter.Reference('dspin_out_width')), 43 Port('caba:dspin_input', 'p_dspin_clack', 44 dspin_data_size = parameter.Reference('dspin_in_width')), 43 45 Port('caba:bit_in','p_irq', parameter.Constant('n_irq')), 44 46 Port('caba:bit_in', 'p_resetn', auto = 'resetn'), -
branches/ODCCP/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h
r460 r479 89 89 // handling coherence requests 90 90 ICACHE_CC_CHECK, 91 ICACHE_CC_UPDT, 91 92 ICACHE_CC_INVAL, 92 ICACHE_CC_UPDT,93 ICACHE_CC_BROADCAST,94 ICACHE_CC_SEND_WAIT,95 93 }; 96 94 … … 141 139 // handling coherence requests 142 140 DCACHE_CC_CHECK, 141 DCACHE_CC_UPDT, 142 DCACHE_CC_INVAL, 143 143 DCACHE_CC_INVAL_DATA, 144 DCACHE_CC_INVAL,145 DCACHE_CC_UPDT,146 DCACHE_CC_BROADCAST,147 DCACHE_CC_SEND_WAIT,148 144 // handling TLB inval (after a coherence or XTN request) 149 145 DCACHE_INVAL_TLB_SCAN, … … 177 173 { 178 174 CC_RECEIVE_IDLE, 179 CC_RECEIVE_CLACK,180 175 CC_RECEIVE_BRDCAST_HEADER, 181 176 CC_RECEIVE_BRDCAST_NLINE, 182 CC_RECEIVE_INVAL_HEADER, 183 CC_RECEIVE_INVAL_NLINE, 184 CC_RECEIVE_UPDT_HEADER, 185 CC_RECEIVE_UPDT_NLINE, 186 CC_RECEIVE_UPDT_DATA, 177 CC_RECEIVE_INS_INVAL_HEADER, 178 CC_RECEIVE_INS_INVAL_NLINE, 179 CC_RECEIVE_INS_UPDT_HEADER, 180 CC_RECEIVE_INS_UPDT_NLINE, 181 CC_RECEIVE_INS_UPDT_DATA, 182 CC_RECEIVE_DATA_INVAL_HEADER, 183 CC_RECEIVE_DATA_INVAL_NLINE, 184 CC_RECEIVE_DATA_UPDT_HEADER, 185 CC_RECEIVE_DATA_UPDT_NLINE, 186 CC_RECEIVE_DATA_UPDT_DATA, 187 187 }; 188 188 … … 301 301 302 302 public: 303 sc_in<bool> p_clk; 304 sc_in<bool> p_resetn; 305 sc_in<bool> p_irq[iss_t::n_irq]; 306 soclib::caba::VciInitiator<vci_param> p_vci; 307 soclib::caba::DspinInput <dspin_in_width> p_dspin_in; 308 soclib::caba::DspinOutput<dspin_out_width> p_dspin_out; 303 sc_in<bool> p_clk; 304 sc_in<bool> p_resetn; 305 sc_in<bool> p_irq[iss_t::n_irq]; 306 soclib::caba::VciInitiator<vci_param> p_vci; 307 soclib::caba::DspinInput<dspin_in_width> p_dspin_m2p; 308 soclib::caba::DspinOutput<dspin_out_width> p_dspin_p2m; 309 soclib::caba::DspinInput<dspin_in_width> p_dspin_clack; 309 310 310 311 private: … … 387 388 sc_signal<bool> r_icache_cc_need_write; // activate the cache for writing 388 389 390 // coherence clack handling 391 sc_signal<bool> r_icache_clack_req; // clack request 392 sc_signal<size_t> r_icache_clack_way; // clack way 393 sc_signal<size_t> r_icache_clack_set; // clack set 394 389 395 // icache flush handling 390 396 sc_signal<size_t> r_icache_flush_count; // slot counter used for cache flush … … 459 465 sc_signal<size_t> r_dcache_cc_word; // word counter for cc update 460 466 sc_signal<bool> r_dcache_cc_need_write; // activate the cache for writing 467 468 // coherence clack handling 469 sc_signal<bool> r_dcache_clack_req; // clack request 470 sc_signal<size_t> r_dcache_clack_way; // clack way 471 sc_signal<size_t> r_dcache_clack_set; // clack set 461 472 462 473 // dcache flush handling … … 586 597 sc_signal<paddr_t> r_cc_receive_dcache_nline; // cache line physical address 587 598 599 /////////////////////////////////// 600 // DSPIN CLACK INTERFACE REGISTER 601 /////////////////////////////////// 602 sc_signal<bool> r_dspin_clack_req; 603 sc_signal<uint64_t> r_dspin_clack_flit; 604 588 605 ////////////////////////////////////////////////////////////////// 589 606 // processor, write buffer, caches , TLBs -
branches/ODCCP/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp
r460 r479 65 65 66 66 "ICACHE_CC_CHECK", 67 "ICACHE_CC_UPDT", 67 68 "ICACHE_CC_INVAL", 68 "ICACHE_CC_UPDT",69 "ICACHE_CC_BROADCAST",70 "ICACHE_CC_SEND_WAIT",71 69 }; 72 70 … … 116 114 117 115 "DCACHE_CC_CHECK", 116 "DCACHE_CC_UPDT", 117 "DCACHE_CC_INVAL", 118 118 "DCACHE_CC_INVAL_DATA", 119 "DCACHE_CC_INVAL",120 "DCACHE_CC_UPDT",121 "DCACHE_CC_BROADCAST",122 "DCACHE_CC_SEND_WAIT",123 119 124 120 "DCACHE_INVAL_TLB_SCAN", … … 167 163 const char *cc_receive_fsm_state_str[] = { 168 164 "CC_RECEIVE_IDLE", 169 "CC_RECEIVE_CLACK",170 165 "CC_RECEIVE_BRDCAST_HEADER", 171 166 "CC_RECEIVE_BRDCAST_NLINE", 172 "CC_RECEIVE_INVAL_HEADER", 173 "CC_RECEIVE_INVAL_NLINE", 174 "CC_RECEIVE_UPDT_HEADER", 175 "CC_RECEIVE_UPDT_NLINE", 176 "CC_RECEIVE_UPDT_DATA", 167 "CC_RECEIVE_INS_INVAL_HEADER", 168 "CC_RECEIVE_INS_INVAL_NLINE", 169 "CC_RECEIVE_INS_UPDT_HEADER", 170 "CC_RECEIVE_INS_UPDT_NLINE", 171 "CC_RECEIVE_INS_UPDT_DATA", 172 "CC_RECEIVE_DATA_INVAL_HEADER", 173 "CC_RECEIVE_DATA_INVAL_NLINE", 174 "CC_RECEIVE_DATA_UPDT_HEADER", 175 "CC_RECEIVE_DATA_UPDT_NLINE", 176 "CC_RECEIVE_DATA_UPDT_DATA", 177 177 }; 178 178 … … 224 224 p_resetn("p_resetn"), 225 225 p_vci("p_vci"), 226 p_dspin_in("p_dspin_in"), 227 p_dspin_out("p_dspin_out"), 226 p_dspin_m2p("p_dspin_m2p"), 227 p_dspin_p2m("p_dspin_p2m"), 228 p_dspin_clack("p_dspin_clack"), 228 229 229 230 m_cacheability_table( mtd.getCacheabilityTable() ), … … 792 793 r_icache_cc_send_req = false; 793 794 795 r_icache_clack_req = false; 796 794 797 // No pending write in pipeline 795 798 r_dcache_wbuf_req = false; … … 812 815 r_dcache_cc_send_req = false; 813 816 817 r_dcache_clack_req = false; 818 814 819 // No request from CC_RECEIVE FSM to ICACHE/DCACHE FSMs 815 820 r_cc_receive_icache_req = false; … … 826 831 r_icache_miss_inval = false; 827 832 r_dcache_miss_inval = false; 833 834 r_dspin_clack_req = false; 828 835 829 836 // No signalisation of errors … … 1077 1084 // 5/ uncacheable read miss => ICACHE_UNC_REQ 1078 1085 { 1086 // coherence clack interrupt 1087 if ( r_icache_clack_req.read() ) 1088 { 1089 r_icache_fsm = ICACHE_CC_CHECK; 1090 r_icache_fsm_save = r_icache_fsm.read(); 1091 break; 1092 } 1093 1079 1094 // coherence interrupt 1080 1095 if ( r_cc_receive_icache_req.read()) … … 1306 1321 // external coherence request are accepted in this state. 1307 1322 { 1323 // coherence clack interrupt 1324 if ( r_icache_clack_req.read() ) 1325 { 1326 r_icache_fsm = ICACHE_CC_CHECK; 1327 r_icache_fsm_save = r_icache_fsm.read(); 1328 break; 1329 } 1330 1308 1331 // coherence interrupt 1309 1332 if ( r_cc_receive_icache_req.read() ) … … 1350 1373 // A cleanup request is generated for each valid line 1351 1374 { 1375 // coherence clack interrupt 1376 if ( r_icache_clack_req.read() ) 1377 { 1378 r_icache_fsm = ICACHE_CC_CHECK; 1379 r_icache_fsm_save = r_icache_fsm.read(); 1380 break; 1381 } 1382 1352 1383 // coherence request (from CC_RECEIVE FSM) 1353 1384 if ( r_cc_receive_icache_req.read() ) … … 1548 1579 { 1549 1580 if (m_ireq.valid) m_cost_ins_miss_frz++; 1581 1582 // coherence clack interrupt 1583 if ( r_icache_clack_req.read() ) 1584 { 1585 r_icache_fsm = ICACHE_CC_CHECK; 1586 r_icache_fsm_save = r_icache_fsm.read(); 1587 break; 1588 } 1550 1589 1551 1590 // coherence interrupt … … 1638 1677 if (m_ireq.valid) m_cost_ins_miss_frz++; 1639 1678 1679 // coherence clack interrupt 1680 if ( r_icache_clack_req.read() ) 1681 { 1682 r_icache_fsm = ICACHE_CC_CHECK; 1683 r_icache_fsm_save = r_icache_fsm.read(); 1684 break; 1685 } 1686 1640 1687 // coherence interrupt 1641 1688 if ( r_cc_receive_icache_req.read() ) … … 1709 1756 if ( m_ireq.valid ) m_cost_ins_miss_frz++; 1710 1757 1758 // coherence clack interrupt 1759 if ( r_icache_clack_req.read() ) 1760 { 1761 r_icache_fsm = ICACHE_CC_CHECK; 1762 r_icache_fsm_save = r_icache_fsm.read(); 1763 break; 1764 } 1765 1711 1766 // coherence interrupt 1712 1767 if ( r_cc_receive_icache_req.read() ) … … 1780 1835 case ICACHE_UNC_WAIT: // waiting a response to an uncacheable read from VCI_RSP FSM 1781 1836 { 1837 // coherence clack interrupt 1838 if ( r_icache_clack_req.read() ) 1839 { 1840 r_icache_fsm = ICACHE_CC_CHECK; 1841 r_icache_fsm_save = r_icache_fsm.read(); 1842 break; 1843 } 1844 1782 1845 // coherence interrupt 1783 1846 if ( r_cc_receive_icache_req.read() ) … … 1820 1883 paddr_t mask = ~((m_icache_words<<2)-1); 1821 1884 1822 if (r_cc_receive_icache_type.read() == CC_TYPE_CLACK) 1823 // We switch the directory slot to EMPTY state 1824 // and reset r_icache_miss_clack if the cleanup ack 1825 // is matching a pending miss 1826 { 1827 1828 if ( m_ireq.valid ) m_cost_ins_miss_frz++; 1829 1830 #ifdef INSTRUMENTATION 1831 m_cpt_icache_dir_write++; 1832 #endif 1833 r_icache.write_dir( 0, 1834 r_cc_receive_icache_way.read(), 1835 r_cc_receive_icache_set.read(), 1836 CACHE_SLOT_STATE_EMPTY); 1837 1838 if ( (r_icache_miss_set.read() == r_cc_receive_icache_set.read()) and 1839 (r_icache_miss_way.read() == r_cc_receive_icache_way.read()) ) 1840 r_icache_miss_clack = false; 1841 1842 r_icache_fsm = r_icache_fsm_save.read() ; 1843 r_cc_receive_icache_req = false; 1844 1845 #if DEBUG_ICACHE 1846 if ( m_debug_activated ) 1847 { 1848 std::cout << " <PROC " << name() 1849 << " ICACHE_CC_CHECK> CC_TYPE_CLACK slot returns to empty state" 1850 << " set = " << r_cc_receive_icache_set.read() 1851 << " / way = " << r_cc_receive_icache_way.read() << std::endl; 1852 } 1853 #endif 1854 } 1855 else if( ((r_icache_fsm_save.read() == ICACHE_MISS_SELECT) or 1856 (r_icache_fsm_save.read() == ICACHE_MISS_WAIT) or 1857 (r_icache_fsm_save.read() == ICACHE_MISS_DIR_UPDT)) and 1858 ((r_icache_vci_paddr.read() & mask) == (paddr & mask)) ) // matching 1885 1886 // Match between MISS address and CC address 1887 // note: In the same cycle we can handle a CLACK and a MISS match 1888 // because the CLACK access the directory but the MISS match dont. 1889 if (r_cc_receive_icache_req.read() and 1890 ((r_icache_fsm_save.read() == ICACHE_MISS_SELECT ) or 1891 (r_icache_fsm_save.read() == ICACHE_MISS_WAIT ) or 1892 (r_icache_fsm_save.read() == ICACHE_MISS_DIR_UPDT)) and 1893 ((r_icache_vci_paddr.read() & mask) == (paddr & mask)) ) // matching 1859 1894 { 1860 1895 // signaling the matching … … 1867 1902 r_icache_fsm = ICACHE_CC_UPDT; 1868 1903 r_icache_cc_word = r_cc_receive_word_idx.read(); 1904 1869 1905 // just pop the fifo , don't write in icache 1870 1906 r_icache_cc_need_write = false; … … 1885 1921 #endif 1886 1922 } 1887 else // no match 1888 { 1889 int state = 0; 1890 size_t way = 0; 1891 size_t set = 0; 1892 size_t word = 0; 1923 1924 // CLACK handler 1925 // We switch the directory slot to EMPTY state 1926 // and reset r_icache_miss_clack if the cleanup ack 1927 // is matching a pending miss. 1928 if ( r_icache_clack_req.read() ) 1929 { 1930 1931 if ( m_ireq.valid ) m_cost_ins_miss_frz++; 1893 1932 1894 1933 #ifdef INSTRUMENTATION 1895 m_cpt_icache_dir_read++; 1896 #endif 1897 r_icache.read_dir(paddr, 1898 &state, 1899 &way, 1900 &set, 1901 &word); 1902 1903 r_icache_cc_way = way; 1904 r_icache_cc_set = set; 1905 1906 if ( state == CACHE_SLOT_STATE_VALID_CC) // hit 1907 { 1908 // need to update the cache state 1909 r_icache_cc_need_write = true; 1910 if (r_cc_receive_icache_type.read() == CC_TYPE_UPDT) // hit update 1911 { 1912 r_icache_fsm = ICACHE_CC_UPDT; 1913 r_icache_cc_word = r_cc_receive_word_idx.read(); 1914 } 1915 else if (r_cc_receive_icache_type.read() == CC_TYPE_INVAL) // hit inval 1916 { 1917 r_icache_fsm = ICACHE_CC_INVAL; 1918 } 1919 else if (r_cc_receive_icache_type.read() == CC_TYPE_BRDCAST) // hit broadcast 1920 { 1921 r_icache_fsm = ICACHE_CC_BROADCAST; 1922 } 1923 } 1924 else // miss 1925 { 1926 // multicast acknowledgement required in case of update 1927 if(r_cc_receive_icache_type.read() == CC_TYPE_UPDT) 1928 { 1929 r_icache_fsm = ICACHE_CC_UPDT; 1930 r_icache_cc_word = r_cc_receive_word_idx.read(); 1931 // just pop the fifo , don't write in icache 1932 r_icache_cc_need_write = false; 1933 } 1934 else // No response needed 1935 { 1936 r_cc_receive_icache_req = false; 1937 r_icache_fsm = r_icache_fsm_save.read(); 1938 } 1939 } 1940 } 1941 break; 1942 } 1943 ///////////////////// 1944 case ICACHE_CC_INVAL: // hit inval : switch slot to EMPTY state 1945 { 1934 m_cpt_icache_dir_write++; 1935 #endif 1936 r_icache.write_dir( 0, 1937 r_icache_clack_way.read(), 1938 r_icache_clack_set.read(), 1939 CACHE_SLOT_STATE_EMPTY); 1940 1941 if ( (r_icache_miss_set.read() == r_icache_clack_set.read()) and 1942 (r_icache_miss_way.read() == r_icache_clack_way.read()) ) 1943 { 1944 r_icache_miss_clack = false; 1945 } 1946 1947 r_icache_clack_req = false; 1948 1949 // return to cc_save state if no pending CC request 1950 if ( not r_cc_receive_icache_req.read() ) 1951 r_icache_fsm = r_icache_fsm_save.read(); 1946 1952 1947 1953 #if DEBUG_ICACHE … … 1949 1955 { 1950 1956 std::cout << " <PROC " << name() 1951 << " ICACHE_//CC_INVAL>slot returns to empty state"1952 << " set = " << r_icache_cc_set.read()1953 << " / way = " << r_icache_cc_way.read() << std::endl;1957 << " ICACHE_CC_CHECK> CC_TYPE_CLACK slot returns to empty state" 1958 << " set = " << r_icache_clack_set.read() 1959 << " / way = " << r_icache_clack_way.read() << std::endl; 1954 1960 } 1955 1961 #endif 1962 1963 break; 1964 } 1965 1966 // wait if pending request to CC_SEND. This way if there are pending 1967 // CLACK they can be treated in this state and then a deadlock 1968 // situation is avoided 1969 if ( r_icache_cc_send_req.read() ) break; 1970 1971 // CC request handler 1972 1973 int state = 0; 1974 size_t way = 0; 1975 size_t set = 0; 1976 size_t word = 0; 1956 1977 1957 1978 #ifdef INSTRUMENTATION 1958 1979 m_cpt_icache_dir_read++; 1959 1980 #endif 1960 1961 if (r_icache_cc_need_write.read()) 1962 { 1963 r_icache.write_dir( 0, 1964 r_icache_cc_way.read(), 1965 r_icache_cc_set.read(), 1966 CACHE_SLOT_STATE_EMPTY ); 1967 // no need to write in the cache anymore 1981 r_icache.read_dir(paddr, 1982 &state, 1983 &way, 1984 &set, 1985 &word); 1986 1987 r_icache_cc_way = way; 1988 r_icache_cc_set = set; 1989 1990 if ( state == CACHE_SLOT_STATE_VALID_CC) // hit 1991 { 1992 // need to update the cache state 1993 if (r_cc_receive_icache_type.read() == CC_TYPE_UPDT) // hit update 1994 { 1995 r_icache_cc_need_write = true; 1996 r_icache_fsm = ICACHE_CC_UPDT; 1997 r_icache_cc_word = r_cc_receive_word_idx.read(); 1998 } 1999 else if ( r_cc_receive_icache_type.read() == CC_TYPE_INVAL ) // hit inval 2000 { 2001 r_icache_fsm = ICACHE_CC_INVAL; 2002 } 2003 } 2004 else // miss 2005 { 2006 // multicast acknowledgement required in case of update 2007 if(r_cc_receive_icache_type.read() == CC_TYPE_UPDT) 2008 { 2009 r_icache_fsm = ICACHE_CC_UPDT; 2010 r_icache_cc_word = r_cc_receive_word_idx.read(); 2011 2012 // just pop the fifo , don't write in icache 1968 2013 r_icache_cc_need_write = false; 1969 2014 } 1970 // multicast acknowledgement 1971 // send a request to cc_send_fsm 1972 if(not r_icache_cc_send_req.read()) // cc_send is available 1973 { 1974 // coherence request completed 1975 r_cc_receive_icache_req = false; 1976 // request multicast acknowledgement 1977 r_icache_cc_send_req = true; 1978 r_icache_cc_send_nline = r_cc_receive_icache_nline.read(); 1979 r_icache_cc_send_updt_tab_idx = r_cc_receive_icache_updt_tab_idx.read(); 1980 r_icache_cc_send_type = CC_TYPE_MULTI_ACK; 1981 1982 r_icache_fsm = r_icache_fsm_save.read(); 1983 } 1984 //else wait for previous cc_send request to be sent 2015 else // No response needed 2016 { 2017 r_cc_receive_icache_req = false; 2018 r_icache_fsm = r_icache_fsm_save.read(); 2019 } 2020 } 2021 break; 2022 } 2023 ///////////////////// 2024 case ICACHE_CC_INVAL: // hit inval : switch slot to ZOMBI state 2025 { 2026 assert (not r_icache_cc_send_req.read() && 2027 "ERROR in ICACHE_CC_INVAL: the r_icache_cc_send_req " 2028 "must not be set"); 2029 2030 #ifdef INSTRUMENTATION 2031 m_cpt_icache_dir_read++; 2032 #endif 2033 2034 // Switch slot state to ZOMBI and send CLEANUP command 2035 r_icache.write_dir( 0, 2036 r_icache_cc_way.read(), 2037 r_icache_cc_set.read(), 2038 CACHE_SLOT_STATE_ZOMBI ); 2039 2040 // coherence request completed 2041 r_icache_cc_send_req = true; 2042 r_icache_cc_send_nline = r_cc_receive_icache_nline.read(); 2043 r_icache_cc_send_way = r_icache_cc_way.read(); 2044 r_icache_cc_send_type = CC_TYPE_CLEANUP; 2045 2046 r_icache_fsm = r_icache_fsm_save.read(); 2047 2048 #if DEBUG_ICACHE 2049 if ( m_debug_activated ) 2050 { 2051 std::cout << " <PROC " << name() 2052 << " ICACHE_CC_INVAL> slot returns to ZOMBI state" 2053 << " set = " << r_icache_cc_set.read() 2054 << " / way = " << r_icache_cc_way.read() << std::endl; 2055 } 2056 #endif 2057 1985 2058 break; 1986 2059 } … … 1988 2061 case ICACHE_CC_UPDT: // hit update : write one word per cycle 1989 2062 { 2063 assert (not r_icache_cc_send_req.read() && 2064 "ERROR in ICACHE_CC_UPDT: the r_icache_cc_send_req " 2065 "must not be set"); 2066 2067 if ( not r_cc_receive_updt_fifo_be.rok() ) break; 2068 2069 2070 size_t word = r_icache_cc_word.read(); 2071 size_t way = r_icache_cc_way.read(); 2072 size_t set = r_icache_cc_set.read(); 2073 2074 if (r_icache_cc_need_write.read()) 2075 { 2076 r_icache.write( way, 2077 set, 2078 word, 2079 r_cc_receive_updt_fifo_data.read(), 2080 r_cc_receive_updt_fifo_be.read() ); 2081 2082 r_icache_cc_word = word+1; 2083 2084 #ifdef INSTRUMENTATION 2085 m_cpt_icache_data_write++; 2086 #endif 1990 2087 1991 2088 #if DEBUG_ICACHE … … 1999 2096 } 2000 2097 #endif 2001 2002 #ifdef INSTRUMENTATION 2003 m_cpt_icache_data_write++; 2004 #endif 2005 size_t word = r_icache_cc_word.read(); 2006 size_t way = r_icache_cc_way.read(); 2007 size_t set = r_icache_cc_set.read(); 2008 2009 if (r_cc_receive_updt_fifo_be.rok()) 2010 { 2011 if (r_icache_cc_need_write.read()) 2012 { 2013 r_icache.write( way, 2014 set, 2015 word, 2016 r_cc_receive_updt_fifo_data.read(), 2017 r_cc_receive_updt_fifo_be.read() ); 2018 2019 r_icache_cc_word = word+1; 2020 } 2021 if ( r_cc_receive_updt_fifo_eop.read() ) // last word 2022 { 2098 } 2099 2100 if ( r_cc_receive_updt_fifo_eop.read() ) // last word 2101 { 2023 2102 // no need to write in the cache anymore 2024 r_icache_cc_need_write = false; 2025 // wait to send a request to cc_send_fsm 2026 if(not r_icache_cc_send_req.read()) // cc_send is available 2027 { 2028 //consume last flit 2029 cc_receive_updt_fifo_get = true; 2030 // coherence request completed 2031 r_cc_receive_icache_req = false; 2032 // request multicast acknowledgement 2033 r_icache_cc_send_req = true; 2034 r_icache_cc_send_nline = r_cc_receive_icache_nline.read(); 2035 r_icache_cc_send_updt_tab_idx = r_cc_receive_icache_updt_tab_idx.read(); 2036 r_icache_cc_send_type = CC_TYPE_MULTI_ACK; 2037 2038 r_icache_fsm = r_icache_fsm_save.read(); 2039 } 2040 } 2041 else 2042 { 2043 //consume fifo if not eop 2044 cc_receive_updt_fifo_get = true; 2045 } 2046 } 2103 r_icache_cc_need_write = false; 2104 2105 // coherence request completed 2106 r_cc_receive_icache_req = false; 2107 2108 // request multicast acknowledgement 2109 r_icache_cc_send_req = true; 2110 r_icache_cc_send_nline = r_cc_receive_icache_nline.read(); 2111 r_icache_cc_send_updt_tab_idx = r_cc_receive_icache_updt_tab_idx.read(); 2112 r_icache_cc_send_type = CC_TYPE_MULTI_ACK; 2113 2114 r_icache_fsm = r_icache_fsm_save.read(); 2115 } 2116 //consume fifo if not eop 2117 cc_receive_updt_fifo_get = true; 2118 2047 2119 break; 2048 2120 } 2049 ///////////////////////// 2050 case ICACHE_CC_BROADCAST: // hit broadcast : switch slot to ZOMBI state 2051 // and request a cleanup 2052 { 2053 2054 #if DEBUG_ICACHE 2055 if ( m_debug_activated ) 2056 { 2057 std::cout << " <PROC " << name() 2058 << " ICACHE_CC_BROADCAST > Slot goes to zombi state " 2059 << " set = " << r_icache_cc_set.read() 2060 << " / way = " << r_icache_cc_way.read() << std::endl; 2061 } 2062 #endif 2063 2064 #ifdef INSTRUMENTATION 2065 m_cpt_icache_dir_write++; 2066 #endif 2067 if (r_icache_cc_need_write.read()) 2068 { 2069 r_icache.write_dir( r_icache_cc_way.read(), 2070 r_icache_cc_set.read(), 2071 CACHE_SLOT_STATE_ZOMBI ); 2072 // no need to write in the cache anymore 2073 r_icache_cc_need_write = false; 2074 } 2075 2076 // cleanup 2077 // send a request to cc_send_fsm 2078 if(not r_icache_cc_send_req.read()) // cc_send is available 2079 { 2080 // coherence request completed 2081 r_cc_receive_icache_req = false; 2082 // request cleanup 2083 r_icache_cc_send_req = true; 2084 r_icache_cc_send_nline = r_cc_receive_icache_nline.read(); 2085 r_icache_cc_send_way = r_icache_cc_way.read(); 2086 r_icache_cc_send_type = CC_TYPE_CLEANUP; 2087 2088 r_icache_fsm = r_icache_fsm_save.read(); 2089 } 2090 //else wait for previous cc_send request to be sent 2091 break; 2092 } 2121 2093 2122 } // end switch r_icache_fsm 2094 2123 … … 2371 2400 } 2372 2401 2402 // coherence clack request (from DSPIN CLACK) 2403 else if ( r_dcache_clack_req.read() ) 2404 { 2405 r_dcache_fsm = DCACHE_CC_CHECK; 2406 r_dcache_fsm_cc_save = r_dcache_fsm.read(); 2407 } 2373 2408 // coherence request (from CC_RECEIVE FSM) 2374 2409 else if ( r_cc_receive_dcache_req.read() ) … … 3067 3102 case DCACHE_TLB_PTE1_GET: // try to read a PT1 entry in dcache 3068 3103 { 3104 // coherence clack request (from DSPIN CLACK) 3105 if ( r_dcache_clack_req.read() ) 3106 { 3107 r_dcache_fsm = DCACHE_CC_CHECK; 3108 r_dcache_fsm_cc_save = r_dcache_fsm.read(); 3109 break; 3110 } 3111 3069 3112 // coherence request (from CC_RECEIVE FSM) 3070 3113 if ( r_cc_receive_dcache_req.read() ) … … 3366 3409 case DCACHE_TLB_PTE2_GET: // Try to get a PTE2 (64 bits) in the dcache 3367 3410 { 3411 // coherence clack request (from DSPIN CLACK) 3412 if ( r_dcache_clack_req.read() ) 3413 { 3414 r_dcache_fsm = DCACHE_CC_CHECK; 3415 r_dcache_fsm_cc_save = r_dcache_fsm.read(); 3416 break; 3417 } 3418 3368 3419 // coherence request (from CC_RECEIVE FSM) 3369 3420 if ( r_cc_receive_dcache_req.read() ) … … 3665 3716 3666 3717 { 3718 // coherence clack request (from DSPIN CLACK) 3719 if ( r_dcache_clack_req.read() ) 3720 { 3721 r_dcache_fsm = DCACHE_CC_CHECK; 3722 r_dcache_fsm_cc_save = r_dcache_fsm.read(); 3723 break; 3724 } 3725 3667 3726 // coherence request (from CC_RECEIVE FSM) 3668 3727 if ( r_cc_receive_dcache_req.read() ) … … 3736 3795 // as there is a risk of dead-lock 3737 3796 { 3797 // coherence clack request (from DSPIN CLACK) 3798 if ( r_dcache_clack_req.read() ) 3799 { 3800 r_dcache_fsm = DCACHE_CC_CHECK; 3801 r_dcache_fsm_cc_save = r_dcache_fsm.read(); 3802 break; 3803 } 3804 3738 3805 // coherence request (from CC_RECEIVE FSM) 3739 3806 if ( r_cc_receive_dcache_req.read() ) … … 3741 3808 r_dcache_fsm = DCACHE_CC_CHECK; 3742 3809 r_dcache_fsm_cc_save = r_dcache_fsm.read(); 3810 break; 3743 3811 } 3744 3812 … … 3757 3825 // and because it can exist a simultaneous ITLB miss 3758 3826 { 3827 // coherence clack request (from DSPIN CLACK) 3828 if ( r_dcache_clack_req.read() ) 3829 { 3830 r_dcache_fsm = DCACHE_CC_CHECK; 3831 r_dcache_fsm_cc_save = r_dcache_fsm.read(); 3832 break; 3833 } 3834 3759 3835 // coherence request (from CC_RECEIVE FSM) 3760 3836 if ( r_cc_receive_dcache_req.read() ) … … 3792 3868 // returns to IDLE and flush TLBs when last slot 3793 3869 { 3870 // coherence clack request (from DSPIN CLACK) 3871 if ( r_dcache_clack_req.read() ) 3872 { 3873 r_dcache_fsm = DCACHE_CC_CHECK; 3874 r_dcache_fsm_cc_save = r_dcache_fsm.read(); 3875 break; 3876 } 3877 3794 3878 // coherence request (from CC_RECEIVE FSM) 3795 3879 if ( r_cc_receive_dcache_req.read() ) … … 3895 3979 r_dcache_xtn_flush_addr_data = r_dcache_xtn_flush_addr_data.read() + 4; 3896 3980 3897 cleanup_data_updt_fifo_dcache_get = false;3898 3981 cleanup_data_updt_fifo_dcache_put = true; 3899 3982 cleanup_data_updt_fifo_dcache_data = rdata; … … 4158 4241 r_dcache_xtn_data_addr = r_dcache_xtn_data_addr.read() + 4; 4159 4242 4160 cleanup_data_updt_fifo_dcache_get = false;4161 4243 cleanup_data_updt_fifo_dcache_put = true; 4162 4244 cleanup_data_updt_fifo_dcache_data = rdata; … … 4193 4275 { 4194 4276 if ( m_dreq.valid) m_cost_data_miss_frz++; 4277 4278 // coherence clack request (from DSPIN CLACK) 4279 if ( r_dcache_clack_req.read() ) 4280 { 4281 r_dcache_fsm = DCACHE_CC_CHECK; 4282 r_dcache_fsm_cc_save = r_dcache_fsm.read(); 4283 break; 4284 } 4195 4285 4196 4286 // coherence request (from CC_RECEIVE FSM) … … 4247 4337 r_dcache_fsm = DCACHE_MISS_DATA; 4248 4338 m_cpt_data_cleanup_dirty ++; 4249 4339 4250 4340 /*STATS DIRTY*/ 4251 4341 for (size_t w = 0; w < m_dcache_words; w++) … … 4294 4384 size_t set; 4295 4385 size_t word; 4296 4297 4386 r_dcache.read_neutral(r_dcache_miss_data_addr, 4298 4387 &rdata, … … 4300 4389 &set, 4301 4390 &word); 4391 4302 4392 if(r_cc_send_data_fifo.wok()) 4303 4393 { 4304 4394 r_dcache_miss_data_addr = r_dcache_miss_data_addr.read() + 4; 4305 4395 4306 cleanup_data_updt_fifo_dcache_get = false;4307 4396 cleanup_data_updt_fifo_dcache_put = true; 4308 4397 cleanup_data_updt_fifo_dcache_data = rdata; … … 4314 4403 r_dcache_fsm = DCACHE_MISS_CLEAN; 4315 4404 } 4405 #if DEBUG_DCACHE 4406 if ( m_debug_activated ) 4407 { 4408 std::cout << " <PROC " << name() 4409 << " DCACHE_MISS_DATA>:" << std::hex 4410 << " / DATA = " << rdata 4411 << " / WORD = " << word 4412 << " / PADDR = " << std::hex << r_dcache_miss_data_addr.read() << std::endl; 4413 } 4414 #endif 4316 4415 } 4317 4416 break; … … 4370 4469 { 4371 4470 if ( m_dreq.valid) m_cost_data_miss_frz++; 4471 4472 // coherence clack request (from DSPIN CLACK) 4473 if ( r_dcache_clack_req.read() ) 4474 { 4475 r_dcache_fsm = DCACHE_CC_CHECK; 4476 r_dcache_fsm_cc_save = r_dcache_fsm.read(); 4477 break; 4478 } 4372 4479 4373 4480 // coherence request (from CC_RECEIVE FSM) … … 4486 4593 if ( m_dreq.valid) m_cost_data_miss_frz++; 4487 4594 4595 // coherence clack request (from DSPIN CLACK) 4596 if ( r_dcache_clack_req.read() ) 4597 { 4598 r_dcache_fsm = DCACHE_CC_CHECK; 4599 r_dcache_fsm_cc_save = r_dcache_fsm.read(); 4600 break; 4601 } 4602 4488 4603 // coherence request (from CC_RECEIVE FSM) 4489 4604 if ( r_cc_receive_dcache_req.read() ) … … 4592 4707 case DCACHE_UNC_WAIT: // waiting a response to an uncacheable read 4593 4708 { 4709 // coherence clack request (from DSPIN CLACK) 4710 if ( r_dcache_clack_req.read() ) 4711 { 4712 r_dcache_fsm = DCACHE_CC_CHECK; 4713 r_dcache_fsm_cc_save = r_dcache_fsm.read(); 4714 break; 4715 } 4716 4594 4717 // coherence request (from CC_RECEIVE FSM) 4595 4718 if ( r_cc_receive_dcache_req.read() ) … … 4629 4752 case DCACHE_LL_WAIT: // waiting VCI response to a LL transaction 4630 4753 { 4754 // coherence clack request (from DSPIN CLACK) 4755 if ( r_dcache_clack_req.read() ) 4756 { 4757 r_dcache_fsm = DCACHE_CC_CHECK; 4758 r_dcache_fsm_cc_save = r_dcache_fsm.read(); 4759 break; 4760 } 4761 4631 4762 // coherence request (from CC_RECEIVE FSM) 4632 4763 if ( r_cc_receive_dcache_req.read() ) … … 4675 4806 case DCACHE_SC_WAIT: // waiting VCI response to a SC transaction 4676 4807 { 4808 // coherence clack request (from DSPIN CLACK) 4809 if ( r_dcache_clack_req.read() ) 4810 { 4811 r_dcache_fsm = DCACHE_CC_CHECK; 4812 r_dcache_fsm_cc_save = r_dcache_fsm.read(); 4813 break; 4814 } 4815 4677 4816 // coherence request (from CC_RECEIVE FSM) 4678 4817 if ( r_cc_receive_dcache_req.read() ) … … 4714 4853 size_t way; 4715 4854 size_t set; 4716 size_t word; 4855 size_t word; // unused 4717 4856 int state; 4718 4857 … … 4767 4906 // - if the CAS is a failure, we just retry the write. 4768 4907 { 4908 // coherence clack request (from DSPIN CLACK) 4909 if ( r_dcache_clack_req.read() ) 4910 { 4911 r_dcache_fsm = DCACHE_CC_CHECK; 4912 r_dcache_fsm_cc_save = r_dcache_fsm.read(); 4913 break; 4914 } 4915 4769 4916 // coherence request (from CC_RECEIVE FSM) 4770 4917 if ( r_cc_receive_dcache_req.read() ) … … 4775 4922 } 4776 4923 4777 if ( r_vci_rsp_data_error.read() ) 4924 if ( r_vci_rsp_data_error.read() ) // bus error 4778 4925 { 4779 4926 std::cout << "BUS ERROR in DCACHE_DIRTY_WAIT state" << std::endl; … … 4781 4928 exit(0); 4782 4929 } 4783 else if ( r_vci_rsp_fifo_dcache.rok() ) 4930 else if ( r_vci_rsp_fifo_dcache.rok() ) // response available 4784 4931 { 4785 4932 vci_rsp_fifo_dcache_get = true; … … 4825 4972 #endif 4826 4973 4827 if (r_cc_receive_dcache_type.read() == CC_TYPE_CLACK) 4828 // We switch the directory slot to EMPTY state 4829 // and reset r_icache_miss_clack if the cleanup ack 4830 // is matching a pending miss. 4831 { 4832 4833 if ( m_dreq.valid ) m_cost_data_miss_frz++; 4834 4835 #ifdef INSTRUMENTATION 4836 m_cpt_dcache_dir_write++; 4837 #endif 4838 r_dcache.write_dir( 0, 4839 r_cc_receive_dcache_way.read(), 4840 r_cc_receive_dcache_set.read(), 4841 CACHE_SLOT_STATE_EMPTY); 4842 4843 /*STATS DIRTY*/ 4844 for (size_t word = 0; word < m_dcache_words; word++) 4845 { 4846 dirty_stats[(r_cc_receive_dcache_way * m_dcache_sets + r_cc_receive_dcache_set) * m_dcache_words + word] = false; 4847 } 4848 4849 4850 if ( (r_dcache_miss_set.read() == r_cc_receive_dcache_set.read()) and 4851 (r_dcache_miss_way.read() == r_cc_receive_dcache_way.read()) ) 4852 r_dcache_miss_clack = false; 4853 4854 r_dcache_fsm = r_dcache_fsm_cc_save.read() ; 4855 r_cc_receive_dcache_req = false; 4856 #if DEBUG_DCACHE 4857 if ( m_debug_activated ) 4858 { 4859 std::cout << " <PROC " << name() 4860 << " DCACHE_CC_CHECK> CC_TYPE_CLACK Switch slot to EMPTY state" 4861 << " set = " << r_cc_receive_dcache_set.read() 4862 << " / way = " << r_cc_receive_dcache_way.read() << std::endl; 4863 } 4864 #endif 4865 } 4866 else if( ((r_dcache_fsm_cc_save == DCACHE_MISS_SELECT) or 4867 (r_dcache_fsm_cc_save == DCACHE_MISS_WAIT) or 4868 (r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT)) and 4869 ((r_dcache_vci_paddr.read() & mask) == (paddr & mask)) ) // matching 4974 4975 // Match between MISS address and CC address 4976 // note: In the same cycle we can handle a CLACK and a MISS match 4977 // because the CLACK access the directory but the MISS match dont. 4978 if (r_cc_receive_dcache_req.read() and 4979 ((r_dcache_fsm_cc_save == DCACHE_MISS_SELECT ) or 4980 (r_dcache_fsm_cc_save == DCACHE_MISS_WAIT ) or 4981 (r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT)) and 4982 ((r_dcache_vci_paddr.read() & mask) == (paddr & mask))) // matching 4870 4983 { 4871 4984 // signaling matching … … 4878 4991 r_dcache_fsm = DCACHE_CC_UPDT; 4879 4992 r_dcache_cc_word = r_cc_receive_word_idx.read(); 4993 4880 4994 // just pop the fifo , don't write in icache 4881 4995 r_dcache_cc_need_write = false; … … 4885 4999 { 4886 5000 r_cc_receive_dcache_req = false; 4887 r_dcache_fsm = r_dcache_fsm_cc_save.read();5001 r_dcache_fsm = r_dcache_fsm_cc_save.read(); 4888 5002 } 4889 5003 … … 4896 5010 } 4897 5011 #endif 4898 4899 } 4900 else // no match 4901 { 4902 int state = 0; 4903 size_t way = 0; 4904 size_t set = 0; 4905 size_t word = 0; 5012 } 5013 5014 // CLACK handler 5015 // We switch the directory slot to EMPTY state and reset 5016 // r_dcache_miss_clack if the cleanup ack is matching a pending miss. 5017 if ( r_dcache_clack_req.read() ) 5018 { 5019 if ( m_dreq.valid ) m_cost_data_miss_frz++; 5020 5021 #ifdef INSTRUMENTATION 5022 m_cpt_dcache_dir_write++; 5023 #endif 5024 r_dcache.write_dir( 0, 5025 r_dcache_clack_way.read(), 5026 r_dcache_clack_set.read(), 5027 CACHE_SLOT_STATE_EMPTY); 5028 /*STATS DIRTY*/ 5029 for (size_t word = 0; word < m_dcache_words; word++) 5030 { 5031 dirty_stats[(r_cc_receive_dcache_way * m_dcache_sets + r_cc_receive_dcache_set) * m_dcache_words + word] = false; 5032 } 5033 5034 if ( (r_dcache_miss_set.read() == r_dcache_clack_set.read()) and 5035 (r_dcache_miss_way.read() == r_dcache_clack_way.read()) ) 5036 { 5037 r_dcache_miss_clack = false; 5038 } 5039 5040 r_dcache_clack_req = false; 5041 5042 // return to cc_save state if no pending CC request 5043 if ( not r_cc_receive_dcache_req.read() ) 5044 { 5045 r_dcache_fsm = r_dcache_fsm_cc_save.read() ; 5046 } 5047 5048 #if DEBUG_DCACHE 5049 if ( m_debug_activated ) 5050 { 5051 std::cout << " <PROC " << name() 5052 << " DCACHE_CC_CHECK> CC_TYPE_CLACK Switch slot to EMPTY state" 5053 << " set = " << r_dcache_clack_set.read() 5054 << " / way = " << r_dcache_clack_way.read() << std::endl; 5055 } 5056 #endif 5057 break; 5058 } 5059 5060 // wait if pending request to CC_SEND. This way if there are pending 5061 // CLACK they can be treated in this state and then a deadlock 5062 // situation is avoided 5063 if ( r_dcache_cc_send_req.read() ) break; 5064 5065 // CC request handler 5066 5067 int state = 0; 5068 size_t way = 0; 5069 size_t set = 0; 5070 size_t word = 0; 4906 5071 4907 5072 #ifdef INSTRUMENTATION 4908 5073 m_cpt_dcache_dir_read++; 4909 5074 #endif 4910 r_dcache.read_dir( paddr, 4911 &state, 4912 &way, 4913 &set, 4914 &word ); // unused 4915 4916 r_dcache_cc_way = way; 4917 r_dcache_cc_set = set; 4918 /*ODCCP*/ 4919 if ((state == CACHE_SLOT_STATE_VALID_CC) or (state == CACHE_SLOT_STATE_VALID_NCC)) // hit 4920 { 4921 // need to update the cache state 4922 r_dcache_cleanup_ncc = false; 4923 r_dcache_cc_need_write = true; 4924 if (r_cc_receive_dcache_type.read() == CC_TYPE_UPDT) // hit update 5075 r_dcache.read_dir( paddr, 5076 &state, 5077 &way, 5078 &set, 5079 &word ); // unused 5080 5081 r_dcache_cc_way = way; 5082 r_dcache_cc_set = set; 5083 /*ODCCP*/ 5084 if ((state == CACHE_SLOT_STATE_VALID_CC) or (state == CACHE_SLOT_STATE_VALID_NCC)) // hit 5085 { 5086 r_dcache_cleanup_ncc = false; 5087 r_dcache_cc_need_write = true; 5088 if (r_cc_receive_dcache_type.read() == CC_TYPE_UPDT) // hit update 5089 { 5090 /*ODCCP*/ // we can't receive a CC_UPDT on a NCC line 5091 if (state == CACHE_SLOT_STATE_VALID_NCC) 5092 std::cout << "DCACHE_CC_CHECK : IMPOSSIBLE NCC STATE FOR CC_UPDT at cycle " << m_cpt_total_cycles << std::endl; 5093 assert((state != CACHE_SLOT_STATE_VALID_NCC) and "DCACHE_CC_CHECK : IMPOSSIBLE NCC STATE FOR CC_UPDT"); 5094 5095 r_dcache_fsm = DCACHE_CC_UPDT; 5096 r_dcache_cc_word = r_cc_receive_word_idx.read(); 5097 } 5098 else if (r_cc_receive_dcache_type.read() == CC_TYPE_INVAL) // hit inval 5099 { 5100 if ( (state == CACHE_SLOT_STATE_VALID_NCC) ) 4925 5101 { 4926 /*ODCCP*/ // we can't receive a CC_UPDT on a NCC line 4927 if (state == CACHE_SLOT_STATE_VALID_NCC) 4928 std::cout << "DCACHE_CC_CHECK : IMPOSSIBLE NCC STATE FOR CC_UPDT at cycle " << m_cpt_total_cycles << std::endl; 4929 assert((state != CACHE_SLOT_STATE_VALID_NCC) and "DCACHE_CC_CHECK : IMPOSSIBLE NCC STATE FOR CC_UPDT"); 4930 4931 r_dcache_fsm = DCACHE_CC_UPDT; 4932 r_dcache_cc_word = r_cc_receive_word_idx.read(); 5102 if (r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_DATA_DIRTY) 5103 m_cpt_data_cleanup_dirty ++; 5104 r_dcache_cc_state = state; 5105 r_dcache_cc_inval_addr = (paddr &~0x3F); 5106 r_dcache_cc_inval_data_cpt = 0; 4933 5107 } 4934 else if (r_cc_receive_dcache_type.read() == CC_TYPE_INVAL) // hit inval5108 else 4935 5109 { 4936 if ( (state == CACHE_SLOT_STATE_VALID_NCC) ) 4937 { 4938 if (r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_DATA_DIRTY) 4939 m_cpt_data_cleanup_dirty ++; 4940 r_dcache_cc_state = state; 4941 r_dcache_cc_inval_addr = (paddr &~0x3F); 4942 r_dcache_cc_inval_data_cpt = 0; 4943 } 4944 else 4945 { 4946 r_dcache_cc_state = state; 4947 r_dcache_cc_inval_addr = (paddr &~0x3F); 4948 } 4949 r_dcache_fsm = DCACHE_CC_INVAL; 5110 r_dcache_cc_state = state; 5111 r_dcache_cc_inval_addr = (paddr &~0x3F); 4950 5112 } 4951 else if ( r_cc_receive_dcache_type.read() == CC_TYPE_BRDCAST) // hit broadcast 4952 { 4953 assert((state != CACHE_SLOT_STATE_VALID_NCC) and "DCACHE_CC_CHECK : IMPOSSIBLE NCC STATE FOR CC_BROADCAST"); 4954 r_dcache_fsm = DCACHE_CC_BROADCAST; 4955 } 4956 } 4957 else // miss 4958 { 4959 // multicast acknowledgement required in case of update 4960 if(r_cc_receive_dcache_type.read() == CC_TYPE_UPDT) 4961 { 4962 r_dcache_fsm = DCACHE_CC_UPDT; 4963 r_dcache_cc_word = r_cc_receive_word_idx.read(); 4964 // just pop the fifo , don't write in icache 4965 r_dcache_cc_need_write = false; 4966 } 4967 else // No response needed 4968 { 4969 r_cc_receive_dcache_req = false; 4970 r_dcache_fsm = r_dcache_fsm_cc_save.read(); 4971 } 4972 } 5113 r_dcache_fsm = DCACHE_CC_INVAL; 5114 } 5115 } 5116 else // miss 5117 { 5118 // multicast acknowledgement required in case of update 5119 if(r_cc_receive_dcache_type.read() == CC_TYPE_UPDT) 5120 { 5121 r_dcache_fsm = DCACHE_CC_UPDT; 5122 r_dcache_cc_word = r_cc_receive_word_idx.read(); 5123 5124 // just pop the fifo , don't write in icache 5125 r_dcache_cc_need_write = false; 5126 } 5127 else // No response needed 5128 { 5129 r_cc_receive_dcache_req = false; 5130 r_dcache_fsm = r_dcache_fsm_cc_save.read(); 5131 } 5132 } 4973 5133 4974 5134 #if DEBUG_DCACHE … … 4982 5142 } 4983 5143 #endif 5144 5145 break; 5146 } 5147 ///////////////////// 5148 case DCACHE_CC_INVAL: // hit inval: switch slot to ZOMBI state and send a 5149 // CLEANUP after possible invalidation of copies in 5150 // TLBs 5151 { 5152 size_t way = r_dcache_cc_way.read(); 5153 size_t set = r_dcache_cc_set.read(); 5154 int state = r_dcache_cc_state.read(); 5155 if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_IN_TLB ) 5156 { 5157 r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_NOT_DIRTY; 5158 r_dcache_tlb_inval_line = r_cc_receive_dcache_nline.read(); 5159 r_dcache_tlb_inval_set = 0; 5160 r_dcache_fsm_scan_save = r_dcache_fsm.read(); 5161 r_dcache_fsm = DCACHE_INVAL_TLB_SCAN; 5162 break; 5163 } 5164 if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_CONTAINS_PTD ) 5165 { 5166 r_itlb.reset(); 5167 r_dtlb.reset(); 5168 r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_NOT_DIRTY; 5169 5170 #if DEBUG_DCACHE 5171 if ( m_debug_activated ) 5172 { 5173 std::cout << " <PROC " << name() 5174 << " DCACHE_CC_INVAL> Flush DTLB & ITLB" << std::endl; 5175 } 5176 #endif 5177 } 5178 5179 5180 if ( state == CACHE_SLOT_STATE_VALID_CC ) 5181 { 5182 // Switch slot state to ZOMBI and send CLEANUP command 5183 r_dcache.write_dir( way, 5184 set, 5185 CACHE_SLOT_STATE_ZOMBI ); 5186 #if DEBUG_DCACHE 5187 if ( m_debug_activated ) 5188 { 5189 std::cout << " <PROC " << name() 5190 << " DCACHE_CC_INVAL> Switch slot valid CC to ZOMBI state:" << std::dec 5191 << " / WAY = " << way 5192 << " / SET = " << set << std::endl; 5193 } 5194 #endif 5195 } 5196 5197 assert (not r_dcache_cc_send_req.read() && 5198 "ERROR in DCACHE_CC_INVAL: the r_dcache_cc_send_req " 5199 "must not be set"); 5200 5201 // coherence request completed 5202 r_cc_receive_dcache_req = false; 5203 r_dcache_cc_send_req = true; 5204 r_dcache_cc_send_nline = r_cc_receive_dcache_nline.read(); 5205 r_dcache_cc_send_way = way; 5206 r_dcache_cc_send_type = CC_TYPE_CLEANUP; 5207 r_dcache_fsm = r_dcache_fsm_cc_save.read(); 5208 5209 if ( (state == CACHE_SLOT_STATE_VALID_NCC) ) 5210 { 5211 r_dcache_cleanup_ncc = true; 5212 5213 if (r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_DATA_DIRTY) 5214 { 5215 r_dcache_cc_cleanup_updt_data = true; 5216 r_dcache_fsm = DCACHE_CC_INVAL_DATA; 5217 5218 /*STATS DIRTY*/ 5219 for (size_t w = 0; w < m_dcache_words; w++) 5220 { 5221 if(dirty_stats[(way * m_dcache_sets + set) * m_dcache_words + w] == true) 5222 m_cpt_words_dirty++; 5223 } 5224 } 5225 else 5226 { 5227 r_dcache_cc_cleanup_updt_data = false; 5228 r_dcache.write_dir( way, 5229 set, 5230 CACHE_SLOT_STATE_ZOMBI ); 5231 r_dcache_fsm = r_dcache_fsm_cc_save.read(); 5232 } 4984 5233 } 4985 5234 break; … … 5001 5250 r_dcache_cc_inval_addr = r_dcache_cc_inval_addr.read() + 4; 5002 5251 5003 cleanup_data_updt_fifo_dcache_get = false;5004 5252 cleanup_data_updt_fifo_dcache_put = true; 5005 5253 cleanup_data_updt_fifo_dcache_data = rdata; … … 5026 5274 break; 5027 5275 } 5028 /////////////////// //5029 case DCACHE_CC_ INVAL: // hit inval: switch slot to EMPTY state,5276 /////////////////// 5277 case DCACHE_CC_UPDT: // hit update: write one word per cycle, 5030 5278 // after possible invalidation of copies in TLBs 5031 5279 { 5032 size_t way = r_dcache_cc_way.read(); 5033 size_t set = r_dcache_cc_set.read(); 5034 int state = r_dcache_cc_state.read(); 5035 if (r_dcache_cc_need_write.read()) 5036 { 5037 if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_IN_TLB ) 5038 { 5039 r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_NOT_DIRTY; 5040 r_dcache_tlb_inval_line = r_cc_receive_dcache_nline.read(); 5041 r_dcache_tlb_inval_set = 0; 5042 r_dcache_fsm_scan_save = r_dcache_fsm.read(); 5043 r_dcache_fsm = DCACHE_INVAL_TLB_SCAN; 5044 break; 5045 } 5046 else 5047 { 5048 if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_CONTAINS_PTD ) 5049 { 5050 r_itlb.reset(); 5051 r_dtlb.reset(); 5052 r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_NOT_DIRTY; 5053 5054 #if DEBUG_DCACHE 5055 if ( m_debug_activated ) 5056 { 5057 std::cout << " <PROC " << name() 5058 << " DCACHE_CC_INVAL> Flush DTLB & ITLB" << std::endl; 5059 } 5060 #endif 5061 } 5062 5063 if ( state == CACHE_SLOT_STATE_VALID_CC ) 5064 { 5065 r_dcache.write_dir( 0, 5066 way, 5067 set, 5068 CACHE_SLOT_STATE_EMPTY ); 5069 #if DEBUG_DCACHE 5070 if ( m_debug_activated ) 5071 { 5072 std::cout << " <PROC " << name() 5073 5074 << " DCACHE_CC_INVAL> Switch slot to EMPTY state:" << std::dec 5075 << " / WAY = " << way 5076 << " / SET = " << set << std::endl; 5077 } 5078 #endif 5079 } 5080 r_dcache_cc_need_write = false; 5081 5082 } 5083 } 5084 5085 // multicast acknowledgement 5086 // send a request to cc_send_fsm 5087 if(not r_dcache_cc_send_req.read()) // cc_send is available 5088 { 5089 5090 // coherence request completed 5091 r_cc_receive_dcache_req = false; 5092 r_dcache_cc_send_req = true; 5093 r_dcache_cc_send_nline = r_cc_receive_dcache_nline.read(); 5094 5095 5096 if ( (state == CACHE_SLOT_STATE_VALID_NCC) ) 5097 { 5098 r_dcache_cleanup_ncc = true; 5099 r_dcache_cc_send_type = CC_TYPE_CLEANUP; 5100 r_dcache_cc_send_way = way; 5101 5102 if (r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_DATA_DIRTY) 5103 { 5104 r_dcache_cc_cleanup_updt_data = true; 5105 r_dcache_fsm = DCACHE_CC_INVAL_DATA; 5106 5107 /*STATS DIRTY*/ 5108 for (size_t w = 0; w < m_dcache_words; w++) 5109 { 5110 if(dirty_stats[(way * m_dcache_sets + set) * m_dcache_words + w] == true) 5111 m_cpt_words_dirty++; 5112 } 5113 } 5114 else 5115 { 5116 r_dcache_cc_cleanup_updt_data = false; 5117 r_dcache.write_dir( way, 5118 set, 5119 CACHE_SLOT_STATE_ZOMBI ); 5120 r_dcache_fsm = r_dcache_fsm_cc_save.read(); 5121 } 5122 } 5123 else 5124 { 5125 // request multicast acknowledgement 5126 r_dcache_cc_send_updt_tab_idx = r_cc_receive_dcache_updt_tab_idx.read(); 5127 r_dcache_cc_send_type = CC_TYPE_MULTI_ACK; 5128 r_dcache_fsm = r_dcache_fsm_cc_save.read(); 5129 } 5130 } 5131 //else wait for previous cc_send request to be sent 5132 break; 5133 } 5134 /////////////////// 5135 case DCACHE_CC_UPDT: // hit update: write one word per cycle, 5136 // after possible invalidation of copies in TLBs 5137 { 5138 size_t word = r_dcache_cc_word.read(); 5139 size_t way = r_dcache_cc_way.read(); 5140 size_t set = r_dcache_cc_set.read(); 5141 5142 if (r_cc_receive_updt_fifo_be.rok()) 5143 { 5144 if (r_dcache_cc_need_write.read()) 5145 { 5146 // selective TLB inval 5147 if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_IN_TLB ) 5148 { 5149 r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_NOT_DIRTY; 5150 r_dcache_tlb_inval_line = r_cc_receive_dcache_nline.read(); 5151 r_dcache_tlb_inval_set = 0; 5152 r_dcache_fsm_scan_save = r_dcache_fsm.read(); 5153 r_dcache_fsm = DCACHE_INVAL_TLB_SCAN; 5154 break; 5155 } 5156 // TLB flush 5157 if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_CONTAINS_PTD ) 5158 { 5159 r_itlb.reset(); 5160 r_dtlb.reset(); 5161 r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_NOT_DIRTY; 5280 size_t word = r_dcache_cc_word.read(); 5281 size_t way = r_dcache_cc_way.read(); 5282 size_t set = r_dcache_cc_set.read(); 5283 5284 // selective TLB inval 5285 if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_IN_TLB ) 5286 { 5287 r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_NOT_DIRTY; 5288 r_dcache_tlb_inval_line = r_cc_receive_dcache_nline.read(); 5289 r_dcache_tlb_inval_set = 0; 5290 r_dcache_fsm_scan_save = r_dcache_fsm.read(); 5291 r_dcache_fsm = DCACHE_INVAL_TLB_SCAN; 5292 break; 5293 } 5294 // TLB flush 5295 if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_CONTAINS_PTD ) 5296 { 5297 r_itlb.reset(); 5298 r_dtlb.reset(); 5299 r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_NOT_DIRTY; 5162 5300 5163 5301 #if DEBUG_DCACHE … … 5165 5303 { 5166 5304 std::cout << " <PROC " << name() 5167 5305 << " DCACHE_CC_UPDT> Flush DTLB & ITLB" << std::endl; 5168 5306 } 5169 5307 #endif 5170 } 5171 5308 } 5309 5310 assert (not r_dcache_cc_send_req.read() && 5311 "ERROR in DCACHE_CC_INVAL: the r_dcache_cc_send_req " 5312 "must not be set"); 5313 5314 if ( not r_cc_receive_updt_fifo_be.rok() ) break; 5315 5316 if (r_dcache_cc_need_write.read()) 5317 { 5318 5172 5319 #ifdef INSTRUMENTATION 5173 5320 m_cpt_dcache_data_write++; 5174 5321 #endif 5175 5176 5177 5178 5179 5180 5181 5322 r_dcache.write( way, 5323 set, 5324 word, 5325 r_cc_receive_updt_fifo_data.read(), 5326 r_cc_receive_updt_fifo_be.read() ); 5327 5328 r_dcache_cc_word = word + 1; 5182 5329 5183 5330 #if DEBUG_DCACHE … … 5192 5339 } 5193 5340 #endif 5194 } 5195 5196 if ( r_cc_receive_updt_fifo_eop.read() ) // last word 5197 { 5198 // no need to write in the cache anymore 5199 r_dcache_cc_need_write = false; 5200 5201 // wait to send a request to cc_send_fsm 5202 if(not r_dcache_cc_send_req.read()) 5203 // cc_send is available 5204 { 5205 //consume last fifo flit if eop and request to cc_send possible 5206 cc_receive_updt_fifo_get = true; 5207 5208 // coherence request completed 5209 r_cc_receive_dcache_req = false; 5210 5211 // request multicast acknowledgement 5212 r_dcache_cc_send_req = true; 5213 r_dcache_cc_send_nline = r_cc_receive_dcache_nline.read(); 5214 r_dcache_cc_send_updt_tab_idx = r_cc_receive_dcache_updt_tab_idx.read(); 5215 r_dcache_cc_send_type = CC_TYPE_MULTI_ACK; 5216 5217 r_dcache_fsm = r_dcache_fsm_cc_save.read(); 5218 } 5219 } 5220 else 5221 { 5222 //consume fifo if not eop 5223 cc_receive_updt_fifo_get = true; 5224 } 5225 } 5226 break; 5227 } 5228 ///////////////////////// 5229 case DCACHE_CC_BROADCAST: // hit broadcast : switch state to ZOMBI state 5230 // and request a cleanup, after possible 5231 // invalidation of copies in TLBs 5232 { 5233 size_t way = r_dcache_cc_way.read(); 5234 size_t set = r_dcache_cc_set.read(); 5235 paddr_t nline = r_cc_receive_dcache_nline.read(); 5236 5237 if (r_dcache_cc_need_write.read()) 5238 { 5239 // selective TLB inval 5240 if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_IN_TLB ) 5241 { 5242 r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_NOT_DIRTY; 5243 r_dcache_tlb_inval_line = nline; 5244 r_dcache_tlb_inval_set = 0; 5245 r_dcache_fsm_scan_save = r_dcache_fsm.read(); 5246 r_dcache_fsm = DCACHE_INVAL_TLB_SCAN; 5247 break; 5248 } 5249 else 5250 { 5251 // TLB flush 5252 if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_CONTAINS_PTD ) 5253 { 5254 r_itlb.reset(); 5255 r_dtlb.reset(); 5256 r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_NOT_DIRTY; 5257 5258 #if DEBUG_DCACHE 5259 if ( m_debug_activated ) 5260 { 5261 std::cout << " <PROC " << name() 5262 << " DCACHE_CC_BROADCAST> Flush DTLB & ITLB" << std::endl; 5263 } 5264 #endif 5265 } 5266 5267 #ifdef INSTRUMENTATION 5268 m_cpt_dcache_dir_write++; 5269 #endif 5270 r_dcache.write_dir( way, 5271 set, 5272 CACHE_SLOT_STATE_ZOMBI ); 5273 5274 r_dcache_cc_need_write = false; 5275 #if DEBUG_DCACHE 5276 if ( m_debug_activated ) 5277 { 5278 std::cout << " <PROC " << name() 5279 << " DCACHE_CC_BROADCAST > Slot goes to ZOMBI state " 5280 << " SET = " << set 5281 << " / WAY = " << way << std::endl; 5282 } 5283 #endif 5284 } 5285 } 5286 // cleanup 5287 // send a request to cc_send_fsm 5288 if(not r_dcache_cc_send_req.read()) // cc_send is available 5289 { 5341 } 5342 5343 if ( r_cc_receive_updt_fifo_eop.read() ) // last word 5344 { 5345 // no need to write in the cache anymore 5346 r_dcache_cc_need_write = false; 5347 5290 5348 // coherence request completed 5291 5349 r_cc_receive_dcache_req = false; 5292 // request cleanup 5293 r_dcache_cc_send_req = true; 5294 r_dcache_cc_send_nline = r_cc_receive_dcache_nline.read(); 5295 r_dcache_cc_send_way = r_dcache_cc_way.read(); 5296 r_dcache_cc_send_type = CC_TYPE_CLEANUP; 5297 5298 r_dcache_fsm = r_dcache_fsm_cc_save.read(); 5299 } 5300 //else wait for previous cc_send request to be sent 5350 5351 // request multicast acknowledgement 5352 r_dcache_cc_send_req = true; 5353 r_dcache_cc_send_nline = r_cc_receive_dcache_nline.read(); 5354 r_dcache_cc_send_updt_tab_idx = r_cc_receive_dcache_updt_tab_idx.read(); 5355 r_dcache_cc_send_type = CC_TYPE_MULTI_ACK; 5356 5357 r_dcache_fsm = r_dcache_fsm_cc_save.read(); 5358 } 5359 5360 //consume fifo if not eop 5361 cc_receive_updt_fifo_get = true; 5362 5301 5363 break; 5302 5364 } … … 5689 5751 if ( r_vci_rsp_fifo_icache.wok() ) 5690 5752 { 5691 assert( (r_vci_rsp_cpt.read() < m_icache_words) and 5692 "The VCI response packet for instruction miss is too long" ); 5693 5753 if ( r_vci_rsp_cpt.read() >= m_icache_words ) 5754 { 5755 std::cout << "ERROR in VCI_CC_VCACHE " << name() 5756 << " VCI response packet too long " 5757 << " for instruction miss" << std::endl; 5758 exit(0); 5759 } 5694 5760 r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1; 5695 5761 vci_rsp_fifo_icache_put = true, … … 5697 5763 if ( p_vci.reop.read() ) 5698 5764 { 5699 assert( (r_vci_rsp_cpt.read() == m_icache_words - 1) and 5700 "The VCI response packet for instruction miss is too short"); 5701 5765 if ( r_vci_rsp_cpt.read() != (m_icache_words - 1) ) 5766 { 5767 std::cout << "ERROR in VCI_CC_VCACHE " << name() 5768 << " VCI response packet too short" 5769 << " for instruction miss" << std::endl; 5770 exit(0); 5771 } 5702 5772 r_vci_rsp_fsm = RSP_IDLE; 5703 5773 } … … 5902 5972 { 5903 5973 // wait for the first flit to be consumed 5904 if (p_dspin_ out.read.read())5974 if (p_dspin_p2m.read.read()) 5905 5975 r_cc_send_fsm = CC_SEND_CLEANUP_2; 5906 5976 … … 5911 5981 { 5912 5982 // wait for the second flit to be consumed 5913 if (p_dspin_ out.read.read())5983 if (p_dspin_p2m.read.read()) 5914 5984 { 5915 5985 /*ODCCP*/ // If there is a cleanup with data and dcache active request we send other flits contained data … … 5933 6003 case CC_SEND_CLEANUP_DATA_UPDT: /*ODCCP*/ // we send the data values of line cache into [m_dcache_words] flits 5934 6004 { 5935 if (p_dspin_ out.read.read())6005 if (p_dspin_p2m.read.read()) 5936 6006 { 5937 6007 if(r_cc_send_data_fifo.rok()) … … 5956 6026 { 5957 6027 // wait for the flit to be consumed 5958 if(p_dspin_ out.read.read())6028 if(p_dspin_p2m.read.read()) 5959 6029 { 5960 6030 if(r_cc_send_last_client.read() == 0) // dcache active request … … 5970 6040 5971 6041 /////////////////////////////////////////////////////////////////////////////// 5972 // 6042 // CC_RECEIVE FSM 5973 6043 // This FSM receive all coherence packets on a DSPIN40 port. 5974 // There is 7packet types:6044 // There is 5 packet types: 5975 6045 // - CC_DATA_INVAL : DCACHE invalidate request 5976 6046 // - CC_DATA_UPDT : DCACHE update request (multi-words) … … 5978 6048 // - CC_INST_UPDT : ICACHE update request (multi-words) 5979 6049 // - CC_BROADCAST : Broadcast invalidate request (both DCACHE & ICACHE) 5980 // - CC_DATA_CLACK : DCACHE cleanup acknowledge5981 // - CC_INST_CLACK : ICACHE cleanup acknowledge5982 6050 ////////////////////////////////////////////////////////////////////////////// 5983 6051 switch( r_cc_receive_fsm.read() ) … … 5987 6055 { 5988 6056 // a coherence request has arrived 5989 if (p_dspin_ in.write.read())6057 if (p_dspin_m2p.write.read()) 5990 6058 { 5991 6059 // initialize dspin received data 5992 uint64_t receive_data = p_dspin_ in.data.read();6060 uint64_t receive_data = p_dspin_m2p.data.read(); 5993 6061 // initialize coherence packet type 5994 6062 uint64_t receive_type = DspinDhccpParam::dspin_get(receive_data, 5995 DspinDhccpParam::FROM_MC_TYPE); 5996 // initialize data/ins flip_flop (0 data / 1 ins) 5997 r_cc_receive_data_ins = (bool)(receive_type & 0x1); 6063 DspinDhccpParam::M2P_TYPE); 5998 6064 // test for a broadcast 5999 if (DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam:: FROM_MC_BC))6065 if (DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::M2P_BC)) 6000 6066 { 6001 6067 r_cc_receive_fsm = CC_RECEIVE_BRDCAST_HEADER; 6002 6068 } 6003 // test for a CLACK 6004 else if ((receive_type == DspinDhccpParam::TYPE_CLEANUP_ACK_DATA) or 6005 (receive_type == DspinDhccpParam::TYPE_CLEANUP_ACK_INST)) 6069 // test for a multi updt 6070 else if (receive_type == DspinDhccpParam::TYPE_MULTI_UPDT_DATA) 6006 6071 { 6007 r_cc_receive_fsm = CC_RECEIVE_ CLACK;6072 r_cc_receive_fsm = CC_RECEIVE_DATA_UPDT_HEADER; 6008 6073 } 6009 // test for a multi updt 6010 else if ((receive_type == DspinDhccpParam::TYPE_MULTI_UPDT_DATA) or 6011 (receive_type == DspinDhccpParam::TYPE_MULTI_UPDT_INST)) 6074 else if (receive_type == DspinDhccpParam::TYPE_MULTI_UPDT_INST) 6012 6075 { 6013 r_cc_receive_fsm = CC_RECEIVE_ UPDT_HEADER;6076 r_cc_receive_fsm = CC_RECEIVE_INS_UPDT_HEADER; 6014 6077 } 6015 6078 // test for a multi inval 6079 else if (receive_type == DspinDhccpParam::TYPE_MULTI_INVAL_DATA) 6080 { 6081 r_cc_receive_fsm = CC_RECEIVE_DATA_INVAL_HEADER; 6082 } 6016 6083 else 6017 6084 { 6018 r_cc_receive_fsm = CC_RECEIVE_IN VAL_HEADER;6085 r_cc_receive_fsm = CC_RECEIVE_INS_INVAL_HEADER; 6019 6086 } 6020 6087 } 6021 break;6022 }6023 //////////////////////6024 case CC_RECEIVE_CLACK:6025 {6026 // initialize dspin received data6027 uint64_t receive_data = p_dspin_in.data.read();6028 6029 // for data CLACK, wait for dcache to take the request6030 if ((r_cc_receive_data_ins.read() == 0) and6031 not r_cc_receive_dcache_req.read())6032 {6033 // request dcache to handle the CLACK6034 r_cc_receive_dcache_req = true;6035 r_cc_receive_dcache_set = DspinDhccpParam::dspin_get(receive_data,6036 DspinDhccpParam::CLEANUP_ACK_SET) &6037 ((1ULL<<(uint32_log2(m_dcache_sets)))-1);6038 r_cc_receive_dcache_way = DspinDhccpParam::dspin_get(receive_data,6039 DspinDhccpParam::CLEANUP_ACK_WAY) &6040 ((1ULL<<(uint32_log2(m_dcache_ways)))-1);6041 r_cc_receive_dcache_type = CC_TYPE_CLACK;6042 // get back to idle state6043 r_cc_receive_fsm = CC_RECEIVE_IDLE;6044 break;6045 }6046 // for ins CLACK, wait for icache to take the request6047 if ((r_cc_receive_data_ins.read() == 1) and6048 not (r_cc_receive_icache_req.read()))6049 {6050 // request icache to handle the CLACK6051 r_cc_receive_icache_req = true;6052 r_cc_receive_icache_set = DspinDhccpParam::dspin_get(receive_data,6053 DspinDhccpParam::CLEANUP_ACK_SET) &6054 ((1ULL<<(uint32_log2(m_icache_sets)))-1);6055 r_cc_receive_icache_way = DspinDhccpParam::dspin_get(receive_data,6056 DspinDhccpParam::CLEANUP_ACK_WAY) &6057 ((1ULL<<(uint32_log2(m_icache_ways)))-1);6058 r_cc_receive_icache_type = CC_TYPE_CLACK;6059 // get back to idle state6060 r_cc_receive_fsm = CC_RECEIVE_IDLE;6061 break;6062 }6063 // keep waiting for the correct cache to accept the request6064 6088 break; 6065 6089 } … … 6075 6099 { 6076 6100 // initialize dspin received data 6077 uint64_t receive_data = p_dspin_ in.data.read();6101 uint64_t receive_data = p_dspin_m2p.data.read(); 6078 6102 // wait for both dcache and icache to take the request 6079 6103 // TODO maybe we need to wait for both only to leave the state, but … … 6082 6106 if (not (r_cc_receive_icache_req.read()) and 6083 6107 not (r_cc_receive_dcache_req.read()) and 6084 (p_dspin_ in.write.read()))6108 (p_dspin_m2p.write.read())) 6085 6109 { 6086 6110 // request dcache to handle the BROADCAST 6087 r_cc_receive_dcache_req 6111 r_cc_receive_dcache_req = true; 6088 6112 r_cc_receive_dcache_nline = DspinDhccpParam::dspin_get(receive_data, 6089 6113 DspinDhccpParam::BROADCAST_NLINE); 6090 r_cc_receive_dcache_type = CC_TYPE_ BRDCAST;6114 r_cc_receive_dcache_type = CC_TYPE_INVAL; 6091 6115 // request icache to handle the BROADCAST 6092 r_cc_receive_icache_req 6116 r_cc_receive_icache_req = true; 6093 6117 r_cc_receive_icache_nline = DspinDhccpParam::dspin_get(receive_data, 6094 6118 DspinDhccpParam::BROADCAST_NLINE); 6095 r_cc_receive_icache_type = CC_TYPE_ BRDCAST;6119 r_cc_receive_icache_type = CC_TYPE_INVAL; 6096 6120 // get back to idle state 6097 6121 r_cc_receive_fsm = CC_RECEIVE_IDLE; … … 6102 6126 } 6103 6127 ///////////////////////////// 6104 case CC_RECEIVE_ INVAL_HEADER:6128 case CC_RECEIVE_DATA_INVAL_HEADER: 6105 6129 { 6106 6130 // sample updt tab index in the HEADER, then skip to second flit 6107 uint64_t receive_data = p_dspin_in.data.read(); 6131 r_cc_receive_fsm = CC_RECEIVE_DATA_INVAL_NLINE; 6132 break; 6133 } 6134 ///////////////////////////// 6135 case CC_RECEIVE_INS_INVAL_HEADER: 6136 { 6137 // sample updt tab index in the HEADER, then skip to second flit 6138 r_cc_receive_fsm = CC_RECEIVE_INS_INVAL_NLINE; 6139 break; 6140 } 6141 //////////////////////////// 6142 case CC_RECEIVE_DATA_INVAL_NLINE: 6143 { 6144 // sample nline in the second flit 6145 uint64_t receive_data = p_dspin_m2p.data.read(); 6108 6146 // for data INVAL, wait for dcache to take the request 6109 if ((r_cc_receive_data_ins.read() == 0) and 6110 not (r_cc_receive_dcache_req.read())) 6111 { 6112 r_cc_receive_dcache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data, 6113 DspinDhccpParam::MULTI_INVAL_UPDT_INDEX); 6114 r_cc_receive_fsm = CC_RECEIVE_INVAL_NLINE; 6115 break; 6116 } 6117 // for ins INVAL, wait for icache to take the request 6118 if ((r_cc_receive_data_ins.read() == 1) and 6119 not (r_cc_receive_icache_req.read())) 6120 { 6121 r_cc_receive_icache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data, 6122 DspinDhccpParam::MULTI_INVAL_UPDT_INDEX); 6123 r_cc_receive_fsm = CC_RECEIVE_INVAL_NLINE; 6124 break; 6125 } 6126 // keep waiting for the correct cache to accept the request 6127 break; 6128 } 6129 //////////////////////////// 6130 case CC_RECEIVE_INVAL_NLINE: 6131 { 6132 // sample nline in the second flit 6133 uint64_t receive_data = p_dspin_in.data.read(); 6134 // for data INVAL, wait for dcache to take the request 6135 if ( (r_cc_receive_data_ins.read() == 0) and 6136 not (r_cc_receive_dcache_req.read()) and 6137 (p_dspin_in.write.read()) ) 6147 if (p_dspin_m2p.write.read() and not r_cc_receive_dcache_req.read()) 6138 6148 { 6139 6149 // request dcache to handle the INVAL 6140 r_cc_receive_dcache_req 6141 r_cc_receive_dcache_nline 6150 r_cc_receive_dcache_req = true; 6151 r_cc_receive_dcache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_INVAL_NLINE); 6142 6152 r_cc_receive_dcache_type = CC_TYPE_INVAL; 6143 6153 // get back to idle state … … 6145 6155 break; 6146 6156 } 6157 break; 6158 } 6159 ////////////////////////////// 6160 case CC_RECEIVE_INS_INVAL_NLINE: 6161 { 6162 // sample nline in the second flit 6163 uint64_t receive_data = p_dspin_m2p.data.read(); 6147 6164 // for ins INVAL, wait for icache to take the request 6148 if ( (r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()) and (p_dspin_in.write.read()))6165 if (p_dspin_m2p.write.read() and not r_cc_receive_icache_req.read()) 6149 6166 { 6150 6167 // request icache to handle the INVAL 6151 r_cc_receive_icache_req 6152 r_cc_receive_icache_nline 6168 r_cc_receive_icache_req = true; 6169 r_cc_receive_icache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_INVAL_NLINE); 6153 6170 r_cc_receive_icache_type = CC_TYPE_INVAL; 6154 6171 // get back to idle state … … 6156 6173 break; 6157 6174 } 6158 // we should never get there 6159 assert ( false && "ERROR in CC_VCACHE : CC_RECEIVE_INVAL_NLINE\n"); 6175 break; 6160 6176 } 6161 6177 //////////////////////////// 6162 case CC_RECEIVE_ UPDT_HEADER:6178 case CC_RECEIVE_DATA_UPDT_HEADER: 6163 6179 { 6164 6180 // sample updt tab index in the HEADER, than skip to second flit 6165 uint64_t receive_data = p_dspin_ in.data.read();6181 uint64_t receive_data = p_dspin_m2p.data.read(); 6166 6182 // for data INVAL, wait for dcache to take the request and fifo to 6167 6183 // be empty 6168 if ( (r_cc_receive_data_ins.read() == 0) and not r_cc_receive_dcache_req.read() and r_cc_receive_updt_fifo_be.empty())6184 if (not r_cc_receive_dcache_req.read()) 6169 6185 { 6170 6186 r_cc_receive_dcache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_UPDT_INDEX); 6171 r_cc_receive_fsm = CC_RECEIVE_ UPDT_NLINE;6187 r_cc_receive_fsm = CC_RECEIVE_DATA_UPDT_NLINE; 6172 6188 break; 6173 6189 } 6190 break; 6191 } 6192 //////////////////////////// 6193 case CC_RECEIVE_INS_UPDT_HEADER: 6194 { 6195 // sample updt tab index in the HEADER, than skip to second flit 6196 uint64_t receive_data = p_dspin_m2p.data.read(); 6174 6197 // for ins INVAL, wait for icache to take the request and fifo to be 6175 6198 // empty 6176 if ( (r_cc_receive_data_ins.read() == 1) and not r_cc_receive_icache_req.read() and r_cc_receive_updt_fifo_be.empty())6199 if (not r_cc_receive_icache_req.read()) 6177 6200 { 6178 6201 r_cc_receive_icache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_UPDT_INDEX); 6179 r_cc_receive_fsm = CC_RECEIVE_ UPDT_NLINE;6202 r_cc_receive_fsm = CC_RECEIVE_INS_UPDT_NLINE; 6180 6203 break; 6181 6204 } … … 6184 6207 } 6185 6208 /////////////////////////// 6186 case CC_RECEIVE_ UPDT_NLINE:6209 case CC_RECEIVE_DATA_UPDT_NLINE: 6187 6210 { 6188 6211 // sample nline and word index in the second flit 6189 uint64_t receive_data = p_dspin_ in.data.read();6212 uint64_t receive_data = p_dspin_m2p.data.read(); 6190 6213 // for data INVAL, wait for dcache to take the request and fifo to 6191 6214 // be empty 6192 if ( (r_cc_receive_data_ins.read() == 0) and 6193 not (r_cc_receive_dcache_req.read()) and 6194 r_cc_receive_updt_fifo_be.empty() and 6195 (p_dspin_in.write.read()) ) 6196 { 6215 if ( r_cc_receive_updt_fifo_be.empty() and 6216 p_dspin_m2p.write.read() ) 6217 { 6218 r_cc_receive_dcache_req = true; 6197 6219 r_cc_receive_dcache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_NLINE); 6198 6220 r_cc_receive_word_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_WORD_INDEX); 6199 6221 r_cc_receive_dcache_type = CC_TYPE_UPDT; 6200 6222 // get back to idle state 6201 r_cc_receive_fsm = CC_RECEIVE_ UPDT_DATA;6223 r_cc_receive_fsm = CC_RECEIVE_DATA_UPDT_DATA; 6202 6224 break; 6203 6225 } 6226 break; 6227 } 6228 //////////////////////////// 6229 case CC_RECEIVE_INS_UPDT_NLINE: 6230 { 6231 // sample nline and word index in the second flit 6232 uint64_t receive_data = p_dspin_m2p.data.read(); 6204 6233 // for ins INVAL, wait for icache to take the request and fifo to be 6205 6234 // empty 6206 if ( (r_cc_receive_data_ins.read() == 1) and 6207 not (r_cc_receive_icache_req.read()) and 6208 r_cc_receive_updt_fifo_be.empty() and 6209 (p_dspin_in.write.read())) 6210 { 6235 if ( r_cc_receive_updt_fifo_be.empty() and 6236 p_dspin_m2p.write.read() ) 6237 { 6238 r_cc_receive_icache_req = true; 6211 6239 r_cc_receive_icache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_NLINE); 6212 6240 r_cc_receive_word_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_WORD_INDEX); 6213 6241 r_cc_receive_icache_type = CC_TYPE_UPDT; 6214 6242 // get back to idle state 6215 r_cc_receive_fsm = CC_RECEIVE_ UPDT_DATA;6243 r_cc_receive_fsm = CC_RECEIVE_INS_UPDT_DATA; 6216 6244 break; 6217 6245 } 6218 // we should never get there6219 assert ( false && "ERROR in CC_VCACHE : CC_RECEIVE_UPDT_NLINE \n");6220 6246 break; 6221 6247 } 6222 6248 ////////////////////////// 6223 case CC_RECEIVE_UPDT_DATA: 6224 { 6225 if ((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read()) and (p_dspin_in.write.read())) 6226 r_cc_receive_dcache_req = true; 6227 if ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()) and (p_dspin_in.write.read())) 6228 r_cc_receive_icache_req = true; 6229 6249 case CC_RECEIVE_DATA_UPDT_DATA: 6250 { 6230 6251 // wait for the fifo 6231 if (r_cc_receive_updt_fifo_be.wok() and (p_dspin_ in.write.read()))6232 { 6233 uint64_t receive_data = p_dspin_ in.data.read();6234 bool receive_eop = p_dspin_ in.eop.read();6252 if (r_cc_receive_updt_fifo_be.wok() and (p_dspin_m2p.write.read())) 6253 { 6254 uint64_t receive_data = p_dspin_m2p.data.read(); 6255 bool receive_eop = p_dspin_m2p.eop.read(); 6235 6256 cc_receive_updt_fifo_be = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_BE); 6236 6257 cc_receive_updt_fifo_data = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_DATA); … … 6241 6262 break; 6242 6263 } 6264 ////////////////////////// 6265 case CC_RECEIVE_INS_UPDT_DATA: 6266 { 6267 // wait for the fifo 6268 if (r_cc_receive_updt_fifo_be.wok() and (p_dspin_m2p.write.read())) 6269 { 6270 uint64_t receive_data = p_dspin_m2p.data.read(); 6271 bool receive_eop = p_dspin_m2p.eop.read(); 6272 cc_receive_updt_fifo_be = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_BE); 6273 cc_receive_updt_fifo_data = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_DATA); 6274 cc_receive_updt_fifo_eop = receive_eop; 6275 cc_receive_updt_fifo_put = true; 6276 if ( receive_eop ) r_cc_receive_fsm = CC_RECEIVE_IDLE; 6277 } 6278 break; 6279 } 6280 6243 6281 } // end switch CC_RECEIVE FSM 6282 6283 ///////////////// DSPIN CLACK interface /////////////// 6284 6285 uint64_t clack_type = DspinDhccpParam::dspin_get(r_dspin_clack_flit.read(), 6286 DspinDhccpParam::CLACK_TYPE); 6287 6288 size_t clack_way = DspinDhccpParam::dspin_get(r_dspin_clack_flit.read(), 6289 DspinDhccpParam::CLACK_WAY); 6290 6291 size_t clack_set = DspinDhccpParam::dspin_get(r_dspin_clack_flit.read(), 6292 DspinDhccpParam::CLACK_SET); 6293 6294 bool dspin_clack_get = false; 6295 bool dcache_clack_request = (clack_type == DspinDhccpParam::TYPE_CLACK_DATA); 6296 bool icache_clack_request = (clack_type == DspinDhccpParam::TYPE_CLACK_INST); 6297 6298 if (r_dspin_clack_req.read()) 6299 { 6300 // CLACK DATA: Send request to DCACHE FSM 6301 if (dcache_clack_request and not r_dcache_clack_req.read()){ 6302 r_dcache_clack_req = true; 6303 r_dcache_clack_way = clack_way & ((1ULL<<(uint32_log2(m_dcache_ways)))-1); 6304 r_dcache_clack_set = clack_set & ((1ULL<<(uint32_log2(m_dcache_sets)))-1); 6305 dspin_clack_get = true; 6306 } 6307 6308 // CLACK INST: Send request to ICACHE FSM 6309 else if (icache_clack_request and not r_icache_clack_req.read()){ 6310 r_icache_clack_req = true; 6311 r_icache_clack_way = clack_way & ((1ULL<<(uint32_log2(m_dcache_ways)))-1); 6312 r_icache_clack_set = clack_set & ((1ULL<<(uint32_log2(m_icache_sets)))-1); 6313 dspin_clack_get = true; 6314 } 6315 } 6316 else 6317 { 6318 dspin_clack_get = true; 6319 } 6320 6321 if (dspin_clack_get) 6322 { 6323 r_dspin_clack_req = p_dspin_clack.write.read(); 6324 r_dspin_clack_flit = p_dspin_clack.data.read(); 6325 } 6244 6326 6245 6327 ///////////////// Response FIFOs update ////////////////////// … … 6447 6529 case CC_SEND_IDLE: 6448 6530 { 6449 p_dspin_ out.write = false;6531 p_dspin_p2m.write = false; 6450 6532 break; 6451 6533 } … … 6454 6536 { 6455 6537 // initialize dspin send data 6538 // DspinDhccpParam::dspin_set(dspin_send_data, 6539 // 0, 6540 // DspinDhccpParam::P2M_EOP); 6456 6541 DspinDhccpParam::dspin_set(dspin_send_data, 6457 6542 m_cc_global_id, … … 6459 6544 DspinDhccpParam::dspin_set(dspin_send_data, 6460 6545 0, 6461 DspinDhccpParam:: FROM_L1_BC);6546 DspinDhccpParam::P2M_BC); 6462 6547 6463 6548 if(r_cc_send_last_client.read() == 0) // dcache active request … … 6480 6565 DspinDhccpParam::dspin_set(dspin_send_data, 6481 6566 DspinDhccpParam::TYPE_CLEANUP_DATA, 6482 DspinDhccpParam:: FROM_L1_TYPE);6567 DspinDhccpParam::P2M_TYPE); 6483 6568 /*ODCCP*/ // If cleanup on NCC line we set the CLEANUP_NCC bit in cleanup flit 6484 6569 if (r_dcache_cleanup_ncc.read()) … … 6516 6601 DspinDhccpParam::dspin_set(dspin_send_data, 6517 6602 DspinDhccpParam::TYPE_CLEANUP_INST, 6518 DspinDhccpParam:: FROM_L1_TYPE);6603 DspinDhccpParam::P2M_TYPE); 6519 6604 6520 6605 DspinDhccpParam::dspin_set(dspin_send_data, … … 6523 6608 } 6524 6609 // send flit 6525 p_dspin_ out.data = dspin_send_data;6526 p_dspin_ out.write = true;6527 p_dspin_ out.eop = false;6610 p_dspin_p2m.data = dspin_send_data; 6611 p_dspin_p2m.write = true; 6612 p_dspin_p2m.eop = false; 6528 6613 break; 6529 6614 } … … 6535 6620 if (r_dcache_cc_cleanup_updt_data.read() and not r_cc_send_last_client.read()) 6536 6621 { 6537 p_dspin_ out.eop = false;6622 p_dspin_p2m.eop = false; 6538 6623 } 6539 6624 else 6540 6625 { 6541 p_dspin_ out.eop = true;6626 p_dspin_p2m.eop = true; 6542 6627 } 6543 6628 … … 6555 6640 } 6556 6641 // send flit 6557 p_dspin_ out.data = dspin_send_data;6558 p_dspin_ out.write = true;6642 p_dspin_p2m.data = dspin_send_data; 6643 p_dspin_p2m.write = true; 6559 6644 break; 6560 6645 } … … 6564 6649 if (r_cc_send_cpt_word.read() == m_dcache_words-1) /*ODCCP*/ // Last flit sent 6565 6650 { 6566 p_dspin_ out.eop = true;6651 p_dspin_p2m.eop = true; 6567 6652 } 6568 6653 else 6569 6654 { 6570 p_dspin_ out.eop = false;6655 p_dspin_p2m.eop = false; 6571 6656 } 6572 6657 … … 6575 6660 DspinDhccpParam::CLEANUP_DATA_UPDT); 6576 6661 6577 p_dspin_out.data = dspin_send_data; 6578 p_dspin_out.write = true; 6662 p_dspin_p2m.data = dspin_send_data; 6663 //p_dspin_p2m.write = true; 6664 if(r_cc_send_data_fifo.rok()) 6665 p_dspin_p2m.write = true; 6666 else 6667 p_dspin_p2m.write = false; 6579 6668 break; 6580 6669 } … … 6585 6674 // DspinDhccpParam::dspin_set(dspin_send_data, 6586 6675 // 1, 6587 // DspinDhccpParam:: FROM_L1_EOP);6676 // DspinDhccpParam::P2M_EOP); 6588 6677 DspinDhccpParam::dspin_set(dspin_send_data, 6589 6678 0, 6590 DspinDhccpParam:: FROM_L1_BC);6679 DspinDhccpParam::P2M_BC); 6591 6680 DspinDhccpParam::dspin_set(dspin_send_data, 6592 6681 DspinDhccpParam::TYPE_MULTI_ACK, 6593 DspinDhccpParam:: FROM_L1_TYPE);6682 DspinDhccpParam::P2M_TYPE); 6594 6683 6595 6684 if(r_cc_send_last_client.read() == 0) // dcache active request … … 6623 6712 } 6624 6713 // send flit 6625 p_dspin_ out.data = dspin_send_data;6626 p_dspin_ out.write = true;6627 p_dspin_ out.eop = true;6714 p_dspin_p2m.data = dspin_send_data; 6715 p_dspin_p2m.write = true; 6716 p_dspin_p2m.eop = true; 6628 6717 6629 6718 break; … … 6633 6722 // Receive coherence packets 6634 6723 // It depends on the CC_RECEIVE FSM 6635 6636 6724 switch( r_cc_receive_fsm.read() ) 6637 6725 { … … 6639 6727 case CC_RECEIVE_IDLE: 6640 6728 { 6641 p_dspin_in.read = false; 6642 break; 6643 } 6644 ////////////////////// 6645 case CC_RECEIVE_CLACK: 6646 { 6647 if (((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read())) or 6648 ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()))) 6649 p_dspin_in.read = true; 6650 else 6651 p_dspin_in.read = false; 6729 p_dspin_m2p.read = false; 6652 6730 break; 6653 6731 } … … 6655 6733 case CC_RECEIVE_BRDCAST_HEADER: 6656 6734 { 6657 p_dspin_ in.read = true;6735 p_dspin_m2p.read = true; 6658 6736 break; 6659 6737 } … … 6665 6743 // flip_flop to check that ? 6666 6744 if (not (r_cc_receive_icache_req.read()) and not (r_cc_receive_dcache_req.read())) 6667 p_dspin_ in.read = true;6745 p_dspin_m2p.read = true; 6668 6746 else 6669 p_dspin_ in.read = false;6747 p_dspin_m2p.read = false; 6670 6748 break; 6671 6749 } 6672 6750 ///////////////////////////// 6673 case CC_RECEIVE_INVAL_HEADER: 6674 { 6675 if (((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read())) or 6676 ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()))) 6677 p_dspin_in.read = true; 6751 case CC_RECEIVE_DATA_INVAL_HEADER: 6752 case CC_RECEIVE_INS_INVAL_HEADER: 6753 { 6754 p_dspin_m2p.read = true; 6755 break; 6756 } 6757 //////////////////////////// 6758 case CC_RECEIVE_DATA_INVAL_NLINE: 6759 { 6760 p_dspin_m2p.read = not r_cc_receive_dcache_req.read(); 6761 break; 6762 } 6763 case CC_RECEIVE_INS_INVAL_NLINE: 6764 { 6765 p_dspin_m2p.read = not r_cc_receive_icache_req.read(); 6766 break; 6767 } 6768 /////////////////////////// 6769 case CC_RECEIVE_DATA_UPDT_HEADER: 6770 { 6771 if (not r_cc_receive_dcache_req.read()) 6772 p_dspin_m2p.read = true; 6678 6773 else 6679 p_dspin_ in.read = false;6774 p_dspin_m2p.read = false; 6680 6775 break; 6681 6776 } 6682 6777 //////////////////////////// 6683 case CC_RECEIVE_INVAL_NLINE: 6684 { 6685 p_dspin_in.read = true; 6686 break; 6687 } 6688 //////////////////////////// 6689 case CC_RECEIVE_UPDT_HEADER: 6690 { 6691 if (((r_cc_receive_data_ins.read() == 0) and 6692 not r_cc_receive_dcache_req.read() and 6693 r_cc_receive_updt_fifo_be.empty()) 6694 or 6695 (((r_cc_receive_data_ins.read() == 1) and 6696 not r_cc_receive_icache_req.read()) and 6697 r_cc_receive_updt_fifo_be.empty())) 6698 p_dspin_in.read = true; 6778 case CC_RECEIVE_INS_UPDT_HEADER: 6779 { 6780 if ( not r_cc_receive_icache_req.read()) 6781 p_dspin_m2p.read = true; 6699 6782 else 6700 p_dspin_ in.read = false;6783 p_dspin_m2p.read = false; 6701 6784 break; 6702 6785 } 6703 6786 /////////////////////////// 6704 case CC_RECEIVE_UPDT_NLINE: 6705 { 6706 if (((r_cc_receive_data_ins.read() == 0) and 6707 not (r_cc_receive_dcache_req.read()) and 6708 r_cc_receive_updt_fifo_be.empty()) 6709 or 6710 ((r_cc_receive_data_ins.read() == 1) and 6711 not (r_cc_receive_icache_req.read()) and 6712 r_cc_receive_updt_fifo_be.empty())) 6713 p_dspin_in.read = true; 6787 case CC_RECEIVE_DATA_UPDT_NLINE: 6788 case CC_RECEIVE_INS_UPDT_NLINE: 6789 { 6790 if(r_cc_receive_updt_fifo_be.empty()) 6791 p_dspin_m2p.read = true; 6714 6792 else 6715 p_dspin_in.read = false; 6716 break; 6717 } 6718 ////////////////////////// 6719 case CC_RECEIVE_UPDT_DATA: 6793 p_dspin_m2p.read = false; 6794 break; 6795 } 6796 /////////////////////////// 6797 case CC_RECEIVE_DATA_UPDT_DATA: 6798 case CC_RECEIVE_INS_UPDT_DATA: 6720 6799 { 6721 6800 if (r_cc_receive_updt_fifo_be.wok()) 6722 p_dspin_ in.read = true;6801 p_dspin_m2p.read = true; 6723 6802 else 6724 p_dspin_ in.read = false;6803 p_dspin_m2p.read = false; 6725 6804 break; 6726 6805 } 6727 6806 } // end switch CC_RECEIVE FSM 6728 6807 6808 6809 int clack_type = DspinDhccpParam::dspin_get(r_dspin_clack_flit.read(), 6810 DspinDhccpParam::CLACK_TYPE); 6811 6812 bool dspin_clack_get = false; 6813 bool dcache_clack_request = (clack_type == DspinDhccpParam::TYPE_CLACK_DATA); 6814 bool icache_clack_request = (clack_type == DspinDhccpParam::TYPE_CLACK_INST); 6815 6816 if (r_dspin_clack_req.read()) 6817 { 6818 // CLACK DATA: wait if pending request to DCACHE FSM 6819 if (dcache_clack_request and not r_dcache_clack_req.read()) 6820 { 6821 dspin_clack_get = true; 6822 } 6823 6824 // CLACK INST: wait if pending request to ICACHE FSM 6825 else if (icache_clack_request and not r_icache_clack_req.read()) 6826 { 6827 dspin_clack_get = true; 6828 } 6829 } 6830 else 6831 { 6832 dspin_clack_get = true; 6833 } 6834 6835 p_dspin_clack.read = dspin_clack_get; 6729 6836 } // end genMoore 6730 6837 -
branches/ODCCP/modules/vci_mem_cache
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branches/ODCCP/modules/vci_mem_cache/caba/metadata/vci_mem_cache.sd
r434 r479 49 49 Port('caba:vci_initiator', 'p_vci_ixr'), 50 50 Port('caba:dspin_input', 51 'p_dspin_ in',51 'p_dspin_p2m', 52 52 dspin_data_size = parameter.Reference('dspin_in_width') 53 53 ), 54 54 Port('caba:dspin_output', 55 'p_dspin_out', 55 'p_dspin_m2p', 56 dspin_data_size = parameter.Reference('dspin_out_width') 57 ), 58 Port('caba:dspin_output', 59 'p_dspin_clack', 56 60 dspin_data_size = parameter.Reference('dspin_out_width') 57 61 ), -
branches/ODCCP/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h
r460 r479 54 54 #define TRT_ENTRIES 4 // Number of entries in TRT 55 55 #define UPT_ENTRIES 4 // Number of entries in UPT 56 #define IVT_ENTRIES 4 // Number of entries in IVT 56 57 #define HEAP_ENTRIES 1024 // Number of entries in HEAP 57 58 … … 122 123 CC_SEND_WRITE_IDLE, 123 124 CC_SEND_CAS_IDLE, 124 CC_SEND_CLEANUP_IDLE,125 125 CC_SEND_CONFIG_INVAL_HEADER, 126 126 CC_SEND_CONFIG_INVAL_NLINE, 127 127 CC_SEND_CONFIG_BRDCAST_HEADER, 128 128 CC_SEND_CONFIG_BRDCAST_NLINE, 129 CC_SEND_CLEANUP_ACK,130 129 CC_SEND_XRAM_RSP_BRDCAST_HEADER, 131 130 CC_SEND_XRAM_RSP_BRDCAST_NLINE, … … 163 162 CONFIG_DIR_REQ, 164 163 CONFIG_DIR_ACCESS, 165 CONFIG_DIR_ UPT_LOCK,164 CONFIG_DIR_IVT_LOCK, 166 165 CONFIG_BC_SEND, 167 166 CONFIG_BC_WAIT, … … 211 210 WRITE_MISS_XRAM_REQ, 212 211 WRITE_BC_TRT_LOCK, 213 WRITE_BC_ UPT_LOCK,212 WRITE_BC_IVT_LOCK, 214 213 WRITE_BC_DIR_INVAL, 215 214 WRITE_BC_CC_SEND, … … 255 254 IXR_CMD_XRAM_IDLE, 256 255 IXR_CMD_CLEANUP_IDLE, 256 IXR_CMD_TRT_LOCK, 257 257 IXR_CMD_READ, 258 258 IXR_CMD_WRITE, … … 276 276 CAS_UPT_NEXT, 277 277 CAS_BC_TRT_LOCK, 278 CAS_BC_ UPT_LOCK,278 CAS_BC_IVT_LOCK, 279 279 CAS_BC_DIR_INVAL, 280 280 CAS_BC_CC_SEND, … … 302 302 CLEANUP_HEAP_CLEAN, 303 303 CLEANUP_HEAP_FREE, 304 CLEANUP_ UPT_LOCK,305 CLEANUP_ UPT_DECREMENT,306 CLEANUP_ UPT_CLEAR,304 CLEANUP_IVT_LOCK, 305 CLEANUP_IVT_DECREMENT, 306 CLEANUP_IVT_CLEAR, 307 307 CLEANUP_WRITE_RSP, 308 308 CLEANUP_CONFIG_ACK, … … 332 332 ALLOC_TRT_XRAM_RSP, 333 333 ALLOC_TRT_IXR_RSP, 334 ALLOC_TRT_CLEANUP 334 ALLOC_TRT_CLEANUP, 335 ALLOC_TRT_IXR_CMD 335 336 }; 336 337 … … 338 339 enum alloc_upt_fsm_state_e 339 340 { 340 ALLOC_UPT_CONFIG,341 341 ALLOC_UPT_WRITE, 342 ALLOC_UPT_XRAM_RSP, 343 ALLOC_UPT_MULTI_ACK, 344 ALLOC_UPT_CLEANUP, 345 ALLOC_UPT_CAS 342 ALLOC_UPT_CAS, 343 ALLOC_UPT_MULTI_ACK 344 }; 345 346 /* States of the ALLOC_IVT fsm */ 347 enum alloc_ivt_fsm_state_e 348 { 349 ALLOC_IVT_WRITE, 350 ALLOC_IVT_XRAM_RSP, 351 ALLOC_IVT_CLEANUP, 352 ALLOC_IVT_CAS, 353 ALLOC_IVT_CONFIG 346 354 }; 347 355 … … 492 500 uint32_t m_cpt_cas_fsm_upt_used; // NB cycles UPT LOCK used 493 501 494 uint32_t m_cpt_ upt_unused; // NB cycles UPT LOCK unused502 uint32_t m_cpt_ivt_unused; // NB cycles UPT LOCK unused 495 503 496 504 uint32_t m_cpt_read_fsm_heap_lock; // wait HEAP LOCK … … 536 544 soclib::caba::VciTarget<vci_param_int> p_vci_tgt; 537 545 soclib::caba::VciInitiator<vci_param_ext> p_vci_ixr; 538 soclib::caba::DspinInput<dspin_in_width> p_dspin_in; 539 soclib::caba::DspinOutput<dspin_out_width> p_dspin_out; 546 soclib::caba::DspinInput<dspin_in_width> p_dspin_p2m; 547 soclib::caba::DspinOutput<dspin_out_width> p_dspin_m2p; 548 soclib::caba::DspinOutput<dspin_out_width> p_dspin_clack; 540 549 541 550 VciMemCache( … … 553 562 const size_t trt_lines=TRT_ENTRIES, 554 563 const size_t upt_lines=UPT_ENTRIES, 564 const size_t ivt_lines=IVT_ENTRIES, 555 565 const size_t debug_start_cycle=0, 556 566 const bool debug_ok=false ); … … 588 598 TransactionTab m_trt; // xram transaction table 589 599 uint32_t m_upt_lines; 590 UpdateTab m_upt; // pending update & invalidate 600 UpdateTab m_upt; // pending update 601 UpdateTab m_ivt; // pending invalidate 591 602 CacheDirectory m_cache_directory; // data cache directory 592 603 CacheData m_cache_data; // data array[set][way][word] … … 677 688 sc_signal<size_t> r_config_heap_next; // current pointer to scan HEAP 678 689 679 sc_signal<size_t> r_config_ upt_index; // UPT index690 sc_signal<size_t> r_config_ivt_index; // IVT index 680 691 681 692 // Buffer between CONFIG fsm and TGT_RSP fsm (send a done response to L1 cache) … … 866 877 sc_signal<size_t> r_cleanup_to_tgt_rsp_pktid; // transaction pktid 867 878 868 // Buffer between CLEANUP fsm and CC_SEND fsm (acknowledge a cleanup command from L1)869 sc_signal<bool> r_cleanup_to_cc_send_req; // valid request870 sc_signal<size_t> r_cleanup_to_cc_send_srcid; // L1 srcid871 sc_signal<size_t> r_cleanup_to_cc_send_set_index; // L1 set index872 sc_signal<size_t> r_cleanup_to_cc_send_way_index; // L1 way index873 sc_signal<bool> r_cleanup_to_cc_send_inst; // Instruction Cleanup Ack874 875 879 /////////////////////////////////////////////////////// 876 880 // Registers controlled by CAS fsm … … 960 964 sc_signal<size_t> r_xram_rsp_victim_ptr; // victim line pointer to the heap 961 965 sc_signal<data_t> * r_xram_rsp_victim_data; // victim line data 962 sc_signal<size_t> r_xram_rsp_ upt_index; // UPT entry index966 sc_signal<size_t> r_xram_rsp_ivt_index; // IVT entry index 963 967 sc_signal<size_t> r_xram_rsp_next_ptr; // Next pointer to the heap 964 968 … … 1041 1045 1042 1046 //////////////////////////////////////////////////// 1047 // Registers controlled by ALLOC_IVT fsm 1048 //////////////////////////////////////////////////// 1049 1050 sc_signal<int> r_alloc_ivt_fsm; 1051 1052 //////////////////////////////////////////////////// 1043 1053 // Registers controlled by ALLOC_HEAP fsm 1044 1054 //////////////////////////////////////////////////// … … 1056 1066 sc_signal<uint32_t> r_cleanup_pktid; 1057 1067 sc_signal<data_t> *r_cleanup_data; // buffer for saving data from cleanup 1068 sc_signal<data_t> *r_ixr_cmd_data; // buffer for saving data from cleanup 1058 1069 sc_signal<bool> r_cleanup_contains_data; 1059 1070 sc_signal<bool> r_cleanup_ncc; -
branches/ODCCP/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp
r474 r479 102 102 "CC_SEND_WRITE_IDLE", 103 103 "CC_SEND_CAS_IDLE", 104 "CC_SEND_CLEANUP_IDLE",105 104 "CC_SEND_CONFIG_INVAL_HEADER", 106 105 "CC_SEND_CONFIG_INVAL_NLINE", 107 106 "CC_SEND_CONFIG_BRDCAST_HEADER", 108 107 "CC_SEND_CONFIG_BRDCAST_NLINE", 109 "CC_SEND_CLEANUP_ACK",110 108 "CC_SEND_XRAM_RSP_BRDCAST_HEADER", 111 109 "CC_SEND_XRAM_RSP_BRDCAST_NLINE", … … 139 137 "CONFIG_DIR_REQ", 140 138 "CONFIG_DIR_ACCESS", 141 "CONFIG_DIR_ UPT_LOCK",139 "CONFIG_DIR_IVT_LOCK", 142 140 "CONFIG_BC_SEND", 143 141 "CONFIG_BC_WAIT", … … 183 181 "WRITE_MISS_XRAM_REQ", 184 182 "WRITE_BC_TRT_LOCK", 185 "WRITE_BC_ UPT_LOCK",183 "WRITE_BC_IVT_LOCK", 186 184 "WRITE_BC_DIR_INVAL", 187 185 "WRITE_BC_CC_SEND", … … 221 219 "IXR_CMD_XRAM_IDLE", 222 220 "IXR_CMD_CLEANUP_IDLE", 221 "IXR_CMD_TRT_LOCK", 223 222 "IXR_CMD_READ", 224 223 "IXR_CMD_WRITE", … … 240 239 "CAS_UPT_NEXT", 241 240 "CAS_BC_TRT_LOCK", 242 "CAS_BC_ UPT_LOCK",241 "CAS_BC_IVT_LOCK", 243 242 "CAS_BC_DIR_INVAL", 244 243 "CAS_BC_CC_SEND", … … 264 263 "CLEANUP_HEAP_CLEAN", 265 264 "CLEANUP_HEAP_FREE", 266 "CLEANUP_ UPT_LOCK",267 "CLEANUP_ UPT_DECREMENT",268 "CLEANUP_ UPT_CLEAR",265 "CLEANUP_IVT_LOCK", 266 "CLEANUP_IVT_DECREMENT", 267 "CLEANUP_IVT_CLEAR", 269 268 "CLEANUP_WRITE_RSP", 270 269 "CLEANUP_CONFIG_ACK", … … 290 289 "ALLOC_TRT_XRAM_RSP", 291 290 "ALLOC_TRT_IXR_RSP", 292 "ALLOC_TRT_CLEANUP" 291 "ALLOC_TRT_CLEANUP", 292 "ALLOC_TRT_IXR_CMD" 293 293 }; 294 294 const char *alloc_upt_fsm_str[] = … … 296 296 "ALLOC_UPT_CONFIG", 297 297 "ALLOC_UPT_WRITE", 298 "ALLOC_UPT_XRAM_RSP", 299 "ALLOC_UPT_MULTI_ACK", 300 "ALLOC_UPT_CLEANUP", 301 "ALLOC_UPT_CAS" 298 "ALLOC_UPT_CAS", 299 "ALLOC_UPT_MULTI_ACK" 300 }; 301 const char *alloc_ivt_fsm_str[] = 302 { 303 "ALLOC_IVT_WRITE", 304 "ALLOC_IVT_XRAM_RSP", 305 "ALLOC_IVT_CLEANUP", 306 "ALLOC_IVT_CAS", 307 "ALLOC_IVT_CONFIG" 302 308 }; 303 309 const char *alloc_heap_fsm_str[] = … … 339 345 const size_t trt_lines, // number of TRT entries 340 346 const size_t upt_lines, // number of UPT entries 347 const size_t ivt_lines, // number of IVT entries 341 348 const size_t debug_start_cycle, 342 349 const bool debug_ok) … … 350 357 p_vci_tgt( "p_vci_tgt" ), 351 358 p_vci_ixr( "p_vci_ixr" ), 352 p_dspin_in( "p_dspin_in" ), 353 p_dspin_out( "p_dspin_out" ), 359 p_dspin_p2m( "p_dspin_p2m" ), 360 p_dspin_m2p( "p_dspin_m2p" ), 361 p_dspin_clack( "p_dspin_clack" ), 354 362 355 363 m_seglist( mtp.getSegmentList(tgtid_d) ), … … 368 376 m_upt_lines(upt_lines), 369 377 m_upt(upt_lines), 378 m_ivt(ivt_lines), 370 379 m_cache_directory(nways, nsets, nwords, vci_param_int::N), 371 380 m_cache_data(nways, nsets, nwords), … … 459 468 r_alloc_trt_fsm("r_alloc_trt_fsm"), 460 469 r_alloc_upt_fsm("r_alloc_upt_fsm"), 470 r_alloc_ivt_fsm("r_alloc_ivt_fsm"), 461 471 r_alloc_heap_fsm("r_alloc_heap_fsm"), 462 472 r_alloc_heap_reset_cpt("r_alloc_heap_reset_cpt") … … 534 544 // Allocation for ODCCP 535 545 r_cleanup_data = new sc_signal<data_t>[nwords]; 546 r_ixr_cmd_data = new sc_signal<data_t>[nwords]; 536 547 r_cleanup_to_ixr_cmd_data = new sc_signal<data_t>[nwords]; 537 548 … … 641 652 << " | " << ixr_cmd_fsm_str[r_ixr_cmd_fsm.read()] 642 653 << " | " << ixr_rsp_fsm_str[r_ixr_rsp_fsm.read()] 643 << " | " << xram_rsp_fsm_str[r_xram_rsp_fsm ] << std::endl;654 << " | " << xram_rsp_fsm_str[r_xram_rsp_fsm.read()] << std::endl; 644 655 std::cout << " " << alloc_dir_fsm_str[r_alloc_dir_fsm.read()] 645 656 << " | " << alloc_trt_fsm_str[r_alloc_trt_fsm.read()] 646 657 << " | " << alloc_upt_fsm_str[r_alloc_upt_fsm.read()] 658 << " | " << alloc_ivt_fsm_str[r_alloc_ivt_fsm.read()] 647 659 << " | " << alloc_heap_fsm_str[r_alloc_heap_fsm.read()] << std::endl; 648 660 } … … 672 684 m_cpt_trt_rb = 0; 673 685 m_cpt_dir_unused = 0; 674 m_cpt_ upt_unused = 0;686 m_cpt_ivt_unused = 0; 675 687 m_cpt_heap_unused = 0; 676 688 m_cpt_trt_unused = 0; … … 771 783 << "- WAIT UPT LOCK in CAS_FSM = " << (double) m_cpt_cas_fsm_upt_lock/m_cpt_cas_fsm_n_upt_lock << std::endl 772 784 << "- NB CYCLES IN UPT LOCK in CAS_FSM = " << (double) m_cpt_cas_fsm_upt_used/m_cpt_cas_fsm_n_upt_lock << std::endl 773 << "- UPT UNUSED RATE = " << (double) m_cpt_upt_unused/m_cpt_cycles << std::endl << std::endl785 << "- IVT UNUSED RATE = " << (double) m_cpt_ivt_unused/m_cpt_cycles << std::endl << std::endl 774 786 775 787 << "- WAIT HEAP LOCK in READ_FSM = " << (double) m_cpt_read_fsm_heap_lock/m_cpt_read_fsm_n_heap_lock << std::endl … … 805 817 806 818 delete [] r_cleanup_data; 819 delete [] r_ixr_cmd_data; 807 820 delete [] r_cleanup_to_ixr_cmd_data; 808 821 } … … 833 846 r_alloc_trt_fsm = ALLOC_TRT_READ; 834 847 r_alloc_upt_fsm = ALLOC_UPT_WRITE; 848 r_alloc_ivt_fsm = ALLOC_IVT_XRAM_RSP; 835 849 r_ixr_rsp_fsm = IXR_RSP_IDLE; 836 850 r_xram_rsp_fsm = XRAM_RSP_IDLE; … … 845 859 m_trt.init(); 846 860 m_upt.init(); 861 m_ivt.init(); 847 862 m_llsc_table.init(); 848 863 … … 946 961 r_cleanup_contains_data = false; 947 962 r_cleanup_to_ixr_cmd_req = false; 948 r_cleanup_to_ixr_cmd_l1_dirty_ncc = false;949 r_xram_rsp_to_ixr_cmd_inval_ncc_pending = false;963 //r_cleanup_to_ixr_cmd_l1_dirty_ncc = false; 964 //r_xram_rsp_to_ixr_cmd_inval_ncc_pending = false; 950 965 r_cleanup_to_ixr_cmd_srcid = 0; 951 966 r_cleanup_to_ixr_cmd_trdid = 0; … … 956 971 r_cleanup_to_ixr_cmd_data[word] = 0; 957 972 r_cleanup_data[word] = 0; 973 r_ixr_cmd_data[word] = 0; 958 974 } 959 975 … … 980 996 m_cpt_trt_rb = 0; 981 997 m_cpt_dir_unused = 0; 982 m_cpt_ upt_unused = 0;998 m_cpt_ivt_unused = 0; 983 999 m_cpt_heap_unused = 0; 984 1000 m_cpt_trt_unused = 0; … … 1723 1739 r_config_dir_next_ptr = entry.ptr; 1724 1740 1725 r_config_fsm = CONFIG_DIR_ UPT_LOCK;1741 r_config_fsm = CONFIG_DIR_IVT_LOCK; 1726 1742 } 1727 1743 else if ( entry.valid and // hit & sync command … … 1752 1768 } 1753 1769 ///////////////////////// 1754 case CONFIG_DIR_ UPT_LOCK: // enter this state in case of INVAL command1755 // Try to get both DIR & UPT locks, and return1756 // to LOOP state if UPT full.1757 // Register inval in UPT, and invalidate the1758 // directory if UPT not full.1759 { 1760 if ( r_alloc_ upt_fsm.read() == ALLOC_UPT_CONFIG )1770 case CONFIG_DIR_IVT_LOCK: // enter this state in case of INVAL command 1771 // Try to get both DIR & IVT locks, and return 1772 // to LOOP state if IVT full. 1773 // Register inval in IVT, and invalidate the 1774 // directory if IVT not full. 1775 { 1776 if ( r_alloc_ivt_fsm.read() == ALLOC_IVT_CONFIG ) 1761 1777 { 1762 1778 size_t set = m_y[(addr_t)(r_config_address.read())]; … … 1772 1788 #if DEBUG_MEMC_CONFIG 1773 1789 if(m_debug) 1774 std::cout << " <MEMC " << name() << " CONFIG_DIR_ UPT_LOCK>"1790 std::cout << " <MEMC " << name() << " CONFIG_DIR_IVT_LOCK>" 1775 1791 << " No copies in L1 : inval DIR entry" << std::endl; 1776 1792 #endif 1777 1793 } 1778 else // try to register inval in UPT1794 else // try to register inval in IVT 1779 1795 { 1780 1796 bool wok = false; … … 1787 1803 size_t nb_copies = r_config_dir_count.read(); 1788 1804 1789 wok = m_ upt.set(false, // it's an inval transaction1805 wok = m_ivt.set(false, // it's an inval transaction 1790 1806 broadcast, 1791 1807 false, // no response required … … 1798 1814 index); 1799 1815 1800 if ( wok ) // UPT success => inval DIR slot1816 if ( wok ) // IVT success => inval DIR slot 1801 1817 { 1802 1818 m_cache_directory.inval( way, set ); 1803 r_config_ upt_index = index;1819 r_config_ivt_index = index; 1804 1820 if ( broadcast ) r_config_fsm = CONFIG_BC_SEND; 1805 1821 else r_config_fsm = CONFIG_INV_SEND; … … 1807 1823 #if DEBUG_MEMC_CONFIG 1808 1824 if(m_debug) 1809 std::cout << " <MEMC " << name() << " CONFIG_DIR_ UPT_LOCK>"1810 << " Inval DIR entry and register inval in UPT"1825 std::cout << " <MEMC " << name() << " CONFIG_DIR_IVT_LOCK>" 1826 << " Inval DIR entry and register inval in IVT" 1811 1827 << " : index = " << std::dec << index 1812 1828 << " / broadcast = " << broadcast << std::endl; 1813 1829 #endif 1814 1830 } 1815 else // UPT full => release both DIR and UPT locks1831 else // IVT full => release both DIR and IVT locks 1816 1832 { 1817 1833 r_config_fsm = CONFIG_LOOP; … … 1819 1835 #if DEBUG_MEMC_CONFIG 1820 1836 if(m_debug) 1821 std::cout << " <MEMC " << name() << " CONFIG_DIR_ UPT_LOCK>"1822 << " UPT full : release DIR & UPT locks and retry" << std::endl;1837 std::cout << " <MEMC " << name() << " CONFIG_DIR_IVT_LOCK>" 1838 << " IVT full : release DIR & IVT locks and retry" << std::endl; 1823 1839 #endif 1824 1840 } … … 1835 1851 r_config_to_cc_send_multi_req = false; 1836 1852 r_config_to_cc_send_brdcast_req = true; 1837 r_config_to_cc_send_trdid = r_config_ upt_index.read();1853 r_config_to_cc_send_trdid = r_config_ivt_index.read(); 1838 1854 r_config_to_cc_send_nline = m_nline[(addr_t)(r_config_address.read())]; 1839 1855 r_cleanup_to_config_ack = false; … … 1875 1891 r_config_to_cc_send_multi_req = true; 1876 1892 r_config_to_cc_send_brdcast_req = false; 1877 r_config_to_cc_send_trdid = r_config_ upt_index.read();1893 r_config_to_cc_send_trdid = r_config_ivt_index.read(); 1878 1894 r_config_to_cc_send_nline = m_nline[(addr_t)(r_config_address.read())]; 1879 1895 r_multi_ack_to_config_ack = false; … … 2037 2053 switch(r_read_fsm.read()) 2038 2054 { 2039 2040 2041 2055 /////////////// 2056 case READ_IDLE: // waiting a read request 2057 { 2042 2058 if(m_cmd_read_addr_fifo.rok()) 2043 2059 { 2044 2060 2045 2061 #if DEBUG_MEMC_READ 2046 if(m_debug)2047 std::cout << " <MEMC " << name() << " READ_IDLE> Read request"2048 << " : address = " << std::hex << m_cmd_read_addr_fifo.read()2049 << " / srcid = " << m_cmd_read_srcid_fifo.read()2050 << " / trdid = " << m_cmd_read_trdid_fifo.read()2051 << " / pktid = " << m_cmd_read_pktid_fifo.read()2052 << " / nwords = " << std::dec << m_cmd_read_length_fifo.read() << std::endl;2062 if(m_debug) 2063 std::cout << " <MEMC " << name() << " READ_IDLE> Read request" 2064 << " : address = " << std::hex << m_cmd_read_addr_fifo.read() 2065 << " / srcid = " << m_cmd_read_srcid_fifo.read() 2066 << " / trdid = " << m_cmd_read_trdid_fifo.read() 2067 << " / pktid = " << m_cmd_read_pktid_fifo.read() 2068 << " / nwords = " << std::dec << m_cmd_read_length_fifo.read() << std::endl; 2053 2069 #endif 2054 2070 r_read_fsm = READ_DIR_REQ; … … 2154 2170 2155 2171 { 2156 2157 2158 2159 2160 2161 2162 2163 2164 2165 2166 2167 2168 2169 2170 2171 2172 2173 2174 2172 if(r_alloc_dir_fsm.read() == ALLOC_DIR_READ) 2173 { 2174 // check if this is an instruction read, this means pktid is either 2175 // TYPE_READ_INS_UNC 0bX010 with TSAR encoding 2176 // TYPE_READ_INS_MISS 0bX011 with TSAR encoding 2177 bool inst_read = ((m_cmd_read_pktid_fifo.read() & 0x2) != 0); 2178 // check if this is a cached read, this means pktid is either 2179 // TYPE_READ_DATA_MISS 0bX001 with TSAR encoding 2180 // TYPE_READ_INS_MISS 0bX011 with TSAR encoding 2181 bool cached_read = (m_cmd_read_pktid_fifo.read() & 0x1); 2182 bool is_cnt = r_read_is_cnt.read(); 2183 2184 // read data in the cache 2185 size_t set = m_y[(addr_t)(m_cmd_read_addr_fifo.read())]; 2186 size_t way = r_read_way.read(); 2187 2188 m_cache_data.read_line(way, set, r_read_data); 2189 2190 if(m_monitor_ok) check_monitor( m_cmd_read_addr_fifo.read(), r_read_data[0], true); 2175 2191 2176 2192 // update the cache directory … … 2223 2239 2224 2240 #if DEBUG_MEMC_READ 2225 if(m_debug)2226 std::cout << " <MEMC " << name() << " READ_DIR_HIT> Update directory entry:"2227 << " addr = " << std::hex << m_cmd_read_addr_fifo.read()2228 << " / set = " << std::dec << set2229 << " / way = " << way2230 << " / owner_id = " << std::hex << entry.owner.srcid2231 << " / owner_ins = " << std::dec << entry.owner.inst2232 << " / count = " << entry.count2233 << " / is_cnt = " << entry.is_cnt << std::endl;2241 if(m_debug) 2242 std::cout << " <MEMC " << name() << " READ_DIR_HIT> Update directory entry:" 2243 << " addr = " << std::hex << m_cmd_read_addr_fifo.read() 2244 << " / set = " << std::dec << set 2245 << " / way = " << way 2246 << " / owner_id = " << std::hex << entry.owner.srcid 2247 << " / owner_ins = " << std::dec << entry.owner.inst 2248 << " / count = " << entry.count 2249 << " / is_cnt = " << entry.is_cnt << std::endl; 2234 2250 #endif 2235 2251 … … 2977 2993 2978 2994 wok = m_upt.set(true, // it's an update transaction 2979 false, 2980 true, 2981 false, 2995 false, // it's not a broadcast 2996 true, // response required 2997 false, // no acknowledge required 2982 2998 srcid, 2983 2999 trdid, … … 3139 3155 entry.owner.inst) // put the next srcid in the fifo 3140 3156 { 3141 dec_upt_counter 3157 dec_upt_counter = false; 3142 3158 write_to_cc_send_fifo_put = true; 3143 3159 write_to_cc_send_fifo_inst = entry.owner.inst; … … 3192 3208 { 3193 3209 r_write_to_cc_send_multi_req = true; 3194 if(r_write_to_dec.read() or dec_upt_counter) 3210 if(r_write_to_dec.read() or dec_upt_counter) r_write_fsm = WRITE_UPT_DEC; 3195 3211 else r_write_fsm = WRITE_IDLE; 3196 3212 } … … 3444 3460 { 3445 3461 r_write_trt_index = wok_index; 3446 r_write_fsm = WRITE_BC_ UPT_LOCK;3462 r_write_fsm = WRITE_BC_IVT_LOCK; 3447 3463 } 3448 3464 else // wait an empty entry in TRT … … 3465 3481 3466 3482 ////////////////////// 3467 case WRITE_BC_ UPT_LOCK: // register BC transaction in UPT3468 { 3469 if(r_alloc_ upt_fsm.read() == ALLOC_UPT_WRITE)3483 case WRITE_BC_IVT_LOCK: // register BC transaction in IVT 3484 { 3485 if(r_alloc_ivt_fsm.read() == ALLOC_IVT_WRITE) 3470 3486 { 3471 3487 bool wok = false; … … 3477 3493 size_t nb_copies = r_write_count.read(); 3478 3494 3479 wok = m_ upt.set(false, // it's an inval transaction3480 true, 3481 true, 3482 false, 3495 wok = m_ivt.set(false, // it's an inval transaction 3496 true, // it's a broadcast 3497 true, // response required 3498 false, // no acknowledge required 3483 3499 srcid, 3484 3500 trdid, … … 3489 3505 #if DEBUG_MEMC_WRITE 3490 3506 if( m_debug and wok ) 3491 std::cout << " <MEMC " << name() << " WRITE_BC_ UPT_LOCK> Register broadcast inval in UPT"3507 std::cout << " <MEMC " << name() << " WRITE_BC_IVT_LOCK> Register broadcast inval in IVT" 3492 3508 << " / nb_copies = " << r_write_count.read() << std::endl; 3493 3509 #endif … … 3495 3511 3496 3512 if(wok) r_write_fsm = WRITE_BC_DIR_INVAL; 3497 else 3513 else r_write_fsm = WRITE_WAIT; 3498 3514 m_cpt_write_fsm_n_upt_lock++; 3499 3515 } … … 3510 3526 // and invalidate the line in directory 3511 3527 if((r_alloc_trt_fsm.read() != ALLOC_TRT_WRITE) or 3512 (r_alloc_upt_fsm.read() != ALLOC_UPT_WRITE) or3513 3528 (r_alloc_ivt_fsm.read() != ALLOC_IVT_WRITE) or 3529 (r_alloc_dir_fsm.read() != ALLOC_DIR_WRITE)) 3514 3530 { 3515 3531 std::cout << "VCI_MEM_CACHE ERROR " << name() << " WRITE_BC_DIR_INVAL state" << std::endl; 3516 std::cout << "bad TRT, DIR, or UPT allocation" << std::endl;3532 std::cout << "bad TRT, DIR, or IVT allocation" << std::endl; 3517 3533 exit(0); 3518 3534 } … … 3636 3652 else if(r_cas_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_CAS; 3637 3653 else if(r_xram_rsp_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_XRAM; 3654 #if ODCCP_NON_INCLUSIVE 3638 3655 else if(r_cleanup_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_CLEANUP_DATA; 3656 #else 3657 else if(r_cleanup_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_TRT_LOCK; 3658 #endif 3639 3659 else if(r_read_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_READ; 3640 3660 break; … … 3643 3663 if(r_cas_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_CAS; 3644 3664 else if(r_xram_rsp_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_XRAM; 3665 #if ODCCP_NON_INCLUSIVE 3645 3666 else if(r_cleanup_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_CLEANUP_DATA; 3667 #else 3668 else if(r_cleanup_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_TRT_LOCK; 3669 #endif 3646 3670 else if(r_read_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_READ; 3647 3671 else if(r_write_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_WRITE; … … 3650 3674 case IXR_CMD_CAS_IDLE: 3651 3675 if(r_xram_rsp_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_XRAM; 3676 #if ODCCP_NON_INCLUSIVE 3652 3677 else if(r_cleanup_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_CLEANUP_DATA; 3678 #else 3679 else if(r_cleanup_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_TRT_LOCK; 3680 #endif 3653 3681 else if(r_read_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_READ; 3654 3682 else if(r_write_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_WRITE; … … 3657 3685 //////////////////////// 3658 3686 case IXR_CMD_XRAM_IDLE: 3687 #if ODCCP_NON_INCLUSIVE 3659 3688 if(r_cleanup_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_CLEANUP_DATA; 3689 #else 3690 if(r_cleanup_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_TRT_LOCK; 3691 #endif 3660 3692 else if(r_read_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_READ; 3661 3693 else if(r_write_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_WRITE; … … 3669 3701 else if(r_cas_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_CAS; 3670 3702 else if(r_xram_rsp_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_XRAM; 3703 #if ODCCP_NON_INCLUSIVE 3671 3704 else if(r_cleanup_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_CLEANUP_DATA; 3672 break; 3705 #else 3706 else if(r_cleanup_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_TRT_LOCK; 3707 #endif 3708 break; 3709 3710 ///////////////////// 3711 case IXR_CMD_TRT_LOCK: 3712 { 3713 TransactionTabEntry entry; 3714 3715 if(r_alloc_trt_fsm.read() != ALLOC_TRT_IXR_CMD) break; 3716 entry.copy( m_trt.read(r_cleanup_to_ixr_cmd_trdid.read())); 3717 for(size_t i=0; i < m_words; i++) 3718 { 3719 r_ixr_cmd_data[i] = entry.wdata[i]; 3720 } 3721 3722 r_ixr_cmd_fsm = IXR_CMD_CLEANUP_DATA; 3723 break; 3724 } 3725 3673 3726 ////////////////// // send a get from READ FSM 3674 3727 case IXR_CMD_READ: … … 3806 3859 r_ixr_cmd_fsm = IXR_CMD_CLEANUP_IDLE; 3807 3860 r_cleanup_to_ixr_cmd_req = false; 3808 r_xram_rsp_to_ixr_cmd_inval_ncc_pending = false;3861 //r_xram_rsp_to_ixr_cmd_inval_ncc_pending = false; 3809 3862 } 3810 3863 else … … 3990 4043 size_t ptr = r_xram_rsp_trt_index.read(); 3991 4044 size_t lines = m_trt_lines; 4045 3992 4046 for(size_t i=0 ; i<lines ; i++) 3993 4047 { … … 4081 4135 #else 4082 4136 /*ODCCP*/ //if victim is no coherent and there is an inval no coherent pending we wait 4083 if(!victim.coherent and r_xram_rsp_to_ixr_cmd_inval_ncc_pending.read())4137 /*if(!victim.coherent and r_xram_rsp_to_ixr_cmd_inval_ncc_pending.read()) 4084 4138 { 4085 4139 r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT; 4086 4140 } 4087 4141 else 4088 { 4142 {*/ 4089 4143 r_xram_rsp_fsm = XRAM_RSP_INVAL_LOCK; 4090 4144 //} 4091 4145 #endif 4092 4146 } … … 4102 4156 << " way = " << std::dec << way 4103 4157 << " / set = " << set 4158 << " / victim coherent = " << victim.coherent 4159 << " / victim owner id = " << victim.owner.srcid 4104 4160 << " / inval_required = " << inval << std::endl; 4105 4161 #endif … … 4114 4170 } 4115 4171 ///////////////////////// 4116 case XRAM_RSP_INVAL_LOCK: // Take the UPT lock to check a possible pending inval4117 { 4118 if(r_alloc_ upt_fsm == ALLOC_UPT_XRAM_RSP)4172 case XRAM_RSP_INVAL_LOCK: // Take the IVT lock to check a possible pending inval 4173 { 4174 if(r_alloc_ivt_fsm == ALLOC_IVT_XRAM_RSP) 4119 4175 { 4120 4176 size_t index = 0; 4121 if(m_ upt.search_inval(r_xram_rsp_trt_buf.nline, index)) // pending inval4177 if(m_ivt.search_inval(r_xram_rsp_trt_buf.nline, index)) // pending inval 4122 4178 { 4123 4179 r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT; … … 4126 4182 if(m_debug) 4127 4183 std::cout << " <MEMC " << name() << " XRAM_RSP_INVAL_LOCK>" 4128 << " Get acces to UPT, but line invalidation registered"4184 << " Get acces to IVT, but line invalidation registered" 4129 4185 << " / nline = " << std::hex << r_xram_rsp_trt_buf.nline 4130 4186 << " / index = " << std::dec << index << std::endl; … … 4132 4188 4133 4189 } 4134 else if(m_ upt.is_full() and r_xram_rsp_victim_inval.read()) // UPT full4190 else if(m_ivt.is_full() and r_xram_rsp_victim_inval.read()) // IVT full 4135 4191 { 4136 4192 r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT; … … 4139 4195 if(m_debug) 4140 4196 std::cout << " <MEMC " << name() << " XRAM_RSP_INVAL_LOCK>" 4141 << " Get acces to UPT, but inval required and UPT full" << std::endl;4197 << " Get acces to IVT, but inval required and IVT full" << std::endl; 4142 4198 #endif 4143 4199 } … … 4149 4205 if(m_debug) 4150 4206 std::cout << " <MEMC " << name() << " XRAM_RSP_INVAL_LOCK>" 4151 << " Get acces to UPT" << std::endl;4207 << " Get acces to IVT" << std::endl; 4152 4208 #endif 4153 4209 } … … 4173 4229 /////////////////////// 4174 4230 case XRAM_RSP_DIR_UPDT: // updates the cache (both data & directory) 4175 // and possibly set an inval request in UPT4231 // and possibly set an inval request in IVT 4176 4232 { 4177 4233 // check if this is an instruction read, this means pktid is either … … 4241 4297 m_cache_directory.write(set, way, entry); 4242 4298 4243 // request an invalidation request in UPT for victim line4299 // request an invalidation request in IVT for victim line 4244 4300 if(r_xram_rsp_victim_inval.read()) 4245 4301 { … … 4247 4303 size_t index = 0; 4248 4304 size_t count_copies = r_xram_rsp_victim_count.read(); 4249 4250 bool wok = m_ upt.set(false, // it's an inval transaction4305 4306 bool wok = m_ivt.set(false, // it's an inval transaction 4251 4307 broadcast, // set broadcast bit 4252 4308 false, // no response required … … 4259 4315 index); 4260 4316 4261 r_xram_rsp_ upt_index = index;4317 r_xram_rsp_ivt_index = index; 4262 4318 4263 4319 if(!wok) 4264 4320 { 4265 4321 std::cout << "VCI_MEM_CACHE ERROR " << name() << " XRAM_RSP_DIR_UPDT" 4266 << " update_tab entry free but write unsuccessful" << std::endl;4322 << " invalidate_tab entry free but write unsuccessful" << std::endl; 4267 4323 exit(0); 4268 4324 } … … 4313 4369 if(r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP) 4314 4370 { 4315 m_trt.set(r_xram_rsp_trt_index.read(), 4371 std::vector<data_t> data_vector; 4372 data_vector.clear(); 4373 4374 for(size_t i=0; i<m_words; i++) 4375 { 4376 data_vector.push_back(r_xram_rsp_victim_data[i]); 4377 } 4378 /*m_trt.set(r_xram_rsp_trt_index.read(), 4316 4379 false, // write to XRAM 4317 4380 r_xram_rsp_victim_nline.read(), // line index … … 4323 4386 0, 4324 4387 std::vector<be_t> (m_words,0), 4325 std::vector<data_t> (m_words,0)); 4388 std::vector<data_t> (m_words,0));*/ 4389 4390 m_trt.set(r_xram_rsp_trt_index.read(), 4391 false, // write to XRAM 4392 r_xram_rsp_victim_nline.read(), // line index 4393 0, 4394 0, 4395 0, 4396 false, 4397 0, 4398 0, 4399 std::vector<be_t> (m_words,0), 4400 data_vector); 4326 4401 4327 4402 #if DEBUG_MEMC_XRAM_RSP … … 4395 4470 r_xram_rsp_to_cc_send_brdcast_req = r_xram_rsp_victim_is_cnt.read(); 4396 4471 r_xram_rsp_to_cc_send_nline = r_xram_rsp_victim_nline.read(); 4397 r_xram_rsp_to_cc_send_trdid = r_xram_rsp_ upt_index;4472 r_xram_rsp_to_cc_send_trdid = r_xram_rsp_ivt_index; 4398 4473 xram_rsp_to_cc_send_fifo_srcid = r_xram_rsp_victim_copy.read(); 4399 4474 xram_rsp_to_cc_send_fifo_inst = r_xram_rsp_victim_copy_inst.read(); … … 4427 4502 case XRAM_RSP_WRITE_DIRTY: // send a write request to IXR_CMD FSM 4428 4503 { 4429 if((!r_xram_rsp_to_ixr_cmd_req.read()) and (!r_xram_rsp_to_ixr_cmd_inval_ncc_pending.read()))4504 if((!r_xram_rsp_to_ixr_cmd_req.read()) /*and (!r_xram_rsp_to_ixr_cmd_inval_ncc_pending.read())*/) 4430 4505 { 4431 4506 … … 4443 4518 if( (!r_xram_rsp_victim_coherent.read()) and (r_xram_rsp_victim_count.read() == 1) ) 4444 4519 { 4445 r_xram_rsp_to_ixr_cmd_inval_ncc_pending = true; // inval no coherent pending4520 //r_xram_rsp_to_ixr_cmd_inval_ncc_pending = true; // inval no coherent pending 4446 4521 r_xram_rsp_to_ixr_cmd_req = false; 4447 4522 r_xram_rsp_fsm = XRAM_RSP_IDLE; … … 4633 4708 DspinDhccpParam::dspin_get( 4634 4709 flit, 4635 DspinDhccpParam:: FROM_L1_TYPE);4710 DspinDhccpParam::P2M_TYPE); 4636 4711 4637 4712 r_cleanup_way_index = … … 4689 4764 DspinDhccpParam::dspin_get(flit, DspinDhccpParam::CLEANUP_NLINE_LSB); 4690 4765 4691 bool eop = DspinDhccpParam::dspin_get(flit, DspinDhccpParam:: FROM_L1_EOP);4766 bool eop = DspinDhccpParam::dspin_get(flit, DspinDhccpParam::P2M_EOP); 4692 4767 4693 4768 /*ODCCP*/ // if not eop (more than 2 flits) there is a cleanup no coherent with data … … 4711 4786 std::cout << " <MEMC " << name() 4712 4787 << " CLEANUP_GET_NLINE> Cleanup request:" 4788 << " / ncc = " << r_cleanup_ncc.read() 4713 4789 << " / address = " << std::hex << nline * m_words * 4 << std::endl; 4714 4790 #endif … … 4819 4895 else // miss : check UPT for a pending invalidation transaction 4820 4896 { 4821 r_cleanup_fsm = CLEANUP_ UPT_LOCK;4897 r_cleanup_fsm = CLEANUP_IVT_LOCK; 4822 4898 } 4823 4899 … … 5289 5365 } 5290 5366 ////////////////////// 5291 case CLEANUP_ UPT_LOCK: // get the lock protecting the UPT to search a pending5367 case CLEANUP_IVT_LOCK: // get the lock protecting the IVT to search a pending 5292 5368 // invalidate transaction matching the cleanup 5293 5369 { 5294 5370 m_cpt_cleanup_fsm_upt_lock++; 5295 if(r_alloc_ upt_fsm.read() != ALLOC_UPT_CLEANUP) break;5371 if(r_alloc_ivt_fsm.read() != ALLOC_IVT_CLEANUP) break; 5296 5372 5297 5373 size_t index = 0; 5298 5374 bool match_inval; 5299 5375 5300 match_inval = m_ upt.search_inval(r_cleanup_nline.read(), index);5376 match_inval = m_ivt.search_inval(r_cleanup_nline.read(), index); 5301 5377 5302 5378 if ( not match_inval ) // no pending inval … … 5315 5391 if(m_debug) 5316 5392 std::cout << " <MEMC " << name() 5317 << " CLEANUP_ UPT_LOCK> Unexpected cleanup"5318 << " with no corresponding UPT entry:"5393 << " CLEANUP_IVT_LOCK> Unexpected cleanup" 5394 << " with no corresponding IVT entry:" 5319 5395 << " address = " << std::hex 5320 5396 << (r_cleanup_nline.read() *4*m_words) … … 5326 5402 5327 5403 // pending inval 5328 r_cleanup_write_srcid = m_ upt.srcid(index);5329 r_cleanup_write_trdid = m_ upt.trdid(index);5330 r_cleanup_write_pktid = m_ upt.pktid(index);5331 r_cleanup_need_rsp = m_ upt.need_rsp(index);5332 r_cleanup_need_ack = m_ upt.need_ack(index);5404 r_cleanup_write_srcid = m_ivt.srcid(index); 5405 r_cleanup_write_trdid = m_ivt.trdid(index); 5406 r_cleanup_write_pktid = m_ivt.pktid(index); 5407 r_cleanup_need_rsp = m_ivt.need_rsp(index); 5408 r_cleanup_need_ack = m_ivt.need_ack(index); 5333 5409 r_cleanup_index = index; 5334 5410 5335 r_cleanup_fsm = CLEANUP_ UPT_DECREMENT;5411 r_cleanup_fsm = CLEANUP_IVT_DECREMENT; 5336 5412 5337 5413 #if DEBUG_MEMC_CLEANUP 5338 5414 if(m_debug) 5339 5415 std::cout << " <MEMC " << name() 5340 << " CLEANUP_ UPT_LOCK> Cleanup matching pending"5341 << " invalidate transaction on UPT:"5416 << " CLEANUP_IVT_LOCK> Cleanup matching pending" 5417 << " invalidate transaction on IVT:" 5342 5418 << " address = " << std::hex << r_cleanup_nline.read() * m_words * 4 5343 << " / upt_entry = " << index << std::endl;5419 << " / ivt_entry = " << index << std::endl; 5344 5420 #endif 5345 5421 break; 5346 5422 } 5347 5423 /////////////////////////// 5348 case CLEANUP_ UPT_DECREMENT: // decrement response counter in UPT matching entry5349 { 5350 if(r_alloc_ upt_fsm.read() != ALLOC_UPT_CLEANUP)5424 case CLEANUP_IVT_DECREMENT: // decrement response counter in IVT matching entry 5425 { 5426 if(r_alloc_ivt_fsm.read() != ALLOC_IVT_CLEANUP) 5351 5427 { 5352 5428 std::cout 5353 5429 << "VCI_MEM_CACHE ERROR " << name() 5354 << " CLEANUP_ UPT_DECREMENT state" << std::endl5355 << "Bad UPT allocation"5430 << " CLEANUP_IVT_DECREMENT state" << std::endl 5431 << "Bad IVT allocation" 5356 5432 << std::endl; 5357 5433 … … 5360 5436 5361 5437 size_t count = 0; 5362 m_ upt.decrement(r_cleanup_index.read(), count);5438 m_ivt.decrement(r_cleanup_index.read(), count); 5363 5439 5364 5440 if(count == 0) // multi inval transaction completed 5365 5441 { 5366 r_cleanup_fsm = CLEANUP_ UPT_CLEAR;5442 r_cleanup_fsm = CLEANUP_IVT_CLEAR; 5367 5443 } 5368 5444 else // multi inval transaction not completed … … 5381 5457 #if DEBUG_MEMC_CLEANUP 5382 5458 if(m_debug) 5383 std::cout << " <MEMC " << name() << " CLEANUP_ UPT_DECREMENT>"5384 << " Decrement response counter in UPT:"5385 << " UPT_index = " << r_cleanup_index.read()5459 std::cout << " <MEMC " << name() << " CLEANUP_IVT_DECREMENT>" 5460 << " Decrement response counter in IVT:" 5461 << " IVT_index = " << r_cleanup_index.read() 5386 5462 << " / rsp_count = " << count << std::endl; 5387 5463 #endif … … 5389 5465 } 5390 5466 /////////////////////// 5391 case CLEANUP_ UPT_CLEAR: // Clear UPT entry5392 { 5393 if(r_alloc_ upt_fsm.read() != ALLOC_UPT_CLEANUP)5467 case CLEANUP_IVT_CLEAR: // Clear IVT entry 5468 { 5469 if(r_alloc_ivt_fsm.read() != ALLOC_IVT_CLEANUP) 5394 5470 { 5395 5471 std::cout 5396 5472 << "VCI_MEM_CACHE ERROR " << name() 5397 << " CLEANUP_ UPT_CLEAR state" << std::endl5398 << "Bad UPT allocation"5473 << " CLEANUP_IVT_CLEAR state" << std::endl 5474 << "Bad IVT allocation" 5399 5475 << std::endl; 5400 5476 … … 5402 5478 } 5403 5479 5404 m_ upt.clear(r_cleanup_index.read());5480 m_ivt.clear(r_cleanup_index.read()); 5405 5481 5406 5482 if ( r_cleanup_need_rsp.read() ) r_cleanup_fsm = CLEANUP_WRITE_RSP; … … 5412 5488 if(m_debug) 5413 5489 std::cout << " <MEMC " << name() 5414 << " CLEANUP_ UPT_CLEAR> Clear entry in UPT:"5415 << " UPT_index = " << r_cleanup_index.read() << std::endl;5490 << " CLEANUP_IVT_CLEAR> Clear entry in IVT:" 5491 << " IVT_index = " << r_cleanup_index.read() << std::endl; 5416 5492 #endif 5417 5493 break; … … 5487 5563 r_cleanup_to_ixr_cmd_pktid = r_cleanup_pktid.read(); 5488 5564 r_cleanup_to_ixr_cmd_nline = r_cleanup_nline.read(); 5489 r_cleanup_to_ixr_cmd_l1_dirty_ncc = true;5565 //r_cleanup_to_ixr_cmd_l1_dirty_ncc = true; 5490 5566 r_cleanup_fsm = CLEANUP_SEND_CLACK; 5491 5567 } … … 5505 5581 r_cleanup_to_ixr_cmd_req = true; 5506 5582 5507 for(size_t i = 0; i < m_words; i++){ 5508 r_cleanup_to_ixr_cmd_data[i] = r_cleanup_data[i]; 5583 if (r_cleanup_contains_data.read()) 5584 { 5585 std::vector<data_t> data_vector; 5586 data_vector.clear(); 5587 5588 for(size_t i=0; i<m_words; i++) 5589 { 5590 data_vector.push_back(r_cleanup_data[i]); 5591 } 5592 5593 m_trt.set(index, 5594 false, // write to XRAM 5595 r_cleanup_nline.read(), // line index 5596 0, 5597 0, 5598 0, 5599 false, 5600 0, 5601 0, 5602 std::vector<be_t> (m_words,0), 5603 data_vector); 5509 5604 } 5510 5511 5605 r_cleanup_to_ixr_cmd_srcid = r_cleanup_srcid.read(); 5512 5606 r_cleanup_to_ixr_cmd_trdid = index; 5513 5607 r_cleanup_to_ixr_cmd_pktid = r_cleanup_pktid.read(); 5514 5608 r_cleanup_to_ixr_cmd_nline = r_cleanup_nline.read(); 5515 r_cleanup_to_ixr_cmd_l1_dirty_ncc = r_cleanup_contains_data.read();5609 //r_cleanup_to_ixr_cmd_l1_dirty_ncc = r_cleanup_contains_data.read(); 5516 5610 r_cleanup_fsm = CLEANUP_SEND_CLACK; 5517 5611 #endif … … 5547 5641 5548 5642 //////////////////////// 5549 case CLEANUP_SEND_CLACK: // acknowledgement to a cleanup command 5550 // on the coherence network (request to the CC_SEND FSM). 5551 // wait if pending request to the CC_SEND FSM 5552 { 5553 if(r_cleanup_to_cc_send_req.read()) break; 5554 5555 r_cleanup_to_cc_send_req = true; 5556 r_cleanup_to_cc_send_set_index = r_cleanup_nline.read() & 0xFFFF; 5557 r_cleanup_to_cc_send_way_index = r_cleanup_way_index.read(); 5558 r_cleanup_to_cc_send_srcid = r_cleanup_srcid.read(); 5559 r_cleanup_to_cc_send_inst = r_cleanup_inst.read(); 5643 case CLEANUP_SEND_CLACK: // acknowledgement to a cleanup command 5644 // on the coherence CLACK network. 5645 { 5646 if(not p_dspin_clack.read) break; 5560 5647 5561 5648 r_cleanup_fsm = CLEANUP_IDLE; … … 5565 5652 std::cout << " <MEMC " << name() 5566 5653 << " CLEANUP_SEND_CLACK> Send the response to a cleanup request:" 5567 << " srcid = " << std::dec << r_cleanup_srcid.read() << std::endl; 5654 << " nline = " << std::hex << r_cleanup_nline.read() 5655 << " / way = " << std::dec << r_cleanup_way.read() 5656 << " / srcid = " << std::dec << r_cleanup_srcid.read() 5657 << std::endl; 5568 5658 #endif 5569 5659 break; … … 5804 5894 !r_cas_to_cc_send_brdcast_req.read()) 5805 5895 { 5806 r_cas_fsm = CAS_UPT_LOCK; // multi update required5896 r_cas_fsm = CAS_UPT_LOCK; // multi update required 5807 5897 } 5808 5898 else … … 6077 6167 { 6078 6168 r_cas_trt_index = wok_index; 6079 r_cas_fsm = CAS_BC_ UPT_LOCK;6169 r_cas_fsm = CAS_BC_IVT_LOCK; 6080 6170 } 6081 6171 else … … 6096 6186 } 6097 6187 ///////////////////// 6098 case CAS_BC_ UPT_LOCK: // register a broadcast inval transaction in UPT6188 case CAS_BC_IVT_LOCK: // register a broadcast inval transaction in IVT 6099 6189 // write data in cache in case of successful registration 6100 6190 { 6101 if(r_alloc_ upt_fsm.read() == ALLOC_UPT_CAS)6191 if(r_alloc_ivt_fsm.read() == ALLOC_IVT_CAS) 6102 6192 { 6103 6193 bool wok = false; … … 6109 6199 size_t nb_copies = r_cas_count.read(); 6110 6200 6111 // register a broadcast inval transaction in UPT6112 wok = m_ upt.set(false, // it's an inval transaction6113 true, 6114 true, 6115 false, 6201 // register a broadcast inval transaction in IVT 6202 wok = m_ivt.set(false, // it's an inval transaction 6203 true, // it's a broadcast 6204 true, // response required 6205 false, // no acknowledge required 6116 6206 srcid, 6117 6207 trdid, … … 6121 6211 index); 6122 6212 6123 if(wok) // UPT not full6213 if(wok) // IVT not full 6124 6214 { 6125 6215 // cache update … … 6147 6237 if(m_debug) 6148 6238 std::cout << " <MEMC " << name() 6149 << " CAS_BC_ UPT_LOCK> Register a broadcast inval transaction in UPT"6239 << " CAS_BC_IVT_LOCK> Register a broadcast inval transaction in IVT" 6150 6240 << " / nline = " << std::hex << nline 6151 6241 << " / count = " << std::dec << nb_copies 6152 << " / upt_index = " << index << std::endl;6153 #endif 6154 } 6155 else // releases the lock protecting UPT6242 << " / ivt_index = " << index << std::endl; 6243 #endif 6244 } 6245 else // releases the lock protecting IVT 6156 6246 { 6157 6247 r_cas_fsm = CAS_WAIT; … … 6168 6258 { 6169 6259 if((r_alloc_trt_fsm.read() == ALLOC_TRT_CAS) and 6170 (r_alloc_upt_fsm.read() == ALLOC_UPT_CAS) and6171 6260 (r_alloc_ivt_fsm.read() == ALLOC_IVT_CAS) and 6261 (r_alloc_dir_fsm.read() == ALLOC_DIR_CAS)) 6172 6262 { 6173 6263 // set TRT … … 6416 6506 // network, used to update or invalidate cache lines in L1 caches. 6417 6507 // 6418 // This fsm is used also to acknowledge CLEANUP a command after request from 6419 // the CLEANUP fsm. 6420 // 6421 // It implements a round-robin priority between the five possible client FSMs 6422 // XRAM_RSP > CAS > CLEANUP > WRITE > CONFIG 6508 // It implements a round-robin priority between the four possible client FSMs 6509 // XRAM_RSP > CAS > WRITE > CONFIG 6423 6510 // 6424 6511 // Each FSM can request the next services: … … 6432 6519 // r_config_to_cc_send_brdcast_req : broadcast-inval 6433 6520 // 6434 // - r_cleanup_to_cc_send_req : cleanup acknowledgement6435 //6436 6521 // An inval request is a double DSPIN flit command containing: 6437 6522 // 1. the index of the line to be invalidated. … … 6476 6561 break; 6477 6562 } 6478 // CLEANUP6479 if (r_cleanup_to_cc_send_req.read())6480 {6481 r_cc_send_fsm = CC_SEND_CLEANUP_ACK;6482 break;6483 }6484 6563 // WRITE 6485 6564 if(m_write_to_cc_send_inst_fifo.rok() or … … 6555 6634 break; 6556 6635 } 6557 // CLEANUP6558 if (r_cleanup_to_cc_send_req.read())6559 {6560 r_cc_send_fsm = CC_SEND_CLEANUP_ACK;6561 break;6562 }6563 6636 // WRITE 6564 6637 if(m_write_to_cc_send_inst_fifo.rok() or … … 6594 6667 break; 6595 6668 } 6596 // CLEANUP6597 if(r_cleanup_to_cc_send_req.read())6598 {6599 r_cc_send_fsm = CC_SEND_CLEANUP_ACK;6600 break;6601 }6602 6669 // WRITE 6603 6670 if(m_write_to_cc_send_inst_fifo.rok() or … … 6647 6714 case CC_SEND_CAS_IDLE: // CLEANUP FSM has highest priority 6648 6715 { 6649 if(r_cleanup_to_cc_send_req.read())6650 {6651 r_cc_send_fsm = CC_SEND_CLEANUP_ACK;6652 break;6653 }6654 6716 if(m_write_to_cc_send_inst_fifo.rok() or 6655 6717 r_write_to_cc_send_multi_req.read()) … … 6706 6768 break; 6707 6769 } 6708 //////////////////////////6709 case CC_SEND_CLEANUP_IDLE: // WRITE FSM has highest priority6710 {6711 // WRITE6712 if(m_write_to_cc_send_inst_fifo.rok() or6713 r_write_to_cc_send_multi_req.read())6714 {6715 r_cc_send_fsm = CC_SEND_WRITE_UPDT_HEADER;6716 m_cpt_update++;6717 break;6718 }6719 if(r_write_to_cc_send_brdcast_req.read())6720 {6721 r_cc_send_fsm = CC_SEND_WRITE_BRDCAST_HEADER;6722 m_cpt_inval++;6723 break;6724 }6725 // CONFIG6726 if(r_config_to_cc_send_multi_req.read())6727 {6728 r_cc_send_fsm = CC_SEND_CONFIG_INVAL_HEADER;6729 m_cpt_inval++;6730 break;6731 }6732 if(r_config_to_cc_send_brdcast_req.read())6733 {6734 r_cc_send_fsm = CC_SEND_CONFIG_BRDCAST_HEADER;6735 m_cpt_inval++;6736 break;6737 }6738 // XRAM_RSP6739 if(m_xram_rsp_to_cc_send_inst_fifo.rok() or6740 r_xram_rsp_to_cc_send_multi_req.read())6741 {6742 r_cc_send_fsm = CC_SEND_XRAM_RSP_INVAL_HEADER;6743 m_cpt_inval++;6744 break;6745 }6746 if(r_xram_rsp_to_cc_send_brdcast_req.read())6747 {6748 r_cc_send_fsm = CC_SEND_XRAM_RSP_BRDCAST_HEADER;6749 m_cpt_inval++;6750 break;6751 }6752 // CAS6753 if(m_cas_to_cc_send_inst_fifo.rok() or6754 r_cas_to_cc_send_multi_req.read())6755 {6756 r_cc_send_fsm = CC_SEND_CAS_UPDT_HEADER;6757 m_cpt_update++;6758 break;6759 }6760 if(r_cas_to_cc_send_brdcast_req.read())6761 {6762 r_cc_send_fsm = CC_SEND_CAS_BRDCAST_HEADER;6763 m_cpt_inval++;6764 break;6765 }6766 // CLEANUP6767 if(r_cleanup_to_cc_send_req.read())6768 {6769 r_cc_send_fsm = CC_SEND_CLEANUP_ACK;6770 break;6771 }6772 break;6773 }6774 6770 ///////////////////////////////// 6775 6771 case CC_SEND_CONFIG_INVAL_HEADER: // send first flit multi-inval (from CONFIG FSM) … … 6777 6773 if(m_config_to_cc_send_inst_fifo.rok()) 6778 6774 { 6779 if(not p_dspin_ out.read) break;6775 if(not p_dspin_m2p.read) break; 6780 6776 r_cc_send_fsm = CC_SEND_CONFIG_INVAL_NLINE; 6781 6777 break; … … 6788 6784 case CC_SEND_CONFIG_INVAL_NLINE: // send second flit multi-inval (from CONFIG FSM) 6789 6785 { 6790 if(not p_dspin_ out.read) break;6786 if(not p_dspin_m2p.read) break; 6791 6787 m_cpt_inval_mult++; 6792 6788 config_to_cc_send_fifo_get = true; … … 6804 6800 case CC_SEND_CONFIG_BRDCAST_HEADER: // send first flit BC-inval (from CONFIG FSM) 6805 6801 { 6806 if(not p_dspin_ out.read) break;6802 if(not p_dspin_m2p.read) break; 6807 6803 r_cc_send_fsm = CC_SEND_CONFIG_BRDCAST_NLINE; 6808 6804 break; … … 6811 6807 case CC_SEND_CONFIG_BRDCAST_NLINE: // send second flit BC-inval (from CONFIG FSM) 6812 6808 { 6813 if(not p_dspin_ out.read) break;6809 if(not p_dspin_m2p.read) break; 6814 6810 m_cpt_inval_brdcast++; 6815 6811 r_config_to_cc_send_brdcast_req = false; … … 6824 6820 break; 6825 6821 } 6826 /////////////////////////6827 case CC_SEND_CLEANUP_ACK: // send one flit for a cleanup acknowledgement6828 {6829 if(not p_dspin_out.read) break;6830 6831 r_cleanup_to_cc_send_req = false;6832 r_cc_send_fsm = CC_SEND_CLEANUP_IDLE;6833 6834 #if DEBUG_MEMC_CC_SEND6835 if(m_debug)6836 std::cout << " <MEMC " << name()6837 << " CC_SEND_CLEANUP_ACK> Cleanup Ack for srcid "6838 << std::hex << r_cleanup_to_cc_send_srcid.read() << std::endl;6839 #endif6840 break;6841 }6842 6822 /////////////////////////////////// 6843 6823 case CC_SEND_XRAM_RSP_INVAL_HEADER: // send first flit multi-inval (from XRAM_RSP FSM) … … 6845 6825 if(m_xram_rsp_to_cc_send_inst_fifo.rok()) 6846 6826 { 6847 if(not p_dspin_ out.read) break;6827 if(not p_dspin_m2p.read) break; 6848 6828 r_cc_send_fsm = CC_SEND_XRAM_RSP_INVAL_NLINE; 6849 6829 break; … … 6856 6836 case CC_SEND_XRAM_RSP_INVAL_NLINE: // send second flit multi-inval (from XRAM_RSP FSM) 6857 6837 { 6858 if(not p_dspin_ out.read) break;6838 if(not p_dspin_m2p.read) break; 6859 6839 m_cpt_inval_mult++; 6860 6840 xram_rsp_to_cc_send_fifo_get = true; … … 6864 6844 if(m_debug) 6865 6845 std::cout << " <MEMC " << name() 6866 << " CC_SEND_XRAM_RSP_INVAL_NLINE> BC-Inval for line "6846 << " CC_SEND_XRAM_RSP_INVAL_NLINE> Multicast-Inval for line " 6867 6847 << std::hex << r_xram_rsp_to_cc_send_nline.read() << std::endl; 6868 6848 #endif … … 6872 6852 case CC_SEND_XRAM_RSP_BRDCAST_HEADER: // send first flit broadcast-inval (from XRAM_RSP FSM) 6873 6853 { 6874 if(not p_dspin_ out.read) break;6854 if(not p_dspin_m2p.read) break; 6875 6855 r_cc_send_fsm = CC_SEND_XRAM_RSP_BRDCAST_NLINE; 6876 6856 break; … … 6879 6859 case CC_SEND_XRAM_RSP_BRDCAST_NLINE: // send second flit broadcast-inval (from XRAM_RSP FSM) 6880 6860 { 6881 if(not p_dspin_ out.read) break;6861 if(not p_dspin_m2p.read) break; 6882 6862 m_cpt_inval_brdcast++; 6883 6863 r_xram_rsp_to_cc_send_brdcast_req = false; … … 6895 6875 case CC_SEND_WRITE_BRDCAST_HEADER: // send first flit broadcast-inval (from WRITE FSM) 6896 6876 { 6897 if(not p_dspin_ out.read) break;6877 if(not p_dspin_m2p.read) break; 6898 6878 r_cc_send_fsm = CC_SEND_WRITE_BRDCAST_NLINE; 6899 6879 break; … … 6902 6882 case CC_SEND_WRITE_BRDCAST_NLINE: // send second flit broadcast-inval (from WRITE FSM) 6903 6883 { 6904 if(not p_dspin_ out.read) break;6884 if(not p_dspin_m2p.read) break; 6905 6885 6906 6886 m_cpt_inval_brdcast++; … … 6922 6902 if(m_write_to_cc_send_inst_fifo.rok()) 6923 6903 { 6924 if(not p_dspin_ out.read) break;6904 if(not p_dspin_m2p.read) break; 6925 6905 6926 6906 r_cc_send_fsm = CC_SEND_WRITE_UPDT_NLINE; … … 6939 6919 case CC_SEND_WRITE_UPDT_NLINE: // send second flit for a multi-update (from WRITE FSM) 6940 6920 { 6941 if(not p_dspin_ out.read) break;6921 if(not p_dspin_m2p.read) break; 6942 6922 m_cpt_update_mult++; 6943 6923 … … 6956 6936 case CC_SEND_WRITE_UPDT_DATA: // send N data flits for a multi-update (from WRITE FSM) 6957 6937 { 6958 if(not p_dspin_ out.read) break;6938 if(not p_dspin_m2p.read) break; 6959 6939 if(r_cc_send_cpt.read() == (r_write_to_cc_send_count.read()-1)) 6960 6940 { … … 6970 6950 case CC_SEND_CAS_BRDCAST_HEADER: // send first flit broadcast-inval (from CAS FSM) 6971 6951 { 6972 if(not p_dspin_ out.read) break;6952 if(not p_dspin_m2p.read) break; 6973 6953 r_cc_send_fsm = CC_SEND_CAS_BRDCAST_NLINE; 6974 6954 break; … … 6977 6957 case CC_SEND_CAS_BRDCAST_NLINE: // send second flit broadcast-inval (from CAS FSM) 6978 6958 { 6979 if(not p_dspin_ out.read) break;6959 if(not p_dspin_m2p.read) break; 6980 6960 m_cpt_inval_brdcast++; 6981 6961 … … 6996 6976 if(m_cas_to_cc_send_inst_fifo.rok()) 6997 6977 { 6998 if(not p_dspin_ out.read) break;6978 if(not p_dspin_m2p.read) break; 6999 6979 7000 6980 r_cc_send_fsm = CC_SEND_CAS_UPDT_NLINE; … … 7014 6994 case CC_SEND_CAS_UPDT_NLINE: // send second flit for a multi-update (from CAS FSM) 7015 6995 { 7016 if(not p_dspin_ out.read) break;6996 if(not p_dspin_m2p.read) break; 7017 6997 7018 6998 m_cpt_update_mult++; … … 7032 7012 case CC_SEND_CAS_UPDT_DATA: // send first data for a multi-update (from CAS FSM) 7033 7013 { 7034 if(not p_dspin_ out.read) break;7014 if(not p_dspin_m2p.read) break; 7035 7015 7036 7016 if(r_cas_to_cc_send_is_long.read()) … … 7047 7027 case CC_SEND_CAS_UPDT_DATA_HIGH: // send second data for a multi-update (from CAS FSM) 7048 7028 { 7049 if(not p_dspin_ out.read) break;7029 if(not p_dspin_m2p.read) break; 7050 7030 cas_to_cc_send_fifo_get = true; 7051 7031 r_cc_send_fsm = CC_SEND_CAS_UPDT_HEADER; … … 7067 7047 case CC_RECEIVE_IDLE: 7068 7048 { 7069 if(not p_dspin_ in.write) break;7049 if(not p_dspin_p2m.write) break; 7070 7050 7071 7051 uint8_t type = 7072 7052 DspinDhccpParam::dspin_get( 7073 p_dspin_ in.data.read(),7074 DspinDhccpParam:: FROM_L1_TYPE);7053 p_dspin_p2m.data.read(), 7054 DspinDhccpParam::P2M_TYPE); 7075 7055 7076 7056 if((type == DspinDhccpParam::TYPE_CLEANUP_DATA) or … … 7098 7078 // write first CLEANUP flit in CC_RECEIVE to CLEANUP fifo 7099 7079 7100 if(not p_dspin_ in.write or not m_cc_receive_to_cleanup_fifo.wok())7080 if(not p_dspin_p2m.write or not m_cc_receive_to_cleanup_fifo.wok()) 7101 7081 break; 7102 7082 7103 assert(not p_dspin_ in.eop.read() and7083 assert(not p_dspin_p2m.eop.read() and 7104 7084 "VCI_MEM_CACHE ERROR in CC_RECEIVE : " 7105 7085 "CLEANUP command must have two flits"); … … 7115 7095 // write second CLEANUP flit in CC_RECEIVE to CLEANUP fifo or more in case of cleanup data (ODCCP) 7116 7096 7117 if(not p_dspin_ in.write or not m_cc_receive_to_cleanup_fifo.wok())7097 if(not p_dspin_p2m.write or not m_cc_receive_to_cleanup_fifo.wok()) 7118 7098 break; 7119 7099 7120 /*assert(p_dspin_in.eop.read() and7121 "VCI_MEM_CACHE ERROR in CC_RECEIVE : "7122 "CLEANUP command must have two flits");*/7123 7124 7100 cc_receive_to_cleanup_fifo_put = true; 7125 if(p_dspin_ in.eop.read())7101 if(p_dspin_p2m.eop.read()) 7126 7102 r_cc_receive_fsm = CC_RECEIVE_IDLE; 7127 7103 … … 7135 7111 7136 7112 // wait for a WOK in the CC_RECEIVE to MULTI_ACK fifo 7137 if(not p_dspin_ in.write or not m_cc_receive_to_multi_ack_fifo.wok())7113 if(not p_dspin_p2m.write or not m_cc_receive_to_multi_ack_fifo.wok()) 7138 7114 break; 7139 7115 7140 assert(p_dspin_ in.eop.read() and7116 assert(p_dspin_p2m.eop.read() and 7141 7117 "VCI_MEM_CACHE ERROR in CC_RECEIVE : " 7142 7118 "MULTI_ACK command must have one flit"); … … 7548 7524 // ALLOC_UPT FSM 7549 7525 //////////////////////////////////////////////////////////////////////////////////// 7550 // The ALLOC_UPT FSM allocates the access to the Update/Inval Table (UPT), 7551 // with a round robin priority between six FSMs, with the following order: 7552 // CONFIG > MULTI_ACK > WRITE > XRAM_RSP > CLEANUP > CAS 7553 // - The CONFIG FSM initiates an inval transaction and sets a new entry in UPT. 7526 // The ALLOC_UPT FSM allocates the access to the Update Table (UPT), 7527 // with a round robin priority between three FSMs, with the following order: 7528 // WRITE -> CAS -> MULTI_ACK 7529 // - The WRITE FSM initiates update transaction and sets a new entry in UPT. 7530 // - The CAS FSM does the same thing as the WRITE FSM. 7554 7531 // - The MULTI_ACK FSM complete those trasactions and erase the UPT entry. 7555 // - The WRITE FSM initiates update transaction and sets a new entry in UPT.7556 // - The XRAM_RSP FSM initiates an inval transactions and sets a new entry in UPT.7557 // - The CLEANUP FSM decrement an entry in UPT.7558 // - The CAS FSM does the same thing as the WRITE FSM.7559 7532 // The resource is always allocated. 7560 7533 ///////////////////////////////////////////////////////////////////////////////////// 7561 7562 7534 switch(r_alloc_upt_fsm.read()) 7563 7535 { 7564 //////////////////////7565 case ALLOC_UPT_CONFIG: // allocated to CONFIG FSM7566 if (r_config_fsm.read() != CONFIG_DIR_UPT_LOCK)7567 {7568 if(r_multi_ack_fsm.read() == MULTI_ACK_UPT_LOCK)7569 r_alloc_upt_fsm = ALLOC_UPT_MULTI_ACK;7570 7571 else if((r_write_fsm.read() == WRITE_UPT_LOCK) or7572 (r_write_fsm.read() == WRITE_BC_UPT_LOCK))7573 r_alloc_upt_fsm = ALLOC_UPT_WRITE;7574 7575 else if(r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK)7576 r_alloc_upt_fsm = ALLOC_UPT_XRAM_RSP;7577 7578 else if(r_cleanup_fsm.read() == CLEANUP_UPT_LOCK)7579 r_alloc_upt_fsm = ALLOC_UPT_CLEANUP;7580 7581 else if((r_cas_fsm.read() == CAS_UPT_LOCK) or7582 (r_cas_fsm.read() == CAS_BC_UPT_LOCK))7583 r_alloc_upt_fsm = ALLOC_UPT_CAS;7584 }7585 break;7586 7587 7536 ///////////////////////// 7588 case ALLOC_UPT_MULTI_ACK: // allocated to MULTI_ACK FSM 7589 if( (r_multi_ack_fsm.read() != MULTI_ACK_UPT_LOCK) and 7590 (r_multi_ack_fsm.read() != MULTI_ACK_UPT_CLEAR)) 7591 { 7592 if((r_write_fsm.read() == WRITE_UPT_LOCK) or 7593 (r_write_fsm.read() == WRITE_BC_UPT_LOCK)) 7594 r_alloc_upt_fsm = ALLOC_UPT_WRITE; 7595 7596 else if(r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK) 7597 r_alloc_upt_fsm = ALLOC_UPT_XRAM_RSP; 7598 7599 else if(r_cleanup_fsm.read() == CLEANUP_UPT_LOCK) 7600 r_alloc_upt_fsm = ALLOC_UPT_CLEANUP; 7601 7602 else if((r_cas_fsm.read() == CAS_UPT_LOCK) or 7603 (r_cas_fsm.read() == CAS_BC_UPT_LOCK)) 7604 r_alloc_upt_fsm = ALLOC_UPT_CAS; 7605 else if(r_config_fsm.read() == CONFIG_DIR_UPT_LOCK) 7606 r_alloc_upt_fsm = ALLOC_UPT_CONFIG; 7607 else 7608 m_cpt_upt_unused++; 7609 } 7610 else 7611 m_cpt_multi_ack_fsm_upt_used++; 7612 break; 7613 7614 ///////////////////// 7615 case ALLOC_UPT_WRITE: // allocated to WRITE FSM 7616 if((r_write_fsm.read() != WRITE_UPT_LOCK) and 7617 (r_write_fsm.read() != WRITE_BC_UPT_LOCK)) 7618 { 7619 if(r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK) 7620 r_alloc_upt_fsm = ALLOC_UPT_XRAM_RSP; 7621 7622 else if(r_cleanup_fsm.read() == CLEANUP_UPT_LOCK) 7623 r_alloc_upt_fsm = ALLOC_UPT_CLEANUP; 7624 7625 else if((r_cas_fsm.read() == CAS_UPT_LOCK) or 7626 (r_cas_fsm.read() == CAS_BC_UPT_LOCK)) 7627 r_alloc_upt_fsm = ALLOC_UPT_CAS; 7628 7629 else if(r_config_fsm.read() == CONFIG_DIR_UPT_LOCK) 7630 r_alloc_upt_fsm = ALLOC_UPT_CONFIG; 7631 7632 else if(r_multi_ack_fsm.read() == MULTI_ACK_UPT_LOCK) 7633 r_alloc_upt_fsm = ALLOC_UPT_MULTI_ACK; 7634 7635 else 7636 m_cpt_upt_unused++; 7637 } 7638 else 7639 m_cpt_write_fsm_upt_used++; 7640 break; 7641 7642 //////////////////////// 7643 case ALLOC_UPT_XRAM_RSP: 7644 if(r_xram_rsp_fsm.read() != XRAM_RSP_INVAL_LOCK) 7645 { 7646 if(r_cleanup_fsm.read() == CLEANUP_UPT_LOCK) 7647 r_alloc_upt_fsm = ALLOC_UPT_CLEANUP; 7648 7649 else if((r_cas_fsm.read() == CAS_UPT_LOCK) or 7650 (r_cas_fsm.read() == CAS_BC_UPT_LOCK)) 7651 r_alloc_upt_fsm = ALLOC_UPT_CAS; 7652 7653 else if(r_config_fsm.read() == CONFIG_DIR_UPT_LOCK) 7654 r_alloc_upt_fsm = ALLOC_UPT_CONFIG; 7655 7656 else if(r_multi_ack_fsm.read() == MULTI_ACK_UPT_LOCK) 7657 r_alloc_upt_fsm = ALLOC_UPT_MULTI_ACK; 7658 7659 else if((r_write_fsm.read() == WRITE_UPT_LOCK) or 7660 (r_write_fsm.read() == WRITE_BC_UPT_LOCK)) 7661 r_alloc_upt_fsm = ALLOC_UPT_WRITE; 7662 7663 else 7664 m_cpt_upt_unused++; 7665 } 7666 else 7667 m_cpt_xram_rsp_fsm_upt_used++; 7668 break; 7669 7537 case ALLOC_UPT_WRITE: // allocated to WRITE FSM 7538 if (r_write_fsm.read() != WRITE_UPT_LOCK) 7539 { 7540 if (r_cas_fsm.read() == CAS_UPT_LOCK) 7541 r_alloc_upt_fsm = ALLOC_UPT_CAS; 7542 7543 else if (r_multi_ack_fsm.read() == MULTI_ACK_UPT_LOCK) 7544 r_alloc_upt_fsm = ALLOC_UPT_MULTI_ACK; 7545 } 7546 break; 7547 7548 ///////////////////////// 7549 case ALLOC_UPT_CAS: // allocated to CAS FSM 7550 if (r_cas_fsm.read() != CAS_UPT_LOCK) 7551 { 7552 if (r_multi_ack_fsm.read() == MULTI_ACK_UPT_LOCK) 7553 r_alloc_upt_fsm = ALLOC_UPT_MULTI_ACK; 7554 7555 else if (r_write_fsm.read() == WRITE_UPT_LOCK) 7556 r_alloc_upt_fsm = ALLOC_UPT_WRITE; 7557 } 7558 break; 7559 7560 ///////////////////////// 7561 case ALLOC_UPT_MULTI_ACK: // allocated to MULTI_ACK FSM 7562 if ((r_multi_ack_fsm.read() != MULTI_ACK_UPT_LOCK ) and 7563 (r_multi_ack_fsm.read() != MULTI_ACK_UPT_CLEAR)) 7564 { 7565 if (r_write_fsm.read() == WRITE_UPT_LOCK) 7566 r_alloc_upt_fsm = ALLOC_UPT_WRITE; 7567 7568 else if (r_cas_fsm.read() == CAS_UPT_LOCK) 7569 r_alloc_upt_fsm = ALLOC_UPT_CAS; 7570 } 7571 break; 7572 } // end switch r_alloc_upt_fsm 7573 7574 //////////////////////////////////////////////////////////////////////////////////// 7575 // ALLOC_IVT FSM 7576 //////////////////////////////////////////////////////////////////////////////////// 7577 // The ALLOC_IVT FSM allocates the access to the Invalidate Table (IVT), 7578 // with a round robin priority between five FSMs, with the following order: 7579 // WRITE -> XRAM_RSP -> CLEANUP -> CAS -> CONFIG 7580 // - The WRITE FSM initiates broadcast invalidate transactions and sets a new entry 7581 // in IVT. 7582 // - The CAS FSM does the same thing as the WRITE FSM. 7583 // - The XRAM_RSP FSM initiates broadcast/multicast invalidate transaction and sets 7584 // a new entry in the IVT 7585 // - The CONFIG FSM does the same thing as the XRAM_RSP FSM 7586 // - The CLEANUP FSM complete those trasactions and erase the IVT entry. 7587 // The resource is always allocated. 7588 ///////////////////////////////////////////////////////////////////////////////////// 7589 switch(r_alloc_ivt_fsm.read()) 7590 { 7670 7591 ////////////////////////// 7671 case ALLOC_UPT_CLEANUP: 7672 if((r_cleanup_fsm.read() != CLEANUP_UPT_LOCK ) and 7673 (r_cleanup_fsm.read() != CLEANUP_UPT_DECREMENT)) 7674 { 7675 if((r_cas_fsm.read() == CAS_UPT_LOCK) or 7676 (r_cas_fsm.read() == CAS_BC_UPT_LOCK)) 7677 r_alloc_upt_fsm = ALLOC_UPT_CAS; 7678 7679 else if(r_config_fsm.read() == CONFIG_DIR_UPT_LOCK) 7680 r_alloc_upt_fsm = ALLOC_UPT_CONFIG; 7681 7682 else if(r_multi_ack_fsm.read() == MULTI_ACK_UPT_LOCK) 7683 r_alloc_upt_fsm = ALLOC_UPT_MULTI_ACK; 7684 7685 else if((r_write_fsm.read() == WRITE_UPT_LOCK) or 7686 (r_write_fsm.read() == WRITE_BC_UPT_LOCK)) 7687 r_alloc_upt_fsm = ALLOC_UPT_WRITE; 7688 7689 else if(r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK) 7690 r_alloc_upt_fsm = ALLOC_UPT_XRAM_RSP; 7691 7692 else 7693 m_cpt_upt_unused++; 7694 } 7695 else 7696 m_cpt_cleanup_fsm_upt_used++; 7697 break; 7592 case ALLOC_IVT_WRITE: // allocated to WRITE FSM 7593 if (r_write_fsm.read() != WRITE_BC_IVT_LOCK) 7594 { 7595 if (r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK) 7596 r_alloc_ivt_fsm = ALLOC_IVT_XRAM_RSP; 7597 7598 else if (r_cleanup_fsm.read() == CLEANUP_IVT_LOCK) 7599 r_alloc_ivt_fsm = ALLOC_IVT_CLEANUP; 7600 7601 else if (r_cas_fsm.read() == CAS_BC_IVT_LOCK) 7602 r_alloc_ivt_fsm = ALLOC_IVT_CAS; 7603 7604 else if (r_config_fsm.read() == CONFIG_DIR_IVT_LOCK) 7605 r_alloc_ivt_fsm = ALLOC_IVT_CONFIG; 7606 7607 else 7608 m_cpt_ivt_unused++; 7609 } 7610 break; 7698 7611 7699 7612 ////////////////////////// 7700 case ALLOC_UPT_CAS: 7701 if((r_cas_fsm.read() != CAS_UPT_LOCK) and 7702 (r_cas_fsm.read() != CAS_BC_UPT_LOCK)) 7703 { 7704 if(r_config_fsm.read() == CONFIG_DIR_UPT_LOCK) 7705 r_alloc_upt_fsm = ALLOC_UPT_CONFIG; 7706 7707 else if(r_multi_ack_fsm.read() == MULTI_ACK_UPT_LOCK) 7708 r_alloc_upt_fsm = ALLOC_UPT_MULTI_ACK; 7709 7710 else if((r_write_fsm.read() == WRITE_UPT_LOCK) or 7711 (r_write_fsm.read() == WRITE_BC_UPT_LOCK)) 7712 r_alloc_upt_fsm = ALLOC_UPT_WRITE; 7713 7714 else if(r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK) 7715 r_alloc_upt_fsm = ALLOC_UPT_XRAM_RSP; 7716 7717 else if(r_cleanup_fsm.read() == CLEANUP_UPT_LOCK) 7718 r_alloc_upt_fsm = ALLOC_UPT_CLEANUP; 7719 7720 else 7721 m_cpt_upt_unused++; 7722 } 7723 else 7724 m_cpt_cas_fsm_upt_used++; 7725 break; 7726 7727 } // end switch r_alloc_upt_fsm 7613 case ALLOC_IVT_XRAM_RSP: // allocated to XRAM_RSP FSM 7614 if(r_xram_rsp_fsm.read() != XRAM_RSP_INVAL_LOCK) 7615 { 7616 if(r_cleanup_fsm.read() == CLEANUP_IVT_LOCK) 7617 r_alloc_ivt_fsm = ALLOC_IVT_CLEANUP; 7618 7619 else if (r_cas_fsm.read() == CAS_BC_IVT_LOCK) 7620 r_alloc_ivt_fsm = ALLOC_IVT_CAS; 7621 7622 else if (r_config_fsm.read() == CONFIG_DIR_IVT_LOCK) 7623 r_alloc_ivt_fsm = ALLOC_IVT_CONFIG; 7624 7625 else if (r_write_fsm.read() == WRITE_BC_IVT_LOCK) 7626 r_alloc_ivt_fsm = ALLOC_IVT_WRITE; 7627 7628 else 7629 m_cpt_ivt_unused++; 7630 } 7631 break; 7632 7633 ////////////////////////// 7634 case ALLOC_IVT_CLEANUP: // allocated to CLEANUP FSM 7635 if ((r_cleanup_fsm.read() != CLEANUP_IVT_LOCK ) and 7636 (r_cleanup_fsm.read() != CLEANUP_IVT_DECREMENT)) 7637 { 7638 if (r_cas_fsm.read() == CAS_BC_IVT_LOCK) 7639 r_alloc_ivt_fsm = ALLOC_IVT_CAS; 7640 7641 else if (r_config_fsm.read() == CONFIG_DIR_IVT_LOCK) 7642 r_alloc_ivt_fsm = ALLOC_IVT_CONFIG; 7643 7644 else if (r_write_fsm.read() == WRITE_BC_IVT_LOCK) 7645 r_alloc_ivt_fsm = ALLOC_IVT_WRITE; 7646 7647 else if (r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK) 7648 r_alloc_ivt_fsm = ALLOC_IVT_XRAM_RSP; 7649 7650 else 7651 m_cpt_ivt_unused++; 7652 } 7653 break; 7654 7655 ////////////////////////// 7656 case ALLOC_IVT_CAS: // allocated to CAS FSM 7657 if (r_cas_fsm.read() != CAS_BC_IVT_LOCK) 7658 { 7659 if (r_config_fsm.read() == CONFIG_DIR_IVT_LOCK) 7660 r_alloc_ivt_fsm = ALLOC_IVT_CONFIG; 7661 7662 else if (r_write_fsm.read() == WRITE_BC_IVT_LOCK) 7663 r_alloc_ivt_fsm = ALLOC_IVT_WRITE; 7664 7665 else if (r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK) 7666 r_alloc_ivt_fsm = ALLOC_IVT_XRAM_RSP; 7667 7668 else if (r_cleanup_fsm.read() == CLEANUP_IVT_LOCK) 7669 r_alloc_ivt_fsm = ALLOC_IVT_CLEANUP; 7670 7671 else 7672 m_cpt_ivt_unused++; 7673 } 7674 break; 7675 7676 ////////////////////////// 7677 case ALLOC_IVT_CONFIG: // allocated to CONFIG FSM 7678 if (r_config_fsm.read() != CONFIG_DIR_IVT_LOCK) 7679 { 7680 if (r_write_fsm.read() == WRITE_BC_IVT_LOCK) 7681 r_alloc_ivt_fsm = ALLOC_IVT_WRITE; 7682 7683 else if (r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK) 7684 r_alloc_ivt_fsm = ALLOC_IVT_XRAM_RSP; 7685 7686 else if (r_cleanup_fsm.read() == CLEANUP_IVT_LOCK) 7687 r_alloc_ivt_fsm = ALLOC_IVT_CLEANUP; 7688 7689 else if (r_cas_fsm.read() == CAS_BC_IVT_LOCK) 7690 r_alloc_ivt_fsm = ALLOC_IVT_CAS; 7691 7692 else 7693 m_cpt_ivt_unused++; 7694 } 7695 break; 7696 7697 } // end switch r_alloc_ivt_fsm 7728 7698 7729 7699 //////////////////////////////////////////////////////////////////////////////////// … … 7755 7725 if ( (r_config_fsm.read() != CONFIG_DIR_REQ) and 7756 7726 (r_config_fsm.read() != CONFIG_DIR_ACCESS) and 7757 (r_config_fsm.read() != CONFIG_DIR_ UPT_LOCK) )7727 (r_config_fsm.read() != CONFIG_DIR_IVT_LOCK) ) 7758 7728 { 7759 7729 if(r_read_fsm.read() == READ_DIR_REQ) … … 7813 7783 (r_write_fsm.read() != WRITE_DIR_HIT) and 7814 7784 (r_write_fsm.read() != WRITE_BC_TRT_LOCK) and 7815 (r_write_fsm.read() != WRITE_BC_ UPT_LOCK) and7785 (r_write_fsm.read() != WRITE_BC_IVT_LOCK) and 7816 7786 (r_write_fsm.read() != WRITE_MISS_TRT_LOCK) and 7817 7787 (r_write_fsm.read() != WRITE_UPT_LOCK) and … … 7854 7824 (r_cas_fsm.read() != CAS_DIR_HIT_WRITE) and 7855 7825 (r_cas_fsm.read() != CAS_BC_TRT_LOCK) and 7856 (r_cas_fsm.read() != CAS_BC_ UPT_LOCK) and7826 (r_cas_fsm.read() != CAS_BC_IVT_LOCK) and 7857 7827 (r_cas_fsm.read() != CAS_MISS_TRT_LOCK) and 7858 7828 (r_cas_fsm.read() != CAS_UPT_LOCK) and … … 7980 7950 r_alloc_trt_fsm = ALLOC_TRT_CLEANUP; 7981 7951 7952 else if (r_ixr_cmd_fsm.read() == IXR_CMD_TRT_LOCK) 7953 r_alloc_trt_fsm = ALLOC_TRT_IXR_CMD; 7954 7982 7955 else 7983 7956 m_cpt_trt_unused++; … … 7991 7964 if((r_write_fsm.read() != WRITE_MISS_TRT_LOCK) and 7992 7965 (r_write_fsm.read() != WRITE_BC_TRT_LOCK) and 7993 (r_write_fsm.read() != WRITE_BC_ UPT_LOCK))7966 (r_write_fsm.read() != WRITE_BC_IVT_LOCK)) 7994 7967 { 7995 7968 if((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) or … … 8007 7980 else if (r_cleanup_fsm.read() == CLEANUP_IXR_REQ) 8008 7981 r_alloc_trt_fsm = ALLOC_TRT_CLEANUP; 7982 7983 else if (r_ixr_cmd_fsm.read() == IXR_CMD_TRT_LOCK) 7984 r_alloc_trt_fsm = ALLOC_TRT_IXR_CMD; 8009 7985 8010 7986 else if(r_read_fsm.read() == READ_TRT_LOCK) … … 8022 7998 if((r_cas_fsm.read() != CAS_MISS_TRT_LOCK) and 8023 7999 (r_cas_fsm.read() != CAS_BC_TRT_LOCK) and 8024 (r_cas_fsm.read() != CAS_BC_ UPT_LOCK))8000 (r_cas_fsm.read() != CAS_BC_IVT_LOCK)) 8025 8001 { 8026 8002 if((r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) and … … 8034 8010 else if (r_cleanup_fsm.read() == CLEANUP_IXR_REQ) 8035 8011 r_alloc_trt_fsm = ALLOC_TRT_CLEANUP; 8012 8013 else if (r_ixr_cmd_fsm.read() == IXR_CMD_TRT_LOCK) 8014 r_alloc_trt_fsm = ALLOC_TRT_IXR_CMD; 8036 8015 8037 8016 else if(r_read_fsm.read() == READ_TRT_LOCK) … … 8063 8042 else if (r_cleanup_fsm.read() == CLEANUP_IXR_REQ) 8064 8043 r_alloc_trt_fsm = ALLOC_TRT_CLEANUP; 8044 8045 else if (r_ixr_cmd_fsm.read() == IXR_CMD_TRT_LOCK) 8046 r_alloc_trt_fsm = ALLOC_TRT_IXR_CMD; 8065 8047 8066 8048 else if(r_read_fsm.read() == READ_TRT_LOCK) … … 8090 8072 if (r_cleanup_fsm.read() == CLEANUP_IXR_REQ) 8091 8073 r_alloc_trt_fsm = ALLOC_TRT_CLEANUP; 8074 8075 else if (r_ixr_cmd_fsm.read() == IXR_CMD_TRT_LOCK) 8076 r_alloc_trt_fsm = ALLOC_TRT_IXR_CMD; 8092 8077 8093 8078 else if(r_read_fsm.read() == READ_TRT_LOCK) … … 8115 8100 //////////////////////// 8116 8101 case ALLOC_TRT_CLEANUP: 8117 if(r_ixr_rsp_fsm.read() != CLEANUP_IXR_REQ) 8118 { 8119 if(r_read_fsm.read() == READ_TRT_LOCK) 8102 if(r_cleanup_fsm.read() != CLEANUP_IXR_REQ) 8103 { 8104 if (r_ixr_cmd_fsm.read() == IXR_CMD_TRT_LOCK) 8105 r_alloc_trt_fsm = ALLOC_TRT_IXR_CMD; 8106 8107 else if(r_read_fsm.read() == READ_TRT_LOCK) 8120 8108 r_alloc_trt_fsm = ALLOC_TRT_READ; 8121 8109 … … 8138 8126 break; 8139 8127 8128 //////////////////////// 8129 case ALLOC_TRT_IXR_CMD: 8130 if(r_ixr_cmd_fsm.read() != IXR_CMD_TRT_LOCK) 8131 { 8132 if(r_read_fsm.read() == READ_TRT_LOCK) 8133 r_alloc_trt_fsm = ALLOC_TRT_READ; 8134 8135 else if((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) or 8136 (r_write_fsm.read() == WRITE_BC_TRT_LOCK)) 8137 r_alloc_trt_fsm = ALLOC_TRT_WRITE; 8138 8139 else if((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) or 8140 (r_cas_fsm.read() == CAS_BC_TRT_LOCK)) 8141 r_alloc_trt_fsm = ALLOC_TRT_CAS; 8142 8143 else if((r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) and 8144 (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP)) 8145 r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP; 8146 8147 else if((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) || 8148 (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ)) 8149 r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP; 8150 8151 else if (r_cleanup_fsm.read() == CLEANUP_IXR_REQ) 8152 r_alloc_trt_fsm = ALLOC_TRT_CLEANUP; 8153 } 8154 break; 8140 8155 } // end switch alloc_trt_fsm 8141 8156 … … 8406 8421 m_cc_receive_to_cleanup_fifo.update( cc_receive_to_cleanup_fifo_get, 8407 8422 cc_receive_to_cleanup_fifo_put, 8408 ( (uint64_t)(p_dspin_in.eop.read() & 0x1 ) << 32 ) | p_dspin_in.data.read() ); 8423 ( (uint64_t)(p_dspin_p2m.eop.read() & 0x1 ) << 32 ) | p_dspin_p2m.data.read() ); 8424 8409 8425 //////////////////////////////////////////////////////////////////////////////////// 8410 8426 // CC_RECEIVE to MULTI_ACK FIFO … … 8413 8429 m_cc_receive_to_multi_ack_fifo.update( cc_receive_to_multi_ack_fifo_get, 8414 8430 cc_receive_to_multi_ack_fifo_put, 8415 p_dspin_ in.data.read() );8431 p_dspin_p2m.data.read() ); 8416 8432 8417 8433 //////////////////////////////////////////////////////////////////////////////////// … … 8562 8578 p_vci_ixr.address = (addr_t)((r_cleanup_to_ixr_cmd_nline.read() * m_words + 8563 8579 r_ixr_cmd_cpt.read()) * 4); 8580 #if ODCCP_NON_INCLUSIVE 8581 p_vci_ixr.wdata = ((wide_data_t)(r_cleanup_to_ixr_cmd_data[r_ixr_cmd_cpt.read()].read()) | 8582 ((wide_data_t)(r_cleanup_to_ixr_cmd_data[r_ixr_cmd_cpt.read() + 1].read()) << 32)); 8583 #else 8584 p_vci_ixr.wdata = ((wide_data_t)(r_ixr_cmd_data[r_ixr_cmd_cpt.read()].read()) | 8585 ((wide_data_t)(r_ixr_cmd_data[r_ixr_cmd_cpt.read() + 1].read()) << 32)); 8586 #endif 8564 8587 8588 /* 8565 8589 if(r_cleanup_to_ixr_cmd_l1_dirty_ncc.read()) // if cleanup data contains data, we use cleanup_data buffer (cleanup dirty) 8566 8590 { … … 8573 8597 ((wide_data_t)(r_xram_rsp_to_ixr_cmd_data[r_ixr_cmd_cpt.read() + 1].read()) << 32)); 8574 8598 } 8575 8599 */ 8576 8600 p_vci_ixr.trdid = r_cleanup_to_ixr_cmd_trdid.read(); 8577 8601 p_vci_ixr.eop = (r_ixr_cmd_cpt == (m_words - 2)); … … 8777 8801 8778 8802 //////////////////////////////////////////////////////////////////// 8779 // p_dspin_ outport (CC_SEND FSM)8803 // p_dspin_m2p port (CC_SEND FSM) 8780 8804 //////////////////////////////////////////////////////////////////// 8781 8805 8782 p_dspin_ out.write = false;8783 p_dspin_ out.eop = false;8784 p_dspin_ out.data = 0;8806 p_dspin_m2p.write = false; 8807 p_dspin_m2p.eop = false; 8808 p_dspin_m2p.data = 0; 8785 8809 8786 8810 switch(r_cc_send_fsm.read()) … … 8791 8815 case CC_SEND_WRITE_IDLE: 8792 8816 case CC_SEND_CAS_IDLE: 8793 case CC_SEND_CLEANUP_IDLE:8794 8817 { 8795 8818 break; … … 8826 8849 DspinDhccpParam::dspin_set( flit, 8827 8850 multi_inval_type, 8828 DspinDhccpParam:: FROM_MC_TYPE);8829 p_dspin_ out.write = true;8830 p_dspin_ out.data = flit;8851 DspinDhccpParam::M2P_TYPE); 8852 p_dspin_m2p.write = true; 8853 p_dspin_m2p.data = flit; 8831 8854 break; 8832 8855 } … … 8838 8861 r_config_to_cc_send_nline.read(), 8839 8862 DspinDhccpParam::MULTI_INVAL_NLINE); 8840 p_dspin_ out.eop = true;8841 p_dspin_ out.write = true;8842 p_dspin_ out.data = flit;8863 p_dspin_m2p.eop = true; 8864 p_dspin_m2p.write = true; 8865 p_dspin_m2p.data = flit; 8843 8866 break; 8844 8867 } 8845 ////////////////////////8846 case CC_SEND_CLEANUP_ACK:8847 {8848 uint8_t cleanup_ack_type;8849 if(r_cleanup_to_cc_send_inst.read())8850 {8851 cleanup_ack_type = DspinDhccpParam::TYPE_CLEANUP_ACK_INST;8852 }8853 else8854 {8855 cleanup_ack_type = DspinDhccpParam::TYPE_CLEANUP_ACK_DATA;8856 }8857 8858 uint64_t flit = 0;8859 uint64_t dest =8860 r_cleanup_to_cc_send_srcid.read() <<8861 (DspinDhccpParam::SRCID_WIDTH - vci_param_int::S);8862 8863 DspinDhccpParam::dspin_set(8864 flit,8865 dest,8866 DspinDhccpParam::CLEANUP_ACK_DEST);8867 8868 DspinDhccpParam::dspin_set(8869 flit,8870 r_cleanup_to_cc_send_set_index.read(),8871 DspinDhccpParam::CLEANUP_ACK_SET);8872 8873 DspinDhccpParam::dspin_set(8874 flit,8875 r_cleanup_to_cc_send_way_index.read(),8876 DspinDhccpParam::CLEANUP_ACK_WAY);8877 8878 DspinDhccpParam::dspin_set(8879 flit,8880 cleanup_ack_type,8881 DspinDhccpParam::FROM_MC_TYPE);8882 8883 p_dspin_out.eop = true;8884 p_dspin_out.write = true;8885 p_dspin_out.data = flit;8886 8887 break;8888 }8889 8890 8868 /////////////////////////////////// 8891 8869 case CC_SEND_XRAM_RSP_INVAL_HEADER: … … 8921 8899 DspinDhccpParam::dspin_set( flit, 8922 8900 multi_inval_type, 8923 DspinDhccpParam:: FROM_MC_TYPE);8924 p_dspin_ out.write = true;8925 p_dspin_ out.data = flit;8901 DspinDhccpParam::M2P_TYPE); 8902 p_dspin_m2p.write = true; 8903 p_dspin_m2p.data = flit; 8926 8904 break; 8927 8905 } … … 8935 8913 r_xram_rsp_to_cc_send_nline.read(), 8936 8914 DspinDhccpParam::MULTI_INVAL_NLINE); 8937 p_dspin_ out.eop = true;8938 p_dspin_ out.write = true;8939 p_dspin_ out.data = flit;8915 p_dspin_m2p.eop = true; 8916 p_dspin_m2p.write = true; 8917 p_dspin_m2p.data = flit; 8940 8918 break; 8941 8919 } … … 8959 8937 DspinDhccpParam::dspin_set( flit, 8960 8938 1ULL, 8961 DspinDhccpParam:: FROM_MC_BC);8962 p_dspin_ out.write = true;8963 p_dspin_ out.data = flit;