Index: branches/ODCCP/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h
===================================================================
--- branches/ODCCP/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h	(revision 460)
+++ branches/ODCCP/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h	(revision 479)
@@ -54,4 +54,5 @@
 #define TRT_ENTRIES      4      // Number of entries in TRT
 #define UPT_ENTRIES      4      // Number of entries in UPT
+#define IVT_ENTRIES      4      // Number of entries in IVT
 #define HEAP_ENTRIES     1024   // Number of entries in HEAP
 
@@ -122,10 +123,8 @@
         CC_SEND_WRITE_IDLE,
         CC_SEND_CAS_IDLE,
-        CC_SEND_CLEANUP_IDLE,
         CC_SEND_CONFIG_INVAL_HEADER,
         CC_SEND_CONFIG_INVAL_NLINE,
         CC_SEND_CONFIG_BRDCAST_HEADER,
         CC_SEND_CONFIG_BRDCAST_NLINE,
-        CC_SEND_CLEANUP_ACK,
         CC_SEND_XRAM_RSP_BRDCAST_HEADER,
         CC_SEND_XRAM_RSP_BRDCAST_NLINE,
@@ -163,5 +162,5 @@
         CONFIG_DIR_REQ,
         CONFIG_DIR_ACCESS,
-        CONFIG_DIR_UPT_LOCK,
+        CONFIG_DIR_IVT_LOCK,
         CONFIG_BC_SEND,
         CONFIG_BC_WAIT,
@@ -211,5 +210,5 @@
         WRITE_MISS_XRAM_REQ,
         WRITE_BC_TRT_LOCK,
-        WRITE_BC_UPT_LOCK,
+        WRITE_BC_IVT_LOCK,
         WRITE_BC_DIR_INVAL,
         WRITE_BC_CC_SEND,
@@ -255,4 +254,5 @@
         IXR_CMD_XRAM_IDLE,
         IXR_CMD_CLEANUP_IDLE,
+        IXR_CMD_TRT_LOCK,
         IXR_CMD_READ,
         IXR_CMD_WRITE,
@@ -276,5 +276,5 @@
         CAS_UPT_NEXT,
         CAS_BC_TRT_LOCK,
-        CAS_BC_UPT_LOCK,
+        CAS_BC_IVT_LOCK,
         CAS_BC_DIR_INVAL,
         CAS_BC_CC_SEND,
@@ -302,7 +302,7 @@
         CLEANUP_HEAP_CLEAN,
         CLEANUP_HEAP_FREE,
-        CLEANUP_UPT_LOCK,
-        CLEANUP_UPT_DECREMENT,
-        CLEANUP_UPT_CLEAR,
+        CLEANUP_IVT_LOCK,
+        CLEANUP_IVT_DECREMENT,
+        CLEANUP_IVT_CLEAR,
         CLEANUP_WRITE_RSP,
         CLEANUP_CONFIG_ACK,
@@ -332,5 +332,6 @@
         ALLOC_TRT_XRAM_RSP,
         ALLOC_TRT_IXR_RSP,
-        ALLOC_TRT_CLEANUP
+        ALLOC_TRT_CLEANUP,
+        ALLOC_TRT_IXR_CMD
       };
 
@@ -338,10 +339,17 @@
       enum alloc_upt_fsm_state_e
       {
-        ALLOC_UPT_CONFIG,
         ALLOC_UPT_WRITE,
-        ALLOC_UPT_XRAM_RSP,
-        ALLOC_UPT_MULTI_ACK,
-        ALLOC_UPT_CLEANUP,
-        ALLOC_UPT_CAS
+        ALLOC_UPT_CAS,
+        ALLOC_UPT_MULTI_ACK
+      };
+
+      /* States of the ALLOC_IVT fsm */
+      enum alloc_ivt_fsm_state_e
+      {
+        ALLOC_IVT_WRITE,
+        ALLOC_IVT_XRAM_RSP,
+        ALLOC_IVT_CLEANUP,
+        ALLOC_IVT_CAS,
+        ALLOC_IVT_CONFIG
       };
 
@@ -492,5 +500,5 @@
       uint32_t     m_cpt_cas_fsm_upt_used;       // NB cycles UPT LOCK used
       
-      uint32_t     m_cpt_upt_unused;            // NB cycles UPT LOCK unused
+      uint32_t     m_cpt_ivt_unused;            // NB cycles UPT LOCK unused
 
       uint32_t     m_cpt_read_fsm_heap_lock;     // wait HEAP LOCK
@@ -536,6 +544,7 @@
       soclib::caba::VciTarget<vci_param_int>      p_vci_tgt;
       soclib::caba::VciInitiator<vci_param_ext>   p_vci_ixr;
-      soclib::caba::DspinInput<dspin_in_width>    p_dspin_in;
-      soclib::caba::DspinOutput<dspin_out_width>  p_dspin_out;
+      soclib::caba::DspinInput<dspin_in_width>    p_dspin_p2m;
+      soclib::caba::DspinOutput<dspin_out_width>  p_dspin_m2p;
+      soclib::caba::DspinOutput<dspin_out_width>  p_dspin_clack;
 
       VciMemCache(
@@ -553,4 +562,5 @@
           const size_t                       trt_lines=TRT_ENTRIES, 
           const size_t                       upt_lines=UPT_ENTRIES,     
+          const size_t                       ivt_lines=IVT_ENTRIES,     
           const size_t                       debug_start_cycle=0,
           const bool                         debug_ok=false );
@@ -588,5 +598,6 @@
       TransactionTab                     m_trt;              // xram transaction table
       uint32_t                           m_upt_lines;
-      UpdateTab                          m_upt;              // pending update & invalidate
+      UpdateTab                          m_upt;              // pending update
+      UpdateTab                          m_ivt;              // pending invalidate
       CacheDirectory                     m_cache_directory;  // data cache directory
       CacheData                          m_cache_data;       // data array[set][way][word]
@@ -677,5 +688,5 @@
       sc_signal<size_t>   r_config_heap_next;      // current pointer to scan HEAP
 
-      sc_signal<size_t>   r_config_upt_index;  // UPT index
+      sc_signal<size_t>   r_config_ivt_index;      // IVT index
 
       // Buffer between CONFIG fsm and TGT_RSP fsm (send a done response to L1 cache)
@@ -866,11 +877,4 @@
       sc_signal<size_t>   r_cleanup_to_tgt_rsp_pktid; // transaction pktid
 
-      // Buffer between CLEANUP fsm and CC_SEND fsm (acknowledge a cleanup command from L1)
-      sc_signal<bool>     r_cleanup_to_cc_send_req;       // valid request
-      sc_signal<size_t>   r_cleanup_to_cc_send_srcid;     // L1 srcid
-      sc_signal<size_t>   r_cleanup_to_cc_send_set_index; // L1 set index
-      sc_signal<size_t>   r_cleanup_to_cc_send_way_index; // L1 way index
-      sc_signal<bool>     r_cleanup_to_cc_send_inst;      // Instruction Cleanup Ack
-
       ///////////////////////////////////////////////////////
       // Registers controlled by CAS fsm
@@ -960,5 +964,5 @@
       sc_signal<size_t>   r_xram_rsp_victim_ptr;        // victim line pointer to the heap
       sc_signal<data_t> * r_xram_rsp_victim_data;       // victim line data
-      sc_signal<size_t>   r_xram_rsp_upt_index;         // UPT entry index
+      sc_signal<size_t>   r_xram_rsp_ivt_index;         // IVT entry index
       sc_signal<size_t>   r_xram_rsp_next_ptr;          // Next pointer to the heap
 
@@ -1041,4 +1045,10 @@
 
       ////////////////////////////////////////////////////
+      // Registers controlled by ALLOC_IVT fsm
+      ////////////////////////////////////////////////////
+
+      sc_signal<int>      r_alloc_ivt_fsm;
+
+      ////////////////////////////////////////////////////
       // Registers controlled by ALLOC_HEAP fsm
       ////////////////////////////////////////////////////
@@ -1056,4 +1066,5 @@
       sc_signal<uint32_t>  r_cleanup_pktid;
       sc_signal<data_t>    *r_cleanup_data;          // buffer for saving data from cleanup
+      sc_signal<data_t>    *r_ixr_cmd_data;          // buffer for saving data from cleanup
       sc_signal<bool>      r_cleanup_contains_data;
       sc_signal<bool>      r_cleanup_ncc;
