Changeset 479 for branches/ODCCP/modules/vci_mem_cache/caba/source/src
- Timestamp:
- Jul 29, 2013, 11:31:38 AM (11 years ago)
- Location:
- branches/ODCCP/modules/vci_mem_cache
- Files:
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- 2 edited
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branches/ODCCP/modules/vci_mem_cache
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/trunk/modules/vci_mem_cache merged eligible /branches/v5/modules/vci_mem_cache 441-467
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branches/ODCCP/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp
r474 r479 102 102 "CC_SEND_WRITE_IDLE", 103 103 "CC_SEND_CAS_IDLE", 104 "CC_SEND_CLEANUP_IDLE",105 104 "CC_SEND_CONFIG_INVAL_HEADER", 106 105 "CC_SEND_CONFIG_INVAL_NLINE", 107 106 "CC_SEND_CONFIG_BRDCAST_HEADER", 108 107 "CC_SEND_CONFIG_BRDCAST_NLINE", 109 "CC_SEND_CLEANUP_ACK",110 108 "CC_SEND_XRAM_RSP_BRDCAST_HEADER", 111 109 "CC_SEND_XRAM_RSP_BRDCAST_NLINE", … … 139 137 "CONFIG_DIR_REQ", 140 138 "CONFIG_DIR_ACCESS", 141 "CONFIG_DIR_ UPT_LOCK",139 "CONFIG_DIR_IVT_LOCK", 142 140 "CONFIG_BC_SEND", 143 141 "CONFIG_BC_WAIT", … … 183 181 "WRITE_MISS_XRAM_REQ", 184 182 "WRITE_BC_TRT_LOCK", 185 "WRITE_BC_ UPT_LOCK",183 "WRITE_BC_IVT_LOCK", 186 184 "WRITE_BC_DIR_INVAL", 187 185 "WRITE_BC_CC_SEND", … … 221 219 "IXR_CMD_XRAM_IDLE", 222 220 "IXR_CMD_CLEANUP_IDLE", 221 "IXR_CMD_TRT_LOCK", 223 222 "IXR_CMD_READ", 224 223 "IXR_CMD_WRITE", … … 240 239 "CAS_UPT_NEXT", 241 240 "CAS_BC_TRT_LOCK", 242 "CAS_BC_ UPT_LOCK",241 "CAS_BC_IVT_LOCK", 243 242 "CAS_BC_DIR_INVAL", 244 243 "CAS_BC_CC_SEND", … … 264 263 "CLEANUP_HEAP_CLEAN", 265 264 "CLEANUP_HEAP_FREE", 266 "CLEANUP_ UPT_LOCK",267 "CLEANUP_ UPT_DECREMENT",268 "CLEANUP_ UPT_CLEAR",265 "CLEANUP_IVT_LOCK", 266 "CLEANUP_IVT_DECREMENT", 267 "CLEANUP_IVT_CLEAR", 269 268 "CLEANUP_WRITE_RSP", 270 269 "CLEANUP_CONFIG_ACK", … … 290 289 "ALLOC_TRT_XRAM_RSP", 291 290 "ALLOC_TRT_IXR_RSP", 292 "ALLOC_TRT_CLEANUP" 291 "ALLOC_TRT_CLEANUP", 292 "ALLOC_TRT_IXR_CMD" 293 293 }; 294 294 const char *alloc_upt_fsm_str[] = … … 296 296 "ALLOC_UPT_CONFIG", 297 297 "ALLOC_UPT_WRITE", 298 "ALLOC_UPT_XRAM_RSP", 299 "ALLOC_UPT_MULTI_ACK", 300 "ALLOC_UPT_CLEANUP", 301 "ALLOC_UPT_CAS" 298 "ALLOC_UPT_CAS", 299 "ALLOC_UPT_MULTI_ACK" 300 }; 301 const char *alloc_ivt_fsm_str[] = 302 { 303 "ALLOC_IVT_WRITE", 304 "ALLOC_IVT_XRAM_RSP", 305 "ALLOC_IVT_CLEANUP", 306 "ALLOC_IVT_CAS", 307 "ALLOC_IVT_CONFIG" 302 308 }; 303 309 const char *alloc_heap_fsm_str[] = … … 339 345 const size_t trt_lines, // number of TRT entries 340 346 const size_t upt_lines, // number of UPT entries 347 const size_t ivt_lines, // number of IVT entries 341 348 const size_t debug_start_cycle, 342 349 const bool debug_ok) … … 350 357 p_vci_tgt( "p_vci_tgt" ), 351 358 p_vci_ixr( "p_vci_ixr" ), 352 p_dspin_in( "p_dspin_in" ), 353 p_dspin_out( "p_dspin_out" ), 359 p_dspin_p2m( "p_dspin_p2m" ), 360 p_dspin_m2p( "p_dspin_m2p" ), 361 p_dspin_clack( "p_dspin_clack" ), 354 362 355 363 m_seglist( mtp.getSegmentList(tgtid_d) ), … … 368 376 m_upt_lines(upt_lines), 369 377 m_upt(upt_lines), 378 m_ivt(ivt_lines), 370 379 m_cache_directory(nways, nsets, nwords, vci_param_int::N), 371 380 m_cache_data(nways, nsets, nwords), … … 459 468 r_alloc_trt_fsm("r_alloc_trt_fsm"), 460 469 r_alloc_upt_fsm("r_alloc_upt_fsm"), 470 r_alloc_ivt_fsm("r_alloc_ivt_fsm"), 461 471 r_alloc_heap_fsm("r_alloc_heap_fsm"), 462 472 r_alloc_heap_reset_cpt("r_alloc_heap_reset_cpt") … … 534 544 // Allocation for ODCCP 535 545 r_cleanup_data = new sc_signal<data_t>[nwords]; 546 r_ixr_cmd_data = new sc_signal<data_t>[nwords]; 536 547 r_cleanup_to_ixr_cmd_data = new sc_signal<data_t>[nwords]; 537 548 … … 641 652 << " | " << ixr_cmd_fsm_str[r_ixr_cmd_fsm.read()] 642 653 << " | " << ixr_rsp_fsm_str[r_ixr_rsp_fsm.read()] 643 << " | " << xram_rsp_fsm_str[r_xram_rsp_fsm ] << std::endl;654 << " | " << xram_rsp_fsm_str[r_xram_rsp_fsm.read()] << std::endl; 644 655 std::cout << " " << alloc_dir_fsm_str[r_alloc_dir_fsm.read()] 645 656 << " | " << alloc_trt_fsm_str[r_alloc_trt_fsm.read()] 646 657 << " | " << alloc_upt_fsm_str[r_alloc_upt_fsm.read()] 658 << " | " << alloc_ivt_fsm_str[r_alloc_ivt_fsm.read()] 647 659 << " | " << alloc_heap_fsm_str[r_alloc_heap_fsm.read()] << std::endl; 648 660 } … … 672 684 m_cpt_trt_rb = 0; 673 685 m_cpt_dir_unused = 0; 674 m_cpt_ upt_unused = 0;686 m_cpt_ivt_unused = 0; 675 687 m_cpt_heap_unused = 0; 676 688 m_cpt_trt_unused = 0; … … 771 783 << "- WAIT UPT LOCK in CAS_FSM = " << (double) m_cpt_cas_fsm_upt_lock/m_cpt_cas_fsm_n_upt_lock << std::endl 772 784 << "- NB CYCLES IN UPT LOCK in CAS_FSM = " << (double) m_cpt_cas_fsm_upt_used/m_cpt_cas_fsm_n_upt_lock << std::endl 773 << "- UPT UNUSED RATE = " << (double) m_cpt_upt_unused/m_cpt_cycles << std::endl << std::endl785 << "- IVT UNUSED RATE = " << (double) m_cpt_ivt_unused/m_cpt_cycles << std::endl << std::endl 774 786 775 787 << "- WAIT HEAP LOCK in READ_FSM = " << (double) m_cpt_read_fsm_heap_lock/m_cpt_read_fsm_n_heap_lock << std::endl … … 805 817 806 818 delete [] r_cleanup_data; 819 delete [] r_ixr_cmd_data; 807 820 delete [] r_cleanup_to_ixr_cmd_data; 808 821 } … … 833 846 r_alloc_trt_fsm = ALLOC_TRT_READ; 834 847 r_alloc_upt_fsm = ALLOC_UPT_WRITE; 848 r_alloc_ivt_fsm = ALLOC_IVT_XRAM_RSP; 835 849 r_ixr_rsp_fsm = IXR_RSP_IDLE; 836 850 r_xram_rsp_fsm = XRAM_RSP_IDLE; … … 845 859 m_trt.init(); 846 860 m_upt.init(); 861 m_ivt.init(); 847 862 m_llsc_table.init(); 848 863 … … 946 961 r_cleanup_contains_data = false; 947 962 r_cleanup_to_ixr_cmd_req = false; 948 r_cleanup_to_ixr_cmd_l1_dirty_ncc = false;949 r_xram_rsp_to_ixr_cmd_inval_ncc_pending = false;963 //r_cleanup_to_ixr_cmd_l1_dirty_ncc = false; 964 //r_xram_rsp_to_ixr_cmd_inval_ncc_pending = false; 950 965 r_cleanup_to_ixr_cmd_srcid = 0; 951 966 r_cleanup_to_ixr_cmd_trdid = 0; … … 956 971 r_cleanup_to_ixr_cmd_data[word] = 0; 957 972 r_cleanup_data[word] = 0; 973 r_ixr_cmd_data[word] = 0; 958 974 } 959 975 … … 980 996 m_cpt_trt_rb = 0; 981 997 m_cpt_dir_unused = 0; 982 m_cpt_ upt_unused = 0;998 m_cpt_ivt_unused = 0; 983 999 m_cpt_heap_unused = 0; 984 1000 m_cpt_trt_unused = 0; … … 1723 1739 r_config_dir_next_ptr = entry.ptr; 1724 1740 1725 r_config_fsm = CONFIG_DIR_ UPT_LOCK;1741 r_config_fsm = CONFIG_DIR_IVT_LOCK; 1726 1742 } 1727 1743 else if ( entry.valid and // hit & sync command … … 1752 1768 } 1753 1769 ///////////////////////// 1754 case CONFIG_DIR_ UPT_LOCK: // enter this state in case of INVAL command1755 // Try to get both DIR & UPT locks, and return1756 // to LOOP state if UPT full.1757 // Register inval in UPT, and invalidate the1758 // directory if UPT not full.1759 { 1760 if ( r_alloc_ upt_fsm.read() == ALLOC_UPT_CONFIG )1770 case CONFIG_DIR_IVT_LOCK: // enter this state in case of INVAL command 1771 // Try to get both DIR & IVT locks, and return 1772 // to LOOP state if IVT full. 1773 // Register inval in IVT, and invalidate the 1774 // directory if IVT not full. 1775 { 1776 if ( r_alloc_ivt_fsm.read() == ALLOC_IVT_CONFIG ) 1761 1777 { 1762 1778 size_t set = m_y[(addr_t)(r_config_address.read())]; … … 1772 1788 #if DEBUG_MEMC_CONFIG 1773 1789 if(m_debug) 1774 std::cout << " <MEMC " << name() << " CONFIG_DIR_ UPT_LOCK>"1790 std::cout << " <MEMC " << name() << " CONFIG_DIR_IVT_LOCK>" 1775 1791 << " No copies in L1 : inval DIR entry" << std::endl; 1776 1792 #endif 1777 1793 } 1778 else // try to register inval in UPT1794 else // try to register inval in IVT 1779 1795 { 1780 1796 bool wok = false; … … 1787 1803 size_t nb_copies = r_config_dir_count.read(); 1788 1804 1789 wok = m_ upt.set(false, // it's an inval transaction1805 wok = m_ivt.set(false, // it's an inval transaction 1790 1806 broadcast, 1791 1807 false, // no response required … … 1798 1814 index); 1799 1815 1800 if ( wok ) // UPT success => inval DIR slot1816 if ( wok ) // IVT success => inval DIR slot 1801 1817 { 1802 1818 m_cache_directory.inval( way, set ); 1803 r_config_ upt_index = index;1819 r_config_ivt_index = index; 1804 1820 if ( broadcast ) r_config_fsm = CONFIG_BC_SEND; 1805 1821 else r_config_fsm = CONFIG_INV_SEND; … … 1807 1823 #if DEBUG_MEMC_CONFIG 1808 1824 if(m_debug) 1809 std::cout << " <MEMC " << name() << " CONFIG_DIR_ UPT_LOCK>"1810 << " Inval DIR entry and register inval in UPT"1825 std::cout << " <MEMC " << name() << " CONFIG_DIR_IVT_LOCK>" 1826 << " Inval DIR entry and register inval in IVT" 1811 1827 << " : index = " << std::dec << index 1812 1828 << " / broadcast = " << broadcast << std::endl; 1813 1829 #endif 1814 1830 } 1815 else // UPT full => release both DIR and UPT locks1831 else // IVT full => release both DIR and IVT locks 1816 1832 { 1817 1833 r_config_fsm = CONFIG_LOOP; … … 1819 1835 #if DEBUG_MEMC_CONFIG 1820 1836 if(m_debug) 1821 std::cout << " <MEMC " << name() << " CONFIG_DIR_ UPT_LOCK>"1822 << " UPT full : release DIR & UPT locks and retry" << std::endl;1837 std::cout << " <MEMC " << name() << " CONFIG_DIR_IVT_LOCK>" 1838 << " IVT full : release DIR & IVT locks and retry" << std::endl; 1823 1839 #endif 1824 1840 } … … 1835 1851 r_config_to_cc_send_multi_req = false; 1836 1852 r_config_to_cc_send_brdcast_req = true; 1837 r_config_to_cc_send_trdid = r_config_ upt_index.read();1853 r_config_to_cc_send_trdid = r_config_ivt_index.read(); 1838 1854 r_config_to_cc_send_nline = m_nline[(addr_t)(r_config_address.read())]; 1839 1855 r_cleanup_to_config_ack = false; … … 1875 1891 r_config_to_cc_send_multi_req = true; 1876 1892 r_config_to_cc_send_brdcast_req = false; 1877 r_config_to_cc_send_trdid = r_config_ upt_index.read();1893 r_config_to_cc_send_trdid = r_config_ivt_index.read(); 1878 1894 r_config_to_cc_send_nline = m_nline[(addr_t)(r_config_address.read())]; 1879 1895 r_multi_ack_to_config_ack = false; … … 2037 2053 switch(r_read_fsm.read()) 2038 2054 { 2039 2040 2041 2055 /////////////// 2056 case READ_IDLE: // waiting a read request 2057 { 2042 2058 if(m_cmd_read_addr_fifo.rok()) 2043 2059 { 2044 2060 2045 2061 #if DEBUG_MEMC_READ 2046 if(m_debug)2047 std::cout << " <MEMC " << name() << " READ_IDLE> Read request"2048 << " : address = " << std::hex << m_cmd_read_addr_fifo.read()2049 << " / srcid = " << m_cmd_read_srcid_fifo.read()2050 << " / trdid = " << m_cmd_read_trdid_fifo.read()2051 << " / pktid = " << m_cmd_read_pktid_fifo.read()2052 << " / nwords = " << std::dec << m_cmd_read_length_fifo.read() << std::endl;2062 if(m_debug) 2063 std::cout << " <MEMC " << name() << " READ_IDLE> Read request" 2064 << " : address = " << std::hex << m_cmd_read_addr_fifo.read() 2065 << " / srcid = " << m_cmd_read_srcid_fifo.read() 2066 << " / trdid = " << m_cmd_read_trdid_fifo.read() 2067 << " / pktid = " << m_cmd_read_pktid_fifo.read() 2068 << " / nwords = " << std::dec << m_cmd_read_length_fifo.read() << std::endl; 2053 2069 #endif 2054 2070 r_read_fsm = READ_DIR_REQ; … … 2154 2170 2155 2171 { 2156 2157 2158 2159 2160 2161 2162 2163 2164 2165 2166 2167 2168 2169 2170 2171 2172 2173 2174 2172 if(r_alloc_dir_fsm.read() == ALLOC_DIR_READ) 2173 { 2174 // check if this is an instruction read, this means pktid is either 2175 // TYPE_READ_INS_UNC 0bX010 with TSAR encoding 2176 // TYPE_READ_INS_MISS 0bX011 with TSAR encoding 2177 bool inst_read = ((m_cmd_read_pktid_fifo.read() & 0x2) != 0); 2178 // check if this is a cached read, this means pktid is either 2179 // TYPE_READ_DATA_MISS 0bX001 with TSAR encoding 2180 // TYPE_READ_INS_MISS 0bX011 with TSAR encoding 2181 bool cached_read = (m_cmd_read_pktid_fifo.read() & 0x1); 2182 bool is_cnt = r_read_is_cnt.read(); 2183 2184 // read data in the cache 2185 size_t set = m_y[(addr_t)(m_cmd_read_addr_fifo.read())]; 2186 size_t way = r_read_way.read(); 2187 2188 m_cache_data.read_line(way, set, r_read_data); 2189 2190 if(m_monitor_ok) check_monitor( m_cmd_read_addr_fifo.read(), r_read_data[0], true); 2175 2191 2176 2192 // update the cache directory … … 2223 2239 2224 2240 #if DEBUG_MEMC_READ 2225 if(m_debug)2226 std::cout << " <MEMC " << name() << " READ_DIR_HIT> Update directory entry:"2227 << " addr = " << std::hex << m_cmd_read_addr_fifo.read()2228 << " / set = " << std::dec << set2229 << " / way = " << way2230 << " / owner_id = " << std::hex << entry.owner.srcid2231 << " / owner_ins = " << std::dec << entry.owner.inst2232 << " / count = " << entry.count2233 << " / is_cnt = " << entry.is_cnt << std::endl;2241 if(m_debug) 2242 std::cout << " <MEMC " << name() << " READ_DIR_HIT> Update directory entry:" 2243 << " addr = " << std::hex << m_cmd_read_addr_fifo.read() 2244 << " / set = " << std::dec << set 2245 << " / way = " << way 2246 << " / owner_id = " << std::hex << entry.owner.srcid 2247 << " / owner_ins = " << std::dec << entry.owner.inst 2248 << " / count = " << entry.count 2249 << " / is_cnt = " << entry.is_cnt << std::endl; 2234 2250 #endif 2235 2251 … … 2977 2993 2978 2994 wok = m_upt.set(true, // it's an update transaction 2979 false, 2980 true, 2981 false, 2995 false, // it's not a broadcast 2996 true, // response required 2997 false, // no acknowledge required 2982 2998 srcid, 2983 2999 trdid, … … 3139 3155 entry.owner.inst) // put the next srcid in the fifo 3140 3156 { 3141 dec_upt_counter 3157 dec_upt_counter = false; 3142 3158 write_to_cc_send_fifo_put = true; 3143 3159 write_to_cc_send_fifo_inst = entry.owner.inst; … … 3192 3208 { 3193 3209 r_write_to_cc_send_multi_req = true; 3194 if(r_write_to_dec.read() or dec_upt_counter) 3210 if(r_write_to_dec.read() or dec_upt_counter) r_write_fsm = WRITE_UPT_DEC; 3195 3211 else r_write_fsm = WRITE_IDLE; 3196 3212 } … … 3444 3460 { 3445 3461 r_write_trt_index = wok_index; 3446 r_write_fsm = WRITE_BC_ UPT_LOCK;3462 r_write_fsm = WRITE_BC_IVT_LOCK; 3447 3463 } 3448 3464 else // wait an empty entry in TRT … … 3465 3481 3466 3482 ////////////////////// 3467 case WRITE_BC_ UPT_LOCK: // register BC transaction in UPT3468 { 3469 if(r_alloc_ upt_fsm.read() == ALLOC_UPT_WRITE)3483 case WRITE_BC_IVT_LOCK: // register BC transaction in IVT 3484 { 3485 if(r_alloc_ivt_fsm.read() == ALLOC_IVT_WRITE) 3470 3486 { 3471 3487 bool wok = false; … … 3477 3493 size_t nb_copies = r_write_count.read(); 3478 3494 3479 wok = m_ upt.set(false, // it's an inval transaction3480 true, 3481 true, 3482 false, 3495 wok = m_ivt.set(false, // it's an inval transaction 3496 true, // it's a broadcast 3497 true, // response required 3498 false, // no acknowledge required 3483 3499 srcid, 3484 3500 trdid, … … 3489 3505 #if DEBUG_MEMC_WRITE 3490 3506 if( m_debug and wok ) 3491 std::cout << " <MEMC " << name() << " WRITE_BC_ UPT_LOCK> Register broadcast inval in UPT"3507 std::cout << " <MEMC " << name() << " WRITE_BC_IVT_LOCK> Register broadcast inval in IVT" 3492 3508 << " / nb_copies = " << r_write_count.read() << std::endl; 3493 3509 #endif … … 3495 3511 3496 3512 if(wok) r_write_fsm = WRITE_BC_DIR_INVAL; 3497 else 3513 else r_write_fsm = WRITE_WAIT; 3498 3514 m_cpt_write_fsm_n_upt_lock++; 3499 3515 } … … 3510 3526 // and invalidate the line in directory 3511 3527 if((r_alloc_trt_fsm.read() != ALLOC_TRT_WRITE) or 3512 (r_alloc_upt_fsm.read() != ALLOC_UPT_WRITE) or3513 3528 (r_alloc_ivt_fsm.read() != ALLOC_IVT_WRITE) or 3529 (r_alloc_dir_fsm.read() != ALLOC_DIR_WRITE)) 3514 3530 { 3515 3531 std::cout << "VCI_MEM_CACHE ERROR " << name() << " WRITE_BC_DIR_INVAL state" << std::endl; 3516 std::cout << "bad TRT, DIR, or UPT allocation" << std::endl;3532 std::cout << "bad TRT, DIR, or IVT allocation" << std::endl; 3517 3533 exit(0); 3518 3534 } … … 3636 3652 else if(r_cas_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_CAS; 3637 3653 else if(r_xram_rsp_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_XRAM; 3654 #if ODCCP_NON_INCLUSIVE 3638 3655 else if(r_cleanup_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_CLEANUP_DATA; 3656 #else 3657 else if(r_cleanup_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_TRT_LOCK; 3658 #endif 3639 3659 else if(r_read_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_READ; 3640 3660 break; … … 3643 3663 if(r_cas_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_CAS; 3644 3664 else if(r_xram_rsp_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_XRAM; 3665 #if ODCCP_NON_INCLUSIVE 3645 3666 else if(r_cleanup_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_CLEANUP_DATA; 3667 #else 3668 else if(r_cleanup_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_TRT_LOCK; 3669 #endif 3646 3670 else if(r_read_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_READ; 3647 3671 else if(r_write_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_WRITE; … … 3650 3674 case IXR_CMD_CAS_IDLE: 3651 3675 if(r_xram_rsp_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_XRAM; 3676 #if ODCCP_NON_INCLUSIVE 3652 3677 else if(r_cleanup_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_CLEANUP_DATA; 3678 #else 3679 else if(r_cleanup_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_TRT_LOCK; 3680 #endif 3653 3681 else if(r_read_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_READ; 3654 3682 else if(r_write_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_WRITE; … … 3657 3685 //////////////////////// 3658 3686 case IXR_CMD_XRAM_IDLE: 3687 #if ODCCP_NON_INCLUSIVE 3659 3688 if(r_cleanup_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_CLEANUP_DATA; 3689 #else 3690 if(r_cleanup_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_TRT_LOCK; 3691 #endif 3660 3692 else if(r_read_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_READ; 3661 3693 else if(r_write_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_WRITE; … … 3669 3701 else if(r_cas_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_CAS; 3670 3702 else if(r_xram_rsp_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_XRAM; 3703 #if ODCCP_NON_INCLUSIVE 3671 3704 else if(r_cleanup_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_CLEANUP_DATA; 3672 break; 3705 #else 3706 else if(r_cleanup_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_TRT_LOCK; 3707 #endif 3708 break; 3709 3710 ///////////////////// 3711 case IXR_CMD_TRT_LOCK: 3712 { 3713 TransactionTabEntry entry; 3714 3715 if(r_alloc_trt_fsm.read() != ALLOC_TRT_IXR_CMD) break; 3716 entry.copy( m_trt.read(r_cleanup_to_ixr_cmd_trdid.read())); 3717 for(size_t i=0; i < m_words; i++) 3718 { 3719 r_ixr_cmd_data[i] = entry.wdata[i]; 3720 } 3721 3722 r_ixr_cmd_fsm = IXR_CMD_CLEANUP_DATA; 3723 break; 3724 } 3725 3673 3726 ////////////////// // send a get from READ FSM 3674 3727 case IXR_CMD_READ: … … 3806 3859 r_ixr_cmd_fsm = IXR_CMD_CLEANUP_IDLE; 3807 3860 r_cleanup_to_ixr_cmd_req = false; 3808 r_xram_rsp_to_ixr_cmd_inval_ncc_pending = false;3861 //r_xram_rsp_to_ixr_cmd_inval_ncc_pending = false; 3809 3862 } 3810 3863 else … … 3990 4043 size_t ptr = r_xram_rsp_trt_index.read(); 3991 4044 size_t lines = m_trt_lines; 4045 3992 4046 for(size_t i=0 ; i<lines ; i++) 3993 4047 { … … 4081 4135 #else 4082 4136 /*ODCCP*/ //if victim is no coherent and there is an inval no coherent pending we wait 4083 if(!victim.coherent and r_xram_rsp_to_ixr_cmd_inval_ncc_pending.read())4137 /*if(!victim.coherent and r_xram_rsp_to_ixr_cmd_inval_ncc_pending.read()) 4084 4138 { 4085 4139 r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT; 4086 4140 } 4087 4141 else 4088 { 4142 {*/ 4089 4143 r_xram_rsp_fsm = XRAM_RSP_INVAL_LOCK; 4090 4144 //} 4091 4145 #endif 4092 4146 } … … 4102 4156 << " way = " << std::dec << way 4103 4157 << " / set = " << set 4158 << " / victim coherent = " << victim.coherent 4159 << " / victim owner id = " << victim.owner.srcid 4104 4160 << " / inval_required = " << inval << std::endl; 4105 4161 #endif … … 4114 4170 } 4115 4171 ///////////////////////// 4116 case XRAM_RSP_INVAL_LOCK: // Take the UPT lock to check a possible pending inval4117 { 4118 if(r_alloc_ upt_fsm == ALLOC_UPT_XRAM_RSP)4172 case XRAM_RSP_INVAL_LOCK: // Take the IVT lock to check a possible pending inval 4173 { 4174 if(r_alloc_ivt_fsm == ALLOC_IVT_XRAM_RSP) 4119 4175 { 4120 4176 size_t index = 0; 4121 if(m_ upt.search_inval(r_xram_rsp_trt_buf.nline, index)) // pending inval4177 if(m_ivt.search_inval(r_xram_rsp_trt_buf.nline, index)) // pending inval 4122 4178 { 4123 4179 r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT; … … 4126 4182 if(m_debug) 4127 4183 std::cout << " <MEMC " << name() << " XRAM_RSP_INVAL_LOCK>" 4128 << " Get acces to UPT, but line invalidation registered"4184 << " Get acces to IVT, but line invalidation registered" 4129 4185 << " / nline = " << std::hex << r_xram_rsp_trt_buf.nline 4130 4186 << " / index = " << std::dec << index << std::endl; … … 4132 4188 4133 4189 } 4134 else if(m_ upt.is_full() and r_xram_rsp_victim_inval.read()) // UPT full4190 else if(m_ivt.is_full() and r_xram_rsp_victim_inval.read()) // IVT full 4135 4191 { 4136 4192 r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT; … … 4139 4195 if(m_debug) 4140 4196 std::cout << " <MEMC " << name() << " XRAM_RSP_INVAL_LOCK>" 4141 << " Get acces to UPT, but inval required and UPT full" << std::endl;4197 << " Get acces to IVT, but inval required and IVT full" << std::endl; 4142 4198 #endif 4143 4199 } … … 4149 4205 if(m_debug) 4150 4206 std::cout << " <MEMC " << name() << " XRAM_RSP_INVAL_LOCK>" 4151 << " Get acces to UPT" << std::endl;4207 << " Get acces to IVT" << std::endl; 4152 4208 #endif 4153 4209 } … … 4173 4229 /////////////////////// 4174 4230 case XRAM_RSP_DIR_UPDT: // updates the cache (both data & directory) 4175 // and possibly set an inval request in UPT4231 // and possibly set an inval request in IVT 4176 4232 { 4177 4233 // check if this is an instruction read, this means pktid is either … … 4241 4297 m_cache_directory.write(set, way, entry); 4242 4298 4243 // request an invalidation request in UPT for victim line4299 // request an invalidation request in IVT for victim line 4244 4300 if(r_xram_rsp_victim_inval.read()) 4245 4301 { … … 4247 4303 size_t index = 0; 4248 4304 size_t count_copies = r_xram_rsp_victim_count.read(); 4249 4250 bool wok = m_ upt.set(false, // it's an inval transaction4305 4306 bool wok = m_ivt.set(false, // it's an inval transaction 4251 4307 broadcast, // set broadcast bit 4252 4308 false, // no response required … … 4259 4315 index); 4260 4316 4261 r_xram_rsp_ upt_index = index;4317 r_xram_rsp_ivt_index = index; 4262 4318 4263 4319 if(!wok) 4264 4320 { 4265 4321 std::cout << "VCI_MEM_CACHE ERROR " << name() << " XRAM_RSP_DIR_UPDT" 4266 << " update_tab entry free but write unsuccessful" << std::endl;4322 << " invalidate_tab entry free but write unsuccessful" << std::endl; 4267 4323 exit(0); 4268 4324 } … … 4313 4369 if(r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP) 4314 4370 { 4315 m_trt.set(r_xram_rsp_trt_index.read(), 4371 std::vector<data_t> data_vector; 4372 data_vector.clear(); 4373 4374 for(size_t i=0; i<m_words; i++) 4375 { 4376 data_vector.push_back(r_xram_rsp_victim_data[i]); 4377 } 4378 /*m_trt.set(r_xram_rsp_trt_index.read(), 4316 4379 false, // write to XRAM 4317 4380 r_xram_rsp_victim_nline.read(), // line index … … 4323 4386 0, 4324 4387 std::vector<be_t> (m_words,0), 4325 std::vector<data_t> (m_words,0)); 4388 std::vector<data_t> (m_words,0));*/ 4389 4390 m_trt.set(r_xram_rsp_trt_index.read(), 4391 false, // write to XRAM 4392 r_xram_rsp_victim_nline.read(), // line index 4393 0, 4394 0, 4395 0, 4396 false, 4397 0, 4398 0, 4399 std::vector<be_t> (m_words,0), 4400 data_vector); 4326 4401 4327 4402 #if DEBUG_MEMC_XRAM_RSP … … 4395 4470 r_xram_rsp_to_cc_send_brdcast_req = r_xram_rsp_victim_is_cnt.read(); 4396 4471 r_xram_rsp_to_cc_send_nline = r_xram_rsp_victim_nline.read(); 4397 r_xram_rsp_to_cc_send_trdid = r_xram_rsp_ upt_index;4472 r_xram_rsp_to_cc_send_trdid = r_xram_rsp_ivt_index; 4398 4473 xram_rsp_to_cc_send_fifo_srcid = r_xram_rsp_victim_copy.read(); 4399 4474 xram_rsp_to_cc_send_fifo_inst = r_xram_rsp_victim_copy_inst.read(); … … 4427 4502 case XRAM_RSP_WRITE_DIRTY: // send a write request to IXR_CMD FSM 4428 4503 { 4429 if((!r_xram_rsp_to_ixr_cmd_req.read()) and (!r_xram_rsp_to_ixr_cmd_inval_ncc_pending.read()))4504 if((!r_xram_rsp_to_ixr_cmd_req.read()) /*and (!r_xram_rsp_to_ixr_cmd_inval_ncc_pending.read())*/) 4430 4505 { 4431 4506 … … 4443 4518 if( (!r_xram_rsp_victim_coherent.read()) and (r_xram_rsp_victim_count.read() == 1) ) 4444 4519 { 4445 r_xram_rsp_to_ixr_cmd_inval_ncc_pending = true; // inval no coherent pending4520 //r_xram_rsp_to_ixr_cmd_inval_ncc_pending = true; // inval no coherent pending 4446 4521 r_xram_rsp_to_ixr_cmd_req = false; 4447 4522 r_xram_rsp_fsm = XRAM_RSP_IDLE; … … 4633 4708 DspinDhccpParam::dspin_get( 4634 4709 flit, 4635 DspinDhccpParam:: FROM_L1_TYPE);4710 DspinDhccpParam::P2M_TYPE); 4636 4711 4637 4712 r_cleanup_way_index = … … 4689 4764 DspinDhccpParam::dspin_get(flit, DspinDhccpParam::CLEANUP_NLINE_LSB); 4690 4765 4691 bool eop = DspinDhccpParam::dspin_get(flit, DspinDhccpParam:: FROM_L1_EOP);4766 bool eop = DspinDhccpParam::dspin_get(flit, DspinDhccpParam::P2M_EOP); 4692 4767 4693 4768 /*ODCCP*/ // if not eop (more than 2 flits) there is a cleanup no coherent with data … … 4711 4786 std::cout << " <MEMC " << name() 4712 4787 << " CLEANUP_GET_NLINE> Cleanup request:" 4788 << " / ncc = " << r_cleanup_ncc.read() 4713 4789 << " / address = " << std::hex << nline * m_words * 4 << std::endl; 4714 4790 #endif … … 4819 4895 else // miss : check UPT for a pending invalidation transaction 4820 4896 { 4821 r_cleanup_fsm = CLEANUP_ UPT_LOCK;4897 r_cleanup_fsm = CLEANUP_IVT_LOCK; 4822 4898 } 4823 4899 … … 5289 5365 } 5290 5366 ////////////////////// 5291 case CLEANUP_ UPT_LOCK: // get the lock protecting the UPT to search a pending5367 case CLEANUP_IVT_LOCK: // get the lock protecting the IVT to search a pending 5292 5368 // invalidate transaction matching the cleanup 5293 5369 { 5294 5370 m_cpt_cleanup_fsm_upt_lock++; 5295 if(r_alloc_ upt_fsm.read() != ALLOC_UPT_CLEANUP) break;5371 if(r_alloc_ivt_fsm.read() != ALLOC_IVT_CLEANUP) break; 5296 5372 5297 5373 size_t index = 0; 5298 5374 bool match_inval; 5299 5375 5300 match_inval = m_ upt.search_inval(r_cleanup_nline.read(), index);5376 match_inval = m_ivt.search_inval(r_cleanup_nline.read(), index); 5301 5377 5302 5378 if ( not match_inval ) // no pending inval … … 5315 5391 if(m_debug) 5316 5392 std::cout << " <MEMC " << name() 5317 << " CLEANUP_ UPT_LOCK> Unexpected cleanup"5318 << " with no corresponding UPT entry:"5393 << " CLEANUP_IVT_LOCK> Unexpected cleanup" 5394 << " with no corresponding IVT entry:" 5319 5395 << " address = " << std::hex 5320 5396 << (r_cleanup_nline.read() *4*m_words) … … 5326 5402 5327 5403 // pending inval 5328 r_cleanup_write_srcid = m_ upt.srcid(index);5329 r_cleanup_write_trdid = m_ upt.trdid(index);5330 r_cleanup_write_pktid = m_ upt.pktid(index);5331 r_cleanup_need_rsp = m_ upt.need_rsp(index);5332 r_cleanup_need_ack = m_ upt.need_ack(index);5404 r_cleanup_write_srcid = m_ivt.srcid(index); 5405 r_cleanup_write_trdid = m_ivt.trdid(index); 5406 r_cleanup_write_pktid = m_ivt.pktid(index); 5407 r_cleanup_need_rsp = m_ivt.need_rsp(index); 5408 r_cleanup_need_ack = m_ivt.need_ack(index); 5333 5409 r_cleanup_index = index; 5334 5410 5335 r_cleanup_fsm = CLEANUP_ UPT_DECREMENT;5411 r_cleanup_fsm = CLEANUP_IVT_DECREMENT; 5336 5412 5337 5413 #if DEBUG_MEMC_CLEANUP 5338 5414 if(m_debug) 5339 5415 std::cout << " <MEMC " << name() 5340 << " CLEANUP_ UPT_LOCK> Cleanup matching pending"5341 << " invalidate transaction on UPT:"5416 << " CLEANUP_IVT_LOCK> Cleanup matching pending" 5417 << " invalidate transaction on IVT:" 5342 5418 << " address = " << std::hex << r_cleanup_nline.read() * m_words * 4 5343 << " / upt_entry = " << index << std::endl;5419 << " / ivt_entry = " << index << std::endl; 5344 5420 #endif 5345 5421 break; 5346 5422 } 5347 5423 /////////////////////////// 5348 case CLEANUP_ UPT_DECREMENT: // decrement response counter in UPT matching entry5349 { 5350 if(r_alloc_ upt_fsm.read() != ALLOC_UPT_CLEANUP)5424 case CLEANUP_IVT_DECREMENT: // decrement response counter in IVT matching entry 5425 { 5426 if(r_alloc_ivt_fsm.read() != ALLOC_IVT_CLEANUP) 5351 5427 { 5352 5428 std::cout 5353 5429 << "VCI_MEM_CACHE ERROR " << name() 5354 << " CLEANUP_ UPT_DECREMENT state" << std::endl5355 << "Bad UPT allocation"5430 << " CLEANUP_IVT_DECREMENT state" << std::endl 5431 << "Bad IVT allocation" 5356 5432 << std::endl; 5357 5433 … … 5360 5436 5361 5437 size_t count = 0; 5362 m_ upt.decrement(r_cleanup_index.read(), count);5438 m_ivt.decrement(r_cleanup_index.read(), count); 5363 5439 5364 5440 if(count == 0) // multi inval transaction completed 5365 5441 { 5366 r_cleanup_fsm = CLEANUP_ UPT_CLEAR;5442 r_cleanup_fsm = CLEANUP_IVT_CLEAR; 5367 5443 } 5368 5444 else // multi inval transaction not completed … … 5381 5457 #if DEBUG_MEMC_CLEANUP 5382 5458 if(m_debug) 5383 std::cout << " <MEMC " << name() << " CLEANUP_ UPT_DECREMENT>"5384 << " Decrement response counter in UPT:"5385 << " UPT_index = " << r_cleanup_index.read()5459 std::cout << " <MEMC " << name() << " CLEANUP_IVT_DECREMENT>" 5460 << " Decrement response counter in IVT:" 5461 << " IVT_index = " << r_cleanup_index.read() 5386 5462 << " / rsp_count = " << count << std::endl; 5387 5463 #endif … … 5389 5465 } 5390 5466 /////////////////////// 5391 case CLEANUP_ UPT_CLEAR: // Clear UPT entry5392 { 5393 if(r_alloc_ upt_fsm.read() != ALLOC_UPT_CLEANUP)5467 case CLEANUP_IVT_CLEAR: // Clear IVT entry 5468 { 5469 if(r_alloc_ivt_fsm.read() != ALLOC_IVT_CLEANUP) 5394 5470 { 5395 5471 std::cout 5396 5472 << "VCI_MEM_CACHE ERROR " << name() 5397 << " CLEANUP_ UPT_CLEAR state" << std::endl5398 << "Bad UPT allocation"5473 << " CLEANUP_IVT_CLEAR state" << std::endl 5474 << "Bad IVT allocation" 5399 5475 << std::endl; 5400 5476 … … 5402 5478 } 5403 5479 5404 m_ upt.clear(r_cleanup_index.read());5480 m_ivt.clear(r_cleanup_index.read()); 5405 5481 5406 5482 if ( r_cleanup_need_rsp.read() ) r_cleanup_fsm = CLEANUP_WRITE_RSP; … … 5412 5488 if(m_debug) 5413 5489 std::cout << " <MEMC " << name() 5414 << " CLEANUP_ UPT_CLEAR> Clear entry in UPT:"5415 << " UPT_index = " << r_cleanup_index.read() << std::endl;5490 << " CLEANUP_IVT_CLEAR> Clear entry in IVT:" 5491 << " IVT_index = " << r_cleanup_index.read() << std::endl; 5416 5492 #endif 5417 5493 break; … … 5487 5563 r_cleanup_to_ixr_cmd_pktid = r_cleanup_pktid.read(); 5488 5564 r_cleanup_to_ixr_cmd_nline = r_cleanup_nline.read(); 5489 r_cleanup_to_ixr_cmd_l1_dirty_ncc = true;5565 //r_cleanup_to_ixr_cmd_l1_dirty_ncc = true; 5490 5566 r_cleanup_fsm = CLEANUP_SEND_CLACK; 5491 5567 } … … 5505 5581 r_cleanup_to_ixr_cmd_req = true; 5506 5582 5507 for(size_t i = 0; i < m_words; i++){ 5508 r_cleanup_to_ixr_cmd_data[i] = r_cleanup_data[i]; 5583 if (r_cleanup_contains_data.read()) 5584 { 5585 std::vector<data_t> data_vector; 5586 data_vector.clear(); 5587 5588 for(size_t i=0; i<m_words; i++) 5589 { 5590 data_vector.push_back(r_cleanup_data[i]); 5591 } 5592 5593 m_trt.set(index, 5594 false, // write to XRAM 5595 r_cleanup_nline.read(), // line index 5596 0, 5597 0, 5598 0, 5599 false, 5600 0, 5601 0, 5602 std::vector<be_t> (m_words,0), 5603 data_vector); 5509 5604 } 5510 5511 5605 r_cleanup_to_ixr_cmd_srcid = r_cleanup_srcid.read(); 5512 5606 r_cleanup_to_ixr_cmd_trdid = index; 5513 5607 r_cleanup_to_ixr_cmd_pktid = r_cleanup_pktid.read(); 5514 5608 r_cleanup_to_ixr_cmd_nline = r_cleanup_nline.read(); 5515 r_cleanup_to_ixr_cmd_l1_dirty_ncc = r_cleanup_contains_data.read();5609 //r_cleanup_to_ixr_cmd_l1_dirty_ncc = r_cleanup_contains_data.read(); 5516 5610 r_cleanup_fsm = CLEANUP_SEND_CLACK; 5517 5611 #endif … … 5547 5641 5548 5642 //////////////////////// 5549 case CLEANUP_SEND_CLACK: // acknowledgement to a cleanup command 5550 // on the coherence network (request to the CC_SEND FSM). 5551 // wait if pending request to the CC_SEND FSM 5552 { 5553 if(r_cleanup_to_cc_send_req.read()) break; 5554 5555 r_cleanup_to_cc_send_req = true; 5556 r_cleanup_to_cc_send_set_index = r_cleanup_nline.read() & 0xFFFF; 5557 r_cleanup_to_cc_send_way_index = r_cleanup_way_index.read(); 5558 r_cleanup_to_cc_send_srcid = r_cleanup_srcid.read(); 5559 r_cleanup_to_cc_send_inst = r_cleanup_inst.read(); 5643 case CLEANUP_SEND_CLACK: // acknowledgement to a cleanup command 5644 // on the coherence CLACK network. 5645 { 5646 if(not p_dspin_clack.read) break; 5560 5647 5561 5648 r_cleanup_fsm = CLEANUP_IDLE; … … 5565 5652 std::cout << " <MEMC " << name() 5566 5653 << " CLEANUP_SEND_CLACK> Send the response to a cleanup request:" 5567 << " srcid = " << std::dec << r_cleanup_srcid.read() << std::endl; 5654 << " nline = " << std::hex << r_cleanup_nline.read() 5655 << " / way = " << std::dec << r_cleanup_way.read() 5656 << " / srcid = " << std::dec << r_cleanup_srcid.read() 5657 << std::endl; 5568 5658 #endif 5569 5659 break; … … 5804 5894 !r_cas_to_cc_send_brdcast_req.read()) 5805 5895 { 5806 r_cas_fsm = CAS_UPT_LOCK; // multi update required5896 r_cas_fsm = CAS_UPT_LOCK; // multi update required 5807 5897 } 5808 5898 else … … 6077 6167 { 6078 6168 r_cas_trt_index = wok_index; 6079 r_cas_fsm = CAS_BC_ UPT_LOCK;6169 r_cas_fsm = CAS_BC_IVT_LOCK; 6080 6170 } 6081 6171 else … … 6096 6186 } 6097 6187 ///////////////////// 6098 case CAS_BC_ UPT_LOCK: // register a broadcast inval transaction in UPT6188 case CAS_BC_IVT_LOCK: // register a broadcast inval transaction in IVT 6099 6189 // write data in cache in case of successful registration 6100 6190 { 6101 if(r_alloc_ upt_fsm.read() == ALLOC_UPT_CAS)6191 if(r_alloc_ivt_fsm.read() == ALLOC_IVT_CAS) 6102 6192 { 6103 6193 bool wok = false; … … 6109 6199 size_t nb_copies = r_cas_count.read(); 6110 6200 6111 // register a broadcast inval transaction in UPT6112 wok = m_ upt.set(false, // it's an inval transaction6113 true, 6114 true, 6115 false, 6201 // register a broadcast inval transaction in IVT 6202 wok = m_ivt.set(false, // it's an inval transaction 6203 true, // it's a broadcast 6204 true, // response required 6205 false, // no acknowledge required 6116 6206 srcid, 6117 6207 trdid, … … 6121 6211 index); 6122 6212 6123 if(wok) // UPT not full6213 if(wok) // IVT not full 6124 6214 { 6125 6215 // cache update … … 6147 6237 if(m_debug) 6148 6238 std::cout << " <MEMC " << name() 6149 << " CAS_BC_ UPT_LOCK> Register a broadcast inval transaction in UPT"6239 << " CAS_BC_IVT_LOCK> Register a broadcast inval transaction in IVT" 6150 6240 << " / nline = " << std::hex << nline 6151 6241 << " / count = " << std::dec << nb_copies 6152 << " / upt_index = " << index << std::endl;6153 #endif 6154 } 6155 else // releases the lock protecting UPT6242 << " / ivt_index = " << index << std::endl; 6243 #endif 6244 } 6245 else // releases the lock protecting IVT 6156 6246 { 6157 6247 r_cas_fsm = CAS_WAIT; … … 6168 6258 { 6169 6259 if((r_alloc_trt_fsm.read() == ALLOC_TRT_CAS) and 6170 (r_alloc_upt_fsm.read() == ALLOC_UPT_CAS) and6171 6260 (r_alloc_ivt_fsm.read() == ALLOC_IVT_CAS) and 6261 (r_alloc_dir_fsm.read() == ALLOC_DIR_CAS)) 6172 6262 { 6173 6263 // set TRT … … 6416 6506 // network, used to update or invalidate cache lines in L1 caches. 6417 6507 // 6418 // This fsm is used also to acknowledge CLEANUP a command after request from 6419 // the CLEANUP fsm. 6420 // 6421 // It implements a round-robin priority between the five possible client FSMs 6422 // XRAM_RSP > CAS > CLEANUP > WRITE > CONFIG 6508 // It implements a round-robin priority between the four possible client FSMs 6509 // XRAM_RSP > CAS > WRITE > CONFIG 6423 6510 // 6424 6511 // Each FSM can request the next services: … … 6432 6519 // r_config_to_cc_send_brdcast_req : broadcast-inval 6433 6520 // 6434 // - r_cleanup_to_cc_send_req : cleanup acknowledgement6435 //6436 6521 // An inval request is a double DSPIN flit command containing: 6437 6522 // 1. the index of the line to be invalidated. … … 6476 6561 break; 6477 6562 } 6478 // CLEANUP6479 if (r_cleanup_to_cc_send_req.read())6480 {6481 r_cc_send_fsm = CC_SEND_CLEANUP_ACK;6482 break;6483 }6484 6563 // WRITE 6485 6564 if(m_write_to_cc_send_inst_fifo.rok() or … … 6555 6634 break; 6556 6635 } 6557 // CLEANUP6558 if (r_cleanup_to_cc_send_req.read())6559 {6560 r_cc_send_fsm = CC_SEND_CLEANUP_ACK;6561 break;6562 }6563 6636 // WRITE 6564 6637 if(m_write_to_cc_send_inst_fifo.rok() or … … 6594 6667 break; 6595 6668 } 6596 // CLEANUP6597 if(r_cleanup_to_cc_send_req.read())6598 {6599 r_cc_send_fsm = CC_SEND_CLEANUP_ACK;6600 break;6601 }6602 6669 // WRITE 6603 6670 if(m_write_to_cc_send_inst_fifo.rok() or … … 6647 6714 case CC_SEND_CAS_IDLE: // CLEANUP FSM has highest priority 6648 6715 { 6649 if(r_cleanup_to_cc_send_req.read())6650 {6651 r_cc_send_fsm = CC_SEND_CLEANUP_ACK;6652 break;6653 }6654 6716 if(m_write_to_cc_send_inst_fifo.rok() or 6655 6717 r_write_to_cc_send_multi_req.read()) … … 6706 6768 break; 6707 6769 } 6708 //////////////////////////6709 case CC_SEND_CLEANUP_IDLE: // WRITE FSM has highest priority6710 {6711 // WRITE6712 if(m_write_to_cc_send_inst_fifo.rok() or6713 r_write_to_cc_send_multi_req.read())6714 {6715 r_cc_send_fsm = CC_SEND_WRITE_UPDT_HEADER;6716 m_cpt_update++;6717 break;6718 }6719 if(r_write_to_cc_send_brdcast_req.read())6720 {6721 r_cc_send_fsm = CC_SEND_WRITE_BRDCAST_HEADER;6722 m_cpt_inval++;6723 break;6724 }6725 // CONFIG6726 if(r_config_to_cc_send_multi_req.read())6727 {6728 r_cc_send_fsm = CC_SEND_CONFIG_INVAL_HEADER;6729 m_cpt_inval++;6730 break;6731 }6732 if(r_config_to_cc_send_brdcast_req.read())6733 {6734 r_cc_send_fsm = CC_SEND_CONFIG_BRDCAST_HEADER;6735 m_cpt_inval++;6736 break;6737 }6738 // XRAM_RSP6739 if(m_xram_rsp_to_cc_send_inst_fifo.rok() or6740 r_xram_rsp_to_cc_send_multi_req.read())6741 {6742 r_cc_send_fsm = CC_SEND_XRAM_RSP_INVAL_HEADER;6743 m_cpt_inval++;6744 break;6745 }6746 if(r_xram_rsp_to_cc_send_brdcast_req.read())6747 {6748 r_cc_send_fsm = CC_SEND_XRAM_RSP_BRDCAST_HEADER;6749 m_cpt_inval++;6750 break;6751 }6752 // CAS6753 if(m_cas_to_cc_send_inst_fifo.rok() or6754 r_cas_to_cc_send_multi_req.read())6755 {6756 r_cc_send_fsm = CC_SEND_CAS_UPDT_HEADER;6757 m_cpt_update++;6758 break;6759 }6760 if(r_cas_to_cc_send_brdcast_req.read())6761 {6762 r_cc_send_fsm = CC_SEND_CAS_BRDCAST_HEADER;6763 m_cpt_inval++;6764 break;6765 }6766 // CLEANUP6767 if(r_cleanup_to_cc_send_req.read())6768 {6769 r_cc_send_fsm = CC_SEND_CLEANUP_ACK;6770 break;6771 }6772 break;6773 }6774 6770 ///////////////////////////////// 6775 6771 case CC_SEND_CONFIG_INVAL_HEADER: // send first flit multi-inval (from CONFIG FSM) … … 6777 6773 if(m_config_to_cc_send_inst_fifo.rok()) 6778 6774 { 6779 if(not p_dspin_ out.read) break;6775 if(not p_dspin_m2p.read) break; 6780 6776 r_cc_send_fsm = CC_SEND_CONFIG_INVAL_NLINE; 6781 6777 break; … … 6788 6784 case CC_SEND_CONFIG_INVAL_NLINE: // send second flit multi-inval (from CONFIG FSM) 6789 6785 { 6790 if(not p_dspin_ out.read) break;6786 if(not p_dspin_m2p.read) break; 6791 6787 m_cpt_inval_mult++; 6792 6788 config_to_cc_send_fifo_get = true; … … 6804 6800 case CC_SEND_CONFIG_BRDCAST_HEADER: // send first flit BC-inval (from CONFIG FSM) 6805 6801 { 6806 if(not p_dspin_ out.read) break;6802 if(not p_dspin_m2p.read) break; 6807 6803 r_cc_send_fsm = CC_SEND_CONFIG_BRDCAST_NLINE; 6808 6804 break; … … 6811 6807 case CC_SEND_CONFIG_BRDCAST_NLINE: // send second flit BC-inval (from CONFIG FSM) 6812 6808 { 6813 if(not p_dspin_ out.read) break;6809 if(not p_dspin_m2p.read) break; 6814 6810 m_cpt_inval_brdcast++; 6815 6811 r_config_to_cc_send_brdcast_req = false; … … 6824 6820 break; 6825 6821 } 6826 /////////////////////////6827 case CC_SEND_CLEANUP_ACK: // send one flit for a cleanup acknowledgement6828 {6829 if(not p_dspin_out.read) break;6830 6831 r_cleanup_to_cc_send_req = false;6832 r_cc_send_fsm = CC_SEND_CLEANUP_IDLE;6833 6834 #if DEBUG_MEMC_CC_SEND6835 if(m_debug)6836 std::cout << " <MEMC " << name()6837 << " CC_SEND_CLEANUP_ACK> Cleanup Ack for srcid "6838 << std::hex << r_cleanup_to_cc_send_srcid.read() << std::endl;6839 #endif6840 break;6841 }6842 6822 /////////////////////////////////// 6843 6823 case CC_SEND_XRAM_RSP_INVAL_HEADER: // send first flit multi-inval (from XRAM_RSP FSM) … … 6845 6825 if(m_xram_rsp_to_cc_send_inst_fifo.rok()) 6846 6826 { 6847 if(not p_dspin_ out.read) break;6827 if(not p_dspin_m2p.read) break; 6848 6828 r_cc_send_fsm = CC_SEND_XRAM_RSP_INVAL_NLINE; 6849 6829 break; … … 6856 6836 case CC_SEND_XRAM_RSP_INVAL_NLINE: // send second flit multi-inval (from XRAM_RSP FSM) 6857 6837 { 6858 if(not p_dspin_ out.read) break;6838 if(not p_dspin_m2p.read) break; 6859 6839 m_cpt_inval_mult++; 6860 6840 xram_rsp_to_cc_send_fifo_get = true; … … 6864 6844 if(m_debug) 6865 6845 std::cout << " <MEMC " << name() 6866 << " CC_SEND_XRAM_RSP_INVAL_NLINE> BC-Inval for line "6846 << " CC_SEND_XRAM_RSP_INVAL_NLINE> Multicast-Inval for line " 6867 6847 << std::hex << r_xram_rsp_to_cc_send_nline.read() << std::endl; 6868 6848 #endif … … 6872 6852 case CC_SEND_XRAM_RSP_BRDCAST_HEADER: // send first flit broadcast-inval (from XRAM_RSP FSM) 6873 6853 { 6874 if(not p_dspin_ out.read) break;6854 if(not p_dspin_m2p.read) break; 6875 6855 r_cc_send_fsm = CC_SEND_XRAM_RSP_BRDCAST_NLINE; 6876 6856 break; … … 6879 6859 case CC_SEND_XRAM_RSP_BRDCAST_NLINE: // send second flit broadcast-inval (from XRAM_RSP FSM) 6880 6860 { 6881 if(not p_dspin_ out.read) break;6861 if(not p_dspin_m2p.read) break; 6882 6862 m_cpt_inval_brdcast++; 6883 6863 r_xram_rsp_to_cc_send_brdcast_req = false; … … 6895 6875 case CC_SEND_WRITE_BRDCAST_HEADER: // send first flit broadcast-inval (from WRITE FSM) 6896 6876 { 6897 if(not p_dspin_ out.read) break;6877 if(not p_dspin_m2p.read) break; 6898 6878 r_cc_send_fsm = CC_SEND_WRITE_BRDCAST_NLINE; 6899 6879 break; … … 6902 6882 case CC_SEND_WRITE_BRDCAST_NLINE: // send second flit broadcast-inval (from WRITE FSM) 6903 6883 { 6904 if(not p_dspin_ out.read) break;6884 if(not p_dspin_m2p.read) break; 6905 6885 6906 6886 m_cpt_inval_brdcast++; … … 6922 6902 if(m_write_to_cc_send_inst_fifo.rok()) 6923 6903 { 6924 if(not p_dspin_ out.read) break;6904 if(not p_dspin_m2p.read) break; 6925 6905 6926 6906 r_cc_send_fsm = CC_SEND_WRITE_UPDT_NLINE; … … 6939 6919 case CC_SEND_WRITE_UPDT_NLINE: // send second flit for a multi-update (from WRITE FSM) 6940 6920 { 6941 if(not p_dspin_ out.read) break;6921 if(not p_dspin_m2p.read) break; 6942 6922 m_cpt_update_mult++; 6943 6923 … … 6956 6936 case CC_SEND_WRITE_UPDT_DATA: // send N data flits for a multi-update (from WRITE FSM) 6957 6937 { 6958 if(not p_dspin_ out.read) break;6938 if(not p_dspin_m2p.read) break; 6959 6939 if(r_cc_send_cpt.read() == (r_write_to_cc_send_count.read()-1)) 6960 6940 { … … 6970 6950 case CC_SEND_CAS_BRDCAST_HEADER: // send first flit broadcast-inval (from CAS FSM) 6971 6951 { 6972 if(not p_dspin_ out.read) break;6952 if(not p_dspin_m2p.read) break; 6973 6953 r_cc_send_fsm = CC_SEND_CAS_BRDCAST_NLINE; 6974 6954 break; … … 6977 6957 case CC_SEND_CAS_BRDCAST_NLINE: // send second flit broadcast-inval (from CAS FSM) 6978 6958 { 6979 if(not p_dspin_ out.read) break;6959 if(not p_dspin_m2p.read) break; 6980 6960 m_cpt_inval_brdcast++; 6981 6961 … … 6996 6976 if(m_cas_to_cc_send_inst_fifo.rok()) 6997 6977 { 6998 if(not p_dspin_ out.read) break;6978 if(not p_dspin_m2p.read) break; 6999 6979 7000 6980 r_cc_send_fsm = CC_SEND_CAS_UPDT_NLINE; … … 7014 6994 case CC_SEND_CAS_UPDT_NLINE: // send second flit for a multi-update (from CAS FSM) 7015 6995 { 7016 if(not p_dspin_ out.read) break;6996 if(not p_dspin_m2p.read) break; 7017 6997 7018 6998 m_cpt_update_mult++; … … 7032 7012 case CC_SEND_CAS_UPDT_DATA: // send first data for a multi-update (from CAS FSM) 7033 7013 { 7034 if(not p_dspin_ out.read) break;7014 if(not p_dspin_m2p.read) break; 7035 7015 7036 7016 if(r_cas_to_cc_send_is_long.read()) … … 7047 7027 case CC_SEND_CAS_UPDT_DATA_HIGH: // send second data for a multi-update (from CAS FSM) 7048 7028 { 7049 if(not p_dspin_ out.read) break;7029 if(not p_dspin_m2p.read) break; 7050 7030 cas_to_cc_send_fifo_get = true; 7051 7031 r_cc_send_fsm = CC_SEND_CAS_UPDT_HEADER; … … 7067 7047 case CC_RECEIVE_IDLE: 7068 7048 { 7069 if(not p_dspin_ in.write) break;7049 if(not p_dspin_p2m.write) break; 7070 7050 7071 7051 uint8_t type = 7072 7052 DspinDhccpParam::dspin_get( 7073 p_dspin_ in.data.read(),7074 DspinDhccpParam:: FROM_L1_TYPE);7053 p_dspin_p2m.data.read(), 7054 DspinDhccpParam::P2M_TYPE); 7075 7055 7076 7056 if((type == DspinDhccpParam::TYPE_CLEANUP_DATA) or … … 7098 7078 // write first CLEANUP flit in CC_RECEIVE to CLEANUP fifo 7099 7079 7100 if(not p_dspin_ in.write or not m_cc_receive_to_cleanup_fifo.wok())7080 if(not p_dspin_p2m.write or not m_cc_receive_to_cleanup_fifo.wok()) 7101 7081 break; 7102 7082 7103 assert(not p_dspin_ in.eop.read() and7083 assert(not p_dspin_p2m.eop.read() and 7104 7084 "VCI_MEM_CACHE ERROR in CC_RECEIVE : " 7105 7085 "CLEANUP command must have two flits"); … … 7115 7095 // write second CLEANUP flit in CC_RECEIVE to CLEANUP fifo or more in case of cleanup data (ODCCP) 7116 7096 7117 if(not p_dspin_ in.write or not m_cc_receive_to_cleanup_fifo.wok())7097 if(not p_dspin_p2m.write or not m_cc_receive_to_cleanup_fifo.wok()) 7118 7098 break; 7119 7099 7120 /*assert(p_dspin_in.eop.read() and7121 "VCI_MEM_CACHE ERROR in CC_RECEIVE : "7122 "CLEANUP command must have two flits");*/7123 7124 7100 cc_receive_to_cleanup_fifo_put = true; 7125 if(p_dspin_ in.eop.read())7101 if(p_dspin_p2m.eop.read()) 7126 7102 r_cc_receive_fsm = CC_RECEIVE_IDLE; 7127 7103 … … 7135 7111 7136 7112 // wait for a WOK in the CC_RECEIVE to MULTI_ACK fifo 7137 if(not p_dspin_ in.write or not m_cc_receive_to_multi_ack_fifo.wok())7113 if(not p_dspin_p2m.write or not m_cc_receive_to_multi_ack_fifo.wok()) 7138 7114 break; 7139 7115 7140 assert(p_dspin_ in.eop.read() and7116 assert(p_dspin_p2m.eop.read() and 7141 7117 "VCI_MEM_CACHE ERROR in CC_RECEIVE : " 7142 7118 "MULTI_ACK command must have one flit"); … … 7548 7524 // ALLOC_UPT FSM 7549 7525 //////////////////////////////////////////////////////////////////////////////////// 7550 // The ALLOC_UPT FSM allocates the access to the Update/Inval Table (UPT), 7551 // with a round robin priority between six FSMs, with the following order: 7552 // CONFIG > MULTI_ACK > WRITE > XRAM_RSP > CLEANUP > CAS 7553 // - The CONFIG FSM initiates an inval transaction and sets a new entry in UPT. 7526 // The ALLOC_UPT FSM allocates the access to the Update Table (UPT), 7527 // with a round robin priority between three FSMs, with the following order: 7528 // WRITE -> CAS -> MULTI_ACK 7529 // - The WRITE FSM initiates update transaction and sets a new entry in UPT. 7530 // - The CAS FSM does the same thing as the WRITE FSM. 7554 7531 // - The MULTI_ACK FSM complete those trasactions and erase the UPT entry. 7555 // - The WRITE FSM initiates update transaction and sets a new entry in UPT.7556 // - The XRAM_RSP FSM initiates an inval transactions and sets a new entry in UPT.7557 // - The CLEANUP FSM decrement an entry in UPT.7558 // - The CAS FSM does the same thing as the WRITE FSM.7559 7532 // The resource is always allocated. 7560 7533 ///////////////////////////////////////////////////////////////////////////////////// 7561 7562 7534 switch(r_alloc_upt_fsm.read()) 7563 7535 { 7564 //////////////////////7565 case ALLOC_UPT_CONFIG: // allocated to CONFIG FSM7566 if (r_config_fsm.read() != CONFIG_DIR_UPT_LOCK)7567 {7568 if(r_multi_ack_fsm.read() == MULTI_ACK_UPT_LOCK)7569 r_alloc_upt_fsm = ALLOC_UPT_MULTI_ACK;7570 7571 else if((r_write_fsm.read() == WRITE_UPT_LOCK) or7572 (r_write_fsm.read() == WRITE_BC_UPT_LOCK))7573 r_alloc_upt_fsm = ALLOC_UPT_WRITE;7574 7575 else if(r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK)7576 r_alloc_upt_fsm = ALLOC_UPT_XRAM_RSP;7577 7578 else if(r_cleanup_fsm.read() == CLEANUP_UPT_LOCK)7579 r_alloc_upt_fsm = ALLOC_UPT_CLEANUP;7580 7581 else if((r_cas_fsm.read() == CAS_UPT_LOCK) or7582 (r_cas_fsm.read() == CAS_BC_UPT_LOCK))7583 r_alloc_upt_fsm = ALLOC_UPT_CAS;7584 }7585 break;7586 7587 7536 ///////////////////////// 7588 case ALLOC_UPT_MULTI_ACK: // allocated to MULTI_ACK FSM 7589 if( (r_multi_ack_fsm.read() != MULTI_ACK_UPT_LOCK) and 7590 (r_multi_ack_fsm.read() != MULTI_ACK_UPT_CLEAR)) 7591 { 7592 if((r_write_fsm.read() == WRITE_UPT_LOCK) or 7593 (r_write_fsm.read() == WRITE_BC_UPT_LOCK)) 7594 r_alloc_upt_fsm = ALLOC_UPT_WRITE; 7595 7596 else if(r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK) 7597 r_alloc_upt_fsm = ALLOC_UPT_XRAM_RSP; 7598 7599 else if(r_cleanup_fsm.read() == CLEANUP_UPT_LOCK) 7600 r_alloc_upt_fsm = ALLOC_UPT_CLEANUP; 7601 7602 else if((r_cas_fsm.read() == CAS_UPT_LOCK) or 7603 (r_cas_fsm.read() == CAS_BC_UPT_LOCK)) 7604 r_alloc_upt_fsm = ALLOC_UPT_CAS; 7605 else if(r_config_fsm.read() == CONFIG_DIR_UPT_LOCK) 7606 r_alloc_upt_fsm = ALLOC_UPT_CONFIG; 7607 else 7608 m_cpt_upt_unused++; 7609 } 7610 else 7611 m_cpt_multi_ack_fsm_upt_used++; 7612 break; 7613 7614 ///////////////////// 7615 case ALLOC_UPT_WRITE: // allocated to WRITE FSM 7616 if((r_write_fsm.read() != WRITE_UPT_LOCK) and 7617 (r_write_fsm.read() != WRITE_BC_UPT_LOCK)) 7618 { 7619 if(r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK) 7620 r_alloc_upt_fsm = ALLOC_UPT_XRAM_RSP; 7621 7622 else if(r_cleanup_fsm.read() == CLEANUP_UPT_LOCK) 7623 r_alloc_upt_fsm = ALLOC_UPT_CLEANUP; 7624 7625 else if((r_cas_fsm.read() == CAS_UPT_LOCK) or 7626 (r_cas_fsm.read() == CAS_BC_UPT_LOCK)) 7627 r_alloc_upt_fsm = ALLOC_UPT_CAS; 7628 7629 else if(r_config_fsm.read() == CONFIG_DIR_UPT_LOCK) 7630 r_alloc_upt_fsm = ALLOC_UPT_CONFIG; 7631 7632 else if(r_multi_ack_fsm.read() == MULTI_ACK_UPT_LOCK) 7633 r_alloc_upt_fsm = ALLOC_UPT_MULTI_ACK; 7634 7635 else 7636 m_cpt_upt_unused++; 7637 } 7638 else 7639 m_cpt_write_fsm_upt_used++; 7640 break; 7641 7642 //////////////////////// 7643 case ALLOC_UPT_XRAM_RSP: 7644 if(r_xram_rsp_fsm.read() != XRAM_RSP_INVAL_LOCK) 7645 { 7646 if(r_cleanup_fsm.read() == CLEANUP_UPT_LOCK) 7647 r_alloc_upt_fsm = ALLOC_UPT_CLEANUP; 7648 7649 else if((r_cas_fsm.read() == CAS_UPT_LOCK) or 7650 (r_cas_fsm.read() == CAS_BC_UPT_LOCK)) 7651 r_alloc_upt_fsm = ALLOC_UPT_CAS; 7652 7653 else if(r_config_fsm.read() == CONFIG_DIR_UPT_LOCK) 7654 r_alloc_upt_fsm = ALLOC_UPT_CONFIG; 7655 7656 else if(r_multi_ack_fsm.read() == MULTI_ACK_UPT_LOCK) 7657 r_alloc_upt_fsm = ALLOC_UPT_MULTI_ACK; 7658 7659 else if((r_write_fsm.read() == WRITE_UPT_LOCK) or 7660 (r_write_fsm.read() == WRITE_BC_UPT_LOCK)) 7661 r_alloc_upt_fsm = ALLOC_UPT_WRITE; 7662 7663 else 7664 m_cpt_upt_unused++; 7665 } 7666 else 7667 m_cpt_xram_rsp_fsm_upt_used++; 7668 break; 7669 7537 case ALLOC_UPT_WRITE: // allocated to WRITE FSM 7538 if (r_write_fsm.read() != WRITE_UPT_LOCK) 7539 { 7540 if (r_cas_fsm.read() == CAS_UPT_LOCK) 7541 r_alloc_upt_fsm = ALLOC_UPT_CAS; 7542 7543 else if (r_multi_ack_fsm.read() == MULTI_ACK_UPT_LOCK) 7544 r_alloc_upt_fsm = ALLOC_UPT_MULTI_ACK; 7545 } 7546 break; 7547 7548 ///////////////////////// 7549 case ALLOC_UPT_CAS: // allocated to CAS FSM 7550 if (r_cas_fsm.read() != CAS_UPT_LOCK) 7551 { 7552 if (r_multi_ack_fsm.read() == MULTI_ACK_UPT_LOCK) 7553 r_alloc_upt_fsm = ALLOC_UPT_MULTI_ACK; 7554 7555 else if (r_write_fsm.read() == WRITE_UPT_LOCK) 7556 r_alloc_upt_fsm = ALLOC_UPT_WRITE; 7557 } 7558 break; 7559 7560 ///////////////////////// 7561 case ALLOC_UPT_MULTI_ACK: // allocated to MULTI_ACK FSM 7562 if ((r_multi_ack_fsm.read() != MULTI_ACK_UPT_LOCK ) and 7563 (r_multi_ack_fsm.read() != MULTI_ACK_UPT_CLEAR)) 7564 { 7565 if (r_write_fsm.read() == WRITE_UPT_LOCK) 7566 r_alloc_upt_fsm = ALLOC_UPT_WRITE; 7567 7568 else if (r_cas_fsm.read() == CAS_UPT_LOCK) 7569 r_alloc_upt_fsm = ALLOC_UPT_CAS; 7570 } 7571 break; 7572 } // end switch r_alloc_upt_fsm 7573 7574 //////////////////////////////////////////////////////////////////////////////////// 7575 // ALLOC_IVT FSM 7576 //////////////////////////////////////////////////////////////////////////////////// 7577 // The ALLOC_IVT FSM allocates the access to the Invalidate Table (IVT), 7578 // with a round robin priority between five FSMs, with the following order: 7579 // WRITE -> XRAM_RSP -> CLEANUP -> CAS -> CONFIG 7580 // - The WRITE FSM initiates broadcast invalidate transactions and sets a new entry 7581 // in IVT. 7582 // - The CAS FSM does the same thing as the WRITE FSM. 7583 // - The XRAM_RSP FSM initiates broadcast/multicast invalidate transaction and sets 7584 // a new entry in the IVT 7585 // - The CONFIG FSM does the same thing as the XRAM_RSP FSM 7586 // - The CLEANUP FSM complete those trasactions and erase the IVT entry. 7587 // The resource is always allocated. 7588 ///////////////////////////////////////////////////////////////////////////////////// 7589 switch(r_alloc_ivt_fsm.read()) 7590 { 7670 7591 ////////////////////////// 7671 case ALLOC_UPT_CLEANUP: 7672 if((r_cleanup_fsm.read() != CLEANUP_UPT_LOCK ) and 7673 (r_cleanup_fsm.read() != CLEANUP_UPT_DECREMENT)) 7674 { 7675 if((r_cas_fsm.read() == CAS_UPT_LOCK) or 7676 (r_cas_fsm.read() == CAS_BC_UPT_LOCK)) 7677 r_alloc_upt_fsm = ALLOC_UPT_CAS; 7678 7679 else if(r_config_fsm.read() == CONFIG_DIR_UPT_LOCK) 7680 r_alloc_upt_fsm = ALLOC_UPT_CONFIG; 7681 7682 else if(r_multi_ack_fsm.read() == MULTI_ACK_UPT_LOCK) 7683 r_alloc_upt_fsm = ALLOC_UPT_MULTI_ACK; 7684 7685 else if((r_write_fsm.read() == WRITE_UPT_LOCK) or 7686 (r_write_fsm.read() == WRITE_BC_UPT_LOCK)) 7687 r_alloc_upt_fsm = ALLOC_UPT_WRITE; 7688 7689 else if(r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK) 7690 r_alloc_upt_fsm = ALLOC_UPT_XRAM_RSP; 7691 7692 else 7693 m_cpt_upt_unused++; 7694 } 7695 else 7696 m_cpt_cleanup_fsm_upt_used++; 7697 break; 7592 case ALLOC_IVT_WRITE: // allocated to WRITE FSM 7593 if (r_write_fsm.read() != WRITE_BC_IVT_LOCK) 7594 { 7595 if (r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK) 7596 r_alloc_ivt_fsm = ALLOC_IVT_XRAM_RSP; 7597 7598 else if (r_cleanup_fsm.read() == CLEANUP_IVT_LOCK) 7599 r_alloc_ivt_fsm = ALLOC_IVT_CLEANUP; 7600 7601 else if (r_cas_fsm.read() == CAS_BC_IVT_LOCK) 7602 r_alloc_ivt_fsm = ALLOC_IVT_CAS; 7603 7604 else if (r_config_fsm.read() == CONFIG_DIR_IVT_LOCK) 7605 r_alloc_ivt_fsm = ALLOC_IVT_CONFIG; 7606 7607 else 7608 m_cpt_ivt_unused++; 7609 } 7610 break; 7698 7611 7699 7612 ////////////////////////// 7700 case ALLOC_UPT_CAS: 7701 if((r_cas_fsm.read() != CAS_UPT_LOCK) and 7702 (r_cas_fsm.read() != CAS_BC_UPT_LOCK)) 7703 { 7704 if(r_config_fsm.read() == CONFIG_DIR_UPT_LOCK) 7705 r_alloc_upt_fsm = ALLOC_UPT_CONFIG; 7706 7707 else if(r_multi_ack_fsm.read() == MULTI_ACK_UPT_LOCK) 7708 r_alloc_upt_fsm = ALLOC_UPT_MULTI_ACK; 7709 7710 else if((r_write_fsm.read() == WRITE_UPT_LOCK) or 7711 (r_write_fsm.read() == WRITE_BC_UPT_LOCK)) 7712 r_alloc_upt_fsm = ALLOC_UPT_WRITE; 7713 7714 else if(r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK) 7715 r_alloc_upt_fsm = ALLOC_UPT_XRAM_RSP; 7716 7717 else if(r_cleanup_fsm.read() == CLEANUP_UPT_LOCK) 7718 r_alloc_upt_fsm = ALLOC_UPT_CLEANUP; 7719 7720 else 7721 m_cpt_upt_unused++; 7722 } 7723 else 7724 m_cpt_cas_fsm_upt_used++; 7725 break; 7726 7727 } // end switch r_alloc_upt_fsm 7613 case ALLOC_IVT_XRAM_RSP: // allocated to XRAM_RSP FSM 7614 if(r_xram_rsp_fsm.read() != XRAM_RSP_INVAL_LOCK) 7615 { 7616 if(r_cleanup_fsm.read() == CLEANUP_IVT_LOCK) 7617 r_alloc_ivt_fsm = ALLOC_IVT_CLEANUP; 7618 7619 else if (r_cas_fsm.read() == CAS_BC_IVT_LOCK) 7620 r_alloc_ivt_fsm = ALLOC_IVT_CAS; 7621 7622 else if (r_config_fsm.read() == CONFIG_DIR_IVT_LOCK) 7623 r_alloc_ivt_fsm = ALLOC_IVT_CONFIG; 7624 7625 else if (r_write_fsm.read() == WRITE_BC_IVT_LOCK) 7626 r_alloc_ivt_fsm = ALLOC_IVT_WRITE; 7627 7628 else 7629 m_cpt_ivt_unused++; 7630 } 7631 break; 7632 7633 ////////////////////////// 7634 case ALLOC_IVT_CLEANUP: // allocated to CLEANUP FSM 7635 if ((r_cleanup_fsm.read() != CLEANUP_IVT_LOCK ) and 7636 (r_cleanup_fsm.read() != CLEANUP_IVT_DECREMENT)) 7637 { 7638 if (r_cas_fsm.read() == CAS_BC_IVT_LOCK) 7639 r_alloc_ivt_fsm = ALLOC_IVT_CAS; 7640 7641 else if (r_config_fsm.read() == CONFIG_DIR_IVT_LOCK) 7642 r_alloc_ivt_fsm = ALLOC_IVT_CONFIG; 7643 7644 else if (r_write_fsm.read() == WRITE_BC_IVT_LOCK) 7645 r_alloc_ivt_fsm = ALLOC_IVT_WRITE; 7646 7647 else if (r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK) 7648 r_alloc_ivt_fsm = ALLOC_IVT_XRAM_RSP; 7649 7650 else 7651 m_cpt_ivt_unused++; 7652 } 7653 break; 7654 7655 ////////////////////////// 7656 case ALLOC_IVT_CAS: // allocated to CAS FSM 7657 if (r_cas_fsm.read() != CAS_BC_IVT_LOCK) 7658 { 7659 if (r_config_fsm.read() == CONFIG_DIR_IVT_LOCK) 7660 r_alloc_ivt_fsm = ALLOC_IVT_CONFIG; 7661 7662 else if (r_write_fsm.read() == WRITE_BC_IVT_LOCK) 7663 r_alloc_ivt_fsm = ALLOC_IVT_WRITE; 7664 7665 else if (r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK) 7666 r_alloc_ivt_fsm = ALLOC_IVT_XRAM_RSP; 7667 7668 else if (r_cleanup_fsm.read() == CLEANUP_IVT_LOCK) 7669 r_alloc_ivt_fsm = ALLOC_IVT_CLEANUP; 7670 7671 else 7672 m_cpt_ivt_unused++; 7673 } 7674 break; 7675 7676 ////////////////////////// 7677 case ALLOC_IVT_CONFIG: // allocated to CONFIG FSM 7678 if (r_config_fsm.read() != CONFIG_DIR_IVT_LOCK) 7679 { 7680 if (r_write_fsm.read() == WRITE_BC_IVT_LOCK) 7681 r_alloc_ivt_fsm = ALLOC_IVT_WRITE; 7682 7683 else if (r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK) 7684 r_alloc_ivt_fsm = ALLOC_IVT_XRAM_RSP; 7685 7686 else if (r_cleanup_fsm.read() == CLEANUP_IVT_LOCK) 7687 r_alloc_ivt_fsm = ALLOC_IVT_CLEANUP; 7688 7689 else if (r_cas_fsm.read() == CAS_BC_IVT_LOCK) 7690 r_alloc_ivt_fsm = ALLOC_IVT_CAS; 7691 7692 else 7693 m_cpt_ivt_unused++; 7694 } 7695 break; 7696 7697 } // end switch r_alloc_ivt_fsm 7728 7698 7729 7699 //////////////////////////////////////////////////////////////////////////////////// … … 7755 7725 if ( (r_config_fsm.read() != CONFIG_DIR_REQ) and 7756 7726 (r_config_fsm.read() != CONFIG_DIR_ACCESS) and 7757 (r_config_fsm.read() != CONFIG_DIR_ UPT_LOCK) )7727 (r_config_fsm.read() != CONFIG_DIR_IVT_LOCK) ) 7758 7728 { 7759 7729 if(r_read_fsm.read() == READ_DIR_REQ) … … 7813 7783 (r_write_fsm.read() != WRITE_DIR_HIT) and 7814 7784 (r_write_fsm.read() != WRITE_BC_TRT_LOCK) and 7815 (r_write_fsm.read() != WRITE_BC_ UPT_LOCK) and7785 (r_write_fsm.read() != WRITE_BC_IVT_LOCK) and 7816 7786 (r_write_fsm.read() != WRITE_MISS_TRT_LOCK) and 7817 7787 (r_write_fsm.read() != WRITE_UPT_LOCK) and … … 7854 7824 (r_cas_fsm.read() != CAS_DIR_HIT_WRITE) and 7855 7825 (r_cas_fsm.read() != CAS_BC_TRT_LOCK) and 7856 (r_cas_fsm.read() != CAS_BC_ UPT_LOCK) and7826 (r_cas_fsm.read() != CAS_BC_IVT_LOCK) and 7857 7827 (r_cas_fsm.read() != CAS_MISS_TRT_LOCK) and 7858 7828 (r_cas_fsm.read() != CAS_UPT_LOCK) and … … 7980 7950 r_alloc_trt_fsm = ALLOC_TRT_CLEANUP; 7981 7951 7952 else if (r_ixr_cmd_fsm.read() == IXR_CMD_TRT_LOCK) 7953 r_alloc_trt_fsm = ALLOC_TRT_IXR_CMD; 7954 7982 7955 else 7983 7956 m_cpt_trt_unused++; … … 7991 7964 if((r_write_fsm.read() != WRITE_MISS_TRT_LOCK) and 7992 7965 (r_write_fsm.read() != WRITE_BC_TRT_LOCK) and 7993 (r_write_fsm.read() != WRITE_BC_ UPT_LOCK))7966 (r_write_fsm.read() != WRITE_BC_IVT_LOCK)) 7994 7967 { 7995 7968 if((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) or … … 8007 7980 else if (r_cleanup_fsm.read() == CLEANUP_IXR_REQ) 8008 7981 r_alloc_trt_fsm = ALLOC_TRT_CLEANUP; 7982 7983 else if (r_ixr_cmd_fsm.read() == IXR_CMD_TRT_LOCK) 7984 r_alloc_trt_fsm = ALLOC_TRT_IXR_CMD; 8009 7985 8010 7986 else if(r_read_fsm.read() == READ_TRT_LOCK) … … 8022 7998 if((r_cas_fsm.read() != CAS_MISS_TRT_LOCK) and 8023 7999 (r_cas_fsm.read() != CAS_BC_TRT_LOCK) and 8024 (r_cas_fsm.read() != CAS_BC_ UPT_LOCK))8000 (r_cas_fsm.read() != CAS_BC_IVT_LOCK)) 8025 8001 { 8026 8002 if((r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) and … … 8034 8010 else if (r_cleanup_fsm.read() == CLEANUP_IXR_REQ) 8035 8011 r_alloc_trt_fsm = ALLOC_TRT_CLEANUP; 8012 8013 else if (r_ixr_cmd_fsm.read() == IXR_CMD_TRT_LOCK) 8014 r_alloc_trt_fsm = ALLOC_TRT_IXR_CMD; 8036 8015 8037 8016 else if(r_read_fsm.read() == READ_TRT_LOCK) … … 8063 8042 else if (r_cleanup_fsm.read() == CLEANUP_IXR_REQ) 8064 8043 r_alloc_trt_fsm = ALLOC_TRT_CLEANUP; 8044 8045 else if (r_ixr_cmd_fsm.read() == IXR_CMD_TRT_LOCK) 8046 r_alloc_trt_fsm = ALLOC_TRT_IXR_CMD; 8065 8047 8066 8048 else if(r_read_fsm.read() == READ_TRT_LOCK) … … 8090 8072 if (r_cleanup_fsm.read() == CLEANUP_IXR_REQ) 8091 8073 r_alloc_trt_fsm = ALLOC_TRT_CLEANUP; 8074 8075 else if (r_ixr_cmd_fsm.read() == IXR_CMD_TRT_LOCK) 8076 r_alloc_trt_fsm = ALLOC_TRT_IXR_CMD; 8092 8077 8093 8078 else if(r_read_fsm.read() == READ_TRT_LOCK) … … 8115 8100 //////////////////////// 8116 8101 case ALLOC_TRT_CLEANUP: 8117 if(r_ixr_rsp_fsm.read() != CLEANUP_IXR_REQ) 8118 { 8119 if(r_read_fsm.read() == READ_TRT_LOCK) 8102 if(r_cleanup_fsm.read() != CLEANUP_IXR_REQ) 8103 { 8104 if (r_ixr_cmd_fsm.read() == IXR_CMD_TRT_LOCK) 8105 r_alloc_trt_fsm = ALLOC_TRT_IXR_CMD; 8106 8107 else if(r_read_fsm.read() == READ_TRT_LOCK) 8120 8108 r_alloc_trt_fsm = ALLOC_TRT_READ; 8121 8109 … … 8138 8126 break; 8139 8127 8128 //////////////////////// 8129 case ALLOC_TRT_IXR_CMD: 8130 if(r_ixr_cmd_fsm.read() != IXR_CMD_TRT_LOCK) 8131 { 8132 if(r_read_fsm.read() == READ_TRT_LOCK) 8133 r_alloc_trt_fsm = ALLOC_TRT_READ; 8134 8135 else if((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) or 8136 (r_write_fsm.read() == WRITE_BC_TRT_LOCK)) 8137 r_alloc_trt_fsm = ALLOC_TRT_WRITE; 8138 8139 else if((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) or 8140 (r_cas_fsm.read() == CAS_BC_TRT_LOCK)) 8141 r_alloc_trt_fsm = ALLOC_TRT_CAS; 8142 8143 else if((r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) and 8144 (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP)) 8145 r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP; 8146 8147 else if((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) || 8148 (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ)) 8149 r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP; 8150 8151 else if (r_cleanup_fsm.read() == CLEANUP_IXR_REQ) 8152 r_alloc_trt_fsm = ALLOC_TRT_CLEANUP; 8153 } 8154 break; 8140 8155 } // end switch alloc_trt_fsm 8141 8156 … … 8406 8421 m_cc_receive_to_cleanup_fifo.update( cc_receive_to_cleanup_fifo_get, 8407 8422 cc_receive_to_cleanup_fifo_put, 8408 ( (uint64_t)(p_dspin_in.eop.read() & 0x1 ) << 32 ) | p_dspin_in.data.read() ); 8423 ( (uint64_t)(p_dspin_p2m.eop.read() & 0x1 ) << 32 ) | p_dspin_p2m.data.read() ); 8424 8409 8425 //////////////////////////////////////////////////////////////////////////////////// 8410 8426 // CC_RECEIVE to MULTI_ACK FIFO … … 8413 8429 m_cc_receive_to_multi_ack_fifo.update( cc_receive_to_multi_ack_fifo_get, 8414 8430 cc_receive_to_multi_ack_fifo_put, 8415 p_dspin_ in.data.read() );8431 p_dspin_p2m.data.read() ); 8416 8432 8417 8433 //////////////////////////////////////////////////////////////////////////////////// … … 8562 8578 p_vci_ixr.address = (addr_t)((r_cleanup_to_ixr_cmd_nline.read() * m_words + 8563 8579 r_ixr_cmd_cpt.read()) * 4); 8580 #if ODCCP_NON_INCLUSIVE 8581 p_vci_ixr.wdata = ((wide_data_t)(r_cleanup_to_ixr_cmd_data[r_ixr_cmd_cpt.read()].read()) | 8582 ((wide_data_t)(r_cleanup_to_ixr_cmd_data[r_ixr_cmd_cpt.read() + 1].read()) << 32)); 8583 #else 8584 p_vci_ixr.wdata = ((wide_data_t)(r_ixr_cmd_data[r_ixr_cmd_cpt.read()].read()) | 8585 ((wide_data_t)(r_ixr_cmd_data[r_ixr_cmd_cpt.read() + 1].read()) << 32)); 8586 #endif 8564 8587 8588 /* 8565 8589 if(r_cleanup_to_ixr_cmd_l1_dirty_ncc.read()) // if cleanup data contains data, we use cleanup_data buffer (cleanup dirty) 8566 8590 { … … 8573 8597 ((wide_data_t)(r_xram_rsp_to_ixr_cmd_data[r_ixr_cmd_cpt.read() + 1].read()) << 32)); 8574 8598 } 8575 8599 */ 8576 8600 p_vci_ixr.trdid = r_cleanup_to_ixr_cmd_trdid.read(); 8577 8601 p_vci_ixr.eop = (r_ixr_cmd_cpt == (m_words - 2)); … … 8777 8801 8778 8802 //////////////////////////////////////////////////////////////////// 8779 // p_dspin_ outport (CC_SEND FSM)8803 // p_dspin_m2p port (CC_SEND FSM) 8780 8804 //////////////////////////////////////////////////////////////////// 8781 8805 8782 p_dspin_ out.write = false;8783 p_dspin_ out.eop = false;8784 p_dspin_ out.data = 0;8806 p_dspin_m2p.write = false; 8807 p_dspin_m2p.eop = false; 8808 p_dspin_m2p.data = 0; 8785 8809 8786 8810 switch(r_cc_send_fsm.read()) … … 8791 8815 case CC_SEND_WRITE_IDLE: 8792 8816 case CC_SEND_CAS_IDLE: 8793 case CC_SEND_CLEANUP_IDLE:8794 8817 { 8795 8818 break; … … 8826 8849 DspinDhccpParam::dspin_set( flit, 8827 8850 multi_inval_type, 8828 DspinDhccpParam:: FROM_MC_TYPE);8829 p_dspin_ out.write = true;8830 p_dspin_ out.data = flit;8851 DspinDhccpParam::M2P_TYPE); 8852 p_dspin_m2p.write = true; 8853 p_dspin_m2p.data = flit; 8831 8854 break; 8832 8855 } … … 8838 8861 r_config_to_cc_send_nline.read(), 8839 8862 DspinDhccpParam::MULTI_INVAL_NLINE); 8840 p_dspin_ out.eop = true;8841 p_dspin_ out.write = true;8842 p_dspin_ out.data = flit;8863 p_dspin_m2p.eop = true; 8864 p_dspin_m2p.write = true; 8865 p_dspin_m2p.data = flit; 8843 8866 break; 8844 8867 } 8845 ////////////////////////8846 case CC_SEND_CLEANUP_ACK:8847 {8848 uint8_t cleanup_ack_type;8849 if(r_cleanup_to_cc_send_inst.read())8850 {8851 cleanup_ack_type = DspinDhccpParam::TYPE_CLEANUP_ACK_INST;8852 }8853 else8854 {8855 cleanup_ack_type = DspinDhccpParam::TYPE_CLEANUP_ACK_DATA;8856 }8857 8858 uint64_t flit = 0;8859 uint64_t dest =8860 r_cleanup_to_cc_send_srcid.read() <<8861 (DspinDhccpParam::SRCID_WIDTH - vci_param_int::S);8862 8863 DspinDhccpParam::dspin_set(8864 flit,8865 dest,8866 DspinDhccpParam::CLEANUP_ACK_DEST);8867 8868 DspinDhccpParam::dspin_set(8869 flit,8870 r_cleanup_to_cc_send_set_index.read(),8871 DspinDhccpParam::CLEANUP_ACK_SET);8872 8873 DspinDhccpParam::dspin_set(8874 flit,8875 r_cleanup_to_cc_send_way_index.read(),8876 DspinDhccpParam::CLEANUP_ACK_WAY);8877 8878 DspinDhccpParam::dspin_set(8879 flit,8880 cleanup_ack_type,8881 DspinDhccpParam::FROM_MC_TYPE);8882 8883 p_dspin_out.eop = true;8884 p_dspin_out.write = true;8885 p_dspin_out.data = flit;8886 8887 break;8888 }8889 8890 8868 /////////////////////////////////// 8891 8869 case CC_SEND_XRAM_RSP_INVAL_HEADER: … … 8921 8899 DspinDhccpParam::dspin_set( flit, 8922 8900 multi_inval_type, 8923 DspinDhccpParam:: FROM_MC_TYPE);8924 p_dspin_ out.write = true;8925 p_dspin_ out.data = flit;8901 DspinDhccpParam::M2P_TYPE); 8902 p_dspin_m2p.write = true; 8903 p_dspin_m2p.data = flit; 8926 8904 break; 8927 8905 } … … 8935 8913 r_xram_rsp_to_cc_send_nline.read(), 8936 8914 DspinDhccpParam::MULTI_INVAL_NLINE); 8937 p_dspin_ out.eop = true;8938 p_dspin_ out.write = true;8939 p_dspin_ out.data = flit;8915 p_dspin_m2p.eop = true; 8916 p_dspin_m2p.write = true; 8917 p_dspin_m2p.data = flit; 8940 8918 break; 8941 8919 } … … 8959 8937 DspinDhccpParam::dspin_set( flit, 8960 8938 1ULL, 8961 DspinDhccpParam:: FROM_MC_BC);8962 p_dspin_ out.write = true;8963 p_dspin_ out.data = flit;8939 DspinDhccpParam::M2P_BC); 8940 p_dspin_m2p.write = true; 8941 p_dspin_m2p.data = flit; 8964 8942 break; 8965 8943 } … … 8971 8949 r_xram_rsp_to_cc_send_nline.read(), 8972 8950 DspinDhccpParam::BROADCAST_NLINE); 8973 p_dspin_ out.write = true;8974 p_dspin_ out.eop = true;8975 p_dspin_ out.data = flit;8951 p_dspin_m2p.write = true; 8952 p_dspin_m2p.eop = true; 8953 p_dspin_m2p.data = flit; 8976 8954 break; 8977 8955 } … … 8983 8961 r_config_to_cc_send_nline.read(), 8984 8962 DspinDhccpParam::BROADCAST_NLINE); 8985 p_dspin_ out.write = true;8986 p_dspin_ out.eop = true;8987 p_dspin_ out.data = flit;8963 p_dspin_m2p.write = true; 8964 p_dspin_m2p.eop = true; 8965 p_dspin_m2p.data = flit; 8988 8966 break; 8989 8967 } … … 8995 8973 r_write_to_cc_send_nline.read(), 8996 8974 DspinDhccpParam::BROADCAST_NLINE); 8997 p_dspin_ out.write = true;8998 p_dspin_ out.eop = true;8999 p_dspin_ out.data = flit;8975 p_dspin_m2p.write = true; 8976 p_dspin_m2p.eop = true; 8977 p_dspin_m2p.data = flit; 9000 8978 break; 9001 8979 } … … 9007 8985 r_cas_to_cc_send_nline.read(), 9008 8986 DspinDhccpParam::BROADCAST_NLINE); 9009 p_dspin_ out.write = true;9010 p_dspin_ out.eop = true;9011 p_dspin_ out.data = flit;8987 p_dspin_m2p.write = true; 8988 p_dspin_m2p.eop = true; 8989 p_dspin_m2p.data = flit; 9012 8990 break; 9013 8991 } … … 9050 9028 flit, 9051 9029 multi_updt_type, 9052 DspinDhccpParam:: FROM_MC_TYPE);9053 9054 p_dspin_ out.write = true;9055 p_dspin_ out.data = flit;9030 DspinDhccpParam::M2P_TYPE); 9031 9032 p_dspin_m2p.write = true; 9033 p_dspin_m2p.data = flit; 9056 9034 9057 9035 break; … … 9072 9050 DspinDhccpParam::MULTI_UPDT_NLINE); 9073 9051 9074 p_dspin_ out.write = true;9075 p_dspin_ out.data = flit;9052 p_dspin_m2p.write = true; 9053 p_dspin_m2p.data = flit; 9076 9054 9077 9055 break; … … 9099 9077 DspinDhccpParam::MULTI_UPDT_DATA); 9100 9078 9101 p_dspin_ out.write = true;9102 p_dspin_ out.eop = (r_cc_send_cpt.read() == (r_write_to_cc_send_count.read()-1));9103 p_dspin_ out.data = flit;9079 p_dspin_m2p.write = true; 9080 p_dspin_m2p.eop = (r_cc_send_cpt.read() == (r_write_to_cc_send_count.read()-1)); 9081 p_dspin_m2p.data = flit; 9104 9082 9105 9083 break; … … 9143 9121 flit, 9144 9122 multi_updt_type, 9145 DspinDhccpParam:: FROM_MC_TYPE);9146 9147 p_dspin_ out.write = true;9148 p_dspin_ out.data = flit;9123 DspinDhccpParam::M2P_TYPE); 9124 9125 p_dspin_m2p.write = true; 9126 p_dspin_m2p.data = flit; 9149 9127 9150 9128 break; … … 9165 9143 DspinDhccpParam::MULTI_UPDT_NLINE); 9166 9144 9167 p_dspin_ out.write = true;9168 p_dspin_ out.data = flit;9145 p_dspin_m2p.write = true; 9146 p_dspin_m2p.data = flit; 9169 9147 9170 9148 break; … … 9185 9163 DspinDhccpParam::MULTI_UPDT_DATA); 9186 9164 9187 p_dspin_ out.write = true;9188 p_dspin_ out.eop = not r_cas_to_cc_send_is_long.read();9189 p_dspin_ out.data = flit;9165 p_dspin_m2p.write = true; 9166 p_dspin_m2p.eop = not r_cas_to_cc_send_is_long.read(); 9167 p_dspin_m2p.data = flit; 9190 9168 9191 9169 break; … … 9206 9184 DspinDhccpParam::MULTI_UPDT_DATA); 9207 9185 9208 p_dspin_ out.write = true;9209 p_dspin_ out.eop = true;9210 p_dspin_ out.data = flit;9186 p_dspin_m2p.write = true; 9187 p_dspin_m2p.eop = true; 9188 p_dspin_m2p.data = flit; 9211 9189 9212 9190 break; … … 9214 9192 } 9215 9193 9194 //////////////////////////////////////////////////////////////////// 9195 // p_dspin_clack port (CLEANUP FSM) 9196 //////////////////////////////////////////////////////////////////// 9197 9198 switch(r_cleanup_fsm.read()) 9199 { 9200 case CLEANUP_IDLE: 9201 case CLEANUP_GET_NLINE: 9202 case CLEANUP_DIR_REQ: 9203 case CLEANUP_DIR_LOCK: 9204 case CLEANUP_DIR_WRITE: 9205 case CLEANUP_HEAP_REQ: 9206 case CLEANUP_HEAP_LOCK: 9207 case CLEANUP_HEAP_SEARCH: 9208 case CLEANUP_HEAP_CLEAN: 9209 case CLEANUP_HEAP_FREE: 9210 case CLEANUP_IVT_LOCK: 9211 case CLEANUP_IVT_DECREMENT: 9212 case CLEANUP_IVT_CLEAR: 9213 case CLEANUP_WRITE_RSP: 9214 case CLEANUP_CONFIG_ACK: 9215 p_dspin_clack.write = false; 9216 p_dspin_clack.eop = false; 9217 p_dspin_clack.data = 0; 9218 9219 break; 9220 9221 case CLEANUP_SEND_CLACK: 9222 { 9223 uint8_t cleanup_ack_type; 9224 if(r_cleanup_inst.read()) 9225 { 9226 cleanup_ack_type = DspinDhccpParam::TYPE_CLACK_INST; 9227 } 9228 else 9229 { 9230 cleanup_ack_type = DspinDhccpParam::TYPE_CLACK_DATA; 9231 } 9232 9233 uint64_t flit = 0; 9234 uint64_t dest = 9235 r_cleanup_srcid.read() << 9236 (DspinDhccpParam::SRCID_WIDTH - vci_param_int::S); 9237 9238 DspinDhccpParam::dspin_set( 9239 flit, 9240 dest, 9241 DspinDhccpParam::CLACK_DEST); 9242 9243 DspinDhccpParam::dspin_set( 9244 flit, 9245 r_cleanup_nline.read() & 0xFFFF, 9246 DspinDhccpParam::CLACK_SET); 9247 9248 DspinDhccpParam::dspin_set( 9249 flit, 9250 r_cleanup_way_index.read(), 9251 DspinDhccpParam::CLACK_WAY); 9252 9253 DspinDhccpParam::dspin_set( 9254 flit, 9255 cleanup_ack_type, 9256 DspinDhccpParam::CLACK_TYPE); 9257 9258 p_dspin_clack.eop = true; 9259 p_dspin_clack.write = true; 9260 p_dspin_clack.data = flit; 9261 } 9262 break; 9263 } 9264 9216 9265 /////////////////////////////////////////////////////////////////// 9217 // p_dspin_ inport (CC_RECEIVE FSM)9266 // p_dspin_p2m port (CC_RECEIVE FSM) 9218 9267 /////////////////////////////////////////////////////////////////// 9219 p_dspin_in.read = false;9268 // 9220 9269 switch(r_cc_receive_fsm.read()) 9221 9270 { 9222 9271 case CC_RECEIVE_IDLE: 9223 9272 { 9273 p_dspin_p2m.read = false; 9224 9274 break; 9225 9275 } … … 9227 9277 case CC_RECEIVE_CLEANUP_EOP: 9228 9278 { 9229 p_dspin_ in.read = m_cc_receive_to_cleanup_fifo.wok();9279 p_dspin_p2m.read = m_cc_receive_to_cleanup_fifo.wok(); 9230 9280 break; 9231 9281 } 9232 9282 case CC_RECEIVE_MULTI_ACK: 9233 9283 { 9234 p_dspin_ in.read = m_cc_receive_to_multi_ack_fifo.wok();9284 p_dspin_p2m.read = m_cc_receive_to_multi_ack_fifo.wok(); 9235 9285 break; 9236 9286 }
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