Index: branches/ODCCP/modules/vci_cc_vcache_wrapper/caba/metadata/vci_cc_vcache_wrapper.sd =================================================================== --- branches/ODCCP/modules/vci_cc_vcache_wrapper/caba/metadata/vci_cc_vcache_wrapper.sd (revision 474) +++ branches/ODCCP/modules/vci_cc_vcache_wrapper/caba/metadata/vci_cc_vcache_wrapper.sd (revision 479) @@ -37,8 +37,10 @@ ports = [ Port('caba:vci_initiator', 'p_vci'), - Port('caba:dspin_input', 'p_dspin_in', + Port('caba:dspin_input', 'p_dspin_m2p', dspin_data_size = parameter.Reference('dspin_in_width')), - Port('caba:dspin_output', 'p_dspin_out', + Port('caba:dspin_output', 'p_dspin_p2m', dspin_data_size = parameter.Reference('dspin_out_width')), + Port('caba:dspin_input', 'p_dspin_clack', + dspin_data_size = parameter.Reference('dspin_in_width')), Port('caba:bit_in','p_irq', parameter.Constant('n_irq')), Port('caba:bit_in', 'p_resetn', auto = 'resetn'), Index: branches/ODCCP/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h =================================================================== --- branches/ODCCP/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h (revision 474) +++ branches/ODCCP/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h (revision 479) @@ -89,8 +89,6 @@ // handling coherence requests ICACHE_CC_CHECK, + ICACHE_CC_UPDT, ICACHE_CC_INVAL, - ICACHE_CC_UPDT, - ICACHE_CC_BROADCAST, - ICACHE_CC_SEND_WAIT, }; @@ -141,9 +139,7 @@ // handling coherence requests DCACHE_CC_CHECK, + DCACHE_CC_UPDT, + DCACHE_CC_INVAL, DCACHE_CC_INVAL_DATA, - DCACHE_CC_INVAL, - DCACHE_CC_UPDT, - DCACHE_CC_BROADCAST, - DCACHE_CC_SEND_WAIT, // handling TLB inval (after a coherence or XTN request) DCACHE_INVAL_TLB_SCAN, @@ -177,12 +173,16 @@ { CC_RECEIVE_IDLE, - CC_RECEIVE_CLACK, CC_RECEIVE_BRDCAST_HEADER, CC_RECEIVE_BRDCAST_NLINE, - CC_RECEIVE_INVAL_HEADER, - CC_RECEIVE_INVAL_NLINE, - CC_RECEIVE_UPDT_HEADER, - CC_RECEIVE_UPDT_NLINE, - CC_RECEIVE_UPDT_DATA, + CC_RECEIVE_INS_INVAL_HEADER, + CC_RECEIVE_INS_INVAL_NLINE, + CC_RECEIVE_INS_UPDT_HEADER, + CC_RECEIVE_INS_UPDT_NLINE, + CC_RECEIVE_INS_UPDT_DATA, + CC_RECEIVE_DATA_INVAL_HEADER, + CC_RECEIVE_DATA_INVAL_NLINE, + CC_RECEIVE_DATA_UPDT_HEADER, + CC_RECEIVE_DATA_UPDT_NLINE, + CC_RECEIVE_DATA_UPDT_DATA, }; @@ -301,10 +301,11 @@ public: - sc_in p_clk; - sc_in p_resetn; - sc_in p_irq[iss_t::n_irq]; - soclib::caba::VciInitiator p_vci; - soclib::caba::DspinInput p_dspin_in; - soclib::caba::DspinOutput p_dspin_out; + sc_in p_clk; + sc_in p_resetn; + sc_in p_irq[iss_t::n_irq]; + soclib::caba::VciInitiator p_vci; + soclib::caba::DspinInput p_dspin_m2p; + soclib::caba::DspinOutput p_dspin_p2m; + soclib::caba::DspinInput p_dspin_clack; private: @@ -387,4 +388,9 @@ sc_signal r_icache_cc_need_write; // activate the cache for writing + // coherence clack handling + sc_signal r_icache_clack_req; // clack request + sc_signal r_icache_clack_way; // clack way + sc_signal r_icache_clack_set; // clack set + // icache flush handling sc_signal r_icache_flush_count; // slot counter used for cache flush @@ -459,4 +465,9 @@ sc_signal r_dcache_cc_word; // word counter for cc update sc_signal r_dcache_cc_need_write; // activate the cache for writing + + // coherence clack handling + sc_signal r_dcache_clack_req; // clack request + sc_signal r_dcache_clack_way; // clack way + sc_signal r_dcache_clack_set; // clack set // dcache flush handling @@ -586,4 +597,10 @@ sc_signal r_cc_receive_dcache_nline; // cache line physical address + /////////////////////////////////// + // DSPIN CLACK INTERFACE REGISTER + /////////////////////////////////// + sc_signal r_dspin_clack_req; + sc_signal r_dspin_clack_flit; + ////////////////////////////////////////////////////////////////// // processor, write buffer, caches , TLBs Index: branches/ODCCP/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp =================================================================== --- branches/ODCCP/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp (revision 474) +++ branches/ODCCP/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp (revision 479) @@ -65,8 +65,6 @@ "ICACHE_CC_CHECK", + "ICACHE_CC_UPDT", "ICACHE_CC_INVAL", - "ICACHE_CC_UPDT", - "ICACHE_CC_BROADCAST", - "ICACHE_CC_SEND_WAIT", }; @@ -116,9 +114,7 @@ "DCACHE_CC_CHECK", + "DCACHE_CC_UPDT", + "DCACHE_CC_INVAL", "DCACHE_CC_INVAL_DATA", - "DCACHE_CC_INVAL", - "DCACHE_CC_UPDT", - "DCACHE_CC_BROADCAST", - "DCACHE_CC_SEND_WAIT", "DCACHE_INVAL_TLB_SCAN", @@ -167,12 +163,16 @@ const char *cc_receive_fsm_state_str[] = { "CC_RECEIVE_IDLE", - "CC_RECEIVE_CLACK", "CC_RECEIVE_BRDCAST_HEADER", "CC_RECEIVE_BRDCAST_NLINE", - "CC_RECEIVE_INVAL_HEADER", - "CC_RECEIVE_INVAL_NLINE", - "CC_RECEIVE_UPDT_HEADER", - "CC_RECEIVE_UPDT_NLINE", - "CC_RECEIVE_UPDT_DATA", + "CC_RECEIVE_INS_INVAL_HEADER", + "CC_RECEIVE_INS_INVAL_NLINE", + "CC_RECEIVE_INS_UPDT_HEADER", + "CC_RECEIVE_INS_UPDT_NLINE", + "CC_RECEIVE_INS_UPDT_DATA", + "CC_RECEIVE_DATA_INVAL_HEADER", + "CC_RECEIVE_DATA_INVAL_NLINE", + "CC_RECEIVE_DATA_UPDT_HEADER", + "CC_RECEIVE_DATA_UPDT_NLINE", + "CC_RECEIVE_DATA_UPDT_DATA", }; @@ -224,6 +224,7 @@ p_resetn("p_resetn"), p_vci("p_vci"), - p_dspin_in("p_dspin_in"), - p_dspin_out("p_dspin_out"), + p_dspin_m2p("p_dspin_m2p"), + p_dspin_p2m("p_dspin_p2m"), + p_dspin_clack("p_dspin_clack"), m_cacheability_table( mtd.getCacheabilityTable() ), @@ -792,4 +793,6 @@ r_icache_cc_send_req = false; + r_icache_clack_req = false; + // No pending write in pipeline r_dcache_wbuf_req = false; @@ -812,4 +815,6 @@ r_dcache_cc_send_req = false; + r_dcache_clack_req = false; + // No request from CC_RECEIVE FSM to ICACHE/DCACHE FSMs r_cc_receive_icache_req = false; @@ -826,4 +831,6 @@ r_icache_miss_inval = false; r_dcache_miss_inval = false; + + r_dspin_clack_req = false; // No signalisation of errors @@ -1077,4 +1084,12 @@ // 5/ uncacheable read miss => ICACHE_UNC_REQ { + // coherence clack interrupt + if ( r_icache_clack_req.read() ) + { + r_icache_fsm = ICACHE_CC_CHECK; + r_icache_fsm_save = r_icache_fsm.read(); + break; + } + // coherence interrupt if ( r_cc_receive_icache_req.read()) @@ -1306,4 +1321,12 @@ // external coherence request are accepted in this state. { + // coherence clack interrupt + if ( r_icache_clack_req.read() ) + { + r_icache_fsm = ICACHE_CC_CHECK; + r_icache_fsm_save = r_icache_fsm.read(); + break; + } + // coherence interrupt if ( r_cc_receive_icache_req.read() ) @@ -1350,4 +1373,12 @@ // A cleanup request is generated for each valid line { + // coherence clack interrupt + if ( r_icache_clack_req.read() ) + { + r_icache_fsm = ICACHE_CC_CHECK; + r_icache_fsm_save = r_icache_fsm.read(); + break; + } + // coherence request (from CC_RECEIVE FSM) if ( r_cc_receive_icache_req.read() ) @@ -1548,4 +1579,12 @@ { if (m_ireq.valid) m_cost_ins_miss_frz++; + + // coherence clack interrupt + if ( r_icache_clack_req.read() ) + { + r_icache_fsm = ICACHE_CC_CHECK; + r_icache_fsm_save = r_icache_fsm.read(); + break; + } // coherence interrupt @@ -1638,4 +1677,12 @@ if (m_ireq.valid) m_cost_ins_miss_frz++; + // coherence clack interrupt + if ( r_icache_clack_req.read() ) + { + r_icache_fsm = ICACHE_CC_CHECK; + r_icache_fsm_save = r_icache_fsm.read(); + break; + } + // coherence interrupt if ( r_cc_receive_icache_req.read() ) @@ -1709,4 +1756,12 @@ if ( m_ireq.valid ) m_cost_ins_miss_frz++; + // coherence clack interrupt + if ( r_icache_clack_req.read() ) + { + r_icache_fsm = ICACHE_CC_CHECK; + r_icache_fsm_save = r_icache_fsm.read(); + break; + } + // coherence interrupt if ( r_cc_receive_icache_req.read() ) @@ -1780,4 +1835,12 @@ case ICACHE_UNC_WAIT: // waiting a response to an uncacheable read from VCI_RSP FSM { + // coherence clack interrupt + if ( r_icache_clack_req.read() ) + { + r_icache_fsm = ICACHE_CC_CHECK; + r_icache_fsm_save = r_icache_fsm.read(); + break; + } + // coherence interrupt if ( r_cc_receive_icache_req.read() ) @@ -1820,41 +1883,13 @@ paddr_t mask = ~((m_icache_words<<2)-1); - if (r_cc_receive_icache_type.read() == CC_TYPE_CLACK) - // We switch the directory slot to EMPTY state - // and reset r_icache_miss_clack if the cleanup ack - // is matching a pending miss - { - - if ( m_ireq.valid ) m_cost_ins_miss_frz++; - -#ifdef INSTRUMENTATION -m_cpt_icache_dir_write++; -#endif - r_icache.write_dir( 0, - r_cc_receive_icache_way.read(), - r_cc_receive_icache_set.read(), - CACHE_SLOT_STATE_EMPTY); - - if ( (r_icache_miss_set.read() == r_cc_receive_icache_set.read()) and - (r_icache_miss_way.read() == r_cc_receive_icache_way.read()) ) - r_icache_miss_clack = false; - - r_icache_fsm = r_icache_fsm_save.read() ; - r_cc_receive_icache_req = false; - -#if DEBUG_ICACHE -if ( m_debug_activated ) -{ - std::cout << " CC_TYPE_CLACK slot returns to empty state" - << " set = " << r_cc_receive_icache_set.read() - << " / way = " << r_cc_receive_icache_way.read() << std::endl; -} -#endif - } - else if( ((r_icache_fsm_save.read() == ICACHE_MISS_SELECT) or - (r_icache_fsm_save.read() == ICACHE_MISS_WAIT) or - (r_icache_fsm_save.read() == ICACHE_MISS_DIR_UPDT)) and - ((r_icache_vci_paddr.read() & mask) == (paddr & mask)) ) // matching + + // Match between MISS address and CC address + // note: In the same cycle we can handle a CLACK and a MISS match + // because the CLACK access the directory but the MISS match dont. + if (r_cc_receive_icache_req.read() and + ((r_icache_fsm_save.read() == ICACHE_MISS_SELECT ) or + (r_icache_fsm_save.read() == ICACHE_MISS_WAIT ) or + (r_icache_fsm_save.read() == ICACHE_MISS_DIR_UPDT)) and + ((r_icache_vci_paddr.read() & mask) == (paddr & mask)) ) // matching { // signaling the matching @@ -1867,4 +1902,5 @@ r_icache_fsm = ICACHE_CC_UPDT; r_icache_cc_word = r_cc_receive_word_idx.read(); + // just pop the fifo , don't write in icache r_icache_cc_need_write = false; @@ -1885,63 +1921,33 @@ #endif } - else // no match - { - int state = 0; - size_t way = 0; - size_t set = 0; - size_t word = 0; + + // CLACK handler + // We switch the directory slot to EMPTY state + // and reset r_icache_miss_clack if the cleanup ack + // is matching a pending miss. + if ( r_icache_clack_req.read() ) + { + + if ( m_ireq.valid ) m_cost_ins_miss_frz++; #ifdef INSTRUMENTATION -m_cpt_icache_dir_read++; -#endif - r_icache.read_dir(paddr, - &state, - &way, - &set, - &word); - - r_icache_cc_way = way; - r_icache_cc_set = set; - - if ( state == CACHE_SLOT_STATE_VALID_CC) // hit - { - // need to update the cache state - r_icache_cc_need_write = true; - if (r_cc_receive_icache_type.read() == CC_TYPE_UPDT) // hit update - { - r_icache_fsm = ICACHE_CC_UPDT; - r_icache_cc_word = r_cc_receive_word_idx.read(); - } - else if (r_cc_receive_icache_type.read() == CC_TYPE_INVAL) // hit inval - { - r_icache_fsm = ICACHE_CC_INVAL; - } - else if (r_cc_receive_icache_type.read() == CC_TYPE_BRDCAST) // hit broadcast - { - r_icache_fsm = ICACHE_CC_BROADCAST; - } - } - else // miss - { - // multicast acknowledgement required in case of update - if(r_cc_receive_icache_type.read() == CC_TYPE_UPDT) - { - r_icache_fsm = ICACHE_CC_UPDT; - r_icache_cc_word = r_cc_receive_word_idx.read(); - // just pop the fifo , don't write in icache - r_icache_cc_need_write = false; - } - else // No response needed - { - r_cc_receive_icache_req = false; - r_icache_fsm = r_icache_fsm_save.read(); - } - } - } - break; - } - ///////////////////// - case ICACHE_CC_INVAL: // hit inval : switch slot to EMPTY state - { +m_cpt_icache_dir_write++; +#endif + r_icache.write_dir( 0, + r_icache_clack_way.read(), + r_icache_clack_set.read(), + CACHE_SLOT_STATE_EMPTY); + + if ( (r_icache_miss_set.read() == r_icache_clack_set.read()) and + (r_icache_miss_way.read() == r_icache_clack_way.read()) ) + { + r_icache_miss_clack = false; + } + + r_icache_clack_req = false; + + // return to cc_save state if no pending CC request + if ( not r_cc_receive_icache_req.read() ) + r_icache_fsm = r_icache_fsm_save.read(); #if DEBUG_ICACHE @@ -1949,38 +1955,105 @@ { std::cout << " slot returns to empty state" - << " set = " << r_icache_cc_set.read() - << " / way = " << r_icache_cc_way.read() << std::endl; + << " ICACHE_CC_CHECK> CC_TYPE_CLACK slot returns to empty state" + << " set = " << r_icache_clack_set.read() + << " / way = " << r_icache_clack_way.read() << std::endl; } #endif + + break; + } + + // wait if pending request to CC_SEND. This way if there are pending + // CLACK they can be treated in this state and then a deadlock + // situation is avoided + if ( r_icache_cc_send_req.read() ) break; + + // CC request handler + + int state = 0; + size_t way = 0; + size_t set = 0; + size_t word = 0; #ifdef INSTRUMENTATION m_cpt_icache_dir_read++; #endif - - if (r_icache_cc_need_write.read()) - { - r_icache.write_dir( 0, - r_icache_cc_way.read(), - r_icache_cc_set.read(), - CACHE_SLOT_STATE_EMPTY ); - // no need to write in the cache anymore + r_icache.read_dir(paddr, + &state, + &way, + &set, + &word); + + r_icache_cc_way = way; + r_icache_cc_set = set; + + if ( state == CACHE_SLOT_STATE_VALID_CC) // hit + { + // need to update the cache state + if (r_cc_receive_icache_type.read() == CC_TYPE_UPDT) // hit update + { + r_icache_cc_need_write = true; + r_icache_fsm = ICACHE_CC_UPDT; + r_icache_cc_word = r_cc_receive_word_idx.read(); + } + else if ( r_cc_receive_icache_type.read() == CC_TYPE_INVAL ) // hit inval + { + r_icache_fsm = ICACHE_CC_INVAL; + } + } + else // miss + { + // multicast acknowledgement required in case of update + if(r_cc_receive_icache_type.read() == CC_TYPE_UPDT) + { + r_icache_fsm = ICACHE_CC_UPDT; + r_icache_cc_word = r_cc_receive_word_idx.read(); + + // just pop the fifo , don't write in icache r_icache_cc_need_write = false; } - // multicast acknowledgement - // send a request to cc_send_fsm - if(not r_icache_cc_send_req.read()) // cc_send is available - { - // coherence request completed - r_cc_receive_icache_req = false; - // request multicast acknowledgement - r_icache_cc_send_req = true; - r_icache_cc_send_nline = r_cc_receive_icache_nline.read(); - r_icache_cc_send_updt_tab_idx = r_cc_receive_icache_updt_tab_idx.read(); - r_icache_cc_send_type = CC_TYPE_MULTI_ACK; - - r_icache_fsm = r_icache_fsm_save.read(); - } - //else wait for previous cc_send request to be sent + else // No response needed + { + r_cc_receive_icache_req = false; + r_icache_fsm = r_icache_fsm_save.read(); + } + } + break; + } + ///////////////////// + case ICACHE_CC_INVAL: // hit inval : switch slot to ZOMBI state + { + assert (not r_icache_cc_send_req.read() && + "ERROR in ICACHE_CC_INVAL: the r_icache_cc_send_req " + "must not be set"); + +#ifdef INSTRUMENTATION +m_cpt_icache_dir_read++; +#endif + + // Switch slot state to ZOMBI and send CLEANUP command + r_icache.write_dir( 0, + r_icache_cc_way.read(), + r_icache_cc_set.read(), + CACHE_SLOT_STATE_ZOMBI ); + + // coherence request completed + r_icache_cc_send_req = true; + r_icache_cc_send_nline = r_cc_receive_icache_nline.read(); + r_icache_cc_send_way = r_icache_cc_way.read(); + r_icache_cc_send_type = CC_TYPE_CLEANUP; + + r_icache_fsm = r_icache_fsm_save.read(); + +#if DEBUG_ICACHE +if ( m_debug_activated ) +{ +std::cout << " slot returns to ZOMBI state" + << " set = " << r_icache_cc_set.read() + << " / way = " << r_icache_cc_way.read() << std::endl; +} +#endif + break; } @@ -1988,4 +2061,28 @@ case ICACHE_CC_UPDT: // hit update : write one word per cycle { + assert (not r_icache_cc_send_req.read() && + "ERROR in ICACHE_CC_UPDT: the r_icache_cc_send_req " + "must not be set"); + + if ( not r_cc_receive_updt_fifo_be.rok() ) break; + + + size_t word = r_icache_cc_word.read(); + size_t way = r_icache_cc_way.read(); + size_t set = r_icache_cc_set.read(); + + if (r_icache_cc_need_write.read()) + { + r_icache.write( way, + set, + word, + r_cc_receive_updt_fifo_data.read(), + r_cc_receive_updt_fifo_be.read() ); + + r_icache_cc_word = word+1; + +#ifdef INSTRUMENTATION +m_cpt_icache_data_write++; +#endif #if DEBUG_ICACHE @@ -1999,96 +2096,28 @@ } #endif - -#ifdef INSTRUMENTATION -m_cpt_icache_data_write++; -#endif - size_t word = r_icache_cc_word.read(); - size_t way = r_icache_cc_way.read(); - size_t set = r_icache_cc_set.read(); - - if (r_cc_receive_updt_fifo_be.rok()) - { - if (r_icache_cc_need_write.read()) - { - r_icache.write( way, - set, - word, - r_cc_receive_updt_fifo_data.read(), - r_cc_receive_updt_fifo_be.read() ); - - r_icache_cc_word = word+1; - } - if ( r_cc_receive_updt_fifo_eop.read() ) // last word - { + } + + if ( r_cc_receive_updt_fifo_eop.read() ) // last word + { // no need to write in the cache anymore - r_icache_cc_need_write = false; - // wait to send a request to cc_send_fsm - if(not r_icache_cc_send_req.read()) // cc_send is available - { - //consume last flit - cc_receive_updt_fifo_get = true; - // coherence request completed - r_cc_receive_icache_req = false; - // request multicast acknowledgement - r_icache_cc_send_req = true; - r_icache_cc_send_nline = r_cc_receive_icache_nline.read(); - r_icache_cc_send_updt_tab_idx = r_cc_receive_icache_updt_tab_idx.read(); - r_icache_cc_send_type = CC_TYPE_MULTI_ACK; - - r_icache_fsm = r_icache_fsm_save.read(); - } - } - else - { - //consume fifo if not eop - cc_receive_updt_fifo_get = true; - } - } + r_icache_cc_need_write = false; + + // coherence request completed + r_cc_receive_icache_req = false; + + // request multicast acknowledgement + r_icache_cc_send_req = true; + r_icache_cc_send_nline = r_cc_receive_icache_nline.read(); + r_icache_cc_send_updt_tab_idx = r_cc_receive_icache_updt_tab_idx.read(); + r_icache_cc_send_type = CC_TYPE_MULTI_ACK; + + r_icache_fsm = r_icache_fsm_save.read(); + } + //consume fifo if not eop + cc_receive_updt_fifo_get = true; + break; } - ///////////////////////// - case ICACHE_CC_BROADCAST: // hit broadcast : switch slot to ZOMBI state - // and request a cleanup - { - -#if DEBUG_ICACHE -if ( m_debug_activated ) -{ - std::cout << " Slot goes to zombi state " - << " set = " << r_icache_cc_set.read() - << " / way = " << r_icache_cc_way.read() << std::endl; -} -#endif - -#ifdef INSTRUMENTATION -m_cpt_icache_dir_write++; -#endif - if (r_icache_cc_need_write.read()) - { - r_icache.write_dir( r_icache_cc_way.read(), - r_icache_cc_set.read(), - CACHE_SLOT_STATE_ZOMBI ); - // no need to write in the cache anymore - r_icache_cc_need_write = false; - } - - // cleanup - // send a request to cc_send_fsm - if(not r_icache_cc_send_req.read()) // cc_send is available - { - // coherence request completed - r_cc_receive_icache_req = false; - // request cleanup - r_icache_cc_send_req = true; - r_icache_cc_send_nline = r_cc_receive_icache_nline.read(); - r_icache_cc_send_way = r_icache_cc_way.read(); - r_icache_cc_send_type = CC_TYPE_CLEANUP; - - r_icache_fsm = r_icache_fsm_save.read(); - } - //else wait for previous cc_send request to be sent - break; - } + } // end switch r_icache_fsm @@ -2371,4 +2400,10 @@ } + // coherence clack request (from DSPIN CLACK) + else if ( r_dcache_clack_req.read() ) + { + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_fsm_cc_save = r_dcache_fsm.read(); + } // coherence request (from CC_RECEIVE FSM) else if ( r_cc_receive_dcache_req.read() ) @@ -3067,4 +3102,12 @@ case DCACHE_TLB_PTE1_GET: // try to read a PT1 entry in dcache { + // coherence clack request (from DSPIN CLACK) + if ( r_dcache_clack_req.read() ) + { + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_fsm_cc_save = r_dcache_fsm.read(); + break; + } + // coherence request (from CC_RECEIVE FSM) if ( r_cc_receive_dcache_req.read() ) @@ -3366,4 +3409,12 @@ case DCACHE_TLB_PTE2_GET: // Try to get a PTE2 (64 bits) in the dcache { + // coherence clack request (from DSPIN CLACK) + if ( r_dcache_clack_req.read() ) + { + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_fsm_cc_save = r_dcache_fsm.read(); + break; + } + // coherence request (from CC_RECEIVE FSM) if ( r_cc_receive_dcache_req.read() ) @@ -3665,4 +3716,12 @@ { + // coherence clack request (from DSPIN CLACK) + if ( r_dcache_clack_req.read() ) + { + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_fsm_cc_save = r_dcache_fsm.read(); + break; + } + // coherence request (from CC_RECEIVE FSM) if ( r_cc_receive_dcache_req.read() ) @@ -3736,4 +3795,12 @@ // as there is a risk of dead-lock { + // coherence clack request (from DSPIN CLACK) + if ( r_dcache_clack_req.read() ) + { + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_fsm_cc_save = r_dcache_fsm.read(); + break; + } + // coherence request (from CC_RECEIVE FSM) if ( r_cc_receive_dcache_req.read() ) @@ -3741,4 +3808,5 @@ r_dcache_fsm = DCACHE_CC_CHECK; r_dcache_fsm_cc_save = r_dcache_fsm.read(); + break; } @@ -3757,4 +3825,12 @@ // and because it can exist a simultaneous ITLB miss { + // coherence clack request (from DSPIN CLACK) + if ( r_dcache_clack_req.read() ) + { + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_fsm_cc_save = r_dcache_fsm.read(); + break; + } + // coherence request (from CC_RECEIVE FSM) if ( r_cc_receive_dcache_req.read() ) @@ -3792,4 +3868,12 @@ // returns to IDLE and flush TLBs when last slot { + // coherence clack request (from DSPIN CLACK) + if ( r_dcache_clack_req.read() ) + { + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_fsm_cc_save = r_dcache_fsm.read(); + break; + } + // coherence request (from CC_RECEIVE FSM) if ( r_cc_receive_dcache_req.read() ) @@ -3895,5 +3979,4 @@ r_dcache_xtn_flush_addr_data = r_dcache_xtn_flush_addr_data.read() + 4; - cleanup_data_updt_fifo_dcache_get = false; cleanup_data_updt_fifo_dcache_put = true; cleanup_data_updt_fifo_dcache_data = rdata; @@ -4158,5 +4241,4 @@ r_dcache_xtn_data_addr = r_dcache_xtn_data_addr.read() + 4; - cleanup_data_updt_fifo_dcache_get = false; cleanup_data_updt_fifo_dcache_put = true; cleanup_data_updt_fifo_dcache_data = rdata; @@ -4193,4 +4275,12 @@ { if ( m_dreq.valid) m_cost_data_miss_frz++; + + // coherence clack request (from DSPIN CLACK) + if ( r_dcache_clack_req.read() ) + { + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_fsm_cc_save = r_dcache_fsm.read(); + break; + } // coherence request (from CC_RECEIVE FSM) @@ -4247,5 +4337,5 @@ r_dcache_fsm = DCACHE_MISS_DATA; m_cpt_data_cleanup_dirty ++; - + /*STATS DIRTY*/ for (size_t w = 0; w < m_dcache_words; w++) @@ -4294,5 +4384,4 @@ size_t set; size_t word; - r_dcache.read_neutral(r_dcache_miss_data_addr, &rdata, @@ -4300,9 +4389,9 @@ &set, &word); + if(r_cc_send_data_fifo.wok()) { r_dcache_miss_data_addr = r_dcache_miss_data_addr.read() + 4; - cleanup_data_updt_fifo_dcache_get = false; cleanup_data_updt_fifo_dcache_put = true; cleanup_data_updt_fifo_dcache_data = rdata; @@ -4314,4 +4403,14 @@ r_dcache_fsm = DCACHE_MISS_CLEAN; } +#if DEBUG_DCACHE +if ( m_debug_activated ) +{ + std::cout << " :" << std::hex + << " / DATA = " << rdata + << " / WORD = " << word + << " / PADDR = " << std::hex << r_dcache_miss_data_addr.read() << std::endl; +} +#endif } break; @@ -4370,4 +4469,12 @@ { if ( m_dreq.valid) m_cost_data_miss_frz++; + + // coherence clack request (from DSPIN CLACK) + if ( r_dcache_clack_req.read() ) + { + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_fsm_cc_save = r_dcache_fsm.read(); + break; + } // coherence request (from CC_RECEIVE FSM) @@ -4486,4 +4593,12 @@ if ( m_dreq.valid) m_cost_data_miss_frz++; + // coherence clack request (from DSPIN CLACK) + if ( r_dcache_clack_req.read() ) + { + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_fsm_cc_save = r_dcache_fsm.read(); + break; + } + // coherence request (from CC_RECEIVE FSM) if ( r_cc_receive_dcache_req.read() ) @@ -4592,4 +4707,12 @@ case DCACHE_UNC_WAIT: // waiting a response to an uncacheable read { + // coherence clack request (from DSPIN CLACK) + if ( r_dcache_clack_req.read() ) + { + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_fsm_cc_save = r_dcache_fsm.read(); + break; + } + // coherence request (from CC_RECEIVE FSM) if ( r_cc_receive_dcache_req.read() ) @@ -4629,4 +4752,12 @@ case DCACHE_LL_WAIT: // waiting VCI response to a LL transaction { + // coherence clack request (from DSPIN CLACK) + if ( r_dcache_clack_req.read() ) + { + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_fsm_cc_save = r_dcache_fsm.read(); + break; + } + // coherence request (from CC_RECEIVE FSM) if ( r_cc_receive_dcache_req.read() ) @@ -4675,4 +4806,12 @@ case DCACHE_SC_WAIT: // waiting VCI response to a SC transaction { + // coherence clack request (from DSPIN CLACK) + if ( r_dcache_clack_req.read() ) + { + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_fsm_cc_save = r_dcache_fsm.read(); + break; + } + // coherence request (from CC_RECEIVE FSM) if ( r_cc_receive_dcache_req.read() ) @@ -4714,5 +4853,5 @@ size_t way; size_t set; - size_t word; // unused + size_t word; // unused int state; @@ -4767,4 +4906,12 @@ // - if the CAS is a failure, we just retry the write. { + // coherence clack request (from DSPIN CLACK) + if ( r_dcache_clack_req.read() ) + { + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_fsm_cc_save = r_dcache_fsm.read(); + break; + } + // coherence request (from CC_RECEIVE FSM) if ( r_cc_receive_dcache_req.read() ) @@ -4775,5 +4922,5 @@ } - if ( r_vci_rsp_data_error.read() ) // bus error + if ( r_vci_rsp_data_error.read() ) // bus error { std::cout << "BUS ERROR in DCACHE_DIRTY_WAIT state" << std::endl; @@ -4781,5 +4928,5 @@ exit(0); } - else if ( r_vci_rsp_fifo_dcache.rok() ) // response available + else if ( r_vci_rsp_fifo_dcache.rok() ) // response available { vci_rsp_fifo_dcache_get = true; @@ -4825,47 +4972,13 @@ #endif - if (r_cc_receive_dcache_type.read() == CC_TYPE_CLACK) - // We switch the directory slot to EMPTY state - // and reset r_icache_miss_clack if the cleanup ack - // is matching a pending miss. - { - - if ( m_dreq.valid ) m_cost_data_miss_frz++; - -#ifdef INSTRUMENTATION -m_cpt_dcache_dir_write++; -#endif - r_dcache.write_dir( 0, - r_cc_receive_dcache_way.read(), - r_cc_receive_dcache_set.read(), - CACHE_SLOT_STATE_EMPTY); - - /*STATS DIRTY*/ - for (size_t word = 0; word < m_dcache_words; word++) - { - dirty_stats[(r_cc_receive_dcache_way * m_dcache_sets + r_cc_receive_dcache_set) * m_dcache_words + word] = false; - } - - - if ( (r_dcache_miss_set.read() == r_cc_receive_dcache_set.read()) and - (r_dcache_miss_way.read() == r_cc_receive_dcache_way.read()) ) - r_dcache_miss_clack = false; - - r_dcache_fsm = r_dcache_fsm_cc_save.read() ; - r_cc_receive_dcache_req = false; -#if DEBUG_DCACHE -if ( m_debug_activated ) -{ - std::cout << " CC_TYPE_CLACK Switch slot to EMPTY state" - << " set = " << r_cc_receive_dcache_set.read() - << " / way = " << r_cc_receive_dcache_way.read() << std::endl; -} -#endif - } - else if( ((r_dcache_fsm_cc_save == DCACHE_MISS_SELECT) or - (r_dcache_fsm_cc_save == DCACHE_MISS_WAIT) or - (r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT)) and - ((r_dcache_vci_paddr.read() & mask) == (paddr & mask)) ) // matching + + // Match between MISS address and CC address + // note: In the same cycle we can handle a CLACK and a MISS match + // because the CLACK access the directory but the MISS match dont. + if (r_cc_receive_dcache_req.read() and + ((r_dcache_fsm_cc_save == DCACHE_MISS_SELECT ) or + (r_dcache_fsm_cc_save == DCACHE_MISS_WAIT ) or + (r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT)) and + ((r_dcache_vci_paddr.read() & mask) == (paddr & mask))) // matching { // signaling matching @@ -4878,4 +4991,5 @@ r_dcache_fsm = DCACHE_CC_UPDT; r_dcache_cc_word = r_cc_receive_word_idx.read(); + // just pop the fifo , don't write in icache r_dcache_cc_need_write = false; @@ -4885,5 +4999,5 @@ { r_cc_receive_dcache_req = false; - r_dcache_fsm = r_dcache_fsm_cc_save.read(); + r_dcache_fsm = r_dcache_fsm_cc_save.read(); } @@ -4896,79 +5010,125 @@ } #endif - - } - else // no match - { - int state = 0; - size_t way = 0; - size_t set = 0; - size_t word = 0; + } + + // CLACK handler + // We switch the directory slot to EMPTY state and reset + // r_dcache_miss_clack if the cleanup ack is matching a pending miss. + if ( r_dcache_clack_req.read() ) + { + if ( m_dreq.valid ) m_cost_data_miss_frz++; + +#ifdef INSTRUMENTATION +m_cpt_dcache_dir_write++; +#endif + r_dcache.write_dir( 0, + r_dcache_clack_way.read(), + r_dcache_clack_set.read(), + CACHE_SLOT_STATE_EMPTY); + /*STATS DIRTY*/ + for (size_t word = 0; word < m_dcache_words; word++) + { + dirty_stats[(r_cc_receive_dcache_way * m_dcache_sets + r_cc_receive_dcache_set) * m_dcache_words + word] = false; + } + + if ( (r_dcache_miss_set.read() == r_dcache_clack_set.read()) and + (r_dcache_miss_way.read() == r_dcache_clack_way.read()) ) + { + r_dcache_miss_clack = false; + } + + r_dcache_clack_req = false; + + // return to cc_save state if no pending CC request + if ( not r_cc_receive_dcache_req.read() ) + { + r_dcache_fsm = r_dcache_fsm_cc_save.read() ; + } + +#if DEBUG_DCACHE +if ( m_debug_activated ) +{ + std::cout << " CC_TYPE_CLACK Switch slot to EMPTY state" + << " set = " << r_dcache_clack_set.read() + << " / way = " << r_dcache_clack_way.read() << std::endl; +} +#endif + break; + } + + // wait if pending request to CC_SEND. This way if there are pending + // CLACK they can be treated in this state and then a deadlock + // situation is avoided + if ( r_dcache_cc_send_req.read() ) break; + + // CC request handler + + int state = 0; + size_t way = 0; + size_t set = 0; + size_t word = 0; #ifdef INSTRUMENTATION m_cpt_dcache_dir_read++; #endif - r_dcache.read_dir( paddr, - &state, - &way, - &set, - &word ); // unused - - r_dcache_cc_way = way; - r_dcache_cc_set = set; - /*ODCCP*/ - if ((state == CACHE_SLOT_STATE_VALID_CC) or (state == CACHE_SLOT_STATE_VALID_NCC)) // hit - { - // need to update the cache state - r_dcache_cleanup_ncc = false; - r_dcache_cc_need_write = true; - if (r_cc_receive_dcache_type.read() == CC_TYPE_UPDT) // hit update + r_dcache.read_dir( paddr, + &state, + &way, + &set, + &word ); // unused + + r_dcache_cc_way = way; + r_dcache_cc_set = set; + /*ODCCP*/ + if ((state == CACHE_SLOT_STATE_VALID_CC) or (state == CACHE_SLOT_STATE_VALID_NCC)) // hit + { + r_dcache_cleanup_ncc = false; + r_dcache_cc_need_write = true; + if (r_cc_receive_dcache_type.read() == CC_TYPE_UPDT) // hit update + { + /*ODCCP*/ // we can't receive a CC_UPDT on a NCC line + if (state == CACHE_SLOT_STATE_VALID_NCC) + std::cout << "DCACHE_CC_CHECK : IMPOSSIBLE NCC STATE FOR CC_UPDT at cycle " << m_cpt_total_cycles << std::endl; + assert((state != CACHE_SLOT_STATE_VALID_NCC) and "DCACHE_CC_CHECK : IMPOSSIBLE NCC STATE FOR CC_UPDT"); + + r_dcache_fsm = DCACHE_CC_UPDT; + r_dcache_cc_word = r_cc_receive_word_idx.read(); + } + else if (r_cc_receive_dcache_type.read() == CC_TYPE_INVAL) // hit inval + { + if ( (state == CACHE_SLOT_STATE_VALID_NCC) ) { - /*ODCCP*/ // we can't receive a CC_UPDT on a NCC line - if (state == CACHE_SLOT_STATE_VALID_NCC) - std::cout << "DCACHE_CC_CHECK : IMPOSSIBLE NCC STATE FOR CC_UPDT at cycle " << m_cpt_total_cycles << std::endl; - assert((state != CACHE_SLOT_STATE_VALID_NCC) and "DCACHE_CC_CHECK : IMPOSSIBLE NCC STATE FOR CC_UPDT"); - - r_dcache_fsm = DCACHE_CC_UPDT; - r_dcache_cc_word = r_cc_receive_word_idx.read(); + if (r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_DATA_DIRTY) + m_cpt_data_cleanup_dirty ++; + r_dcache_cc_state = state; + r_dcache_cc_inval_addr = (paddr &~0x3F); + r_dcache_cc_inval_data_cpt = 0; } - else if (r_cc_receive_dcache_type.read() == CC_TYPE_INVAL) // hit inval + else { - if ( (state == CACHE_SLOT_STATE_VALID_NCC) ) - { - if (r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_DATA_DIRTY) - m_cpt_data_cleanup_dirty ++; - r_dcache_cc_state = state; - r_dcache_cc_inval_addr = (paddr &~0x3F); - r_dcache_cc_inval_data_cpt = 0; - } - else - { - r_dcache_cc_state = state; - r_dcache_cc_inval_addr = (paddr &~0x3F); - } - r_dcache_fsm = DCACHE_CC_INVAL; + r_dcache_cc_state = state; + r_dcache_cc_inval_addr = (paddr &~0x3F); } - else if ( r_cc_receive_dcache_type.read() == CC_TYPE_BRDCAST) // hit broadcast - { - assert((state != CACHE_SLOT_STATE_VALID_NCC) and "DCACHE_CC_CHECK : IMPOSSIBLE NCC STATE FOR CC_BROADCAST"); - r_dcache_fsm = DCACHE_CC_BROADCAST; - } - } - else // miss - { - // multicast acknowledgement required in case of update - if(r_cc_receive_dcache_type.read() == CC_TYPE_UPDT) - { - r_dcache_fsm = DCACHE_CC_UPDT; - r_dcache_cc_word = r_cc_receive_word_idx.read(); - // just pop the fifo , don't write in icache - r_dcache_cc_need_write = false; - } - else // No response needed - { - r_cc_receive_dcache_req = false; - r_dcache_fsm = r_dcache_fsm_cc_save.read(); - } - } + r_dcache_fsm = DCACHE_CC_INVAL; + } + } + else // miss + { + // multicast acknowledgement required in case of update + if(r_cc_receive_dcache_type.read() == CC_TYPE_UPDT) + { + r_dcache_fsm = DCACHE_CC_UPDT; + r_dcache_cc_word = r_cc_receive_word_idx.read(); + + // just pop the fifo , don't write in icache + r_dcache_cc_need_write = false; + } + else // No response needed + { + r_cc_receive_dcache_req = false; + r_dcache_fsm = r_dcache_fsm_cc_save.read(); + } + } #if DEBUG_DCACHE @@ -4982,4 +5142,93 @@ } #endif + + break; + } + ///////////////////// + case DCACHE_CC_INVAL: // hit inval: switch slot to ZOMBI state and send a + // CLEANUP after possible invalidation of copies in + // TLBs + { + size_t way = r_dcache_cc_way.read(); + size_t set = r_dcache_cc_set.read(); + int state = r_dcache_cc_state.read(); + if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_IN_TLB ) + { + r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_NOT_DIRTY; + r_dcache_tlb_inval_line = r_cc_receive_dcache_nline.read(); + r_dcache_tlb_inval_set = 0; + r_dcache_fsm_scan_save = r_dcache_fsm.read(); + r_dcache_fsm = DCACHE_INVAL_TLB_SCAN; + break; + } + if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_CONTAINS_PTD ) + { + r_itlb.reset(); + r_dtlb.reset(); + r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_NOT_DIRTY; + +#if DEBUG_DCACHE +if ( m_debug_activated ) +{ + std::cout << " Flush DTLB & ITLB" << std::endl; +} +#endif + } + + + if ( state == CACHE_SLOT_STATE_VALID_CC ) + { + // Switch slot state to ZOMBI and send CLEANUP command + r_dcache.write_dir( way, + set, + CACHE_SLOT_STATE_ZOMBI ); +#if DEBUG_DCACHE +if ( m_debug_activated ) +{ + std::cout << " Switch slot valid CC to ZOMBI state:" << std::dec + << " / WAY = " << way + << " / SET = " << set << std::endl; +} +#endif + } + + assert (not r_dcache_cc_send_req.read() && + "ERROR in DCACHE_CC_INVAL: the r_dcache_cc_send_req " + "must not be set"); + + // coherence request completed + r_cc_receive_dcache_req = false; + r_dcache_cc_send_req = true; + r_dcache_cc_send_nline = r_cc_receive_dcache_nline.read(); + r_dcache_cc_send_way = way; + r_dcache_cc_send_type = CC_TYPE_CLEANUP; + r_dcache_fsm = r_dcache_fsm_cc_save.read(); + + if ( (state == CACHE_SLOT_STATE_VALID_NCC) ) + { + r_dcache_cleanup_ncc = true; + + if (r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_DATA_DIRTY) + { + r_dcache_cc_cleanup_updt_data = true; + r_dcache_fsm = DCACHE_CC_INVAL_DATA; + + /*STATS DIRTY*/ + for (size_t w = 0; w < m_dcache_words; w++) + { + if(dirty_stats[(way * m_dcache_sets + set) * m_dcache_words + w] == true) + m_cpt_words_dirty++; + } + } + else + { + r_dcache_cc_cleanup_updt_data = false; + r_dcache.write_dir( way, + set, + CACHE_SLOT_STATE_ZOMBI ); + r_dcache_fsm = r_dcache_fsm_cc_save.read(); + } } break; @@ -5001,5 +5250,4 @@ r_dcache_cc_inval_addr = r_dcache_cc_inval_addr.read() + 4; - cleanup_data_updt_fifo_dcache_get = false; cleanup_data_updt_fifo_dcache_put = true; cleanup_data_updt_fifo_dcache_data = rdata; @@ -5026,138 +5274,28 @@ break; } - ///////////////////// - case DCACHE_CC_INVAL: // hit inval: switch slot to EMPTY state, + /////////////////// + case DCACHE_CC_UPDT: // hit update: write one word per cycle, // after possible invalidation of copies in TLBs { - size_t way = r_dcache_cc_way.read(); - size_t set = r_dcache_cc_set.read(); - int state = r_dcache_cc_state.read(); - if (r_dcache_cc_need_write.read()) - { - if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_IN_TLB ) - { - r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_NOT_DIRTY; - r_dcache_tlb_inval_line = r_cc_receive_dcache_nline.read(); - r_dcache_tlb_inval_set = 0; - r_dcache_fsm_scan_save = r_dcache_fsm.read(); - r_dcache_fsm = DCACHE_INVAL_TLB_SCAN; - break; - } - else - { - if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_CONTAINS_PTD ) - { - r_itlb.reset(); - r_dtlb.reset(); - r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_NOT_DIRTY; - -#if DEBUG_DCACHE - if ( m_debug_activated ) - { - std::cout << " Flush DTLB & ITLB" << std::endl; - } -#endif - } - - if ( state == CACHE_SLOT_STATE_VALID_CC ) - { - r_dcache.write_dir( 0, - way, - set, - CACHE_SLOT_STATE_EMPTY ); -#if DEBUG_DCACHE - if ( m_debug_activated ) - { - std::cout << " Switch slot to EMPTY state:" << std::dec - << " / WAY = " << way - << " / SET = " << set << std::endl; - } -#endif - } - r_dcache_cc_need_write = false; - - } - } - - // multicast acknowledgement - // send a request to cc_send_fsm - if(not r_dcache_cc_send_req.read()) // cc_send is available - { - - // coherence request completed - r_cc_receive_dcache_req = false; - r_dcache_cc_send_req = true; - r_dcache_cc_send_nline = r_cc_receive_dcache_nline.read(); - - - if ( (state == CACHE_SLOT_STATE_VALID_NCC) ) - { - r_dcache_cleanup_ncc = true; - r_dcache_cc_send_type = CC_TYPE_CLEANUP; - r_dcache_cc_send_way = way; - - if (r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_DATA_DIRTY) - { - r_dcache_cc_cleanup_updt_data = true; - r_dcache_fsm = DCACHE_CC_INVAL_DATA; - - /*STATS DIRTY*/ - for (size_t w = 0; w < m_dcache_words; w++) - { - if(dirty_stats[(way * m_dcache_sets + set) * m_dcache_words + w] == true) - m_cpt_words_dirty++; - } - } - else - { - r_dcache_cc_cleanup_updt_data = false; - r_dcache.write_dir( way, - set, - CACHE_SLOT_STATE_ZOMBI ); - r_dcache_fsm = r_dcache_fsm_cc_save.read(); - } - } - else - { - // request multicast acknowledgement - r_dcache_cc_send_updt_tab_idx = r_cc_receive_dcache_updt_tab_idx.read(); - r_dcache_cc_send_type = CC_TYPE_MULTI_ACK; - r_dcache_fsm = r_dcache_fsm_cc_save.read(); - } - } - //else wait for previous cc_send request to be sent - break; - } - /////////////////// - case DCACHE_CC_UPDT: // hit update: write one word per cycle, - // after possible invalidation of copies in TLBs - { - size_t word = r_dcache_cc_word.read(); - size_t way = r_dcache_cc_way.read(); - size_t set = r_dcache_cc_set.read(); - - if (r_cc_receive_updt_fifo_be.rok()) - { - if (r_dcache_cc_need_write.read()) - { - // selective TLB inval - if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_IN_TLB ) - { - r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_NOT_DIRTY; - r_dcache_tlb_inval_line = r_cc_receive_dcache_nline.read(); - r_dcache_tlb_inval_set = 0; - r_dcache_fsm_scan_save = r_dcache_fsm.read(); - r_dcache_fsm = DCACHE_INVAL_TLB_SCAN; - break; - } - // TLB flush - if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_CONTAINS_PTD ) - { - r_itlb.reset(); - r_dtlb.reset(); - r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_NOT_DIRTY; + size_t word = r_dcache_cc_word.read(); + size_t way = r_dcache_cc_way.read(); + size_t set = r_dcache_cc_set.read(); + + // selective TLB inval + if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_IN_TLB ) + { + r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_NOT_DIRTY; + r_dcache_tlb_inval_line = r_cc_receive_dcache_nline.read(); + r_dcache_tlb_inval_set = 0; + r_dcache_fsm_scan_save = r_dcache_fsm.read(); + r_dcache_fsm = DCACHE_INVAL_TLB_SCAN; + break; + } + // TLB flush + if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_CONTAINS_PTD ) + { + r_itlb.reset(); + r_dtlb.reset(); + r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_NOT_DIRTY; #if DEBUG_DCACHE @@ -5165,19 +5303,28 @@ { std::cout << " Flush DTLB & ITLB" << std::endl; + << " DCACHE_CC_UPDT> Flush DTLB & ITLB" << std::endl; } #endif - } - + } + + assert (not r_dcache_cc_send_req.read() && + "ERROR in DCACHE_CC_INVAL: the r_dcache_cc_send_req " + "must not be set"); + + if ( not r_cc_receive_updt_fifo_be.rok() ) break; + + if (r_dcache_cc_need_write.read()) + { + #ifdef INSTRUMENTATION m_cpt_dcache_data_write++; #endif - r_dcache.write( way, - set, - word, - r_cc_receive_updt_fifo_data.read(), - r_cc_receive_updt_fifo_be.read() ); - - r_dcache_cc_word = word + 1; + r_dcache.write( way, + set, + word, + r_cc_receive_updt_fifo_data.read(), + r_cc_receive_updt_fifo_be.read() ); + + r_dcache_cc_word = word + 1; #if DEBUG_DCACHE @@ -5192,111 +5339,26 @@ } #endif - } - - if ( r_cc_receive_updt_fifo_eop.read() ) // last word - { - // no need to write in the cache anymore - r_dcache_cc_need_write = false; - - // wait to send a request to cc_send_fsm - if(not r_dcache_cc_send_req.read()) - // cc_send is available - { - //consume last fifo flit if eop and request to cc_send possible - cc_receive_updt_fifo_get = true; - - // coherence request completed - r_cc_receive_dcache_req = false; - - // request multicast acknowledgement - r_dcache_cc_send_req = true; - r_dcache_cc_send_nline = r_cc_receive_dcache_nline.read(); - r_dcache_cc_send_updt_tab_idx = r_cc_receive_dcache_updt_tab_idx.read(); - r_dcache_cc_send_type = CC_TYPE_MULTI_ACK; - - r_dcache_fsm = r_dcache_fsm_cc_save.read(); - } - } - else - { - //consume fifo if not eop - cc_receive_updt_fifo_get = true; - } - } - break; - } - ///////////////////////// - case DCACHE_CC_BROADCAST: // hit broadcast : switch state to ZOMBI state - // and request a cleanup, after possible - // invalidation of copies in TLBs - { - size_t way = r_dcache_cc_way.read(); - size_t set = r_dcache_cc_set.read(); - paddr_t nline = r_cc_receive_dcache_nline.read(); - - if (r_dcache_cc_need_write.read()) - { - // selective TLB inval - if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_IN_TLB ) - { - r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_NOT_DIRTY; - r_dcache_tlb_inval_line = nline; - r_dcache_tlb_inval_set = 0; - r_dcache_fsm_scan_save = r_dcache_fsm.read(); - r_dcache_fsm = DCACHE_INVAL_TLB_SCAN; - break; - } - else - { - // TLB flush - if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_CONTAINS_PTD ) - { - r_itlb.reset(); - r_dtlb.reset(); - r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_NOT_DIRTY; - -#if DEBUG_DCACHE - if ( m_debug_activated ) - { - std::cout << " Flush DTLB & ITLB" << std::endl; - } -#endif - } - -#ifdef INSTRUMENTATION - m_cpt_dcache_dir_write++; -#endif - r_dcache.write_dir( way, - set, - CACHE_SLOT_STATE_ZOMBI ); - - r_dcache_cc_need_write = false; -#if DEBUG_DCACHE - if ( m_debug_activated ) - { - std::cout << " Slot goes to ZOMBI state " - << " SET = " << set - << " / WAY = " << way << std::endl; - } -#endif - } - } - // cleanup - // send a request to cc_send_fsm - if(not r_dcache_cc_send_req.read()) // cc_send is available - { + } + + if ( r_cc_receive_updt_fifo_eop.read() ) // last word + { + // no need to write in the cache anymore + r_dcache_cc_need_write = false; + // coherence request completed r_cc_receive_dcache_req = false; - // request cleanup - r_dcache_cc_send_req = true; - r_dcache_cc_send_nline = r_cc_receive_dcache_nline.read(); - r_dcache_cc_send_way = r_dcache_cc_way.read(); - r_dcache_cc_send_type = CC_TYPE_CLEANUP; - - r_dcache_fsm = r_dcache_fsm_cc_save.read(); - } - //else wait for previous cc_send request to be sent + + // request multicast acknowledgement + r_dcache_cc_send_req = true; + r_dcache_cc_send_nline = r_cc_receive_dcache_nline.read(); + r_dcache_cc_send_updt_tab_idx = r_cc_receive_dcache_updt_tab_idx.read(); + r_dcache_cc_send_type = CC_TYPE_MULTI_ACK; + + r_dcache_fsm = r_dcache_fsm_cc_save.read(); + } + + //consume fifo if not eop + cc_receive_updt_fifo_get = true; + break; } @@ -5689,7 +5751,11 @@ if ( r_vci_rsp_fifo_icache.wok() ) { - assert( (r_vci_rsp_cpt.read() < m_icache_words) and - "The VCI response packet for instruction miss is too long" ); - + if ( r_vci_rsp_cpt.read() >= m_icache_words ) + { + std::cout << "ERROR in VCI_CC_VCACHE " << name() + << " VCI response packet too long " + << " for instruction miss" << std::endl; + exit(0); + } r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1; vci_rsp_fifo_icache_put = true, @@ -5697,7 +5763,11 @@ if ( p_vci.reop.read() ) { - assert( (r_vci_rsp_cpt.read() == m_icache_words - 1) and - "The VCI response packet for instruction miss is too short"); - + if ( r_vci_rsp_cpt.read() != (m_icache_words - 1) ) + { + std::cout << "ERROR in VCI_CC_VCACHE " << name() + << " VCI response packet too short" + << " for instruction miss" << std::endl; + exit(0); + } r_vci_rsp_fsm = RSP_IDLE; } @@ -5902,5 +5972,5 @@ { // wait for the first flit to be consumed - if (p_dspin_out.read.read()) + if (p_dspin_p2m.read.read()) r_cc_send_fsm = CC_SEND_CLEANUP_2; @@ -5911,5 +5981,5 @@ { // wait for the second flit to be consumed - if (p_dspin_out.read.read()) + if (p_dspin_p2m.read.read()) { /*ODCCP*/ // If there is a cleanup with data and dcache active request we send other flits contained data @@ -5933,5 +6003,5 @@ case CC_SEND_CLEANUP_DATA_UPDT: /*ODCCP*/ // we send the data values of line cache into [m_dcache_words] flits { - if (p_dspin_out.read.read()) + if (p_dspin_p2m.read.read()) { if(r_cc_send_data_fifo.rok()) @@ -5956,5 +6026,5 @@ { // wait for the flit to be consumed - if(p_dspin_out.read.read()) + if(p_dspin_p2m.read.read()) { if(r_cc_send_last_client.read() == 0) // dcache active request @@ -5970,7 +6040,7 @@ /////////////////////////////////////////////////////////////////////////////// - // C_RECEIVE FSM + // CC_RECEIVE FSM // This FSM receive all coherence packets on a DSPIN40 port. - // There is 7 packet types: + // There is 5 packet types: // - CC_DATA_INVAL : DCACHE invalidate request // - CC_DATA_UPDT : DCACHE update request (multi-words) @@ -5978,6 +6048,4 @@ // - CC_INST_UPDT : ICACHE update request (multi-words) // - CC_BROADCAST : Broadcast invalidate request (both DCACHE & ICACHE) - // - CC_DATA_CLACK : DCACHE cleanup acknowledge - // - CC_INST_CLACK : ICACHE cleanup acknowledge ////////////////////////////////////////////////////////////////////////////// switch( r_cc_receive_fsm.read() ) @@ -5987,79 +6055,35 @@ { // a coherence request has arrived - if (p_dspin_in.write.read()) + if (p_dspin_m2p.write.read()) { // initialize dspin received data - uint64_t receive_data = p_dspin_in.data.read(); + uint64_t receive_data = p_dspin_m2p.data.read(); // initialize coherence packet type uint64_t receive_type = DspinDhccpParam::dspin_get(receive_data, - DspinDhccpParam::FROM_MC_TYPE); - // initialize data/ins flip_flop (0 data / 1 ins) - r_cc_receive_data_ins = (bool)(receive_type & 0x1); + DspinDhccpParam::M2P_TYPE); // test for a broadcast - if (DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::FROM_MC_BC)) + if (DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::M2P_BC)) { r_cc_receive_fsm = CC_RECEIVE_BRDCAST_HEADER; } - // test for a CLACK - else if ((receive_type == DspinDhccpParam::TYPE_CLEANUP_ACK_DATA) or - (receive_type == DspinDhccpParam::TYPE_CLEANUP_ACK_INST)) + // test for a multi updt + else if (receive_type == DspinDhccpParam::TYPE_MULTI_UPDT_DATA) { - r_cc_receive_fsm = CC_RECEIVE_CLACK; + r_cc_receive_fsm = CC_RECEIVE_DATA_UPDT_HEADER; } - // test for a multi updt - else if ((receive_type == DspinDhccpParam::TYPE_MULTI_UPDT_DATA) or - (receive_type == DspinDhccpParam::TYPE_MULTI_UPDT_INST)) + else if (receive_type == DspinDhccpParam::TYPE_MULTI_UPDT_INST) { - r_cc_receive_fsm = CC_RECEIVE_UPDT_HEADER; + r_cc_receive_fsm = CC_RECEIVE_INS_UPDT_HEADER; } // test for a multi inval + else if (receive_type == DspinDhccpParam::TYPE_MULTI_INVAL_DATA) + { + r_cc_receive_fsm = CC_RECEIVE_DATA_INVAL_HEADER; + } else { - r_cc_receive_fsm = CC_RECEIVE_INVAL_HEADER; + r_cc_receive_fsm = CC_RECEIVE_INS_INVAL_HEADER; } } - break; - } - ////////////////////// - case CC_RECEIVE_CLACK: - { - // initialize dspin received data - uint64_t receive_data = p_dspin_in.data.read(); - - // for data CLACK, wait for dcache to take the request - if ((r_cc_receive_data_ins.read() == 0) and - not r_cc_receive_dcache_req.read()) - { - // request dcache to handle the CLACK - r_cc_receive_dcache_req = true; - r_cc_receive_dcache_set = DspinDhccpParam::dspin_get(receive_data, - DspinDhccpParam::CLEANUP_ACK_SET) & - ((1ULL<<(uint32_log2(m_dcache_sets)))-1); - r_cc_receive_dcache_way = DspinDhccpParam::dspin_get(receive_data, - DspinDhccpParam::CLEANUP_ACK_WAY) & - ((1ULL<<(uint32_log2(m_dcache_ways)))-1); - r_cc_receive_dcache_type = CC_TYPE_CLACK; - // get back to idle state - r_cc_receive_fsm = CC_RECEIVE_IDLE; - break; - } - // for ins CLACK, wait for icache to take the request - if ((r_cc_receive_data_ins.read() == 1) and - not (r_cc_receive_icache_req.read())) - { - // request icache to handle the CLACK - r_cc_receive_icache_req = true; - r_cc_receive_icache_set = DspinDhccpParam::dspin_get(receive_data, - DspinDhccpParam::CLEANUP_ACK_SET) & - ((1ULL<<(uint32_log2(m_icache_sets)))-1); - r_cc_receive_icache_way = DspinDhccpParam::dspin_get(receive_data, - DspinDhccpParam::CLEANUP_ACK_WAY) & - ((1ULL<<(uint32_log2(m_icache_ways)))-1); - r_cc_receive_icache_type = CC_TYPE_CLACK; - // get back to idle state - r_cc_receive_fsm = CC_RECEIVE_IDLE; - break; - } - // keep waiting for the correct cache to accept the request break; } @@ -6075,5 +6099,5 @@ { // initialize dspin received data - uint64_t receive_data = p_dspin_in.data.read(); + uint64_t receive_data = p_dspin_m2p.data.read(); // wait for both dcache and icache to take the request // TODO maybe we need to wait for both only to leave the state, but @@ -6082,16 +6106,16 @@ if (not (r_cc_receive_icache_req.read()) and not (r_cc_receive_dcache_req.read()) and - (p_dspin_in.write.read())) + (p_dspin_m2p.write.read())) { // request dcache to handle the BROADCAST - r_cc_receive_dcache_req = true; + r_cc_receive_dcache_req = true; r_cc_receive_dcache_nline = DspinDhccpParam::dspin_get(receive_data, DspinDhccpParam::BROADCAST_NLINE); - r_cc_receive_dcache_type = CC_TYPE_BRDCAST; + r_cc_receive_dcache_type = CC_TYPE_INVAL; // request icache to handle the BROADCAST - r_cc_receive_icache_req = true; + r_cc_receive_icache_req = true; r_cc_receive_icache_nline = DspinDhccpParam::dspin_get(receive_data, DspinDhccpParam::BROADCAST_NLINE); - r_cc_receive_icache_type = CC_TYPE_BRDCAST; + r_cc_receive_icache_type = CC_TYPE_INVAL; // get back to idle state r_cc_receive_fsm = CC_RECEIVE_IDLE; @@ -6102,42 +6126,28 @@ } ///////////////////////////// - case CC_RECEIVE_INVAL_HEADER: + case CC_RECEIVE_DATA_INVAL_HEADER: { // sample updt tab index in the HEADER, then skip to second flit - uint64_t receive_data = p_dspin_in.data.read(); + r_cc_receive_fsm = CC_RECEIVE_DATA_INVAL_NLINE; + break; + } + ///////////////////////////// + case CC_RECEIVE_INS_INVAL_HEADER: + { + // sample updt tab index in the HEADER, then skip to second flit + r_cc_receive_fsm = CC_RECEIVE_INS_INVAL_NLINE; + break; + } + //////////////////////////// + case CC_RECEIVE_DATA_INVAL_NLINE: + { + // sample nline in the second flit + uint64_t receive_data = p_dspin_m2p.data.read(); // for data INVAL, wait for dcache to take the request - if ((r_cc_receive_data_ins.read() == 0) and - not (r_cc_receive_dcache_req.read())) - { - r_cc_receive_dcache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data, - DspinDhccpParam::MULTI_INVAL_UPDT_INDEX); - r_cc_receive_fsm = CC_RECEIVE_INVAL_NLINE; - break; - } - // for ins INVAL, wait for icache to take the request - if ((r_cc_receive_data_ins.read() == 1) and - not (r_cc_receive_icache_req.read())) - { - r_cc_receive_icache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data, - DspinDhccpParam::MULTI_INVAL_UPDT_INDEX); - r_cc_receive_fsm = CC_RECEIVE_INVAL_NLINE; - break; - } - // keep waiting for the correct cache to accept the request - break; - } - //////////////////////////// - case CC_RECEIVE_INVAL_NLINE: - { - // sample nline in the second flit - uint64_t receive_data = p_dspin_in.data.read(); - // for data INVAL, wait for dcache to take the request - if ( (r_cc_receive_data_ins.read() == 0) and - not (r_cc_receive_dcache_req.read()) and - (p_dspin_in.write.read()) ) + if (p_dspin_m2p.write.read() and not r_cc_receive_dcache_req.read()) { // request dcache to handle the INVAL - r_cc_receive_dcache_req = true; - r_cc_receive_dcache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_INVAL_NLINE); + r_cc_receive_dcache_req = true; + r_cc_receive_dcache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_INVAL_NLINE); r_cc_receive_dcache_type = CC_TYPE_INVAL; // get back to idle state @@ -6145,10 +6155,17 @@ break; } + break; + } + ////////////////////////////// + case CC_RECEIVE_INS_INVAL_NLINE: + { + // sample nline in the second flit + uint64_t receive_data = p_dspin_m2p.data.read(); // for ins INVAL, wait for icache to take the request - if ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()) and (p_dspin_in.write.read())) + if (p_dspin_m2p.write.read() and not r_cc_receive_icache_req.read()) { // request icache to handle the INVAL - r_cc_receive_icache_req = true; - r_cc_receive_icache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_INVAL_NLINE); + r_cc_receive_icache_req = true; + r_cc_receive_icache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_INVAL_NLINE); r_cc_receive_icache_type = CC_TYPE_INVAL; // get back to idle state @@ -6156,26 +6173,32 @@ break; } - // we should never get there - assert ( false && "ERROR in CC_VCACHE : CC_RECEIVE_INVAL_NLINE\n"); + break; } //////////////////////////// - case CC_RECEIVE_UPDT_HEADER: + case CC_RECEIVE_DATA_UPDT_HEADER: { // sample updt tab index in the HEADER, than skip to second flit - uint64_t receive_data = p_dspin_in.data.read(); + uint64_t receive_data = p_dspin_m2p.data.read(); // for data INVAL, wait for dcache to take the request and fifo to // be empty - if ((r_cc_receive_data_ins.read() == 0) and not r_cc_receive_dcache_req.read() and r_cc_receive_updt_fifo_be.empty()) + if (not r_cc_receive_dcache_req.read()) { r_cc_receive_dcache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_UPDT_INDEX); - r_cc_receive_fsm = CC_RECEIVE_UPDT_NLINE; + r_cc_receive_fsm = CC_RECEIVE_DATA_UPDT_NLINE; break; } + break; + } + //////////////////////////// + case CC_RECEIVE_INS_UPDT_HEADER: + { + // sample updt tab index in the HEADER, than skip to second flit + uint64_t receive_data = p_dspin_m2p.data.read(); // for ins INVAL, wait for icache to take the request and fifo to be // empty - if ((r_cc_receive_data_ins.read() == 1) and not r_cc_receive_icache_req.read() and r_cc_receive_updt_fifo_be.empty()) + if (not r_cc_receive_icache_req.read()) { r_cc_receive_icache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_UPDT_INDEX); - r_cc_receive_fsm = CC_RECEIVE_UPDT_NLINE; + r_cc_receive_fsm = CC_RECEIVE_INS_UPDT_NLINE; break; } @@ -6184,53 +6207,51 @@ } /////////////////////////// - case CC_RECEIVE_UPDT_NLINE: + case CC_RECEIVE_DATA_UPDT_NLINE: { // sample nline and word index in the second flit - uint64_t receive_data = p_dspin_in.data.read(); + uint64_t receive_data = p_dspin_m2p.data.read(); // for data INVAL, wait for dcache to take the request and fifo to // be empty - if ( (r_cc_receive_data_ins.read() == 0) and - not (r_cc_receive_dcache_req.read()) and - r_cc_receive_updt_fifo_be.empty() and - (p_dspin_in.write.read()) ) - { + if ( r_cc_receive_updt_fifo_be.empty() and + p_dspin_m2p.write.read() ) + { + r_cc_receive_dcache_req = true; r_cc_receive_dcache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_NLINE); r_cc_receive_word_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_WORD_INDEX); r_cc_receive_dcache_type = CC_TYPE_UPDT; // get back to idle state - r_cc_receive_fsm = CC_RECEIVE_UPDT_DATA; + r_cc_receive_fsm = CC_RECEIVE_DATA_UPDT_DATA; break; } + break; + } + //////////////////////////// + case CC_RECEIVE_INS_UPDT_NLINE: + { + // sample nline and word index in the second flit + uint64_t receive_data = p_dspin_m2p.data.read(); // for ins INVAL, wait for icache to take the request and fifo to be // empty - if ( (r_cc_receive_data_ins.read() == 1) and - not (r_cc_receive_icache_req.read()) and - r_cc_receive_updt_fifo_be.empty() and - (p_dspin_in.write.read())) - { + if ( r_cc_receive_updt_fifo_be.empty() and + p_dspin_m2p.write.read() ) + { + r_cc_receive_icache_req = true; r_cc_receive_icache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_NLINE); r_cc_receive_word_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_WORD_INDEX); r_cc_receive_icache_type = CC_TYPE_UPDT; // get back to idle state - r_cc_receive_fsm = CC_RECEIVE_UPDT_DATA; + r_cc_receive_fsm = CC_RECEIVE_INS_UPDT_DATA; break; } - // we should never get there - assert ( false && "ERROR in CC_VCACHE : CC_RECEIVE_UPDT_NLINE \n"); break; } ////////////////////////// - case CC_RECEIVE_UPDT_DATA: - { - if ((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read()) and (p_dspin_in.write.read())) - r_cc_receive_dcache_req = true; - if ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()) and (p_dspin_in.write.read())) - r_cc_receive_icache_req = true; - + case CC_RECEIVE_DATA_UPDT_DATA: + { // wait for the fifo - if (r_cc_receive_updt_fifo_be.wok() and (p_dspin_in.write.read())) - { - uint64_t receive_data = p_dspin_in.data.read(); - bool receive_eop = p_dspin_in.eop.read(); + if (r_cc_receive_updt_fifo_be.wok() and (p_dspin_m2p.write.read())) + { + uint64_t receive_data = p_dspin_m2p.data.read(); + bool receive_eop = p_dspin_m2p.eop.read(); cc_receive_updt_fifo_be = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_BE); cc_receive_updt_fifo_data = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_DATA); @@ -6241,5 +6262,66 @@ break; } + ////////////////////////// + case CC_RECEIVE_INS_UPDT_DATA: + { + // wait for the fifo + if (r_cc_receive_updt_fifo_be.wok() and (p_dspin_m2p.write.read())) + { + uint64_t receive_data = p_dspin_m2p.data.read(); + bool receive_eop = p_dspin_m2p.eop.read(); + cc_receive_updt_fifo_be = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_BE); + cc_receive_updt_fifo_data = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_DATA); + cc_receive_updt_fifo_eop = receive_eop; + cc_receive_updt_fifo_put = true; + if ( receive_eop ) r_cc_receive_fsm = CC_RECEIVE_IDLE; + } + break; + } + } // end switch CC_RECEIVE FSM + + ///////////////// DSPIN CLACK interface /////////////// + + uint64_t clack_type = DspinDhccpParam::dspin_get(r_dspin_clack_flit.read(), + DspinDhccpParam::CLACK_TYPE); + + size_t clack_way = DspinDhccpParam::dspin_get(r_dspin_clack_flit.read(), + DspinDhccpParam::CLACK_WAY); + + size_t clack_set = DspinDhccpParam::dspin_get(r_dspin_clack_flit.read(), + DspinDhccpParam::CLACK_SET); + + bool dspin_clack_get = false; + bool dcache_clack_request = (clack_type == DspinDhccpParam::TYPE_CLACK_DATA); + bool icache_clack_request = (clack_type == DspinDhccpParam::TYPE_CLACK_INST); + + if (r_dspin_clack_req.read()) + { + // CLACK DATA: Send request to DCACHE FSM + if (dcache_clack_request and not r_dcache_clack_req.read()){ + r_dcache_clack_req = true; + r_dcache_clack_way = clack_way & ((1ULL<<(uint32_log2(m_dcache_ways)))-1); + r_dcache_clack_set = clack_set & ((1ULL<<(uint32_log2(m_dcache_sets)))-1); + dspin_clack_get = true; + } + + // CLACK INST: Send request to ICACHE FSM + else if (icache_clack_request and not r_icache_clack_req.read()){ + r_icache_clack_req = true; + r_icache_clack_way = clack_way & ((1ULL<<(uint32_log2(m_dcache_ways)))-1); + r_icache_clack_set = clack_set & ((1ULL<<(uint32_log2(m_icache_sets)))-1); + dspin_clack_get = true; + } + } + else + { + dspin_clack_get = true; + } + + if (dspin_clack_get) + { + r_dspin_clack_req = p_dspin_clack.write.read(); + r_dspin_clack_flit = p_dspin_clack.data.read(); + } ///////////////// Response FIFOs update ////////////////////// @@ -6447,5 +6529,5 @@ case CC_SEND_IDLE: { - p_dspin_out.write = false; + p_dspin_p2m.write = false; break; } @@ -6454,4 +6536,7 @@ { // initialize dspin send data +// DspinDhccpParam::dspin_set(dspin_send_data, +// 0, +// DspinDhccpParam::P2M_EOP); DspinDhccpParam::dspin_set(dspin_send_data, m_cc_global_id, @@ -6459,5 +6544,5 @@ DspinDhccpParam::dspin_set(dspin_send_data, 0, - DspinDhccpParam::FROM_L1_BC); + DspinDhccpParam::P2M_BC); if(r_cc_send_last_client.read() == 0) // dcache active request @@ -6480,5 +6565,5 @@ DspinDhccpParam::dspin_set(dspin_send_data, DspinDhccpParam::TYPE_CLEANUP_DATA, - DspinDhccpParam::FROM_L1_TYPE); + DspinDhccpParam::P2M_TYPE); /*ODCCP*/ // If cleanup on NCC line we set the CLEANUP_NCC bit in cleanup flit if (r_dcache_cleanup_ncc.read()) @@ -6516,5 +6601,5 @@ DspinDhccpParam::dspin_set(dspin_send_data, DspinDhccpParam::TYPE_CLEANUP_INST, - DspinDhccpParam::FROM_L1_TYPE); + DspinDhccpParam::P2M_TYPE); DspinDhccpParam::dspin_set(dspin_send_data, @@ -6523,7 +6608,7 @@ } // send flit - p_dspin_out.data = dspin_send_data; - p_dspin_out.write = true; - p_dspin_out.eop = false; + p_dspin_p2m.data = dspin_send_data; + p_dspin_p2m.write = true; + p_dspin_p2m.eop = false; break; } @@ -6535,9 +6620,9 @@ if (r_dcache_cc_cleanup_updt_data.read() and not r_cc_send_last_client.read()) { - p_dspin_out.eop = false; + p_dspin_p2m.eop = false; } else { - p_dspin_out.eop = true; + p_dspin_p2m.eop = true; } @@ -6555,6 +6640,6 @@ } // send flit - p_dspin_out.data = dspin_send_data; - p_dspin_out.write = true; + p_dspin_p2m.data = dspin_send_data; + p_dspin_p2m.write = true; break; } @@ -6564,9 +6649,9 @@ if (r_cc_send_cpt_word.read() == m_dcache_words-1) /*ODCCP*/ // Last flit sent { - p_dspin_out.eop = true; + p_dspin_p2m.eop = true; } else { - p_dspin_out.eop = false; + p_dspin_p2m.eop = false; } @@ -6575,6 +6660,10 @@ DspinDhccpParam::CLEANUP_DATA_UPDT); - p_dspin_out.data = dspin_send_data; - p_dspin_out.write = true; + p_dspin_p2m.data = dspin_send_data; + //p_dspin_p2m.write = true; + if(r_cc_send_data_fifo.rok()) + p_dspin_p2m.write = true; + else + p_dspin_p2m.write = false; break; } @@ -6585,11 +6674,11 @@ // DspinDhccpParam::dspin_set(dspin_send_data, // 1, -// DspinDhccpParam::FROM_L1_EOP); +// DspinDhccpParam::P2M_EOP); DspinDhccpParam::dspin_set(dspin_send_data, 0, - DspinDhccpParam::FROM_L1_BC); + DspinDhccpParam::P2M_BC); DspinDhccpParam::dspin_set(dspin_send_data, DspinDhccpParam::TYPE_MULTI_ACK, - DspinDhccpParam::FROM_L1_TYPE); + DspinDhccpParam::P2M_TYPE); if(r_cc_send_last_client.read() == 0) // dcache active request @@ -6623,7 +6712,7 @@ } // send flit - p_dspin_out.data = dspin_send_data; - p_dspin_out.write = true; - p_dspin_out.eop = true; + p_dspin_p2m.data = dspin_send_data; + p_dspin_p2m.write = true; + p_dspin_p2m.eop = true; break; @@ -6633,5 +6722,4 @@ // Receive coherence packets // It depends on the CC_RECEIVE FSM - switch( r_cc_receive_fsm.read() ) { @@ -6639,15 +6727,5 @@ case CC_RECEIVE_IDLE: { - p_dspin_in.read = false; - break; - } - ////////////////////// - case CC_RECEIVE_CLACK: - { - if (((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read())) or - ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()))) - p_dspin_in.read = true; - else - p_dspin_in.read = false; + p_dspin_m2p.read = false; break; } @@ -6655,5 +6733,5 @@ case CC_RECEIVE_BRDCAST_HEADER: { - p_dspin_in.read = true; + p_dspin_m2p.read = true; break; } @@ -6665,66 +6743,95 @@ // flip_flop to check that ? if (not (r_cc_receive_icache_req.read()) and not (r_cc_receive_dcache_req.read())) - p_dspin_in.read = true; + p_dspin_m2p.read = true; else - p_dspin_in.read = false; + p_dspin_m2p.read = false; break; } ///////////////////////////// - case CC_RECEIVE_INVAL_HEADER: - { - if (((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read())) or - ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()))) - p_dspin_in.read = true; + case CC_RECEIVE_DATA_INVAL_HEADER: + case CC_RECEIVE_INS_INVAL_HEADER: + { + p_dspin_m2p.read = true; + break; + } + //////////////////////////// + case CC_RECEIVE_DATA_INVAL_NLINE: + { + p_dspin_m2p.read = not r_cc_receive_dcache_req.read(); + break; + } + case CC_RECEIVE_INS_INVAL_NLINE: + { + p_dspin_m2p.read = not r_cc_receive_icache_req.read(); + break; + } + /////////////////////////// + case CC_RECEIVE_DATA_UPDT_HEADER: + { + if (not r_cc_receive_dcache_req.read()) + p_dspin_m2p.read = true; else - p_dspin_in.read = false; + p_dspin_m2p.read = false; break; } //////////////////////////// - case CC_RECEIVE_INVAL_NLINE: - { - p_dspin_in.read = true; - break; - } - //////////////////////////// - case CC_RECEIVE_UPDT_HEADER: - { - if (((r_cc_receive_data_ins.read() == 0) and - not r_cc_receive_dcache_req.read() and - r_cc_receive_updt_fifo_be.empty()) - or - (((r_cc_receive_data_ins.read() == 1) and - not r_cc_receive_icache_req.read()) and - r_cc_receive_updt_fifo_be.empty())) - p_dspin_in.read = true; + case CC_RECEIVE_INS_UPDT_HEADER: + { + if ( not r_cc_receive_icache_req.read()) + p_dspin_m2p.read = true; else - p_dspin_in.read = false; + p_dspin_m2p.read = false; break; } /////////////////////////// - case CC_RECEIVE_UPDT_NLINE: - { - if (((r_cc_receive_data_ins.read() == 0) and - not (r_cc_receive_dcache_req.read()) and - r_cc_receive_updt_fifo_be.empty()) - or - ((r_cc_receive_data_ins.read() == 1) and - not (r_cc_receive_icache_req.read()) and - r_cc_receive_updt_fifo_be.empty())) - p_dspin_in.read = true; + case CC_RECEIVE_DATA_UPDT_NLINE: + case CC_RECEIVE_INS_UPDT_NLINE: + { + if(r_cc_receive_updt_fifo_be.empty()) + p_dspin_m2p.read = true; else - p_dspin_in.read = false; - break; - } - ////////////////////////// - case CC_RECEIVE_UPDT_DATA: + p_dspin_m2p.read = false; + break; + } + /////////////////////////// + case CC_RECEIVE_DATA_UPDT_DATA: + case CC_RECEIVE_INS_UPDT_DATA: { if (r_cc_receive_updt_fifo_be.wok()) - p_dspin_in.read = true; + p_dspin_m2p.read = true; else - p_dspin_in.read = false; + p_dspin_m2p.read = false; break; } } // end switch CC_RECEIVE FSM + + int clack_type = DspinDhccpParam::dspin_get(r_dspin_clack_flit.read(), + DspinDhccpParam::CLACK_TYPE); + + bool dspin_clack_get = false; + bool dcache_clack_request = (clack_type == DspinDhccpParam::TYPE_CLACK_DATA); + bool icache_clack_request = (clack_type == DspinDhccpParam::TYPE_CLACK_INST); + + if (r_dspin_clack_req.read()) + { + // CLACK DATA: wait if pending request to DCACHE FSM + if (dcache_clack_request and not r_dcache_clack_req.read()) + { + dspin_clack_get = true; + } + + // CLACK INST: wait if pending request to ICACHE FSM + else if (icache_clack_request and not r_icache_clack_req.read()) + { + dspin_clack_get = true; + } + } + else + { + dspin_clack_get = true; + } + + p_dspin_clack.read = dspin_clack_get; } // end genMoore Index: branches/ODCCP/modules/vci_mem_cache/caba/metadata/vci_mem_cache.sd =================================================================== --- branches/ODCCP/modules/vci_mem_cache/caba/metadata/vci_mem_cache.sd (revision 474) +++ branches/ODCCP/modules/vci_mem_cache/caba/metadata/vci_mem_cache.sd (revision 479) @@ -49,9 +49,13 @@ Port('caba:vci_initiator', 'p_vci_ixr'), Port('caba:dspin_input', - 'p_dspin_in', + 'p_dspin_p2m', dspin_data_size = parameter.Reference('dspin_in_width') ), Port('caba:dspin_output', - 'p_dspin_out', + 'p_dspin_m2p', + dspin_data_size = parameter.Reference('dspin_out_width') + ), + Port('caba:dspin_output', + 'p_dspin_clack', dspin_data_size = parameter.Reference('dspin_out_width') ), Index: branches/ODCCP/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h =================================================================== --- branches/ODCCP/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h (revision 474) +++ branches/ODCCP/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h (revision 479) @@ -54,4 +54,5 @@ #define TRT_ENTRIES 4 // Number of entries in TRT #define UPT_ENTRIES 4 // Number of entries in UPT +#define IVT_ENTRIES 4 // Number of entries in IVT #define HEAP_ENTRIES 1024 // Number of entries in HEAP @@ -122,10 +123,8 @@ CC_SEND_WRITE_IDLE, CC_SEND_CAS_IDLE, - CC_SEND_CLEANUP_IDLE, CC_SEND_CONFIG_INVAL_HEADER, CC_SEND_CONFIG_INVAL_NLINE, CC_SEND_CONFIG_BRDCAST_HEADER, CC_SEND_CONFIG_BRDCAST_NLINE, - CC_SEND_CLEANUP_ACK, CC_SEND_XRAM_RSP_BRDCAST_HEADER, CC_SEND_XRAM_RSP_BRDCAST_NLINE, @@ -163,5 +162,5 @@ CONFIG_DIR_REQ, CONFIG_DIR_ACCESS, - CONFIG_DIR_UPT_LOCK, + CONFIG_DIR_IVT_LOCK, CONFIG_BC_SEND, CONFIG_BC_WAIT, @@ -211,5 +210,5 @@ WRITE_MISS_XRAM_REQ, WRITE_BC_TRT_LOCK, - WRITE_BC_UPT_LOCK, + WRITE_BC_IVT_LOCK, WRITE_BC_DIR_INVAL, WRITE_BC_CC_SEND, @@ -255,4 +254,5 @@ IXR_CMD_XRAM_IDLE, IXR_CMD_CLEANUP_IDLE, + IXR_CMD_TRT_LOCK, IXR_CMD_READ, IXR_CMD_WRITE, @@ -276,5 +276,5 @@ CAS_UPT_NEXT, CAS_BC_TRT_LOCK, - CAS_BC_UPT_LOCK, + CAS_BC_IVT_LOCK, CAS_BC_DIR_INVAL, CAS_BC_CC_SEND, @@ -302,7 +302,7 @@ CLEANUP_HEAP_CLEAN, CLEANUP_HEAP_FREE, - CLEANUP_UPT_LOCK, - CLEANUP_UPT_DECREMENT, - CLEANUP_UPT_CLEAR, + CLEANUP_IVT_LOCK, + CLEANUP_IVT_DECREMENT, + CLEANUP_IVT_CLEAR, CLEANUP_WRITE_RSP, CLEANUP_CONFIG_ACK, @@ -332,5 +332,6 @@ ALLOC_TRT_XRAM_RSP, ALLOC_TRT_IXR_RSP, - ALLOC_TRT_CLEANUP + ALLOC_TRT_CLEANUP, + ALLOC_TRT_IXR_CMD }; @@ -338,10 +339,17 @@ enum alloc_upt_fsm_state_e { - ALLOC_UPT_CONFIG, ALLOC_UPT_WRITE, - ALLOC_UPT_XRAM_RSP, - ALLOC_UPT_MULTI_ACK, - ALLOC_UPT_CLEANUP, - ALLOC_UPT_CAS + ALLOC_UPT_CAS, + ALLOC_UPT_MULTI_ACK + }; + + /* States of the ALLOC_IVT fsm */ + enum alloc_ivt_fsm_state_e + { + ALLOC_IVT_WRITE, + ALLOC_IVT_XRAM_RSP, + ALLOC_IVT_CLEANUP, + ALLOC_IVT_CAS, + ALLOC_IVT_CONFIG }; @@ -492,5 +500,5 @@ uint32_t m_cpt_cas_fsm_upt_used; // NB cycles UPT LOCK used - uint32_t m_cpt_upt_unused; // NB cycles UPT LOCK unused + uint32_t m_cpt_ivt_unused; // NB cycles UPT LOCK unused uint32_t m_cpt_read_fsm_heap_lock; // wait HEAP LOCK @@ -536,6 +544,7 @@ soclib::caba::VciTarget p_vci_tgt; soclib::caba::VciInitiator p_vci_ixr; - soclib::caba::DspinInput p_dspin_in; - soclib::caba::DspinOutput p_dspin_out; + soclib::caba::DspinInput p_dspin_p2m; + soclib::caba::DspinOutput p_dspin_m2p; + soclib::caba::DspinOutput p_dspin_clack; VciMemCache( @@ -553,4 +562,5 @@ const size_t trt_lines=TRT_ENTRIES, const size_t upt_lines=UPT_ENTRIES, + const size_t ivt_lines=IVT_ENTRIES, const size_t debug_start_cycle=0, const bool debug_ok=false ); @@ -588,5 +598,6 @@ TransactionTab m_trt; // xram transaction table uint32_t m_upt_lines; - UpdateTab m_upt; // pending update & invalidate + UpdateTab m_upt; // pending update + UpdateTab m_ivt; // pending invalidate CacheDirectory m_cache_directory; // data cache directory CacheData m_cache_data; // data array[set][way][word] @@ -677,5 +688,5 @@ sc_signal r_config_heap_next; // current pointer to scan HEAP - sc_signal r_config_upt_index; // UPT index + sc_signal r_config_ivt_index; // IVT index // Buffer between CONFIG fsm and TGT_RSP fsm (send a done response to L1 cache) @@ -866,11 +877,4 @@ sc_signal r_cleanup_to_tgt_rsp_pktid; // transaction pktid - // Buffer between CLEANUP fsm and CC_SEND fsm (acknowledge a cleanup command from L1) - sc_signal r_cleanup_to_cc_send_req; // valid request - sc_signal r_cleanup_to_cc_send_srcid; // L1 srcid - sc_signal r_cleanup_to_cc_send_set_index; // L1 set index - sc_signal r_cleanup_to_cc_send_way_index; // L1 way index - sc_signal r_cleanup_to_cc_send_inst; // Instruction Cleanup Ack - /////////////////////////////////////////////////////// // Registers controlled by CAS fsm @@ -960,5 +964,5 @@ sc_signal r_xram_rsp_victim_ptr; // victim line pointer to the heap sc_signal * r_xram_rsp_victim_data; // victim line data - sc_signal r_xram_rsp_upt_index; // UPT entry index + sc_signal r_xram_rsp_ivt_index; // IVT entry index sc_signal r_xram_rsp_next_ptr; // Next pointer to the heap @@ -1041,4 +1045,10 @@ //////////////////////////////////////////////////// + // Registers controlled by ALLOC_IVT fsm + //////////////////////////////////////////////////// + + sc_signal r_alloc_ivt_fsm; + + //////////////////////////////////////////////////// // Registers controlled by ALLOC_HEAP fsm //////////////////////////////////////////////////// @@ -1056,4 +1066,5 @@ sc_signal r_cleanup_pktid; sc_signal *r_cleanup_data; // buffer for saving data from cleanup + sc_signal *r_ixr_cmd_data; // buffer for saving data from cleanup sc_signal r_cleanup_contains_data; sc_signal r_cleanup_ncc; Index: branches/ODCCP/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp =================================================================== --- branches/ODCCP/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp (revision 474) +++ branches/ODCCP/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp (revision 479) @@ -102,10 +102,8 @@ "CC_SEND_WRITE_IDLE", "CC_SEND_CAS_IDLE", - "CC_SEND_CLEANUP_IDLE", "CC_SEND_CONFIG_INVAL_HEADER", "CC_SEND_CONFIG_INVAL_NLINE", "CC_SEND_CONFIG_BRDCAST_HEADER", "CC_SEND_CONFIG_BRDCAST_NLINE", - "CC_SEND_CLEANUP_ACK", "CC_SEND_XRAM_RSP_BRDCAST_HEADER", "CC_SEND_XRAM_RSP_BRDCAST_NLINE", @@ -139,5 +137,5 @@ "CONFIG_DIR_REQ", "CONFIG_DIR_ACCESS", - "CONFIG_DIR_UPT_LOCK", + "CONFIG_DIR_IVT_LOCK", "CONFIG_BC_SEND", "CONFIG_BC_WAIT", @@ -183,5 +181,5 @@ "WRITE_MISS_XRAM_REQ", "WRITE_BC_TRT_LOCK", - "WRITE_BC_UPT_LOCK", + "WRITE_BC_IVT_LOCK", "WRITE_BC_DIR_INVAL", "WRITE_BC_CC_SEND", @@ -221,4 +219,5 @@ "IXR_CMD_XRAM_IDLE", "IXR_CMD_CLEANUP_IDLE", + "IXR_CMD_TRT_LOCK", "IXR_CMD_READ", "IXR_CMD_WRITE", @@ -240,5 +239,5 @@ "CAS_UPT_NEXT", "CAS_BC_TRT_LOCK", - "CAS_BC_UPT_LOCK", + "CAS_BC_IVT_LOCK", "CAS_BC_DIR_INVAL", "CAS_BC_CC_SEND", @@ -264,7 +263,7 @@ "CLEANUP_HEAP_CLEAN", "CLEANUP_HEAP_FREE", - "CLEANUP_UPT_LOCK", - "CLEANUP_UPT_DECREMENT", - "CLEANUP_UPT_CLEAR", + "CLEANUP_IVT_LOCK", + "CLEANUP_IVT_DECREMENT", + "CLEANUP_IVT_CLEAR", "CLEANUP_WRITE_RSP", "CLEANUP_CONFIG_ACK", @@ -290,5 +289,6 @@ "ALLOC_TRT_XRAM_RSP", "ALLOC_TRT_IXR_RSP", - "ALLOC_TRT_CLEANUP" + "ALLOC_TRT_CLEANUP", + "ALLOC_TRT_IXR_CMD" }; const char *alloc_upt_fsm_str[] = @@ -296,8 +296,14 @@ "ALLOC_UPT_CONFIG", "ALLOC_UPT_WRITE", - "ALLOC_UPT_XRAM_RSP", - "ALLOC_UPT_MULTI_ACK", - "ALLOC_UPT_CLEANUP", - "ALLOC_UPT_CAS" + "ALLOC_UPT_CAS", + "ALLOC_UPT_MULTI_ACK" +}; +const char *alloc_ivt_fsm_str[] = +{ + "ALLOC_IVT_WRITE", + "ALLOC_IVT_XRAM_RSP", + "ALLOC_IVT_CLEANUP", + "ALLOC_IVT_CAS", + "ALLOC_IVT_CONFIG" }; const char *alloc_heap_fsm_str[] = @@ -339,4 +345,5 @@ const size_t trt_lines, // number of TRT entries const size_t upt_lines, // number of UPT entries + const size_t ivt_lines, // number of IVT entries const size_t debug_start_cycle, const bool debug_ok) @@ -350,6 +357,7 @@ p_vci_tgt( "p_vci_tgt" ), p_vci_ixr( "p_vci_ixr" ), - p_dspin_in( "p_dspin_in" ), - p_dspin_out( "p_dspin_out" ), + p_dspin_p2m( "p_dspin_p2m" ), + p_dspin_m2p( "p_dspin_m2p" ), + p_dspin_clack( "p_dspin_clack" ), m_seglist( mtp.getSegmentList(tgtid_d) ), @@ -368,4 +376,5 @@ m_upt_lines(upt_lines), m_upt(upt_lines), + m_ivt(ivt_lines), m_cache_directory(nways, nsets, nwords, vci_param_int::N), m_cache_data(nways, nsets, nwords), @@ -459,4 +468,5 @@ r_alloc_trt_fsm("r_alloc_trt_fsm"), r_alloc_upt_fsm("r_alloc_upt_fsm"), + r_alloc_ivt_fsm("r_alloc_ivt_fsm"), r_alloc_heap_fsm("r_alloc_heap_fsm"), r_alloc_heap_reset_cpt("r_alloc_heap_reset_cpt") @@ -534,4 +544,5 @@ // Allocation for ODCCP r_cleanup_data = new sc_signal[nwords]; + r_ixr_cmd_data = new sc_signal[nwords]; r_cleanup_to_ixr_cmd_data = new sc_signal[nwords]; @@ -641,8 +652,9 @@ << " | " << ixr_cmd_fsm_str[r_ixr_cmd_fsm.read()] << " | " << ixr_rsp_fsm_str[r_ixr_rsp_fsm.read()] - << " | " << xram_rsp_fsm_str[r_xram_rsp_fsm] << std::endl; + << " | " << xram_rsp_fsm_str[r_xram_rsp_fsm.read()] << std::endl; std::cout << " " << alloc_dir_fsm_str[r_alloc_dir_fsm.read()] << " | " << alloc_trt_fsm_str[r_alloc_trt_fsm.read()] << " | " << alloc_upt_fsm_str[r_alloc_upt_fsm.read()] + << " | " << alloc_ivt_fsm_str[r_alloc_ivt_fsm.read()] << " | " << alloc_heap_fsm_str[r_alloc_heap_fsm.read()] << std::endl; } @@ -672,5 +684,5 @@ m_cpt_trt_rb = 0; m_cpt_dir_unused = 0; - m_cpt_upt_unused = 0; + m_cpt_ivt_unused = 0; m_cpt_heap_unused = 0; m_cpt_trt_unused = 0; @@ -771,5 +783,5 @@ << "- WAIT UPT LOCK in CAS_FSM = " << (double) m_cpt_cas_fsm_upt_lock/m_cpt_cas_fsm_n_upt_lock << std::endl << "- NB CYCLES IN UPT LOCK in CAS_FSM = " << (double) m_cpt_cas_fsm_upt_used/m_cpt_cas_fsm_n_upt_lock << std::endl - << "- UPT UNUSED RATE = " << (double) m_cpt_upt_unused/m_cpt_cycles << std::endl << std::endl + << "- IVT UNUSED RATE = " << (double) m_cpt_ivt_unused/m_cpt_cycles << std::endl << std::endl << "- WAIT HEAP LOCK in READ_FSM = " << (double) m_cpt_read_fsm_heap_lock/m_cpt_read_fsm_n_heap_lock << std::endl @@ -805,4 +817,5 @@ delete [] r_cleanup_data; + delete [] r_ixr_cmd_data; delete [] r_cleanup_to_ixr_cmd_data; } @@ -833,4 +846,5 @@ r_alloc_trt_fsm = ALLOC_TRT_READ; r_alloc_upt_fsm = ALLOC_UPT_WRITE; + r_alloc_ivt_fsm = ALLOC_IVT_XRAM_RSP; r_ixr_rsp_fsm = IXR_RSP_IDLE; r_xram_rsp_fsm = XRAM_RSP_IDLE; @@ -845,4 +859,5 @@ m_trt.init(); m_upt.init(); + m_ivt.init(); m_llsc_table.init(); @@ -946,6 +961,6 @@ r_cleanup_contains_data = false; r_cleanup_to_ixr_cmd_req = false; - r_cleanup_to_ixr_cmd_l1_dirty_ncc = false; - r_xram_rsp_to_ixr_cmd_inval_ncc_pending = false; + //r_cleanup_to_ixr_cmd_l1_dirty_ncc = false; + //r_xram_rsp_to_ixr_cmd_inval_ncc_pending = false; r_cleanup_to_ixr_cmd_srcid = 0; r_cleanup_to_ixr_cmd_trdid = 0; @@ -956,4 +971,5 @@ r_cleanup_to_ixr_cmd_data[word] = 0; r_cleanup_data[word] = 0; + r_ixr_cmd_data[word] = 0; } @@ -980,5 +996,5 @@ m_cpt_trt_rb = 0; m_cpt_dir_unused = 0; - m_cpt_upt_unused = 0; + m_cpt_ivt_unused = 0; m_cpt_heap_unused = 0; m_cpt_trt_unused = 0; @@ -1723,5 +1739,5 @@ r_config_dir_next_ptr = entry.ptr; - r_config_fsm = CONFIG_DIR_UPT_LOCK; + r_config_fsm = CONFIG_DIR_IVT_LOCK; } else if ( entry.valid and // hit & sync command @@ -1752,11 +1768,11 @@ } ///////////////////////// - case CONFIG_DIR_UPT_LOCK: // enter this state in case of INVAL command - // Try to get both DIR & UPT locks, and return - // to LOOP state if UPT full. - // Register inval in UPT, and invalidate the - // directory if UPT not full. - { - if ( r_alloc_upt_fsm.read() == ALLOC_UPT_CONFIG ) + case CONFIG_DIR_IVT_LOCK: // enter this state in case of INVAL command + // Try to get both DIR & IVT locks, and return + // to LOOP state if IVT full. + // Register inval in IVT, and invalidate the + // directory if IVT not full. + { + if ( r_alloc_ivt_fsm.read() == ALLOC_IVT_CONFIG ) { size_t set = m_y[(addr_t)(r_config_address.read())]; @@ -1772,9 +1788,9 @@ #if DEBUG_MEMC_CONFIG if(m_debug) -std::cout << " " +std::cout << " " << " No copies in L1 : inval DIR entry" << std::endl; #endif } - else // try to register inval in UPT + else // try to register inval in IVT { bool wok = false; @@ -1787,5 +1803,5 @@ size_t nb_copies = r_config_dir_count.read(); - wok = m_upt.set(false, // it's an inval transaction + wok = m_ivt.set(false, // it's an inval transaction broadcast, false, // no response required @@ -1798,8 +1814,8 @@ index); - if ( wok ) // UPT success => inval DIR slot + if ( wok ) // IVT success => inval DIR slot { m_cache_directory.inval( way, set ); - r_config_upt_index = index; + r_config_ivt_index = index; if ( broadcast ) r_config_fsm = CONFIG_BC_SEND; else r_config_fsm = CONFIG_INV_SEND; @@ -1807,11 +1823,11 @@ #if DEBUG_MEMC_CONFIG if(m_debug) -std::cout << " " - << " Inval DIR entry and register inval in UPT" +std::cout << " " + << " Inval DIR entry and register inval in IVT" << " : index = " << std::dec << index << " / broadcast = " << broadcast << std::endl; #endif } - else // UPT full => release both DIR and UPT locks + else // IVT full => release both DIR and IVT locks { r_config_fsm = CONFIG_LOOP; @@ -1819,6 +1835,6 @@ #if DEBUG_MEMC_CONFIG if(m_debug) -std::cout << " " - << " UPT full : release DIR & UPT locks and retry" << std::endl; +std::cout << " " + << " IVT full : release DIR & IVT locks and retry" << std::endl; #endif } @@ -1835,5 +1851,5 @@ r_config_to_cc_send_multi_req = false; r_config_to_cc_send_brdcast_req = true; - r_config_to_cc_send_trdid = r_config_upt_index.read(); + r_config_to_cc_send_trdid = r_config_ivt_index.read(); r_config_to_cc_send_nline = m_nline[(addr_t)(r_config_address.read())]; r_cleanup_to_config_ack = false; @@ -1875,5 +1891,5 @@ r_config_to_cc_send_multi_req = true; r_config_to_cc_send_brdcast_req = false; - r_config_to_cc_send_trdid = r_config_upt_index.read(); + r_config_to_cc_send_trdid = r_config_ivt_index.read(); r_config_to_cc_send_nline = m_nline[(addr_t)(r_config_address.read())]; r_multi_ack_to_config_ack = false; @@ -2037,18 +2053,18 @@ switch(r_read_fsm.read()) { - /////////////// - case READ_IDLE: // waiting a read request - { + /////////////// + case READ_IDLE: // waiting a read request + { if(m_cmd_read_addr_fifo.rok()) { #if DEBUG_MEMC_READ -if(m_debug) -std::cout << " Read request" - << " : address = " << std::hex << m_cmd_read_addr_fifo.read() - << " / srcid = " << m_cmd_read_srcid_fifo.read() - << " / trdid = " << m_cmd_read_trdid_fifo.read() - << " / pktid = " << m_cmd_read_pktid_fifo.read() - << " / nwords = " << std::dec << m_cmd_read_length_fifo.read() << std::endl; + if(m_debug) + std::cout << " Read request" + << " : address = " << std::hex << m_cmd_read_addr_fifo.read() + << " / srcid = " << m_cmd_read_srcid_fifo.read() + << " / trdid = " << m_cmd_read_trdid_fifo.read() + << " / pktid = " << m_cmd_read_pktid_fifo.read() + << " / nwords = " << std::dec << m_cmd_read_length_fifo.read() << std::endl; #endif r_read_fsm = READ_DIR_REQ; @@ -2154,23 +2170,23 @@ { - if(r_alloc_dir_fsm.read() == ALLOC_DIR_READ) - { - // check if this is an instruction read, this means pktid is either - // TYPE_READ_INS_UNC 0bX010 with TSAR encoding - // TYPE_READ_INS_MISS 0bX011 with TSAR encoding - bool inst_read = ((m_cmd_read_pktid_fifo.read() & 0x2) != 0); - // check if this is a cached read, this means pktid is either - // TYPE_READ_DATA_MISS 0bX001 with TSAR encoding - // TYPE_READ_INS_MISS 0bX011 with TSAR encoding - bool cached_read = (m_cmd_read_pktid_fifo.read() & 0x1); - bool is_cnt = r_read_is_cnt.read(); - - // read data in the cache - size_t set = m_y[(addr_t)(m_cmd_read_addr_fifo.read())]; - size_t way = r_read_way.read(); - - m_cache_data.read_line(way, set, r_read_data); - - if(m_monitor_ok) check_monitor( m_cmd_read_addr_fifo.read(), r_read_data[0], true); + if(r_alloc_dir_fsm.read() == ALLOC_DIR_READ) + { + // check if this is an instruction read, this means pktid is either + // TYPE_READ_INS_UNC 0bX010 with TSAR encoding + // TYPE_READ_INS_MISS 0bX011 with TSAR encoding + bool inst_read = ((m_cmd_read_pktid_fifo.read() & 0x2) != 0); + // check if this is a cached read, this means pktid is either + // TYPE_READ_DATA_MISS 0bX001 with TSAR encoding + // TYPE_READ_INS_MISS 0bX011 with TSAR encoding + bool cached_read = (m_cmd_read_pktid_fifo.read() & 0x1); + bool is_cnt = r_read_is_cnt.read(); + + // read data in the cache + size_t set = m_y[(addr_t)(m_cmd_read_addr_fifo.read())]; + size_t way = r_read_way.read(); + + m_cache_data.read_line(way, set, r_read_data); + + if(m_monitor_ok) check_monitor( m_cmd_read_addr_fifo.read(), r_read_data[0], true); // update the cache directory @@ -2223,13 +2239,13 @@ #if DEBUG_MEMC_READ -if(m_debug) -std::cout << " Update directory entry:" - << " addr = " << std::hex << m_cmd_read_addr_fifo.read() - << " / set = " << std::dec << set - << " / way = " << way - << " / owner_id = " << std::hex << entry.owner.srcid - << " / owner_ins = " << std::dec << entry.owner.inst - << " / count = " << entry.count - << " / is_cnt = " << entry.is_cnt << std::endl; + if(m_debug) + std::cout << " Update directory entry:" + << " addr = " << std::hex << m_cmd_read_addr_fifo.read() + << " / set = " << std::dec << set + << " / way = " << way + << " / owner_id = " << std::hex << entry.owner.srcid + << " / owner_ins = " << std::dec << entry.owner.inst + << " / count = " << entry.count + << " / is_cnt = " << entry.is_cnt << std::endl; #endif @@ -2977,7 +2993,7 @@ wok = m_upt.set(true, // it's an update transaction - false, // it's not a broadcast - true, // response required - false, // no acknowledge required + false, // it's not a broadcast + true, // response required + false, // no acknowledge required srcid, trdid, @@ -3139,5 +3155,5 @@ entry.owner.inst) // put the next srcid in the fifo { - dec_upt_counter = false; + dec_upt_counter = false; write_to_cc_send_fifo_put = true; write_to_cc_send_fifo_inst = entry.owner.inst; @@ -3192,5 +3208,5 @@ { r_write_to_cc_send_multi_req = true; - if(r_write_to_dec.read() or dec_upt_counter) r_write_fsm = WRITE_UPT_DEC; + if(r_write_to_dec.read() or dec_upt_counter) r_write_fsm = WRITE_UPT_DEC; else r_write_fsm = WRITE_IDLE; } @@ -3444,5 +3460,5 @@ { r_write_trt_index = wok_index; - r_write_fsm = WRITE_BC_UPT_LOCK; + r_write_fsm = WRITE_BC_IVT_LOCK; } else // wait an empty entry in TRT @@ -3465,7 +3481,7 @@ ////////////////////// - case WRITE_BC_UPT_LOCK: // register BC transaction in UPT - { - if(r_alloc_upt_fsm.read() == ALLOC_UPT_WRITE) + case WRITE_BC_IVT_LOCK: // register BC transaction in IVT + { + if(r_alloc_ivt_fsm.read() == ALLOC_IVT_WRITE) { bool wok = false; @@ -3477,8 +3493,8 @@ size_t nb_copies = r_write_count.read(); - wok = m_upt.set(false, // it's an inval transaction - true, // it's a broadcast - true, // response required - false, // no acknowledge required + wok = m_ivt.set(false, // it's an inval transaction + true, // it's a broadcast + true, // response required + false, // no acknowledge required srcid, trdid, @@ -3489,5 +3505,5 @@ #if DEBUG_MEMC_WRITE if( m_debug and wok ) -std::cout << " Register broadcast inval in UPT" +std::cout << " Register broadcast inval in IVT" << " / nb_copies = " << r_write_count.read() << std::endl; #endif @@ -3495,5 +3511,5 @@ if(wok) r_write_fsm = WRITE_BC_DIR_INVAL; - else r_write_fsm = WRITE_WAIT; + else r_write_fsm = WRITE_WAIT; m_cpt_write_fsm_n_upt_lock++; } @@ -3510,9 +3526,9 @@ // and invalidate the line in directory if((r_alloc_trt_fsm.read() != ALLOC_TRT_WRITE) or - (r_alloc_upt_fsm.read() != ALLOC_UPT_WRITE) or - (r_alloc_dir_fsm.read() != ALLOC_DIR_WRITE)) + (r_alloc_ivt_fsm.read() != ALLOC_IVT_WRITE) or + (r_alloc_dir_fsm.read() != ALLOC_DIR_WRITE)) { std::cout << "VCI_MEM_CACHE ERROR " << name() << " WRITE_BC_DIR_INVAL state" << std::endl; - std::cout << "bad TRT, DIR, or UPT allocation" << std::endl; + std::cout << "bad TRT, DIR, or IVT allocation" << std::endl; exit(0); } @@ -3636,5 +3652,9 @@ else if(r_cas_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_CAS; else if(r_xram_rsp_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_XRAM; +#if ODCCP_NON_INCLUSIVE else if(r_cleanup_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_CLEANUP_DATA; +#else + else if(r_cleanup_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_TRT_LOCK; +#endif else if(r_read_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_READ; break; @@ -3643,5 +3663,9 @@ if(r_cas_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_CAS; else if(r_xram_rsp_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_XRAM; +#if ODCCP_NON_INCLUSIVE else if(r_cleanup_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_CLEANUP_DATA; +#else + else if(r_cleanup_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_TRT_LOCK; +#endif else if(r_read_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_READ; else if(r_write_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_WRITE; @@ -3650,5 +3674,9 @@ case IXR_CMD_CAS_IDLE: if(r_xram_rsp_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_XRAM; +#if ODCCP_NON_INCLUSIVE else if(r_cleanup_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_CLEANUP_DATA; +#else + else if(r_cleanup_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_TRT_LOCK; +#endif else if(r_read_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_READ; else if(r_write_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_WRITE; @@ -3657,5 +3685,9 @@ //////////////////////// case IXR_CMD_XRAM_IDLE: +#if ODCCP_NON_INCLUSIVE if(r_cleanup_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_CLEANUP_DATA; +#else + if(r_cleanup_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_TRT_LOCK; +#endif else if(r_read_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_READ; else if(r_write_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_WRITE; @@ -3669,6 +3701,27 @@ else if(r_cas_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_CAS; else if(r_xram_rsp_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_XRAM; +#if ODCCP_NON_INCLUSIVE else if(r_cleanup_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_CLEANUP_DATA; - break; +#else + else if(r_cleanup_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_TRT_LOCK; +#endif + break; + + ///////////////////// + case IXR_CMD_TRT_LOCK: + { + TransactionTabEntry entry; + + if(r_alloc_trt_fsm.read() != ALLOC_TRT_IXR_CMD) break; + entry.copy( m_trt.read(r_cleanup_to_ixr_cmd_trdid.read())); + for(size_t i=0; i < m_words; i++) + { + r_ixr_cmd_data[i] = entry.wdata[i]; + } + + r_ixr_cmd_fsm = IXR_CMD_CLEANUP_DATA; + break; + } + ////////////////// // send a get from READ FSM case IXR_CMD_READ: @@ -3806,5 +3859,5 @@ r_ixr_cmd_fsm = IXR_CMD_CLEANUP_IDLE; r_cleanup_to_ixr_cmd_req = false; - r_xram_rsp_to_ixr_cmd_inval_ncc_pending = false; + //r_xram_rsp_to_ixr_cmd_inval_ncc_pending = false; } else @@ -3990,4 +4043,5 @@ size_t ptr = r_xram_rsp_trt_index.read(); size_t lines = m_trt_lines; + for(size_t i=0 ; i" - << " Get acces to UPT, but line invalidation registered" + << " Get acces to IVT, but line invalidation registered" << " / nline = " << std::hex << r_xram_rsp_trt_buf.nline << " / index = " << std::dec << index << std::endl; @@ -4132,5 +4188,5 @@ } - else if(m_upt.is_full() and r_xram_rsp_victim_inval.read()) // UPT full + else if(m_ivt.is_full() and r_xram_rsp_victim_inval.read()) // IVT full { r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT; @@ -4139,5 +4195,5 @@ if(m_debug) std::cout << " " - << " Get acces to UPT, but inval required and UPT full" << std::endl; + << " Get acces to IVT, but inval required and IVT full" << std::endl; #endif } @@ -4149,5 +4205,5 @@ if(m_debug) std::cout << " " - << " Get acces to UPT" << std::endl; + << " Get acces to IVT" << std::endl; #endif } @@ -4173,5 +4229,5 @@ /////////////////////// case XRAM_RSP_DIR_UPDT: // updates the cache (both data & directory) - // and possibly set an inval request in UPT + // and possibly set an inval request in IVT { // check if this is an instruction read, this means pktid is either @@ -4241,5 +4297,5 @@ m_cache_directory.write(set, way, entry); - // request an invalidation request in UPT for victim line + // request an invalidation request in IVT for victim line if(r_xram_rsp_victim_inval.read()) { @@ -4247,6 +4303,6 @@ size_t index = 0; size_t count_copies = r_xram_rsp_victim_count.read(); - - bool wok = m_upt.set(false, // it's an inval transaction + + bool wok = m_ivt.set(false, // it's an inval transaction broadcast, // set broadcast bit false, // no response required @@ -4259,10 +4315,10 @@ index); - r_xram_rsp_upt_index = index; + r_xram_rsp_ivt_index = index; if(!wok) { std::cout << "VCI_MEM_CACHE ERROR " << name() << " XRAM_RSP_DIR_UPDT" - << " update_tab entry free but write unsuccessful" << std::endl; + << " invalidate_tab entry free but write unsuccessful" << std::endl; exit(0); } @@ -4313,5 +4369,12 @@ if(r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP) { - m_trt.set(r_xram_rsp_trt_index.read(), + std::vector data_vector; + data_vector.clear(); + + for(size_t i=0; i (m_words,0), - std::vector (m_words,0)); + std::vector (m_words,0));*/ + + m_trt.set(r_xram_rsp_trt_index.read(), + false, // write to XRAM + r_xram_rsp_victim_nline.read(), // line index + 0, + 0, + 0, + false, + 0, + 0, + std::vector (m_words,0), + data_vector); #if DEBUG_MEMC_XRAM_RSP @@ -4395,5 +4470,5 @@ r_xram_rsp_to_cc_send_brdcast_req = r_xram_rsp_victim_is_cnt.read(); r_xram_rsp_to_cc_send_nline = r_xram_rsp_victim_nline.read(); - r_xram_rsp_to_cc_send_trdid = r_xram_rsp_upt_index; + r_xram_rsp_to_cc_send_trdid = r_xram_rsp_ivt_index; xram_rsp_to_cc_send_fifo_srcid = r_xram_rsp_victim_copy.read(); xram_rsp_to_cc_send_fifo_inst = r_xram_rsp_victim_copy_inst.read(); @@ -4427,5 +4502,5 @@ case XRAM_RSP_WRITE_DIRTY: // send a write request to IXR_CMD FSM { - if((!r_xram_rsp_to_ixr_cmd_req.read()) and (!r_xram_rsp_to_ixr_cmd_inval_ncc_pending.read())) + if((!r_xram_rsp_to_ixr_cmd_req.read()) /*and (!r_xram_rsp_to_ixr_cmd_inval_ncc_pending.read())*/) { @@ -4443,5 +4518,5 @@ if( (!r_xram_rsp_victim_coherent.read()) and (r_xram_rsp_victim_count.read() == 1) ) { - r_xram_rsp_to_ixr_cmd_inval_ncc_pending = true; // inval no coherent pending + //r_xram_rsp_to_ixr_cmd_inval_ncc_pending = true; // inval no coherent pending r_xram_rsp_to_ixr_cmd_req = false; r_xram_rsp_fsm = XRAM_RSP_IDLE; @@ -4633,5 +4708,5 @@ DspinDhccpParam::dspin_get( flit, - DspinDhccpParam::FROM_L1_TYPE); + DspinDhccpParam::P2M_TYPE); r_cleanup_way_index = @@ -4689,5 +4764,5 @@ DspinDhccpParam::dspin_get(flit, DspinDhccpParam::CLEANUP_NLINE_LSB); - bool eop = DspinDhccpParam::dspin_get(flit, DspinDhccpParam::FROM_L1_EOP); + bool eop = DspinDhccpParam::dspin_get(flit, DspinDhccpParam::P2M_EOP); /*ODCCP*/ // if not eop (more than 2 flits) there is a cleanup no coherent with data @@ -4711,4 +4786,5 @@ std::cout << " Cleanup request:" + << " / ncc = " << r_cleanup_ncc.read() << " / address = " << std::hex << nline * m_words * 4 << std::endl; #endif @@ -4819,5 +4895,5 @@ else // miss : check UPT for a pending invalidation transaction { - r_cleanup_fsm = CLEANUP_UPT_LOCK; + r_cleanup_fsm = CLEANUP_IVT_LOCK; } @@ -5289,14 +5365,14 @@ } ////////////////////// - case CLEANUP_UPT_LOCK: // get the lock protecting the UPT to search a pending + case CLEANUP_IVT_LOCK: // get the lock protecting the IVT to search a pending // invalidate transaction matching the cleanup { m_cpt_cleanup_fsm_upt_lock++; - if(r_alloc_upt_fsm.read() != ALLOC_UPT_CLEANUP) break; + if(r_alloc_ivt_fsm.read() != ALLOC_IVT_CLEANUP) break; size_t index = 0; bool match_inval; - match_inval = m_upt.search_inval(r_cleanup_nline.read(), index); + match_inval = m_ivt.search_inval(r_cleanup_nline.read(), index); if ( not match_inval ) // no pending inval @@ -5315,6 +5391,6 @@ if(m_debug) std::cout << " Unexpected cleanup" - << " with no corresponding UPT entry:" + << " CLEANUP_IVT_LOCK> Unexpected cleanup" + << " with no corresponding IVT entry:" << " address = " << std::hex << (r_cleanup_nline.read() *4*m_words) @@ -5326,32 +5402,32 @@ // pending inval - r_cleanup_write_srcid = m_upt.srcid(index); - r_cleanup_write_trdid = m_upt.trdid(index); - r_cleanup_write_pktid = m_upt.pktid(index); - r_cleanup_need_rsp = m_upt.need_rsp(index); - r_cleanup_need_ack = m_upt.need_ack(index); + r_cleanup_write_srcid = m_ivt.srcid(index); + r_cleanup_write_trdid = m_ivt.trdid(index); + r_cleanup_write_pktid = m_ivt.pktid(index); + r_cleanup_need_rsp = m_ivt.need_rsp(index); + r_cleanup_need_ack = m_ivt.need_ack(index); r_cleanup_index = index; - r_cleanup_fsm = CLEANUP_UPT_DECREMENT; + r_cleanup_fsm = CLEANUP_IVT_DECREMENT; #if DEBUG_MEMC_CLEANUP if(m_debug) std::cout << " Cleanup matching pending" - << " invalidate transaction on UPT:" + << " CLEANUP_IVT_LOCK> Cleanup matching pending" + << " invalidate transaction on IVT:" << " address = " << std::hex << r_cleanup_nline.read() * m_words * 4 - << " / upt_entry = " << index << std::endl; + << " / ivt_entry = " << index << std::endl; #endif break; } /////////////////////////// - case CLEANUP_UPT_DECREMENT: // decrement response counter in UPT matching entry - { - if(r_alloc_upt_fsm.read() != ALLOC_UPT_CLEANUP) + case CLEANUP_IVT_DECREMENT: // decrement response counter in IVT matching entry + { + if(r_alloc_ivt_fsm.read() != ALLOC_IVT_CLEANUP) { std::cout << "VCI_MEM_CACHE ERROR " << name() - << " CLEANUP_UPT_DECREMENT state" << std::endl - << "Bad UPT allocation" + << " CLEANUP_IVT_DECREMENT state" << std::endl + << "Bad IVT allocation" << std::endl; @@ -5360,9 +5436,9 @@ size_t count = 0; - m_upt.decrement(r_cleanup_index.read(), count); + m_ivt.decrement(r_cleanup_index.read(), count); if(count == 0) // multi inval transaction completed { - r_cleanup_fsm = CLEANUP_UPT_CLEAR; + r_cleanup_fsm = CLEANUP_IVT_CLEAR; } else // multi inval transaction not completed @@ -5381,7 +5457,7 @@ #if DEBUG_MEMC_CLEANUP if(m_debug) -std::cout << " " - << " Decrement response counter in UPT:" - << " UPT_index = " << r_cleanup_index.read() +std::cout << " " + << " Decrement response counter in IVT:" + << " IVT_index = " << r_cleanup_index.read() << " / rsp_count = " << count << std::endl; #endif @@ -5389,12 +5465,12 @@ } /////////////////////// - case CLEANUP_UPT_CLEAR: // Clear UPT entry - { - if(r_alloc_upt_fsm.read() != ALLOC_UPT_CLEANUP) + case CLEANUP_IVT_CLEAR: // Clear IVT entry + { + if(r_alloc_ivt_fsm.read() != ALLOC_IVT_CLEANUP) { std::cout << "VCI_MEM_CACHE ERROR " << name() - << " CLEANUP_UPT_CLEAR state" << std::endl - << "Bad UPT allocation" + << " CLEANUP_IVT_CLEAR state" << std::endl + << "Bad IVT allocation" << std::endl; @@ -5402,5 +5478,5 @@ } - m_upt.clear(r_cleanup_index.read()); + m_ivt.clear(r_cleanup_index.read()); if ( r_cleanup_need_rsp.read() ) r_cleanup_fsm = CLEANUP_WRITE_RSP; @@ -5412,6 +5488,6 @@ if(m_debug) std::cout << " Clear entry in UPT:" - << " UPT_index = " << r_cleanup_index.read() << std::endl; + << " CLEANUP_IVT_CLEAR> Clear entry in IVT:" + << " IVT_index = " << r_cleanup_index.read() << std::endl; #endif break; @@ -5487,5 +5563,5 @@ r_cleanup_to_ixr_cmd_pktid = r_cleanup_pktid.read(); r_cleanup_to_ixr_cmd_nline = r_cleanup_nline.read(); - r_cleanup_to_ixr_cmd_l1_dirty_ncc = true; + //r_cleanup_to_ixr_cmd_l1_dirty_ncc = true; r_cleanup_fsm = CLEANUP_SEND_CLACK; } @@ -5505,13 +5581,31 @@ r_cleanup_to_ixr_cmd_req = true; - for(size_t i = 0; i < m_words; i++){ - r_cleanup_to_ixr_cmd_data[i] = r_cleanup_data[i]; + if (r_cleanup_contains_data.read()) + { + std::vector data_vector; + data_vector.clear(); + + for(size_t i=0; i (m_words,0), + data_vector); } - r_cleanup_to_ixr_cmd_srcid = r_cleanup_srcid.read(); r_cleanup_to_ixr_cmd_trdid = index; r_cleanup_to_ixr_cmd_pktid = r_cleanup_pktid.read(); r_cleanup_to_ixr_cmd_nline = r_cleanup_nline.read(); - r_cleanup_to_ixr_cmd_l1_dirty_ncc = r_cleanup_contains_data.read(); + //r_cleanup_to_ixr_cmd_l1_dirty_ncc = r_cleanup_contains_data.read(); r_cleanup_fsm = CLEANUP_SEND_CLACK; #endif @@ -5547,15 +5641,8 @@ //////////////////////// - case CLEANUP_SEND_CLACK: // acknowledgement to a cleanup command - // on the coherence network (request to the CC_SEND FSM). - // wait if pending request to the CC_SEND FSM - { - if(r_cleanup_to_cc_send_req.read()) break; - - r_cleanup_to_cc_send_req = true; - r_cleanup_to_cc_send_set_index = r_cleanup_nline.read() & 0xFFFF; - r_cleanup_to_cc_send_way_index = r_cleanup_way_index.read(); - r_cleanup_to_cc_send_srcid = r_cleanup_srcid.read(); - r_cleanup_to_cc_send_inst = r_cleanup_inst.read(); + case CLEANUP_SEND_CLACK: // acknowledgement to a cleanup command + // on the coherence CLACK network. + { + if(not p_dspin_clack.read) break; r_cleanup_fsm = CLEANUP_IDLE; @@ -5565,5 +5652,8 @@ std::cout << " Send the response to a cleanup request:" - << " srcid = " << std::dec << r_cleanup_srcid.read() << std::endl; + << " nline = " << std::hex << r_cleanup_nline.read() + << " / way = " << std::dec << r_cleanup_way.read() + << " / srcid = " << std::dec << r_cleanup_srcid.read() + << std::endl; #endif break; @@ -5804,5 +5894,5 @@ !r_cas_to_cc_send_brdcast_req.read()) { - r_cas_fsm = CAS_UPT_LOCK; // multi update required + r_cas_fsm = CAS_UPT_LOCK; // multi update required } else @@ -6077,5 +6167,5 @@ { r_cas_trt_index = wok_index; - r_cas_fsm = CAS_BC_UPT_LOCK; + r_cas_fsm = CAS_BC_IVT_LOCK; } else @@ -6096,8 +6186,8 @@ } ///////////////////// - case CAS_BC_UPT_LOCK: // register a broadcast inval transaction in UPT + case CAS_BC_IVT_LOCK: // register a broadcast inval transaction in IVT // write data in cache in case of successful registration { - if(r_alloc_upt_fsm.read() == ALLOC_UPT_CAS) + if(r_alloc_ivt_fsm.read() == ALLOC_IVT_CAS) { bool wok = false; @@ -6109,9 +6199,9 @@ size_t nb_copies = r_cas_count.read(); - // register a broadcast inval transaction in UPT - wok = m_upt.set(false, // it's an inval transaction - true, // it's a broadcast - true, // response required - false, // no acknowledge required + // register a broadcast inval transaction in IVT + wok = m_ivt.set(false, // it's an inval transaction + true, // it's a broadcast + true, // response required + false, // no acknowledge required srcid, trdid, @@ -6121,5 +6211,5 @@ index); - if(wok) // UPT not full + if(wok) // IVT not full { // cache update @@ -6147,11 +6237,11 @@ if(m_debug) std::cout << " Register a broadcast inval transaction in UPT" + << " CAS_BC_IVT_LOCK> Register a broadcast inval transaction in IVT" << " / nline = " << std::hex << nline << " / count = " << std::dec << nb_copies - << " / upt_index = " << index << std::endl; -#endif - } - else // releases the lock protecting UPT + << " / ivt_index = " << index << std::endl; +#endif + } + else // releases the lock protecting IVT { r_cas_fsm = CAS_WAIT; @@ -6168,6 +6258,6 @@ { if((r_alloc_trt_fsm.read() == ALLOC_TRT_CAS) and - (r_alloc_upt_fsm.read() == ALLOC_UPT_CAS) and - (r_alloc_dir_fsm.read() == ALLOC_DIR_CAS)) + (r_alloc_ivt_fsm.read() == ALLOC_IVT_CAS) and + (r_alloc_dir_fsm.read() == ALLOC_DIR_CAS)) { // set TRT @@ -6416,9 +6506,6 @@ // network, used to update or invalidate cache lines in L1 caches. // - // This fsm is used also to acknowledge CLEANUP a command after request from - // the CLEANUP fsm. - // - // It implements a round-robin priority between the five possible client FSMs - // XRAM_RSP > CAS > CLEANUP > WRITE > CONFIG + // It implements a round-robin priority between the four possible client FSMs + // XRAM_RSP > CAS > WRITE > CONFIG // // Each FSM can request the next services: @@ -6432,6 +6519,4 @@ // r_config_to_cc_send_brdcast_req : broadcast-inval // - // - r_cleanup_to_cc_send_req : cleanup acknowledgement - // // An inval request is a double DSPIN flit command containing: // 1. the index of the line to be invalidated. @@ -6476,10 +6561,4 @@ break; } - // CLEANUP - if (r_cleanup_to_cc_send_req.read()) - { - r_cc_send_fsm = CC_SEND_CLEANUP_ACK; - break; - } // WRITE if(m_write_to_cc_send_inst_fifo.rok() or @@ -6555,10 +6634,4 @@ break; } - // CLEANUP - if (r_cleanup_to_cc_send_req.read()) - { - r_cc_send_fsm = CC_SEND_CLEANUP_ACK; - break; - } // WRITE if(m_write_to_cc_send_inst_fifo.rok() or @@ -6594,10 +6667,4 @@ break; } - // CLEANUP - if(r_cleanup_to_cc_send_req.read()) - { - r_cc_send_fsm = CC_SEND_CLEANUP_ACK; - break; - } // WRITE if(m_write_to_cc_send_inst_fifo.rok() or @@ -6647,9 +6714,4 @@ case CC_SEND_CAS_IDLE: // CLEANUP FSM has highest priority { - if(r_cleanup_to_cc_send_req.read()) - { - r_cc_send_fsm = CC_SEND_CLEANUP_ACK; - break; - } if(m_write_to_cc_send_inst_fifo.rok() or r_write_to_cc_send_multi_req.read()) @@ -6706,70 +6768,4 @@ break; } - ////////////////////////// - case CC_SEND_CLEANUP_IDLE: // WRITE FSM has highest priority - { - // WRITE - if(m_write_to_cc_send_inst_fifo.rok() or - r_write_to_cc_send_multi_req.read()) - { - r_cc_send_fsm = CC_SEND_WRITE_UPDT_HEADER; - m_cpt_update++; - break; - } - if(r_write_to_cc_send_brdcast_req.read()) - { - r_cc_send_fsm = CC_SEND_WRITE_BRDCAST_HEADER; - m_cpt_inval++; - break; - } - // CONFIG - if(r_config_to_cc_send_multi_req.read()) - { - r_cc_send_fsm = CC_SEND_CONFIG_INVAL_HEADER; - m_cpt_inval++; - break; - } - if(r_config_to_cc_send_brdcast_req.read()) - { - r_cc_send_fsm = CC_SEND_CONFIG_BRDCAST_HEADER; - m_cpt_inval++; - break; - } - // XRAM_RSP - if(m_xram_rsp_to_cc_send_inst_fifo.rok() or - r_xram_rsp_to_cc_send_multi_req.read()) - { - r_cc_send_fsm = CC_SEND_XRAM_RSP_INVAL_HEADER; - m_cpt_inval++; - break; - } - if(r_xram_rsp_to_cc_send_brdcast_req.read()) - { - r_cc_send_fsm = CC_SEND_XRAM_RSP_BRDCAST_HEADER; - m_cpt_inval++; - break; - } - // CAS - if(m_cas_to_cc_send_inst_fifo.rok() or - r_cas_to_cc_send_multi_req.read()) - { - r_cc_send_fsm = CC_SEND_CAS_UPDT_HEADER; - m_cpt_update++; - break; - } - if(r_cas_to_cc_send_brdcast_req.read()) - { - r_cc_send_fsm = CC_SEND_CAS_BRDCAST_HEADER; - m_cpt_inval++; - break; - } - // CLEANUP - if(r_cleanup_to_cc_send_req.read()) - { - r_cc_send_fsm = CC_SEND_CLEANUP_ACK; - break; - } - break; - } ///////////////////////////////// case CC_SEND_CONFIG_INVAL_HEADER: // send first flit multi-inval (from CONFIG FSM) @@ -6777,5 +6773,5 @@ if(m_config_to_cc_send_inst_fifo.rok()) { - if(not p_dspin_out.read) break; + if(not p_dspin_m2p.read) break; r_cc_send_fsm = CC_SEND_CONFIG_INVAL_NLINE; break; @@ -6788,5 +6784,5 @@ case CC_SEND_CONFIG_INVAL_NLINE: // send second flit multi-inval (from CONFIG FSM) { - if(not p_dspin_out.read) break; + if(not p_dspin_m2p.read) break; m_cpt_inval_mult++; config_to_cc_send_fifo_get = true; @@ -6804,5 +6800,5 @@ case CC_SEND_CONFIG_BRDCAST_HEADER: // send first flit BC-inval (from CONFIG FSM) { - if(not p_dspin_out.read) break; + if(not p_dspin_m2p.read) break; r_cc_send_fsm = CC_SEND_CONFIG_BRDCAST_NLINE; break; @@ -6811,5 +6807,5 @@ case CC_SEND_CONFIG_BRDCAST_NLINE: // send second flit BC-inval (from CONFIG FSM) { - if(not p_dspin_out.read) break; + if(not p_dspin_m2p.read) break; m_cpt_inval_brdcast++; r_config_to_cc_send_brdcast_req = false; @@ -6824,20 +6820,4 @@ break; } - ///////////////////////// - case CC_SEND_CLEANUP_ACK: // send one flit for a cleanup acknowledgement - { - if(not p_dspin_out.read) break; - - r_cleanup_to_cc_send_req = false; - r_cc_send_fsm = CC_SEND_CLEANUP_IDLE; - -#if DEBUG_MEMC_CC_SEND -if(m_debug) -std::cout << " Cleanup Ack for srcid " - << std::hex << r_cleanup_to_cc_send_srcid.read() << std::endl; -#endif - break; - } /////////////////////////////////// case CC_SEND_XRAM_RSP_INVAL_HEADER: // send first flit multi-inval (from XRAM_RSP FSM) @@ -6845,5 +6825,5 @@ if(m_xram_rsp_to_cc_send_inst_fifo.rok()) { - if(not p_dspin_out.read) break; + if(not p_dspin_m2p.read) break; r_cc_send_fsm = CC_SEND_XRAM_RSP_INVAL_NLINE; break; @@ -6856,5 +6836,5 @@ case CC_SEND_XRAM_RSP_INVAL_NLINE: // send second flit multi-inval (from XRAM_RSP FSM) { - if(not p_dspin_out.read) break; + if(not p_dspin_m2p.read) break; m_cpt_inval_mult++; xram_rsp_to_cc_send_fifo_get = true; @@ -6864,5 +6844,5 @@ if(m_debug) std::cout << " BC-Inval for line " + << " CC_SEND_XRAM_RSP_INVAL_NLINE> Multicast-Inval for line " << std::hex << r_xram_rsp_to_cc_send_nline.read() << std::endl; #endif @@ -6872,5 +6852,5 @@ case CC_SEND_XRAM_RSP_BRDCAST_HEADER: // send first flit broadcast-inval (from XRAM_RSP FSM) { - if(not p_dspin_out.read) break; + if(not p_dspin_m2p.read) break; r_cc_send_fsm = CC_SEND_XRAM_RSP_BRDCAST_NLINE; break; @@ -6879,5 +6859,5 @@ case CC_SEND_XRAM_RSP_BRDCAST_NLINE: // send second flit broadcast-inval (from XRAM_RSP FSM) { - if(not p_dspin_out.read) break; + if(not p_dspin_m2p.read) break; m_cpt_inval_brdcast++; r_xram_rsp_to_cc_send_brdcast_req = false; @@ -6895,5 +6875,5 @@ case CC_SEND_WRITE_BRDCAST_HEADER: // send first flit broadcast-inval (from WRITE FSM) { - if(not p_dspin_out.read) break; + if(not p_dspin_m2p.read) break; r_cc_send_fsm = CC_SEND_WRITE_BRDCAST_NLINE; break; @@ -6902,5 +6882,5 @@ case CC_SEND_WRITE_BRDCAST_NLINE: // send second flit broadcast-inval (from WRITE FSM) { - if(not p_dspin_out.read) break; + if(not p_dspin_m2p.read) break; m_cpt_inval_brdcast++; @@ -6922,5 +6902,5 @@ if(m_write_to_cc_send_inst_fifo.rok()) { - if(not p_dspin_out.read) break; + if(not p_dspin_m2p.read) break; r_cc_send_fsm = CC_SEND_WRITE_UPDT_NLINE; @@ -6939,5 +6919,5 @@ case CC_SEND_WRITE_UPDT_NLINE: // send second flit for a multi-update (from WRITE FSM) { - if(not p_dspin_out.read) break; + if(not p_dspin_m2p.read) break; m_cpt_update_mult++; @@ -6956,5 +6936,5 @@ case CC_SEND_WRITE_UPDT_DATA: // send N data flits for a multi-update (from WRITE FSM) { - if(not p_dspin_out.read) break; + if(not p_dspin_m2p.read) break; if(r_cc_send_cpt.read() == (r_write_to_cc_send_count.read()-1)) { @@ -6970,5 +6950,5 @@ case CC_SEND_CAS_BRDCAST_HEADER: // send first flit broadcast-inval (from CAS FSM) { - if(not p_dspin_out.read) break; + if(not p_dspin_m2p.read) break; r_cc_send_fsm = CC_SEND_CAS_BRDCAST_NLINE; break; @@ -6977,5 +6957,5 @@ case CC_SEND_CAS_BRDCAST_NLINE: // send second flit broadcast-inval (from CAS FSM) { - if(not p_dspin_out.read) break; + if(not p_dspin_m2p.read) break; m_cpt_inval_brdcast++; @@ -6996,5 +6976,5 @@ if(m_cas_to_cc_send_inst_fifo.rok()) { - if(not p_dspin_out.read) break; + if(not p_dspin_m2p.read) break; r_cc_send_fsm = CC_SEND_CAS_UPDT_NLINE; @@ -7014,5 +6994,5 @@ case CC_SEND_CAS_UPDT_NLINE: // send second flit for a multi-update (from CAS FSM) { - if(not p_dspin_out.read) break; + if(not p_dspin_m2p.read) break; m_cpt_update_mult++; @@ -7032,5 +7012,5 @@ case CC_SEND_CAS_UPDT_DATA: // send first data for a multi-update (from CAS FSM) { - if(not p_dspin_out.read) break; + if(not p_dspin_m2p.read) break; if(r_cas_to_cc_send_is_long.read()) @@ -7047,5 +7027,5 @@ case CC_SEND_CAS_UPDT_DATA_HIGH: // send second data for a multi-update (from CAS FSM) { - if(not p_dspin_out.read) break; + if(not p_dspin_m2p.read) break; cas_to_cc_send_fifo_get = true; r_cc_send_fsm = CC_SEND_CAS_UPDT_HEADER; @@ -7067,10 +7047,10 @@ case CC_RECEIVE_IDLE: { - if(not p_dspin_in.write) break; + if(not p_dspin_p2m.write) break; uint8_t type = DspinDhccpParam::dspin_get( - p_dspin_in.data.read(), - DspinDhccpParam::FROM_L1_TYPE); + p_dspin_p2m.data.read(), + DspinDhccpParam::P2M_TYPE); if((type == DspinDhccpParam::TYPE_CLEANUP_DATA) or @@ -7098,8 +7078,8 @@ // write first CLEANUP flit in CC_RECEIVE to CLEANUP fifo - if(not p_dspin_in.write or not m_cc_receive_to_cleanup_fifo.wok()) + if(not p_dspin_p2m.write or not m_cc_receive_to_cleanup_fifo.wok()) break; - assert(not p_dspin_in.eop.read() and + assert(not p_dspin_p2m.eop.read() and "VCI_MEM_CACHE ERROR in CC_RECEIVE : " "CLEANUP command must have two flits"); @@ -7115,13 +7095,9 @@ // write second CLEANUP flit in CC_RECEIVE to CLEANUP fifo or more in case of cleanup data (ODCCP) - if(not p_dspin_in.write or not m_cc_receive_to_cleanup_fifo.wok()) + if(not p_dspin_p2m.write or not m_cc_receive_to_cleanup_fifo.wok()) break; - /*assert(p_dspin_in.eop.read() and - "VCI_MEM_CACHE ERROR in CC_RECEIVE : " - "CLEANUP command must have two flits");*/ - cc_receive_to_cleanup_fifo_put = true; - if(p_dspin_in.eop.read()) + if(p_dspin_p2m.eop.read()) r_cc_receive_fsm = CC_RECEIVE_IDLE; @@ -7135,8 +7111,8 @@ // wait for a WOK in the CC_RECEIVE to MULTI_ACK fifo - if(not p_dspin_in.write or not m_cc_receive_to_multi_ack_fifo.wok()) + if(not p_dspin_p2m.write or not m_cc_receive_to_multi_ack_fifo.wok()) break; - assert(p_dspin_in.eop.read() and + assert(p_dspin_p2m.eop.read() and "VCI_MEM_CACHE ERROR in CC_RECEIVE : " "MULTI_ACK command must have one flit"); @@ -7548,182 +7524,176 @@ // ALLOC_UPT FSM //////////////////////////////////////////////////////////////////////////////////// - // The ALLOC_UPT FSM allocates the access to the Update/Inval Table (UPT), - // with a round robin priority between six FSMs, with the following order: - // CONFIG > MULTI_ACK > WRITE > XRAM_RSP > CLEANUP > CAS - // - The CONFIG FSM initiates an inval transaction and sets a new entry in UPT. + // The ALLOC_UPT FSM allocates the access to the Update Table (UPT), + // with a round robin priority between three FSMs, with the following order: + // WRITE -> CAS -> MULTI_ACK + // - The WRITE FSM initiates update transaction and sets a new entry in UPT. + // - The CAS FSM does the same thing as the WRITE FSM. // - The MULTI_ACK FSM complete those trasactions and erase the UPT entry. - // - The WRITE FSM initiates update transaction and sets a new entry in UPT. - // - The XRAM_RSP FSM initiates an inval transactions and sets a new entry in UPT. - // - The CLEANUP FSM decrement an entry in UPT. - // - The CAS FSM does the same thing as the WRITE FSM. // The resource is always allocated. ///////////////////////////////////////////////////////////////////////////////////// - switch(r_alloc_upt_fsm.read()) { - ////////////////////// - case ALLOC_UPT_CONFIG: // allocated to CONFIG FSM - if (r_config_fsm.read() != CONFIG_DIR_UPT_LOCK) - { - if(r_multi_ack_fsm.read() == MULTI_ACK_UPT_LOCK) - r_alloc_upt_fsm = ALLOC_UPT_MULTI_ACK; - - else if((r_write_fsm.read() == WRITE_UPT_LOCK) or - (r_write_fsm.read() == WRITE_BC_UPT_LOCK)) - r_alloc_upt_fsm = ALLOC_UPT_WRITE; - - else if(r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK) - r_alloc_upt_fsm = ALLOC_UPT_XRAM_RSP; - - else if(r_cleanup_fsm.read() == CLEANUP_UPT_LOCK) - r_alloc_upt_fsm = ALLOC_UPT_CLEANUP; - - else if((r_cas_fsm.read() == CAS_UPT_LOCK) or - (r_cas_fsm.read() == CAS_BC_UPT_LOCK)) - r_alloc_upt_fsm = ALLOC_UPT_CAS; - } - break; - ///////////////////////// - case ALLOC_UPT_MULTI_ACK: // allocated to MULTI_ACK FSM - if( (r_multi_ack_fsm.read() != MULTI_ACK_UPT_LOCK) and - (r_multi_ack_fsm.read() != MULTI_ACK_UPT_CLEAR)) - { - if((r_write_fsm.read() == WRITE_UPT_LOCK) or - (r_write_fsm.read() == WRITE_BC_UPT_LOCK)) - r_alloc_upt_fsm = ALLOC_UPT_WRITE; - - else if(r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK) - r_alloc_upt_fsm = ALLOC_UPT_XRAM_RSP; - - else if(r_cleanup_fsm.read() == CLEANUP_UPT_LOCK) - r_alloc_upt_fsm = ALLOC_UPT_CLEANUP; - - else if((r_cas_fsm.read() == CAS_UPT_LOCK) or - (r_cas_fsm.read() == CAS_BC_UPT_LOCK)) - r_alloc_upt_fsm = ALLOC_UPT_CAS; - else if(r_config_fsm.read() == CONFIG_DIR_UPT_LOCK) - r_alloc_upt_fsm = ALLOC_UPT_CONFIG; - else - m_cpt_upt_unused++; - } - else - m_cpt_multi_ack_fsm_upt_used++; - break; - - ///////////////////// - case ALLOC_UPT_WRITE: // allocated to WRITE FSM - if((r_write_fsm.read() != WRITE_UPT_LOCK) and - (r_write_fsm.read() != WRITE_BC_UPT_LOCK)) - { - if(r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK) - r_alloc_upt_fsm = ALLOC_UPT_XRAM_RSP; - - else if(r_cleanup_fsm.read() == CLEANUP_UPT_LOCK) - r_alloc_upt_fsm = ALLOC_UPT_CLEANUP; - - else if((r_cas_fsm.read() == CAS_UPT_LOCK) or - (r_cas_fsm.read() == CAS_BC_UPT_LOCK)) - r_alloc_upt_fsm = ALLOC_UPT_CAS; - - else if(r_config_fsm.read() == CONFIG_DIR_UPT_LOCK) - r_alloc_upt_fsm = ALLOC_UPT_CONFIG; - - else if(r_multi_ack_fsm.read() == MULTI_ACK_UPT_LOCK) - r_alloc_upt_fsm = ALLOC_UPT_MULTI_ACK; - - else - m_cpt_upt_unused++; - } - else - m_cpt_write_fsm_upt_used++; - break; - - //////////////////////// - case ALLOC_UPT_XRAM_RSP: - if(r_xram_rsp_fsm.read() != XRAM_RSP_INVAL_LOCK) - { - if(r_cleanup_fsm.read() == CLEANUP_UPT_LOCK) - r_alloc_upt_fsm = ALLOC_UPT_CLEANUP; - - else if((r_cas_fsm.read() == CAS_UPT_LOCK) or - (r_cas_fsm.read() == CAS_BC_UPT_LOCK)) - r_alloc_upt_fsm = ALLOC_UPT_CAS; - - else if(r_config_fsm.read() == CONFIG_DIR_UPT_LOCK) - r_alloc_upt_fsm = ALLOC_UPT_CONFIG; - - else if(r_multi_ack_fsm.read() == MULTI_ACK_UPT_LOCK) - r_alloc_upt_fsm = ALLOC_UPT_MULTI_ACK; - - else if((r_write_fsm.read() == WRITE_UPT_LOCK) or - (r_write_fsm.read() == WRITE_BC_UPT_LOCK)) - r_alloc_upt_fsm = ALLOC_UPT_WRITE; - - else - m_cpt_upt_unused++; - } - else - m_cpt_xram_rsp_fsm_upt_used++; - break; - + case ALLOC_UPT_WRITE: // allocated to WRITE FSM + if (r_write_fsm.read() != WRITE_UPT_LOCK) + { + if (r_cas_fsm.read() == CAS_UPT_LOCK) + r_alloc_upt_fsm = ALLOC_UPT_CAS; + + else if (r_multi_ack_fsm.read() == MULTI_ACK_UPT_LOCK) + r_alloc_upt_fsm = ALLOC_UPT_MULTI_ACK; + } + break; + + ///////////////////////// + case ALLOC_UPT_CAS: // allocated to CAS FSM + if (r_cas_fsm.read() != CAS_UPT_LOCK) + { + if (r_multi_ack_fsm.read() == MULTI_ACK_UPT_LOCK) + r_alloc_upt_fsm = ALLOC_UPT_MULTI_ACK; + + else if (r_write_fsm.read() == WRITE_UPT_LOCK) + r_alloc_upt_fsm = ALLOC_UPT_WRITE; + } + break; + + ///////////////////////// + case ALLOC_UPT_MULTI_ACK: // allocated to MULTI_ACK FSM + if ((r_multi_ack_fsm.read() != MULTI_ACK_UPT_LOCK ) and + (r_multi_ack_fsm.read() != MULTI_ACK_UPT_CLEAR)) + { + if (r_write_fsm.read() == WRITE_UPT_LOCK) + r_alloc_upt_fsm = ALLOC_UPT_WRITE; + + else if (r_cas_fsm.read() == CAS_UPT_LOCK) + r_alloc_upt_fsm = ALLOC_UPT_CAS; + } + break; + } // end switch r_alloc_upt_fsm + + //////////////////////////////////////////////////////////////////////////////////// + // ALLOC_IVT FSM + //////////////////////////////////////////////////////////////////////////////////// + // The ALLOC_IVT FSM allocates the access to the Invalidate Table (IVT), + // with a round robin priority between five FSMs, with the following order: + // WRITE -> XRAM_RSP -> CLEANUP -> CAS -> CONFIG + // - The WRITE FSM initiates broadcast invalidate transactions and sets a new entry + // in IVT. + // - The CAS FSM does the same thing as the WRITE FSM. + // - The XRAM_RSP FSM initiates broadcast/multicast invalidate transaction and sets + // a new entry in the IVT + // - The CONFIG FSM does the same thing as the XRAM_RSP FSM + // - The CLEANUP FSM complete those trasactions and erase the IVT entry. + // The resource is always allocated. + ///////////////////////////////////////////////////////////////////////////////////// + switch(r_alloc_ivt_fsm.read()) + { ////////////////////////// - case ALLOC_UPT_CLEANUP: - if((r_cleanup_fsm.read() != CLEANUP_UPT_LOCK ) and - (r_cleanup_fsm.read() != CLEANUP_UPT_DECREMENT)) - { - if((r_cas_fsm.read() == CAS_UPT_LOCK) or - (r_cas_fsm.read() == CAS_BC_UPT_LOCK)) - r_alloc_upt_fsm = ALLOC_UPT_CAS; - - else if(r_config_fsm.read() == CONFIG_DIR_UPT_LOCK) - r_alloc_upt_fsm = ALLOC_UPT_CONFIG; - - else if(r_multi_ack_fsm.read() == MULTI_ACK_UPT_LOCK) - r_alloc_upt_fsm = ALLOC_UPT_MULTI_ACK; - - else if((r_write_fsm.read() == WRITE_UPT_LOCK) or - (r_write_fsm.read() == WRITE_BC_UPT_LOCK)) - r_alloc_upt_fsm = ALLOC_UPT_WRITE; - - else if(r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK) - r_alloc_upt_fsm = ALLOC_UPT_XRAM_RSP; - - else - m_cpt_upt_unused++; - } - else - m_cpt_cleanup_fsm_upt_used++; - break; + case ALLOC_IVT_WRITE: // allocated to WRITE FSM + if (r_write_fsm.read() != WRITE_BC_IVT_LOCK) + { + if (r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_XRAM_RSP; + + else if (r_cleanup_fsm.read() == CLEANUP_IVT_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_CLEANUP; + + else if (r_cas_fsm.read() == CAS_BC_IVT_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_CAS; + + else if (r_config_fsm.read() == CONFIG_DIR_IVT_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_CONFIG; + + else + m_cpt_ivt_unused++; + } + break; ////////////////////////// - case ALLOC_UPT_CAS: - if((r_cas_fsm.read() != CAS_UPT_LOCK) and - (r_cas_fsm.read() != CAS_BC_UPT_LOCK)) - { - if(r_config_fsm.read() == CONFIG_DIR_UPT_LOCK) - r_alloc_upt_fsm = ALLOC_UPT_CONFIG; - - else if(r_multi_ack_fsm.read() == MULTI_ACK_UPT_LOCK) - r_alloc_upt_fsm = ALLOC_UPT_MULTI_ACK; - - else if((r_write_fsm.read() == WRITE_UPT_LOCK) or - (r_write_fsm.read() == WRITE_BC_UPT_LOCK)) - r_alloc_upt_fsm = ALLOC_UPT_WRITE; - - else if(r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK) - r_alloc_upt_fsm = ALLOC_UPT_XRAM_RSP; - - else if(r_cleanup_fsm.read() == CLEANUP_UPT_LOCK) - r_alloc_upt_fsm = ALLOC_UPT_CLEANUP; - - else - m_cpt_upt_unused++; - } - else - m_cpt_cas_fsm_upt_used++; - break; - - } // end switch r_alloc_upt_fsm + case ALLOC_IVT_XRAM_RSP: // allocated to XRAM_RSP FSM + if(r_xram_rsp_fsm.read() != XRAM_RSP_INVAL_LOCK) + { + if(r_cleanup_fsm.read() == CLEANUP_IVT_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_CLEANUP; + + else if (r_cas_fsm.read() == CAS_BC_IVT_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_CAS; + + else if (r_config_fsm.read() == CONFIG_DIR_IVT_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_CONFIG; + + else if (r_write_fsm.read() == WRITE_BC_IVT_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_WRITE; + + else + m_cpt_ivt_unused++; + } + break; + + ////////////////////////// + case ALLOC_IVT_CLEANUP: // allocated to CLEANUP FSM + if ((r_cleanup_fsm.read() != CLEANUP_IVT_LOCK ) and + (r_cleanup_fsm.read() != CLEANUP_IVT_DECREMENT)) + { + if (r_cas_fsm.read() == CAS_BC_IVT_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_CAS; + + else if (r_config_fsm.read() == CONFIG_DIR_IVT_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_CONFIG; + + else if (r_write_fsm.read() == WRITE_BC_IVT_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_WRITE; + + else if (r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_XRAM_RSP; + + else + m_cpt_ivt_unused++; + } + break; + + ////////////////////////// + case ALLOC_IVT_CAS: // allocated to CAS FSM + if (r_cas_fsm.read() != CAS_BC_IVT_LOCK) + { + if (r_config_fsm.read() == CONFIG_DIR_IVT_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_CONFIG; + + else if (r_write_fsm.read() == WRITE_BC_IVT_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_WRITE; + + else if (r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_XRAM_RSP; + + else if (r_cleanup_fsm.read() == CLEANUP_IVT_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_CLEANUP; + + else + m_cpt_ivt_unused++; + } + break; + + ////////////////////////// + case ALLOC_IVT_CONFIG: // allocated to CONFIG FSM + if (r_config_fsm.read() != CONFIG_DIR_IVT_LOCK) + { + if (r_write_fsm.read() == WRITE_BC_IVT_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_WRITE; + + else if (r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_XRAM_RSP; + + else if (r_cleanup_fsm.read() == CLEANUP_IVT_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_CLEANUP; + + else if (r_cas_fsm.read() == CAS_BC_IVT_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_CAS; + + else + m_cpt_ivt_unused++; + } + break; + + } // end switch r_alloc_ivt_fsm //////////////////////////////////////////////////////////////////////////////////// @@ -7755,5 +7725,5 @@ if ( (r_config_fsm.read() != CONFIG_DIR_REQ) and (r_config_fsm.read() != CONFIG_DIR_ACCESS) and - (r_config_fsm.read() != CONFIG_DIR_UPT_LOCK) ) + (r_config_fsm.read() != CONFIG_DIR_IVT_LOCK) ) { if(r_read_fsm.read() == READ_DIR_REQ) @@ -7813,5 +7783,5 @@ (r_write_fsm.read() != WRITE_DIR_HIT) and (r_write_fsm.read() != WRITE_BC_TRT_LOCK) and - (r_write_fsm.read() != WRITE_BC_UPT_LOCK) and + (r_write_fsm.read() != WRITE_BC_IVT_LOCK) and (r_write_fsm.read() != WRITE_MISS_TRT_LOCK) and (r_write_fsm.read() != WRITE_UPT_LOCK) and @@ -7854,5 +7824,5 @@ (r_cas_fsm.read() != CAS_DIR_HIT_WRITE) and (r_cas_fsm.read() != CAS_BC_TRT_LOCK) and - (r_cas_fsm.read() != CAS_BC_UPT_LOCK) and + (r_cas_fsm.read() != CAS_BC_IVT_LOCK) and (r_cas_fsm.read() != CAS_MISS_TRT_LOCK) and (r_cas_fsm.read() != CAS_UPT_LOCK) and @@ -7980,4 +7950,7 @@ r_alloc_trt_fsm = ALLOC_TRT_CLEANUP; + else if (r_ixr_cmd_fsm.read() == IXR_CMD_TRT_LOCK) + r_alloc_trt_fsm = ALLOC_TRT_IXR_CMD; + else m_cpt_trt_unused++; @@ -7991,5 +7964,5 @@ if((r_write_fsm.read() != WRITE_MISS_TRT_LOCK) and (r_write_fsm.read() != WRITE_BC_TRT_LOCK) and - (r_write_fsm.read() != WRITE_BC_UPT_LOCK)) + (r_write_fsm.read() != WRITE_BC_IVT_LOCK)) { if((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) or @@ -8007,4 +7980,7 @@ else if (r_cleanup_fsm.read() == CLEANUP_IXR_REQ) r_alloc_trt_fsm = ALLOC_TRT_CLEANUP; + + else if (r_ixr_cmd_fsm.read() == IXR_CMD_TRT_LOCK) + r_alloc_trt_fsm = ALLOC_TRT_IXR_CMD; else if(r_read_fsm.read() == READ_TRT_LOCK) @@ -8022,5 +7998,5 @@ if((r_cas_fsm.read() != CAS_MISS_TRT_LOCK) and (r_cas_fsm.read() != CAS_BC_TRT_LOCK) and - (r_cas_fsm.read() != CAS_BC_UPT_LOCK)) + (r_cas_fsm.read() != CAS_BC_IVT_LOCK)) { if((r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) and @@ -8034,4 +8010,7 @@ else if (r_cleanup_fsm.read() == CLEANUP_IXR_REQ) r_alloc_trt_fsm = ALLOC_TRT_CLEANUP; + + else if (r_ixr_cmd_fsm.read() == IXR_CMD_TRT_LOCK) + r_alloc_trt_fsm = ALLOC_TRT_IXR_CMD; else if(r_read_fsm.read() == READ_TRT_LOCK) @@ -8063,4 +8042,7 @@ else if (r_cleanup_fsm.read() == CLEANUP_IXR_REQ) r_alloc_trt_fsm = ALLOC_TRT_CLEANUP; + + else if (r_ixr_cmd_fsm.read() == IXR_CMD_TRT_LOCK) + r_alloc_trt_fsm = ALLOC_TRT_IXR_CMD; else if(r_read_fsm.read() == READ_TRT_LOCK) @@ -8090,4 +8072,7 @@ if (r_cleanup_fsm.read() == CLEANUP_IXR_REQ) r_alloc_trt_fsm = ALLOC_TRT_CLEANUP; + + else if (r_ixr_cmd_fsm.read() == IXR_CMD_TRT_LOCK) + r_alloc_trt_fsm = ALLOC_TRT_IXR_CMD; else if(r_read_fsm.read() == READ_TRT_LOCK) @@ -8115,7 +8100,10 @@ //////////////////////// case ALLOC_TRT_CLEANUP: - if(r_ixr_rsp_fsm.read() != CLEANUP_IXR_REQ) - { - if(r_read_fsm.read() == READ_TRT_LOCK) + if(r_cleanup_fsm.read() != CLEANUP_IXR_REQ) + { + if (r_ixr_cmd_fsm.read() == IXR_CMD_TRT_LOCK) + r_alloc_trt_fsm = ALLOC_TRT_IXR_CMD; + + else if(r_read_fsm.read() == READ_TRT_LOCK) r_alloc_trt_fsm = ALLOC_TRT_READ; @@ -8138,4 +8126,31 @@ break; + //////////////////////// + case ALLOC_TRT_IXR_CMD: + if(r_ixr_cmd_fsm.read() != IXR_CMD_TRT_LOCK) + { + if(r_read_fsm.read() == READ_TRT_LOCK) + r_alloc_trt_fsm = ALLOC_TRT_READ; + + else if((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) or + (r_write_fsm.read() == WRITE_BC_TRT_LOCK)) + r_alloc_trt_fsm = ALLOC_TRT_WRITE; + + else if((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) or + (r_cas_fsm.read() == CAS_BC_TRT_LOCK)) + r_alloc_trt_fsm = ALLOC_TRT_CAS; + + else if((r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) and + (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP)) + r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP; + + else if((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) || + (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ)) + r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP; + + else if (r_cleanup_fsm.read() == CLEANUP_IXR_REQ) + r_alloc_trt_fsm = ALLOC_TRT_CLEANUP; + } + break; } // end switch alloc_trt_fsm @@ -8406,5 +8421,6 @@ m_cc_receive_to_cleanup_fifo.update( cc_receive_to_cleanup_fifo_get, cc_receive_to_cleanup_fifo_put, - ( (uint64_t)(p_dspin_in.eop.read() & 0x1 ) << 32 ) | p_dspin_in.data.read() ); + ( (uint64_t)(p_dspin_p2m.eop.read() & 0x1 ) << 32 ) | p_dspin_p2m.data.read() ); + //////////////////////////////////////////////////////////////////////////////////// // CC_RECEIVE to MULTI_ACK FIFO @@ -8413,5 +8429,5 @@ m_cc_receive_to_multi_ack_fifo.update( cc_receive_to_multi_ack_fifo_get, cc_receive_to_multi_ack_fifo_put, - p_dspin_in.data.read() ); + p_dspin_p2m.data.read() ); //////////////////////////////////////////////////////////////////////////////////// @@ -8562,5 +8578,13 @@ p_vci_ixr.address = (addr_t)((r_cleanup_to_ixr_cmd_nline.read() * m_words + r_ixr_cmd_cpt.read()) * 4); +#if ODCCP_NON_INCLUSIVE + p_vci_ixr.wdata = ((wide_data_t)(r_cleanup_to_ixr_cmd_data[r_ixr_cmd_cpt.read()].read()) | + ((wide_data_t)(r_cleanup_to_ixr_cmd_data[r_ixr_cmd_cpt.read() + 1].read()) << 32)); +#else + p_vci_ixr.wdata = ((wide_data_t)(r_ixr_cmd_data[r_ixr_cmd_cpt.read()].read()) | + ((wide_data_t)(r_ixr_cmd_data[r_ixr_cmd_cpt.read() + 1].read()) << 32)); +#endif + /* if(r_cleanup_to_ixr_cmd_l1_dirty_ncc.read()) // if cleanup data contains data, we use cleanup_data buffer (cleanup dirty) { @@ -8573,5 +8597,5 @@ ((wide_data_t)(r_xram_rsp_to_ixr_cmd_data[r_ixr_cmd_cpt.read() + 1].read()) << 32)); } - + */ p_vci_ixr.trdid = r_cleanup_to_ixr_cmd_trdid.read(); p_vci_ixr.eop = (r_ixr_cmd_cpt == (m_words - 2)); @@ -8777,10 +8801,10 @@ //////////////////////////////////////////////////////////////////// - // p_dspin_out port (CC_SEND FSM) + // p_dspin_m2p port (CC_SEND FSM) //////////////////////////////////////////////////////////////////// - p_dspin_out.write = false; - p_dspin_out.eop = false; - p_dspin_out.data = 0; + p_dspin_m2p.write = false; + p_dspin_m2p.eop = false; + p_dspin_m2p.data = 0; switch(r_cc_send_fsm.read()) @@ -8791,5 +8815,4 @@ case CC_SEND_WRITE_IDLE: case CC_SEND_CAS_IDLE: - case CC_SEND_CLEANUP_IDLE: { break; @@ -8826,7 +8849,7 @@ DspinDhccpParam::dspin_set( flit, multi_inval_type, - DspinDhccpParam::FROM_MC_TYPE); - p_dspin_out.write = true; - p_dspin_out.data = flit; + DspinDhccpParam::M2P_TYPE); + p_dspin_m2p.write = true; + p_dspin_m2p.data = flit; break; } @@ -8838,54 +8861,9 @@ r_config_to_cc_send_nline.read(), DspinDhccpParam::MULTI_INVAL_NLINE); - p_dspin_out.eop = true; - p_dspin_out.write = true; - p_dspin_out.data = flit; + p_dspin_m2p.eop = true; + p_dspin_m2p.write = true; + p_dspin_m2p.data = flit; break; } - //////////////////////// - case CC_SEND_CLEANUP_ACK: - { - uint8_t cleanup_ack_type; - if(r_cleanup_to_cc_send_inst.read()) - { - cleanup_ack_type = DspinDhccpParam::TYPE_CLEANUP_ACK_INST; - } - else - { - cleanup_ack_type = DspinDhccpParam::TYPE_CLEANUP_ACK_DATA; - } - - uint64_t flit = 0; - uint64_t dest = - r_cleanup_to_cc_send_srcid.read() << - (DspinDhccpParam::SRCID_WIDTH - vci_param_int::S); - - DspinDhccpParam::dspin_set( - flit, - dest, - DspinDhccpParam::CLEANUP_ACK_DEST); - - DspinDhccpParam::dspin_set( - flit, - r_cleanup_to_cc_send_set_index.read(), - DspinDhccpParam::CLEANUP_ACK_SET); - - DspinDhccpParam::dspin_set( - flit, - r_cleanup_to_cc_send_way_index.read(), - DspinDhccpParam::CLEANUP_ACK_WAY); - - DspinDhccpParam::dspin_set( - flit, - cleanup_ack_type, - DspinDhccpParam::FROM_MC_TYPE); - - p_dspin_out.eop = true; - p_dspin_out.write = true; - p_dspin_out.data = flit; - - break; - } - /////////////////////////////////// case CC_SEND_XRAM_RSP_INVAL_HEADER: @@ -8921,7 +8899,7 @@ DspinDhccpParam::dspin_set( flit, multi_inval_type, - DspinDhccpParam::FROM_MC_TYPE); - p_dspin_out.write = true; - p_dspin_out.data = flit; + DspinDhccpParam::M2P_TYPE); + p_dspin_m2p.write = true; + p_dspin_m2p.data = flit; break; } @@ -8935,7 +8913,7 @@ r_xram_rsp_to_cc_send_nline.read(), DspinDhccpParam::MULTI_INVAL_NLINE); - p_dspin_out.eop = true; - p_dspin_out.write = true; - p_dspin_out.data = flit; + p_dspin_m2p.eop = true; + p_dspin_m2p.write = true; + p_dspin_m2p.data = flit; break; } @@ -8959,7 +8937,7 @@ DspinDhccpParam::dspin_set( flit, 1ULL, - DspinDhccpParam::FROM_MC_BC); - p_dspin_out.write = true; - p_dspin_out.data = flit; + DspinDhccpParam::M2P_BC); + p_dspin_m2p.write = true; + p_dspin_m2p.data = flit; break; } @@ -8971,7 +8949,7 @@ r_xram_rsp_to_cc_send_nline.read(), DspinDhccpParam::BROADCAST_NLINE); - p_dspin_out.write = true; - p_dspin_out.eop = true; - p_dspin_out.data = flit; + p_dspin_m2p.write = true; + p_dspin_m2p.eop = true; + p_dspin_m2p.data = flit; break; } @@ -8983,7 +8961,7 @@ r_config_to_cc_send_nline.read(), DspinDhccpParam::BROADCAST_NLINE); - p_dspin_out.write = true; - p_dspin_out.eop = true; - p_dspin_out.data = flit; + p_dspin_m2p.write = true; + p_dspin_m2p.eop = true; + p_dspin_m2p.data = flit; break; } @@ -8995,7 +8973,7 @@ r_write_to_cc_send_nline.read(), DspinDhccpParam::BROADCAST_NLINE); - p_dspin_out.write = true; - p_dspin_out.eop = true; - p_dspin_out.data = flit; + p_dspin_m2p.write = true; + p_dspin_m2p.eop = true; + p_dspin_m2p.data = flit; break; } @@ -9007,7 +8985,7 @@ r_cas_to_cc_send_nline.read(), DspinDhccpParam::BROADCAST_NLINE); - p_dspin_out.write = true; - p_dspin_out.eop = true; - p_dspin_out.data = flit; + p_dspin_m2p.write = true; + p_dspin_m2p.eop = true; + p_dspin_m2p.data = flit; break; } @@ -9050,8 +9028,8 @@ flit, multi_updt_type, - DspinDhccpParam::FROM_MC_TYPE); - - p_dspin_out.write = true; - p_dspin_out.data = flit; + DspinDhccpParam::M2P_TYPE); + + p_dspin_m2p.write = true; + p_dspin_m2p.data = flit; break; @@ -9072,6 +9050,6 @@ DspinDhccpParam::MULTI_UPDT_NLINE); - p_dspin_out.write = true; - p_dspin_out.data = flit; + p_dspin_m2p.write = true; + p_dspin_m2p.data = flit; break; @@ -9099,7 +9077,7 @@ DspinDhccpParam::MULTI_UPDT_DATA); - p_dspin_out.write = true; - p_dspin_out.eop = (r_cc_send_cpt.read() == (r_write_to_cc_send_count.read()-1)); - p_dspin_out.data = flit; + p_dspin_m2p.write = true; + p_dspin_m2p.eop = (r_cc_send_cpt.read() == (r_write_to_cc_send_count.read()-1)); + p_dspin_m2p.data = flit; break; @@ -9143,8 +9121,8 @@ flit, multi_updt_type, - DspinDhccpParam::FROM_MC_TYPE); - - p_dspin_out.write = true; - p_dspin_out.data = flit; + DspinDhccpParam::M2P_TYPE); + + p_dspin_m2p.write = true; + p_dspin_m2p.data = flit; break; @@ -9165,6 +9143,6 @@ DspinDhccpParam::MULTI_UPDT_NLINE); - p_dspin_out.write = true; - p_dspin_out.data = flit; + p_dspin_m2p.write = true; + p_dspin_m2p.data = flit; break; @@ -9185,7 +9163,7 @@ DspinDhccpParam::MULTI_UPDT_DATA); - p_dspin_out.write = true; - p_dspin_out.eop = not r_cas_to_cc_send_is_long.read(); - p_dspin_out.data = flit; + p_dspin_m2p.write = true; + p_dspin_m2p.eop = not r_cas_to_cc_send_is_long.read(); + p_dspin_m2p.data = flit; break; @@ -9206,7 +9184,7 @@ DspinDhccpParam::MULTI_UPDT_DATA); - p_dspin_out.write = true; - p_dspin_out.eop = true; - p_dspin_out.data = flit; + p_dspin_m2p.write = true; + p_dspin_m2p.eop = true; + p_dspin_m2p.data = flit; break; @@ -9214,12 +9192,84 @@ } + //////////////////////////////////////////////////////////////////// + // p_dspin_clack port (CLEANUP FSM) + //////////////////////////////////////////////////////////////////// + + switch(r_cleanup_fsm.read()) + { + case CLEANUP_IDLE: + case CLEANUP_GET_NLINE: + case CLEANUP_DIR_REQ: + case CLEANUP_DIR_LOCK: + case CLEANUP_DIR_WRITE: + case CLEANUP_HEAP_REQ: + case CLEANUP_HEAP_LOCK: + case CLEANUP_HEAP_SEARCH: + case CLEANUP_HEAP_CLEAN: + case CLEANUP_HEAP_FREE: + case CLEANUP_IVT_LOCK: + case CLEANUP_IVT_DECREMENT: + case CLEANUP_IVT_CLEAR: + case CLEANUP_WRITE_RSP: + case CLEANUP_CONFIG_ACK: + p_dspin_clack.write = false; + p_dspin_clack.eop = false; + p_dspin_clack.data = 0; + + break; + + case CLEANUP_SEND_CLACK: + { + uint8_t cleanup_ack_type; + if(r_cleanup_inst.read()) + { + cleanup_ack_type = DspinDhccpParam::TYPE_CLACK_INST; + } + else + { + cleanup_ack_type = DspinDhccpParam::TYPE_CLACK_DATA; + } + + uint64_t flit = 0; + uint64_t dest = + r_cleanup_srcid.read() << + (DspinDhccpParam::SRCID_WIDTH - vci_param_int::S); + + DspinDhccpParam::dspin_set( + flit, + dest, + DspinDhccpParam::CLACK_DEST); + + DspinDhccpParam::dspin_set( + flit, + r_cleanup_nline.read() & 0xFFFF, + DspinDhccpParam::CLACK_SET); + + DspinDhccpParam::dspin_set( + flit, + r_cleanup_way_index.read(), + DspinDhccpParam::CLACK_WAY); + + DspinDhccpParam::dspin_set( + flit, + cleanup_ack_type, + DspinDhccpParam::CLACK_TYPE); + + p_dspin_clack.eop = true; + p_dspin_clack.write = true; + p_dspin_clack.data = flit; + } + break; + } + /////////////////////////////////////////////////////////////////// - // p_dspin_in port (CC_RECEIVE FSM) + // p_dspin_p2m port (CC_RECEIVE FSM) /////////////////////////////////////////////////////////////////// - p_dspin_in.read = false; + // switch(r_cc_receive_fsm.read()) { case CC_RECEIVE_IDLE: { + p_dspin_p2m.read = false; break; } @@ -9227,10 +9277,10 @@ case CC_RECEIVE_CLEANUP_EOP: { - p_dspin_in.read = m_cc_receive_to_cleanup_fifo.wok(); + p_dspin_p2m.read = m_cc_receive_to_cleanup_fifo.wok(); break; } case CC_RECEIVE_MULTI_ACK: { - p_dspin_in.read = m_cc_receive_to_multi_ack_fifo.wok(); + p_dspin_p2m.read = m_cc_receive_to_multi_ack_fifo.wok(); break; }