Changeset 48 for trunk/modules/vci_cc_vcache_wrapper2_v1/caba/source
- Timestamp:
- Jun 13, 2010, 8:29:15 AM (15 years ago)
- Location:
- trunk/modules/vci_cc_vcache_wrapper2_v1/caba/source
- Files:
-
- 2 edited
-
include/vci_cc_vcache_wrapper2_v1.h (modified) (4 diffs)
-
src/vci_cc_vcache_wrapper2_v1.cpp (modified) (192 diffs)
Legend:
- Unmodified
- Added
- Removed
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trunk/modules/vci_cc_vcache_wrapper2_v1/caba/source/include/vci_cc_vcache_wrapper2_v1.h
r37 r48 440 440 441 441 uint32_t m_cpt_frz_cycles; // number of cycles where the cpu is frozen 442 uint32_t m_cpt_total_cycles; // total number of cycles 442 uint32_t m_cpt_total_cycles; // total number of cycles 443 uint32_t m_cpt_dcache_frz_cycles; // number of cycles where the data cache is frozen 443 444 444 445 // Cache activity counters … … 460 461 uint32_t m_cpt_unc_transaction; // number of VCI uncached read transactions 461 462 uint32_t m_cpt_write_transaction; // number of VCI write transactions 463 uint32_t m_cpt_icache_unc_transaction; 462 464 463 465 uint32_t m_cost_imiss_transaction; // cumulated duration for VCI IMISS transactions … … 465 467 uint32_t m_cost_unc_transaction; // cumulated duration for VCI UNC transactions 466 468 uint32_t m_cost_write_transaction; // cumulated duration for VCI WRITE transactions 469 uint32_t m_cost_icache_unc_transaction; // cumulated duration for VCI IUNC transactions 467 470 uint32_t m_length_write_transaction; // cumulated length for VCI WRITE transactions 468 471 … … 470 473 uint32_t m_cpt_ins_tlb_read; // number of instruction tlb read 471 474 uint32_t m_cpt_ins_tlb_miss; // number of instruction tlb miss 472 uint32_t m_cpt_ins_tlb_write_et; // number of instruction tlb write ET 473 475 uint32_t m_cpt_ins_tlb_update_acc; // number of instruction tlb update acc 474 476 uint32_t m_cpt_data_tlb_read; // number of data tlb read 475 477 uint32_t m_cpt_data_tlb_miss; // number of data tlb miss 476 uint32_t m_cpt_data_tlb_write_et; // number of data tlb write ET 477 uint32_t m_cpt_data_tlb_write_dirty; // number of data tlb write dirty 478 uint32_t m_cpt_data_tlb_update_acc; // number of data tlb update acc 479 uint32_t m_cpt_data_tlb_update_dirty; // number of data tlb update dirty 480 uint32_t m_cpt_ins_tlb_hit_dcache; // number of instruction tlb hit in data cache 481 uint32_t m_cpt_data_tlb_hit_dcache; // number of data tlb hit in data cache 482 uint32_t m_cpt_ins_tlb_occup_cache; // number of instruction tlb occupy data cache line 483 uint32_t m_cpt_data_tlb_occup_cache; // number of data tlb occupy data cache line 484 uint32_t m_cpt_tlb_occupy_dcache; 478 485 479 486 uint32_t m_cost_ins_tlb_miss_frz; // number of frozen cycles related to instruction tlb miss 480 487 uint32_t m_cost_data_tlb_miss_frz; // number of frozen cycles related to data tlb miss 481 482 uint32_t m_cost_ins_waste_wait_frz; // number of frozen cycles related to ins wait coherence operate 483 uint32_t m_cost_ins_tlb_sw_frz; // number of frozen cycles related to ins context switch 484 uint32_t m_cost_ins_cache_flush_frz; // number of frozen cycles related to ins cache flush 485 486 uint32_t m_cpt_ins_tlb_cleanup; // number of ins tlb cleanup 487 uint32_t m_cost_data_waste_wait_frz; // number of frozen cycles related to data wait coherence operate 488 uint32_t m_cost_data_tlb_sw_frz; // number of frozen cycles related to data context switch 489 uint32_t m_cost_data_cache_flush_frz; // number of frozen cycles related to data cache flush 490 491 uint32_t m_cpt_itlbmiss_transaction; // number of itlb miss transactions 492 uint32_t m_cpt_itlb_write_transaction; // number of itlb write ET transactions 493 uint32_t m_cpt_dtlbmiss_transaction; // number of dtlb miss transactions 494 uint32_t m_cpt_dtlb_write_transaction; // number of dtlb write ET and dirty transactions 495 496 uint32_t m_cost_itlbmiss_transaction; // cumulated duration for VCI instruction TLB miss transactions 497 uint32_t m_cost_itlb_write_transaction; // cumulated duration for VCI instruction TLB write ET transactions 498 uint32_t m_cost_dtlbmiss_transaction; // cumulated duration for VCI data TLB miss transactions 499 uint32_t m_cost_dtlb_write_transaction; // cumulated duration for VCI data TLB write transactions 500 501 uint32_t m_cpt_cc_update; // number of coherence update packets 502 uint32_t m_cpt_cc_inval; // number of coherence inval packets 503 uint32_t m_cpt_cc_broadcast; // number of coherence broadcast packets 488 uint32_t m_cost_ins_tlb_update_acc_frz; // number of frozen cycles related to instruction tlb update acc 489 uint32_t m_cost_data_tlb_update_acc_frz; // number of frozen cycles related to data tlb update acc 490 uint32_t m_cost_data_tlb_update_dirty_frz; // number of frozen cycles related to data tlb update dirty 491 uint32_t m_cost_ins_tlb_occup_cache_frz; // number of frozen cycles related to instruction tlb miss operate in dcache 492 uint32_t m_cost_data_tlb_occup_cache_frz; // number of frozen cycles related to data tlb miss operate in dcache 493 494 uint32_t m_cpt_itlbmiss_transaction; // number of itlb miss transactions 495 uint32_t m_cpt_itlb_ll_transaction; // number of itlb ll acc transactions 496 uint32_t m_cpt_itlb_sc_transaction; // number of itlb sc acc transactions 497 uint32_t m_cpt_dtlbmiss_transaction; // number of dtlb miss transactions 498 uint32_t m_cpt_dtlb_ll_transaction; // number of dtlb ll acc transactions 499 uint32_t m_cpt_dtlb_sc_transaction; // number of dtlb sc acc transactions 500 uint32_t m_cpt_dtlb_ll_dirty_transaction; // number of dtlb ll dirty transactions 501 uint32_t m_cpt_dtlb_sc_dirty_transaction; // number of dtlb sc dirty transactions 502 503 uint32_t m_cost_itlbmiss_transaction; // cumulated duration for VCI instruction TLB miss transactions 504 uint32_t m_cost_itlb_ll_transaction; // cumulated duration for VCI instruction TLB ll acc transactions 505 uint32_t m_cost_itlb_sc_transaction; // cumulated duration for VCI instruction TLB sc acc transactions 506 uint32_t m_cost_dtlbmiss_transaction; // cumulated duration for VCI data TLB miss transactions 507 uint32_t m_cost_dtlb_ll_transaction; // cumulated duration for VCI data TLB ll acc transactions 508 uint32_t m_cost_dtlb_sc_transaction; // cumulated duration for VCI data TLB sc acc transactions 509 uint32_t m_cost_dtlb_ll_dirty_transaction;// cumulated duration for VCI data TLB ll dirty transactions 510 uint32_t m_cost_dtlb_sc_dirty_transaction;// cumulated duration for VCI data TLB sc dirty transactions 511 512 uint32_t m_cpt_cc_update_data; // number of coherence update data packets 513 uint32_t m_cpt_cc_inval_ins; // number of coherence inval instruction packets 514 uint32_t m_cpt_cc_inval_data; // number of coherence inval data packets 515 uint32_t m_cpt_cc_broadcast; // number of coherence broadcast packets 504 516 505 517 uint32_t m_cost_ins_tlb_inval_frz; // number of frozen cycles related to checking ins tlb invalidate -
trunk/modules/vci_cc_vcache_wrapper2_v1/caba/source/src/vci_cc_vcache_wrapper2_v1.cpp
r37 r48 367 367 float run_cycles = (float)(m_cpt_total_cycles - m_cpt_frz_cycles); 368 368 std::cout << name() << std::endl 369 << "- CPI = " << (float)m_cpt_total_cycles/run_cycles << std::endl 370 << "- READ RATE = " << (float)m_cpt_read/run_cycles << std::endl 371 << "- WRITE RATE = " << (float)m_cpt_write/run_cycles << std::endl 372 << "- UNCACHED READ RATE = " << (float)m_cpt_unc_read/m_cpt_read << std::endl 373 << "- CACHED WRITE RATE = " << (float)m_cpt_write_cached/m_cpt_write << std::endl 374 << "- IMISS_RATE = " << (float)m_cpt_ins_miss/m_cpt_ins_read << std::endl 375 << "- DMISS RATE = " << (float)m_cpt_data_miss/(m_cpt_read-m_cpt_unc_read) << std::endl 376 << "- INS MISS COST = " << (float)m_cost_ins_miss_frz/m_cpt_ins_miss << std::endl 377 << "- IMISS TRANSACTION = " << (float)m_cost_imiss_transaction/m_cpt_imiss_transaction << std::endl 378 << "- DMISS COST = " << (float)m_cost_data_miss_frz/m_cpt_data_miss << std::endl 379 << "- DMISS TRANSACTION = " << (float)m_cost_dmiss_transaction/m_cpt_dmiss_transaction << std::endl 380 << "- UNC COST = " << (float)m_cost_unc_read_frz/m_cpt_unc_read << std::endl 381 << "- UNC TRANSACTION = " << (float)m_cost_unc_transaction/m_cpt_unc_transaction << std::endl 382 << "- WRITE COST = " << (float)m_cost_write_frz/m_cpt_write << std::endl 383 << "- WRITE TRANSACTION = " << (float)m_cost_write_transaction/m_cpt_write_transaction << std::endl 384 << "- WRITE LENGTH = " << (float)m_length_write_transaction/m_cpt_write_transaction << std::endl 385 << "- INS TLB MISS RATE = " << (float)m_cpt_ins_tlb_miss/m_cpt_ins_tlb_read << std::endl 386 << "- DATA TLB MISS RATE = " << (float)m_cpt_data_tlb_miss/m_cpt_data_tlb_read << std::endl 387 << "- ITLB MISS TRANSACTION = " << (float)m_cost_itlbmiss_transaction/m_cpt_itlbmiss_transaction << std::endl 388 << "- ITLB WRITE TRANSACTION = " << (float)m_cost_itlb_write_transaction/m_cpt_itlb_write_transaction << std::endl 389 << "- ITLB MISS COST = " << (float)m_cost_ins_tlb_miss_frz/(m_cpt_ins_tlb_miss+m_cpt_ins_tlb_write_et) << std::endl 390 << "- DTLB MISS TRANSACTION = " << (float)m_cost_dtlbmiss_transaction/m_cpt_dtlbmiss_transaction << std::endl 391 << "- DTLB WRITE TRANSACTION = " << (float)m_cost_dtlb_write_transaction/m_cpt_dtlb_write_transaction << std::endl 392 << "- DTLB MISS COST = " << (float)m_cost_data_tlb_miss_frz/(m_cpt_data_tlb_miss+m_cpt_data_tlb_write_et+m_cpt_data_tlb_write_dirty) << std::endl; 369 << "- CPI = " << (float)m_cpt_total_cycles/run_cycles << std::endl 370 << "- READ RATE = " << (float)m_cpt_read/run_cycles << std::endl 371 << "- WRITE RATE = " << (float)m_cpt_write/run_cycles << std::endl 372 << "- IMISS_RATE = " << (float)m_cpt_ins_miss/m_cpt_ins_read << std::endl 373 << "- DMISS RATE = " << (float)m_cpt_data_miss/(m_cpt_read-m_cpt_unc_read) << std::endl 374 << "- INS MISS COST = " << (float)m_cost_ins_miss_frz/m_cpt_ins_miss << std::endl 375 << "- DATA MISS COST = " << (float)m_cost_data_miss_frz/m_cpt_data_miss << std::endl 376 << "- WRITE COST = " << (float)m_cost_write_frz/m_cpt_write << std::endl 377 << "- UNC COST = " << (float)m_cost_unc_read_frz/m_cpt_unc_read << std::endl 378 << "- UNCACHED READ RATE = " << (float)m_cpt_unc_read/m_cpt_read << std::endl 379 << "- CACHED WRITE RATE = " << (float)m_cpt_write_cached/m_cpt_write << std::endl 380 << "- INS TLB MISS RATE = " << (float)m_cpt_ins_tlb_miss/m_cpt_ins_tlb_read << std::endl 381 << "- DATA TLB MISS RATE = " << (float)m_cpt_data_tlb_miss/m_cpt_data_tlb_read << std::endl 382 << "- ITLB MISS COST = " << (float)m_cost_ins_tlb_miss_frz/m_cpt_ins_tlb_miss << std::endl 383 << "- DTLB MISS COST = " << (float)m_cost_data_tlb_miss_frz/m_cpt_data_tlb_miss << std::endl 384 << "- ITLB UPDATE ACC COST = " << (float)m_cost_ins_tlb_update_acc_frz/m_cpt_ins_tlb_update_acc << std::endl 385 << "- DTLB UPDATE ACC COST = " << (float)m_cost_data_tlb_update_acc_frz/m_cpt_data_tlb_update_acc << std::endl 386 << "- DTLB UPDATE DIRTY COST = " << (float)m_cost_data_tlb_update_dirty_frz/m_cpt_data_tlb_update_dirty << std::endl 387 << "- ITLB HIT IN DCACHE RATE= " << (float)m_cpt_ins_tlb_hit_dcache/m_cpt_ins_tlb_miss << std::endl 388 << "- DTLB HIT IN DCACHE RATE= " << (float)m_cpt_data_tlb_hit_dcache/m_cpt_data_tlb_miss << std::endl 389 << "- DCACHE FROZEN BY TLB OP= " << (float)(m_cost_ins_tlb_occup_cache_frz+m_cost_data_tlb_occup_cache_frz)/m_cpt_dcache_frz_cycles << std::endl 390 << "- DCACHE FOR TLB % = " << (float)m_cpt_tlb_occup_dcache/(m_dcache_ways*m_dcache_sets) << std::endl 391 << "- NB CC BROADCAST = " << m_cpt_cc_broadcast << std::endl 392 << "- NB CC UPDATE DATA = " << m_cpt_cc_update_data << std::endl 393 << "- NB CC INVAL DATA = " << m_cpt_cc_inval_data << std::endl 394 << "- NB CC INVAL INS = " << m_cpt_cc_inval_ins << std::endl 395 << "- NB CC CLEANUP DATA = " << m_cpt_cc_cleanup_data << std::endl 396 << "- NB CC CLEANUP INS = " << m_cpt_cc_cleanup_ins << std::endl 397 << "- IMISS TRANSACTION = " << (float)m_cost_imiss_transaction/m_cpt_imiss_transaction << std::endl 398 << "- DMISS TRANSACTION = " << (float)m_cost_dmiss_transaction/m_cpt_dmiss_transaction << std::endl 399 << "- UNC TRANSACTION = " << (float)m_cost_unc_transaction/m_cpt_unc_transaction << std::endl 400 << "- WRITE TRANSACTION = " << (float)m_cost_write_transaction/m_cpt_write_transaction << std::endl 401 << "- WRITE LENGTH = " << (float)m_length_write_transaction/m_cpt_write_transaction << std::endl 402 << "- ITLB MISS TRANSACTION = " << (float)m_cost_itlbmiss_transaction/m_cpt_itlbmiss_transaction << std::endl 403 << "- DTLB MISS TRANSACTION = " << (float)m_cost_dtlbmiss_transaction/m_cpt_dtlbmiss_transaction << std::endl; 393 404 } 394 405 … … 464 475 r_dcache_dirty_save = false; 465 476 r_dcache_hit_p_save = false; 477 r_dcache_cached_save = false; 466 478 467 479 r_icache_buf_unc_valid = false; … … 527 539 m_cpt_icache_dir_write = 0; 528 540 529 m_cpt_frz_cycles = 0; 530 m_cpt_total_cycles = 0; 541 m_cpt_frz_cycles = 0; 542 m_cpt_dcache_frz_cycles = 0; 543 m_cpt_total_cycles = 0; 531 544 532 545 m_cpt_read = 0; … … 543 556 m_cost_ins_miss_frz = 0; 544 557 545 m_cpt_imiss_transaction = 0; 546 m_cpt_dmiss_transaction = 0; 547 m_cpt_unc_transaction = 0; 548 m_cpt_write_transaction = 0; 549 550 m_cost_imiss_transaction = 0; 551 m_cost_dmiss_transaction = 0; 552 m_cost_unc_transaction = 0; 553 m_cost_write_transaction = 0; 554 m_length_write_transaction = 0; 555 556 m_cpt_ins_tlb_read = 0; 557 m_cpt_ins_tlb_miss = 0; 558 m_cpt_ins_tlb_write_et = 0; 559 560 m_cpt_data_tlb_read = 0; 561 m_cpt_data_tlb_miss = 0; 562 m_cpt_data_tlb_write_et = 0; 563 m_cpt_data_tlb_write_dirty = 0; 564 565 m_cost_ins_tlb_miss_frz = 0; 566 m_cost_data_tlb_miss_frz = 0; 567 568 m_cpt_itlbmiss_transaction = 0; 569 m_cpt_itlb_write_transaction = 0; 570 m_cpt_dtlbmiss_transaction = 0; 571 m_cpt_dtlb_write_transaction = 0; 558 m_cpt_imiss_transaction = 0; 559 m_cpt_dmiss_transaction = 0; 560 m_cpt_unc_transaction = 0; 561 m_cpt_write_transaction = 0; 562 m_cpt_icache_unc_transaction = 0; 563 564 m_cost_imiss_transaction = 0; 565 m_cost_dmiss_transaction = 0; 566 m_cost_unc_transaction = 0; 567 m_cost_write_transaction = 0; 568 m_cost_icache_unc_transaction = 0; 569 m_length_write_transaction = 0; 570 571 m_cpt_ins_tlb_read = 0; 572 m_cpt_ins_tlb_miss = 0; 573 m_cpt_ins_tlb_update_acc = 0; 574 575 m_cpt_data_tlb_read = 0; 576 m_cpt_data_tlb_miss = 0; 577 m_cpt_data_tlb_update_acc = 0; 578 m_cpt_data_tlb_update_dirty = 0; 579 m_cpt_ins_tlb_hit_dcache = 0; 580 m_cpt_data_tlb_hit_dcache = 0; 581 m_cpt_ins_tlb_occup_cache = 0; 582 m_cpt_data_tlb_occup_cache = 0; 583 584 m_cost_ins_tlb_miss_frz = 0; 585 m_cost_data_tlb_miss_frz = 0; 586 m_cost_ins_tlb_update_acc_frz = 0; 587 m_cost_data_tlb_update_acc_frz = 0; 588 m_cost_data_tlb_update_dirty_frz = 0; 589 m_cost_ins_tlb_occup_cache_frz = 0; 590 m_cost_data_tlb_occup_cache_frz = 0; 591 592 m_cpt_itlbmiss_transaction = 0; 593 m_cpt_itlb_ll_transaction = 0; 594 m_cpt_itlb_sc_transaction = 0; 595 m_cpt_dtlbmiss_transaction = 0; 596 m_cpt_dtlb_ll_transaction = 0; 597 m_cpt_dtlb_sc_transaction = 0; 598 m_cpt_dtlb_ll_dirty_transaction = 0; 599 m_cpt_dtlb_sc_dirty_transaction = 0; 572 600 573 m_cost_itlbmiss_transaction = 0; 574 m_cost_itlb_write_transaction = 0; 575 m_cost_dtlbmiss_transaction = 0; 576 m_cost_dtlb_write_transaction = 0; 601 m_cost_itlbmiss_transaction = 0; 602 m_cost_itlb_ll_transaction = 0; 603 m_cost_itlb_sc_transaction = 0; 604 m_cost_dtlbmiss_transaction = 0; 605 m_cost_dtlb_ll_transaction = 0; 606 m_cost_dtlb_sc_transaction = 0; 607 m_cost_dtlb_ll_dirty_transaction = 0; 608 m_cost_dtlb_sc_dirty_transaction = 0; 577 609 return; 578 610 } … … 691 723 r_tgt_update = false; 692 724 r_vci_tgt_fsm = TGT_REQ_DCACHE; 693 m_cpt_cc_inval ++ ;725 m_cpt_cc_inval_data++ ; 694 726 } 695 727 else if (cell == 4) // update … … 703 735 r_tgt_update = true; 704 736 r_vci_tgt_fsm = TGT_UPDT_WORD; 705 m_cpt_cc_update ++ ;737 m_cpt_cc_update_data++ ; 706 738 } 707 739 else if (cell == 8) … … 715 747 r_tgt_update = false; 716 748 r_vci_tgt_fsm = TGT_REQ_ICACHE; 717 m_cpt_cc_inval ++ ;749 m_cpt_cc_inval_ins++ ; 718 750 719 751 } … … 948 980 if ( r_tgt_icache_req ) 949 981 { 950 if ( ireq.valid ) m_cost_ins_waste_wait_frz++;951 982 r_icache_fsm = ICACHE_CC_INVAL; 952 983 r_icache_fsm_save = r_icache_fsm; … … 957 988 if ( r_dcache_itlb_inval_req ) 958 989 { 959 if ( ireq.valid ) m_cost_ins_waste_wait_frz++;960 990 r_itlb_inval_req = true; 961 991 r_icache_fsm = ICACHE_TLB_CC_INVAL; … … 1119 1149 case ICACHE_BIS: 1120 1150 { 1121 m_cost_ins_miss_frz++;1122 1151 // external cache invalidate request 1123 1152 if ( r_tgt_icache_req ) 1124 1153 { 1154 if ( ireq.valid ) m_cost_ins_miss_frz++; 1125 1155 r_icache_fsm = ICACHE_CC_INVAL; 1126 1156 r_icache_fsm_save = r_icache_fsm; 1127 m_cost_ins_waste_wait_frz++;1128 1157 break; 1129 1158 } … … 1132 1161 if ( r_dcache_itlb_inval_req ) 1133 1162 { 1163 if ( ireq.valid ) m_cost_ins_miss_frz++; 1134 1164 r_itlb_inval_req = true; 1135 1165 r_icache_fsm = ICACHE_TLB_CC_INVAL; 1136 1166 r_icache_fsm_save = r_icache_fsm; 1137 m_cost_ins_waste_wait_frz++;1138 1167 break; 1139 1168 } … … 1142 1171 if ( r_icache_inval_tlb_rsp ) 1143 1172 { 1173 if ( ireq.valid ) m_cost_ins_miss_frz++; 1144 1174 r_icache_inval_tlb_rsp = false; 1145 1175 r_icache_fsm = ICACHE_IDLE; 1146 m_cost_ins_tlb_miss_frz++;1147 1176 break; 1148 1177 } … … 1167 1196 r_icache_fsm = ICACHE_MISS_WAIT; 1168 1197 m_cpt_ins_miss++; 1198 m_cost_ins_miss_frz++; 1169 1199 } 1170 1200 else … … 1191 1221 case ICACHE_TLB1_READ: 1192 1222 { 1193 m_cost_ins_tlb_miss_frz++;1223 if ( ireq.valid ) m_cost_ins_tlb_miss_frz++; 1194 1224 1195 1225 // external cache invalidate request … … 1198 1228 r_icache_fsm = ICACHE_CC_INVAL; 1199 1229 r_icache_fsm_save = r_icache_fsm; 1200 m_cost_ins_waste_wait_frz++;1201 1230 break; 1202 1231 } … … 1208 1237 r_icache_fsm = ICACHE_TLB_CC_INVAL; 1209 1238 r_icache_fsm_save = r_icache_fsm; 1210 m_cost_ins_waste_wait_frz++;1211 1239 break; 1212 1240 } … … 1262 1290 r_itlb_acc_dcache_req = true; 1263 1291 r_icache_fsm = ICACHE_TLB1_WRITE; 1264 m_cpt_ins_tlb_write_et++; 1292 m_cpt_ins_tlb_update_acc++; 1293 m_cost_ins_tlb_update_acc_frz++; 1265 1294 } 1266 1295 } … … 1277 1306 r_itlb_acc_dcache_req = true; 1278 1307 r_icache_fsm = ICACHE_TLB1_WRITE; 1279 m_cpt_ins_tlb_write_et++; 1308 m_cpt_ins_tlb_update_acc++; 1309 m_cost_ins_tlb_update_acc_frz++; 1280 1310 } 1281 1311 } … … 1311 1341 case ICACHE_TLB1_WRITE: 1312 1342 { 1313 m_cost_ins_tlb_miss_frz++; 1343 if ( ireq.valid ) m_cost_ins_tlb_miss_frz++; 1344 m_cost_ins_tlb_update_acc_frz++; 1314 1345 1315 1346 // external cache invalidate request … … 1318 1349 r_icache_fsm = ICACHE_CC_INVAL; 1319 1350 r_icache_fsm_save = r_icache_fsm; 1320 m_cost_ins_waste_wait_frz++;1321 1351 break; 1322 1352 } … … 1327 1357 r_icache_fsm = ICACHE_TLB_CC_INVAL; 1328 1358 r_icache_fsm_save = r_icache_fsm; 1329 m_cost_ins_waste_wait_frz++;1330 1359 break; 1331 1360 } … … 1368 1397 case ICACHE_TLB1_UPDT: 1369 1398 { 1370 m_cost_ins_tlb_miss_frz++;1399 if ( ireq.valid ) m_cost_ins_tlb_miss_frz++; 1371 1400 1372 1401 // external cache invalidate request … … 1375 1404 r_icache_fsm = ICACHE_CC_INVAL; 1376 1405 r_icache_fsm_save = r_icache_fsm; 1377 m_cost_ins_waste_wait_frz++;1378 1406 break; 1379 1407 } … … 1385 1413 r_icache_fsm = ICACHE_TLB_CC_INVAL; 1386 1414 r_icache_fsm_save = r_icache_fsm; 1387 m_cost_ins_waste_wait_frz++;1388 1415 break; 1389 1416 } … … 1395 1422 r_dcache_itlb_cleanup_req = icache_tlb.update(r_icache_pte_update,r_icache_vaddr_req.read(),(r_icache_paddr_save.read() >> (uint32_log2(m_dcache_words)+2)),&victim_index); 1396 1423 r_dcache_itlb_cleanup_line = victim_index; 1424 m_cpt_cc_cleanup_ins++; 1397 1425 r_icache_fsm = ICACHE_IDLE; 1398 1426 } … … 1409 1437 case ICACHE_TLB2_READ: 1410 1438 { 1411 m_cost_ins_tlb_miss_frz++;1439 if ( ireq.valid ) m_cost_ins_tlb_miss_frz++; 1412 1440 1413 1441 // external cache invalidate request … … 1416 1444 r_icache_fsm = ICACHE_CC_INVAL; 1417 1445 r_icache_fsm_save = r_icache_fsm; 1418 m_cost_ins_waste_wait_frz++;1419 1446 break; 1420 1447 } … … 1426 1453 r_icache_fsm = ICACHE_TLB_CC_INVAL; 1427 1454 r_icache_fsm_save = r_icache_fsm; 1428 m_cost_ins_waste_wait_frz++;1429 1455 break; 1430 1456 } … … 1466 1492 r_itlb_acc_dcache_req = true; 1467 1493 r_icache_fsm = ICACHE_TLB2_WRITE; 1468 m_cpt_ins_tlb_write_et++; 1494 m_cpt_ins_tlb_update_acc++; 1495 m_cost_ins_tlb_update_acc_frz++; 1469 1496 } 1470 1497 } … … 1481 1508 r_itlb_acc_dcache_req = true; 1482 1509 r_icache_fsm = ICACHE_TLB2_WRITE; 1483 m_cpt_ins_tlb_write_et++; 1510 m_cpt_ins_tlb_update_acc++; 1511 m_cost_ins_tlb_update_acc_frz++; 1484 1512 } 1485 1513 } … … 1515 1543 case ICACHE_TLB2_WRITE: 1516 1544 { 1517 m_cost_ins_tlb_miss_frz++; 1545 if ( ireq.valid ) m_cost_ins_tlb_miss_frz++; 1546 m_cost_ins_tlb_update_acc_frz++; 1518 1547 1519 1548 // external cache invalidate request … … 1522 1551 r_icache_fsm = ICACHE_CC_INVAL; 1523 1552 r_icache_fsm_save = r_icache_fsm; 1524 m_cost_ins_waste_wait_frz++;1525 1553 break; 1526 1554 } … … 1531 1559 r_icache_fsm = ICACHE_TLB_CC_INVAL; 1532 1560 r_icache_fsm_save = r_icache_fsm; 1533 m_cost_ins_waste_wait_frz++;1534 1561 break; 1535 1562 } … … 1572 1599 case ICACHE_TLB2_UPDT: 1573 1600 { 1574 m_cost_ins_tlb_miss_frz++;1601 if ( ireq.valid ) m_cost_ins_tlb_miss_frz++; 1575 1602 1576 1603 // external cache invalidate request … … 1579 1606 r_icache_fsm = ICACHE_CC_INVAL; 1580 1607 r_icache_fsm_save = r_icache_fsm; 1581 m_cost_ins_waste_wait_frz++;1582 1608 break; 1583 1609 } … … 1589 1615 r_icache_fsm = ICACHE_TLB_CC_INVAL; 1590 1616 r_icache_fsm_save = r_icache_fsm; 1591 m_cost_ins_waste_wait_frz++;1592 1617 break; 1593 1618 } … … 1599 1624 r_dcache_itlb_cleanup_req = icache_tlb.update(r_icache_pte_update,r_dcache_rsp_itlb_ppn,r_icache_vaddr_req.read(),(r_icache_paddr_save.read() >> (uint32_log2(m_dcache_words)+2)),&victim_index); 1600 1625 r_dcache_itlb_cleanup_line = victim_index; 1626 m_cpt_cc_cleanup_ins++; 1601 1627 r_icache_fsm = ICACHE_IDLE; 1602 1628 } … … 1616 1642 bool clean = false; 1617 1643 1618 if ( ireq.valid ) m_cost_ins_waste_wait_frz++;1619 1644 m_cost_ins_tlb_sw_frz++; 1620 1645 … … 1654 1679 case ICACHE_TLB_FLUSH: 1655 1680 { 1656 if ( ireq.valid ) m_cost_ins_waste_wait_frz++;1657 1658 1681 // data cache flush leads to ins tlb flush, flush all tlb entry 1659 1682 icache_tlb.flush(true); // global entries are invalidated … … 1672 1695 r_icache_fsm = ICACHE_CC_INVAL; 1673 1696 r_icache_fsm_save = r_icache_fsm; 1674 m_cost_ins_waste_wait_frz++;1675 1697 break; 1676 1698 } … … 1679 1701 size_t set = r_icache_set; 1680 1702 bool clean = false; 1681 1682 m_cost_ins_cache_flush_frz++;1683 if ( ireq.valid ) m_cost_ins_waste_wait_frz++;1684 1703 1685 1704 // cache flush and send cleanup to external … … 1696 1715 r_icache_cleanup_req = true; 1697 1716 r_icache_cleanup_line = victim_index; 1717 m_cpt_cc_cleanup_ins++; 1698 1718 r_icache_way = way + ((set+1)/m_icache_sets); 1699 1719 r_icache_set = (set+1) % m_icache_sets; … … 1715 1735 case ICACHE_TLB_INVAL: 1716 1736 { 1717 if ( ireq.valid ) m_cost_ins_waste_wait_frz++;1718 1737 paddr_t victim_index = 0; 1719 1738 … … 1722 1741 r_dcache_itlb_cleanup_req = icache_tlb.inval(r_dcache_wdata_save, &victim_index); 1723 1742 r_dcache_itlb_cleanup_line = victim_index; 1743 m_cpt_cc_cleanup_ins++; 1724 1744 r_dcache_xtn_req = false; 1725 1745 r_itlb_translation_valid = false; … … 1732 1752 case ICACHE_CACHE_INVAL: 1733 1753 { 1734 if ( ireq.valid ) m_cost_ins_waste_wait_frz++;1735 1754 // external cache invalidate request 1736 1755 if ( r_tgt_icache_req ) … … 1738 1757 r_icache_fsm = ICACHE_CC_INVAL; 1739 1758 r_icache_fsm_save = r_icache_fsm; 1740 m_cost_ins_waste_wait_frz++;1741 1759 break; 1742 1760 } … … 1760 1778 // invalidate and cleanup if necessary 1761 1779 r_icache_cleanup_req = r_icache.inval(ipaddr); 1762 r_icache_cleanup_line = ipaddr >> (uint32_log2(m_icache_words) + 2); 1780 r_icache_cleanup_line = ipaddr >> (uint32_log2(m_icache_words) + 2); 1781 m_cpt_cc_cleanup_ins++; 1763 1782 } 1764 1783 r_dcache_xtn_req = false; … … 1775 1794 r_icache_fsm = ICACHE_CC_INVAL; 1776 1795 r_icache_fsm_save = r_icache_fsm; 1777 m_cost_ins_waste_wait_frz++;1778 1796 break; 1779 1797 } … … 1785 1803 // invalidate and cleanup if necessary 1786 1804 r_icache_cleanup_req = r_icache.inval(ipaddr); 1787 r_icache_cleanup_line = ipaddr >> (uint32_log2(m_icache_words) + 2); 1805 r_icache_cleanup_line = ipaddr >> (uint32_log2(m_icache_words) + 2); 1806 m_cpt_cc_cleanup_ins++; 1788 1807 r_dcache_xtn_req = false; 1789 1808 r_icache_fsm = ICACHE_IDLE; … … 1801 1820 r_icache_fsm = ICACHE_CC_INVAL; 1802 1821 r_icache_fsm_save = r_icache_fsm; 1803 m_cost_ins_waste_wait_frz++;1804 1822 break; 1805 1823 } … … 1811 1829 r_icache_fsm = ICACHE_TLB_CC_INVAL; 1812 1830 r_icache_fsm_save = r_icache_fsm; 1813 m_cost_ins_waste_wait_frz++;1814 1831 break; 1815 1832 } … … 1832 1849 if ( r_icache_cleanup_req ) break; 1833 1850 r_icache_cleanup_req = true; 1834 r_icache_cleanup_line = r_icache_paddr_save.read() >> (uint32_log2(m_icache_words) + 2); 1851 r_icache_cleanup_line = r_icache_paddr_save.read() >> (uint32_log2(m_icache_words) + 2); 1852 m_cpt_cc_cleanup_ins++; 1835 1853 r_icache_fsm = ICACHE_IDLE; 1836 1854 r_icache_inval_tlb_rsp = false; 1837 1855 if ( r_icache_inval_rsp ) r_icache_inval_rsp = false; 1838 m_cost_ins_tlb_miss_frz++;1839 1856 break; 1840 1857 } … … 1845 1862 r_icache_cleanup_req = true; 1846 1863 r_icache_cleanup_line = r_icache_paddr_save.read() >> (uint32_log2(m_icache_words) + 2); 1864 m_cpt_cc_cleanup_ins++; 1847 1865 r_icache_fsm = ICACHE_IDLE; 1848 1866 r_icache_inval_rsp = false; … … 1856 1874 case ICACHE_UNC_WAIT: 1857 1875 { 1858 m_cost_ins_miss_frz++;1859 1860 1876 // external cache invalidate request 1861 1877 if ( r_tgt_icache_req ) … … 1863 1879 r_icache_fsm = ICACHE_CC_INVAL; 1864 1880 r_icache_fsm_save = r_icache_fsm; 1865 m_cost_ins_waste_wait_frz++;1866 1881 break; 1867 1882 } … … 1873 1888 r_icache_fsm = ICACHE_TLB_CC_INVAL; 1874 1889 r_icache_fsm_save = r_icache_fsm; 1875 m_cost_ins_waste_wait_frz++;1876 1890 break; 1877 1891 } … … 1913 1927 r_icache_fsm = ICACHE_CC_INVAL; 1914 1928 r_icache_fsm_save = r_icache_fsm; 1915 m_cost_ins_waste_wait_frz++;1916 1929 break; 1917 1930 } … … 1923 1936 r_icache_fsm = ICACHE_TLB_CC_INVAL; 1924 1937 r_icache_fsm_save = r_icache_fsm; 1925 m_cost_ins_waste_wait_frz++;1926 1938 break; 1927 1939 } … … 1931 1943 if ( r_icache_cleanup_req ) break; 1932 1944 r_icache_cleanup_req = true; 1933 r_icache_cleanup_line = r_icache_paddr_save.read() >> (uint32_log2(m_icache_words) + 2); 1945 r_icache_cleanup_line = r_icache_paddr_save.read() >> (uint32_log2(m_icache_words) + 2); 1946 m_cpt_cc_cleanup_ins++; 1934 1947 r_icache_inval_tlb_rsp = false; 1935 1948 if ( r_icache_inval_rsp ) r_icache_inval_rsp = false; 1936 1949 r_icache_fsm = ICACHE_IDLE; 1937 m_cost_ins_tlb_miss_frz++;1938 1950 break; 1939 1951 } … … 1944 1956 { 1945 1957 r_icache_cleanup_req = true; 1946 r_icache_cleanup_line = r_icache_paddr_save.read() >> (uint32_log2(m_icache_words) + 2); 1958 r_icache_cleanup_line = r_icache_paddr_save.read() >> (uint32_log2(m_icache_words) + 2); 1959 m_cpt_cc_cleanup_ins++; 1947 1960 r_icache_fsm = ICACHE_IDLE; 1948 1961 r_icache_inval_rsp = false; … … 1956 1969 1957 1970 r_icache_cleanup_req = r_icache.update(r_icache_paddr_save.read(), buf, &victim_index); 1958 r_icache_cleanup_line = victim_index; 1959 1971 r_icache_cleanup_line = victim_index; m_cpt_cc_cleanup_ins++; 1960 1972 r_icache_fsm = ICACHE_IDLE; 1961 1973 } … … 1977 1989 case ICACHE_CC_INVAL: 1978 1990 { 1979 if ( ireq.valid ) m_cost_ins_waste_wait_frz++;1980 1991 m_cpt_icache_dir_read += m_icache_ways; 1992 /* activity counter */ 1993 if ( (( r_icache_fsm_save == ICACHE_BIS ) ||( r_icache_fsm_save == ICACHE_MISS_WAIT ) || ( r_icache_fsm_save == ICACHE_MISS_UPDT ) ) && ( ireq.valid ) ) 1994 { 1995 m_cost_ins_miss_frz++; 1996 } 1997 if( (( r_icache_fsm_save == ICACHE_TLB1_READ ) || ( r_icache_fsm_save == ICACHE_TLB2_READ ) || 1998 ( r_icache_fsm_save == ICACHE_TLB1_WRITR ) || ( r_icache_fsm_save == ICACHE_TLB2_WRITE ) || 1999 ( r_icache_fsm_save == ICACHE_TLB1_UPDT ) || ( r_icache_fsm_save == ICACHE_TLB2_UPDT )) && (ireq.valid) ) 2000 { 2001 m_cost_ins_tlb_miss_frz++; 2002 } 1981 2003 1982 2004 // invalidate cache … … 1999 2021 case ICACHE_TLB_CC_INVAL: 2000 2022 { 2001 if ( ireq.valid ) m_cost_ins_waste_wait_frz++; 2023 /* activity counter */ 2024 if ( (( r_icache_fsm_save == ICACHE_BIS ) ||( r_icache_fsm_save == ICACHE_MISS_WAIT ) || ( r_icache_fsm_save == ICACHE_MISS_UPDT ) ) && ( ireq.valid ) ) 2025 { 2026 m_cost_ins_miss_frz++; 2027 } 2028 if( (( r_icache_fsm_save == ICACHE_TLB1_READ ) || ( r_icache_fsm_save == ICACHE_TLB2_READ ) || 2029 ( r_icache_fsm_save == ICACHE_TLB1_WRITR ) || ( r_icache_fsm_save == ICACHE_TLB2_WRITE ) || 2030 ( r_icache_fsm_save == ICACHE_TLB1_UPDT ) || ( r_icache_fsm_save == ICACHE_TLB2_UPDT )) && (ireq.valid) ) 2031 { 2032 m_cost_ins_tlb_miss_frz++; 2033 } 2002 2034 2003 2035 if ( r_itlb_inval_req ) break; … … 2148 2180 r_dcache_fsm = DCACHE_CC_CHECK; 2149 2181 r_dcache_fsm_save = r_dcache_fsm; 2150 if ( dreq.valid ) m_cost_data_waste_wait_frz++;2151 2182 break; 2152 2183 } … … 2194 2225 r_dcache_fsm = DCACHE_CC_CHECK; 2195 2226 r_dcache_fsm_save = DCACHE_IDLE; 2196 if ( dreq.valid ) m_cost_data_waste_wait_frz++;2197 2227 break; 2198 2228 } … … 2202 2232 { 2203 2233 r_dcache_fsm = DCACHE_ITLB_CLEANUP; 2204 m_cpt_ins_tlb_cleanup++;2205 if ( dreq.valid ) m_cost_data_waste_wait_frz++;2206 2234 break; 2207 2235 } … … 2209 2237 if ( r_itlb_read_dcache_req ) 2210 2238 { 2239 if ( dreq.valid ) m_cost_ins_tlb_occup_cache_frz++; 2211 2240 data_t rsp_itlb_miss; 2212 2241 data_t rsp_itlb_ppn; … … 2225 2254 if ( itlb_hit_dcache ) // ins TLB request hits in data cache 2226 2255 { 2256 if (!((rsp_itlb_miss & PTE_T_MASK ) >> PTE_T_SHIFT)) m_cpt_ins_tlb_hit_dcache++; 2227 2257 r_dcache_rsp_itlb_miss = rsp_itlb_miss; 2228 2258 r_dcache_rsp_itlb_ppn = rsp_itlb_ppn; … … 2241 2271 r_dcache_fsm = DCACHE_ITLB_READ; 2242 2272 } 2243 if ( dreq.valid ) m_cost_data_waste_wait_frz++;2244 2273 } 2245 2274 else if ( r_itlb_acc_dcache_req ) // ins tlb write access bit … … 2248 2277 assert(write_hit && "Write on miss ignores data"); 2249 2278 r_dcache_itlb_ll_acc_req = true; 2250 r_dcache_fsm = DCACHE_ITLB_LL_WAIT; 2251 if ( dreq.valid ) m_cost_data_waste_wait_frz++;2279 r_dcache_fsm = DCACHE_ITLB_LL_WAIT; 2280 m_cpt_dcache_data_write++; 2252 2281 } 2253 2282 else if (dreq.valid) … … 2630 2659 r_dcache_hit_p_save = dcache_hit_p; 2631 2660 r_dcache_fsm = DCACHE_BIS; 2632 m_cost_data_ miss_frz++;2661 m_cost_data_tlb_miss_frz++; 2633 2662 } 2634 2663 else // cached or uncached access with a correct speculative physical address … … 2730 2759 m_cpt_write++; 2731 2760 if ( dcache_cached ) m_cpt_write_cached++; 2732 2761 m_cost_write_frz++; 2733 2762 if ( dcache_hit_c && dcache_cached ) // cache update required 2734 2763 { … … 2737 2766 else if ( !dcache_pte_info.d && (r_mmu_mode.read() & DATA_TLB_MASK) ) // dirty bit update required 2738 2767 { 2768 m_cpt_data_tlb_update_dirty++; 2769 m_cost_data_tlb_update_dirty_frz++; 2739 2770 if ( dcache_tlb.getpagesize(dcache_tlb_way, dcache_tlb_set) ) // 2M page size, one level page table 2740 2771 { … … 2743 2774 r_dcache_tlb_ll_dirty_req = true; 2744 2775 r_dcache_fsm = DCACHE_LL_DIRTY_WAIT; 2745 m_cpt_data_tlb_write_dirty++;2746 2776 } 2747 2777 else // 4k page size, two levels page table … … 2753 2783 r_dcache_tlb_ll_dirty_req = true; 2754 2784 r_dcache_fsm = DCACHE_LL_DIRTY_WAIT; 2755 m_cpt_data_tlb_write_dirty++;2756 2785 } 2757 2786 else // get PTBA to calculate the physical address of PTE … … 2763 2792 } 2764 2793 } 2765 m_cost_data_tlb_miss_frz++;2766 2794 } 2767 2795 else // no cache update, not dirty bit update … … 2812 2840 r_dcache_fsm = DCACHE_CC_CHECK; 2813 2841 r_dcache_fsm_save = r_dcache_fsm; 2814 m_cost_data_waste_wait_frz++;2842 if ( dreq.valid ) m_cost_data_miss_frz++; 2815 2843 break; 2816 2844 } … … 2821 2849 r_dcache_inval_tlb_rsp = false; 2822 2850 r_dcache_fsm = DCACHE_IDLE; 2823 m_cost_data_tlb_miss_frz++;2851 if ( dreq.valid ) m_cost_data_miss_frz++; 2824 2852 break; 2825 2853 } … … 2866 2894 else if (!r_dcache_dirty_save && (r_mmu_mode.read() & DATA_TLB_MASK)) // dirty bit update required 2867 2895 { 2896 m_cpt_data_tlb_update_dirty++; 2897 m_cost_data_tlb_update_dirty_frz++; 2868 2898 if (dcache_tlb.getpagesize(r_dcache_tlb_way_save, r_dcache_tlb_set_save)) 2869 2899 { … … 2872 2902 r_dcache_tlb_ll_dirty_req = true; 2873 2903 r_dcache_fsm = DCACHE_LL_DIRTY_WAIT; 2874 m_cpt_data_tlb_write_dirty++;2875 2904 } 2876 2905 else … … 2882 2911 r_dcache_tlb_ll_dirty_req = true; 2883 2912 r_dcache_fsm = DCACHE_LL_DIRTY_WAIT; 2884 m_cpt_data_tlb_write_dirty++;2885 2913 } 2886 2914 else … … 2892 2920 } 2893 2921 } 2894 m_cost_data_tlb_miss_frz++;2895 2922 } 2896 2923 else // no cache update, not dirty bit update … … 2914 2941 case DCACHE_LL_DIRTY_WAIT: 2915 2942 { 2943 m_cost_data_tlb_update_dirty_frz++; 2944 2916 2945 // external cache invalidate request 2917 2946 if ( r_tgt_dcache_req ) … … 2919 2948 r_dcache_fsm = DCACHE_CC_CHECK; 2920 2949 r_dcache_fsm_save = r_dcache_fsm; 2921 m_cost_data_waste_wait_frz++;2922 2950 break; 2923 2951 } … … 2963 2991 r_dcache_inval_tlb_rsp = false; 2964 2992 r_dcache_fsm = DCACHE_IDLE; 2965 m_cost_data_tlb_miss_frz++;2966 2993 } 2967 2994 else if ( r_dcache_inval_rsp ) … … 2983 3010 case DCACHE_SC_DIRTY_WAIT: 2984 3011 { 3012 m_cost_data_tlb_update_dirty_frz++; 2985 3013 // external cache invalidate request 2986 3014 if ( r_tgt_dcache_req ) … … 2988 3016 r_dcache_fsm = DCACHE_CC_CHECK; 2989 3017 r_dcache_fsm_save = r_dcache_fsm; 2990 m_cost_data_waste_wait_frz++;2991 3018 break; 2992 3019 } … … 3018 3045 r_dcache_fsm = DCACHE_IDLE; 3019 3046 if (r_dcache_tlb_sc_fail) r_dcache_tlb_sc_fail = false; 3020 m_cost_data_tlb_miss_frz++;3021 3047 } 3022 3048 else if ( r_dcache_inval_rsp ) … … 3030 3056 r_dcache_tlb_ll_dirty_req = true; 3031 3057 r_dcache_tlb_sc_fail = false; 3032 r_dcache_fsm = DCACHE_LL_DIRTY_WAIT; 3058 r_dcache_fsm = DCACHE_LL_DIRTY_WAIT; 3059 m_cpt_data_tlb_update_dirty++; 3033 3060 } 3034 3061 else … … 3050 3077 r_dcache_fsm = DCACHE_CC_CHECK; 3051 3078 r_dcache_fsm_save = r_dcache_fsm; 3052 m_cost_data_waste_wait_frz++;3053 3079 break; 3054 3080 } … … 3059 3085 r_dcache_inval_tlb_rsp = false; 3060 3086 r_dcache_fsm = DCACHE_IDLE; 3061 m_cost_data_tlb_miss_frz++;3062 3087 break; 3063 3088 } … … 3099 3124 r_dcache_tlb_ll_dirty_req = true; 3100 3125 r_dcache_fsm = DCACHE_LL_DIRTY_WAIT; 3101 m_cpt_data_tlb_write_dirty++; 3126 m_cpt_dcache_data_write++; 3127 m_cost_data_tlb_update_dirty_frz++; 3102 3128 } 3103 3129 else … … 3108 3134 else // PTE 3109 3135 { 3136 m_cpt_data_tlb_hit_dcache++; 3110 3137 r_dcache_ptba_ok = false; 3111 3138 if ( (m_srcid_rw >> 4) == ((r_dcache_tlb_paddr.read() & ((1<<(m_paddr_nbits - PAGE_M_NBITS))-1)) >> (m_paddr_nbits - PAGE_M_NBITS -10)) ) // local … … 3123 3150 assert(write_hit && "Write on miss ignores data"); 3124 3151 r_dcache_fsm = DCACHE_TLB1_LL_WAIT; 3125 m_cpt_ins_tlb_write_et++; 3152 m_cpt_dcache_data_write++; 3153 m_cpt_data_tlb_update_acc++; 3154 m_cost_data_tlb_update_acc_frz++; 3126 3155 } 3127 3156 } … … 3140 3169 assert(write_hit && "Write on miss ignores data"); 3141 3170 r_dcache_fsm = DCACHE_TLB1_LL_WAIT; 3142 m_cpt_ins_tlb_write_et++; 3171 m_cpt_dcache_data_write++; 3172 m_cpt_data_tlb_update_acc++; 3173 m_cost_data_tlb_update_acc_frz++; 3143 3174 } 3144 3175 } … … 3156 3187 case DCACHE_TLB1_LL_WAIT: 3157 3188 { 3189 if ( dreq.valid ) m_cost_data_tlb_miss_frz++; 3190 m_cost_data_tlb_update_acc_frz++; 3158 3191 // external cache invalidate request 3159 3192 if ( r_tgt_dcache_req ) … … 3161 3194 r_dcache_fsm = DCACHE_CC_CHECK; 3162 3195 r_dcache_fsm_save = r_dcache_fsm; 3163 m_cost_data_waste_wait_frz++;3164 3196 break; 3165 3197 } … … 3205 3237 r_dcache_inval_tlb_rsp = false; 3206 3238 r_dcache_fsm = DCACHE_IDLE; 3207 m_cost_data_tlb_miss_frz++;3208 3239 } 3209 3240 else if ( r_dcache_inval_rsp ) … … 3225 3256 case DCACHE_TLB1_SC_WAIT: 3226 3257 { 3258 if ( dreq.valid ) m_cost_data_tlb_miss_frz++; 3259 m_cost_data_tlb_update_acc_frz++; 3227 3260 // external cache invalidate request 3228 3261 if ( r_tgt_dcache_req ) … … 3230 3263 r_dcache_fsm = DCACHE_CC_CHECK; 3231 3264 r_dcache_fsm_save = r_dcache_fsm; 3232 m_cost_data_waste_wait_frz++;3233 3265 break; 3234 3266 } … … 3260 3292 r_dcache_fsm = DCACHE_IDLE; 3261 3293 if (r_dcache_tlb_sc_fail) r_dcache_tlb_sc_fail = false; 3262 m_cost_data_tlb_miss_frz++;3263 3294 } 3264 3295 else if ( r_dcache_inval_rsp ) … … 3272 3303 r_dcache_tlb_sc_fail = false; 3273 3304 r_dcache_tlb_ll_acc_req = true; 3274 r_dcache_fsm = DCACHE_TLB1_LL_WAIT; 3305 r_dcache_fsm = DCACHE_TLB1_LL_WAIT; 3306 m_cpt_data_tlb_update_acc++; 3275 3307 } 3276 3308 else … … 3285 3317 case DCACHE_TLB1_READ: 3286 3318 { 3287 m_cost_data_tlb_miss_frz++;3319 if ( dreq.valid ) m_cost_data_tlb_miss_frz++; 3288 3320 3289 3321 // external cache invalidate request … … 3292 3324 r_dcache_fsm = DCACHE_CC_CHECK; 3293 3325 r_dcache_fsm_save = r_dcache_fsm; 3294 m_cost_data_waste_wait_frz++;3295 3326 break; 3296 3327 } … … 3328 3359 r_dcache_cleanup_req = true; 3329 3360 r_dcache_cleanup_line = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words) + 2); 3361 m_cpt_cc_cleanup_data++; 3330 3362 r_dcache_fsm = DCACHE_IDLE; 3331 3363 r_dcache_inval_rsp = false; … … 3348 3380 r_dcache_fsm = DCACHE_CC_CHECK; 3349 3381 r_dcache_fsm_save = r_dcache_fsm; 3350 m_cost_data_waste_wait_frz++;3351 3382 break; 3352 3383 } … … 3357 3388 r_dcache_inval_tlb_rsp = false; 3358 3389 r_dcache_fsm = DCACHE_IDLE; 3359 m_cost_data_tlb_miss_frz++;3360 3390 break; 3361 3391 } … … 3374 3404 { 3375 3405 r_dcache_cleanup_req = true; 3376 r_dcache_cleanup_line = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words) + 2); 3406 r_dcache_cleanup_line = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words) + 2); 3407 m_cpt_cc_cleanup_data++; 3377 3408 r_dcache_fsm = DCACHE_IDLE; 3378 3409 r_dcache_inval_rsp = false; … … 3396 3427 r_dcache_cleanup_req = true; 3397 3428 r_dcache_cleanup_line = victim_index; 3429 m_cpt_cc_cleanup_data++; 3398 3430 r_dcache_fsm = DCACHE_TLB_CC_INVAL; 3399 3431 r_dcache_fsm_save = r_dcache_fsm; … … 3403 3435 r_dcache.update(r_dcache_tlb_paddr, way, set, r_dcache_miss_buf); 3404 3436 r_dcache.read(r_dcache_tlb_paddr, &rsp_dtlb_miss); 3437 m_cpt_data_tlb_occup_cache++; 3405 3438 3406 3439 if ( !(rsp_dtlb_miss >> PTE_V_SHIFT) ) // unmapped … … 3433 3466 r_dcache_tlb_ll_dirty_req = true; 3434 3467 r_dcache_fsm = DCACHE_LL_DIRTY_WAIT; 3435 m_cpt_data_tlb_write_dirty++; 3468 m_cpt_dcache_data_write++; 3469 m_cpt_data_tlb_update_dirty++; 3470 m_cost_data_tlb_update_dirty_frz++; 3436 3471 } 3437 3472 else … … 3457 3492 assert(write_hit && "Write on miss ignores data"); 3458 3493 r_dcache_fsm = DCACHE_TLB1_LL_WAIT; 3459 m_cpt_ins_tlb_write_et++; 3494 m_cpt_dcache_data_write++; 3495 m_cpt_data_tlb_update_acc++; 3496 m_cost_data_tlb_update_acc_frz++; 3460 3497 } 3461 3498 } … … 3474 3511 assert(write_hit && "Write on miss ignores data"); 3475 3512 r_dcache_fsm = DCACHE_TLB1_LL_WAIT; 3476 m_cpt_ins_tlb_write_et++; 3513 m_cpt_dcache_data_write++; 3514 m_cpt_data_tlb_update_acc++; 3515 m_cost_data_tlb_update_acc_frz++; 3477 3516 } 3478 3517 } … … 3491 3530 r_dcache_fsm = DCACHE_CC_CHECK; 3492 3531 r_dcache_fsm_save = r_dcache_fsm; 3493 m_cost_data_waste_wait_frz++;3494 3532 break; 3495 3533 } … … 3523 3561 r_dcache_fsm = DCACHE_CC_CHECK; 3524 3562 r_dcache_fsm_save = r_dcache_fsm; 3525 m_cost_data_waste_wait_frz++;3526 3563 break; 3527 3564 } … … 3532 3569 r_dcache_inval_tlb_rsp = false; 3533 3570 r_dcache_fsm = DCACHE_IDLE; 3534 m_cost_data_tlb_miss_frz++;3535 3571 break; 3536 3572 } … … 3571 3607 else 3572 3608 { 3609 m_cpt_data_tlb_hit_dcache++; 3573 3610 if ( (m_srcid_rw >> 4) == ((r_dcache_tlb_paddr.read() & ((1<<(m_paddr_nbits - PAGE_M_NBITS))-1)) >> (m_paddr_nbits - PAGE_M_NBITS -10)) ) // local 3574 3611 { … … 3587 3624 assert(write_hit && "Write on miss ignores data"); 3588 3625 r_dcache_fsm = DCACHE_TLB2_LL_WAIT; 3589 m_cpt_ins_tlb_write_et++; 3626 m_cpt_dcache_data_write++; 3627 m_cpt_data_tlb_update_acc++; 3628 m_cost_data_tlb_update_acc_frz++; 3590 3629 } 3591 3630 } … … 3606 3645 assert(write_hit && "Write on miss ignores data"); 3607 3646 r_dcache_fsm = DCACHE_TLB2_LL_WAIT; 3608 m_cpt_ins_tlb_write_et++; 3647 m_cpt_dcache_data_write++; 3648 m_cpt_data_tlb_update_acc++; 3649 m_cost_data_tlb_update_acc_frz++; 3609 3650 } 3610 3651 } … … 3622 3663 case DCACHE_TLB2_LL_WAIT: 3623 3664 { 3665 if ( dreq.valid ) m_cost_data_tlb_miss_frz++; 3666 m_cost_data_tlb_update_acc_frz++; 3667 3624 3668 // external cache invalidate request 3625 3669 if ( r_tgt_dcache_req ) … … 3627 3671 r_dcache_fsm = DCACHE_CC_CHECK; 3628 3672 r_dcache_fsm_save = r_dcache_fsm; 3629 m_cost_data_waste_wait_frz++;3630 3673 break; 3631 3674 } … … 3671 3714 r_dcache_inval_tlb_rsp = false; 3672 3715 r_dcache_fsm = DCACHE_IDLE; 3673 m_cost_data_tlb_miss_frz++;3674 3716 } 3675 3717 else if ( r_dcache_inval_rsp ) … … 3691 3733 case DCACHE_TLB2_SC_WAIT: 3692 3734 { 3735 if ( dreq.valid ) m_cost_data_tlb_miss_frz++; 3736 m_cost_data_tlb_update_acc_frz++; 3693 3737 // external cache invalidate request 3694 3738 if ( r_tgt_dcache_req ) … … 3696 3740 r_dcache_fsm = DCACHE_CC_CHECK; 3697 3741 r_dcache_fsm_save = r_dcache_fsm; 3698 m_cost_data_waste_wait_frz++;3699 3742 break; 3700 3743 } … … 3726 3769 if (r_dcache_tlb_sc_fail) r_dcache_tlb_sc_fail = false; 3727 3770 r_dcache_fsm = DCACHE_IDLE; 3728 m_cost_data_tlb_miss_frz++;3729 3771 } 3730 3772 else if ( r_dcache_inval_rsp ) … … 3738 3780 r_dcache_tlb_ll_acc_req = true; 3739 3781 r_dcache_tlb_sc_fail = false; 3740 r_dcache_fsm = DCACHE_TLB2_LL_WAIT; 3782 r_dcache_fsm = DCACHE_TLB2_LL_WAIT; 3783 m_cpt_data_tlb_update_acc++; 3741 3784 } 3742 3785 else … … 3758 3801 r_dcache_fsm = DCACHE_CC_CHECK; 3759 3802 r_dcache_fsm_save = r_dcache_fsm; 3760 m_cost_data_waste_wait_frz++;3761 3803 break; 3762 3804 } … … 3794 3836 r_dcache_cleanup_req = true; 3795 3837 r_dcache_cleanup_line = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words) + 2); 3838 m_cpt_cc_cleanup_data++; 3796 3839 r_dcache_fsm = DCACHE_IDLE; 3797 3840 r_dcache_inval_rsp = false; … … 3814 3857 r_dcache_fsm = DCACHE_CC_CHECK; 3815 3858 r_dcache_fsm_save = r_dcache_fsm; 3816 m_cost_data_waste_wait_frz++;3817 3859 break; 3818 3860 } … … 3823 3865 r_dcache_inval_tlb_rsp = false; 3824 3866 r_dcache_fsm = DCACHE_IDLE; 3825 m_cost_data_tlb_miss_frz++;3826 3867 break; 3827 3868 } … … 3842 3883 r_dcache_cleanup_req = true; 3843 3884 r_dcache_cleanup_line = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words) + 2); 3885 m_cpt_cc_cleanup_data++; 3844 3886 r_dcache_fsm = DCACHE_IDLE; 3845 3887 r_dcache_inval_rsp = false; … … 3863 3905 r_dcache_cleanup_req = true; 3864 3906 r_dcache_cleanup_line = victim_index; 3907 m_cpt_cc_cleanup_data++; 3865 3908 r_dcache_fsm = DCACHE_TLB_CC_INVAL; 3866 3909 r_dcache_fsm_save = r_dcache_fsm; … … 3870 3913 r_dcache.update(r_dcache_tlb_paddr, way, set, r_dcache_miss_buf); 3871 3914 r_dcache.read(r_dcache_tlb_paddr, &rsp_dtlb_miss); 3915 m_cpt_data_tlb_occup_cache++; 3872 3916 3873 3917 bool tlb_hit_ppn = r_dcache.read(r_dcache_tlb_paddr.read()+4, &tlb_data_ppn); … … 3911 3955 assert(write_hit && "Write on miss ignores data"); 3912 3956 r_dcache_fsm = DCACHE_TLB2_LL_WAIT; 3913 m_cpt_ins_tlb_write_et++; 3957 m_cpt_dcache_data_write++; 3958 m_cpt_data_tlb_update_acc++; 3959 m_cost_data_tlb_update_acc_frz++; 3914 3960 } 3915 3961 } … … 3930 3976 assert(write_hit && "Write on miss ignores data"); 3931 3977 r_dcache_fsm = DCACHE_TLB2_LL_WAIT; 3932 m_cpt_ins_tlb_write_et++; 3978 m_cpt_dcache_data_write++; 3979 m_cpt_data_tlb_update_acc++; 3980 m_cost_data_tlb_update_acc_frz++; 3933 3981 } 3934 3982 } … … 3947 3995 r_dcache_fsm = DCACHE_CC_CHECK; 3948 3996 r_dcache_fsm_save = r_dcache_fsm; 3949 m_cost_data_waste_wait_frz++;3950 3997 break; 3951 3998 } … … 4026 4073 r_dcache_fsm = DCACHE_CC_CHECK; 4027 4074 r_dcache_fsm_save = r_dcache_fsm; 4028 m_cost_data_waste_wait_frz++;4029 4075 break; 4030 4076 } … … 4048 4094 r_dcache_cleanup_req = true; 4049 4095 r_dcache_cleanup_line = victim_index; 4096 m_cpt_cc_cleanup_data++; 4050 4097 r_dcache_way = way + ((set+1)/m_dcache_sets); 4051 4098 r_dcache_set = (set+1) % m_dcache_sets; … … 4099 4146 r_dcache_fsm = DCACHE_CC_CHECK; 4100 4147 r_dcache_fsm_save = r_dcache_fsm; 4101 m_cost_data_waste_wait_frz++;4102 4148 break; 4103 4149 } … … 4126 4172 r_dcache_cleanup_req = r_dcache.inval(dpaddr, &way, &set); 4127 4173 r_dcache_cleanup_line = dpaddr >> (uint32_log2(m_dcache_words)+2); 4174 m_cpt_cc_cleanup_data++; 4128 4175 4129 4176 if ( r_dcache_in_itlb[way*m_dcache_sets+set] || r_dcache_in_dtlb[way*m_dcache_sets+set] ) … … 4156 4203 r_dcache_fsm = DCACHE_CC_CHECK; 4157 4204 r_dcache_fsm_save = r_dcache_fsm; 4158 m_cost_data_waste_wait_frz++;4159 4205 break; 4160 4206 } … … 4168 4214 r_dcache_cleanup_req = r_dcache.inval(dpaddr, &way, &set); 4169 4215 r_dcache_cleanup_line = dpaddr >> (uint32_log2(m_dcache_words)+2); 4216 m_cpt_cc_cleanup_data++; 4170 4217 4171 4218 if ( r_dcache_in_itlb[way*m_dcache_sets+set] || r_dcache_in_dtlb[way*m_dcache_sets+set] ) … … 4210 4257 r_dcache_fsm = DCACHE_CC_CHECK; 4211 4258 r_dcache_fsm_save = r_dcache_fsm; 4212 m_cost_data_waste_wait_frz++;4213 4259 break; 4214 4260 } … … 4232 4278 r_dcache_cleanup_req = true; 4233 4279 r_dcache_cleanup_line = r_dcache_paddr_save.read() >> (uint32_log2(m_dcache_words) + 2); 4280 m_cpt_cc_cleanup_data++; 4234 4281 r_dcache_fsm = DCACHE_IDLE; 4235 4282 r_dcache_inval_tlb_rsp = false; … … 4243 4290 r_dcache_cleanup_req = true; 4244 4291 r_dcache_cleanup_line = r_dcache_paddr_save.read() >> (uint32_log2(m_dcache_words) + 2); 4292 m_cpt_cc_cleanup_data++; 4245 4293 r_dcache_fsm = DCACHE_IDLE; 4246 4294 r_dcache_inval_rsp = false; … … 4262 4310 r_dcache_fsm = DCACHE_CC_CHECK; 4263 4311 r_dcache_fsm_save = r_dcache_fsm; 4264 m_cost_data_waste_wait_frz++;4265 4312 break; 4266 4313 } … … 4271 4318 r_dcache_cleanup_req = true; 4272 4319 r_dcache_cleanup_line = r_dcache_paddr_save.read() >> (uint32_log2(m_dcache_words) + 2); 4320 m_cpt_cc_cleanup_data++; 4273 4321 r_dcache_inval_tlb_rsp = false; 4274 4322 r_dcache_inval_rsp = false; 4275 4323 r_dcache_fsm = DCACHE_IDLE; 4276 m_cost_data_tlb_miss_frz++;4277 4324 break; 4278 4325 } … … 4284 4331 size_t set = 0; 4285 4332 4286 m_cpt_dcache_data_write++;4287 m_cpt_dcache_dir_write++;4288 4289 4333 // Using tlb entry is in the invalidated cache line 4290 4334 if ( r_dcache_inval_rsp ) … … 4292 4336 r_dcache_cleanup_req = true; 4293 4337 r_dcache_cleanup_line = r_dcache_paddr_save.read() >> (uint32_log2(m_dcache_words) + 2); 4338 m_cpt_cc_cleanup_data++; 4294 4339 r_dcache_fsm = DCACHE_IDLE; 4295 4340 r_dcache_inval_rsp = false; … … 4313 4358 r_dcache_cleanup_req = true; 4314 4359 r_dcache_cleanup_line = victim_index; 4360 m_cpt_cc_cleanup_data++; 4315 4361 if ( r_dcache_in_itlb[m_dcache_sets*way+set] || r_dcache_in_dtlb[m_dcache_sets*way+set] ) 4316 4362 { … … 4320 4366 } 4321 4367 } 4322 4368 m_cpt_dcache_dir_write++; 4369 m_cpt_dcache_data_write++; 4323 4370 r_dcache.update(r_dcache_paddr_save.read(), way, set, r_dcache_miss_buf); 4324 4371 r_dcache_fsm = DCACHE_IDLE; … … 4336 4383 r_dcache_fsm = DCACHE_CC_CHECK; 4337 4384 r_dcache_fsm_save = r_dcache_fsm; 4338 m_cost_data_waste_wait_frz++;4339 4385 break; 4340 4386 } … … 4364 4410 r_dcache_cleanup_req = r_dcache.inval(r_dcache_paddr_save, &way, &set); 4365 4411 r_dcache_cleanup_line = r_dcache_paddr_save.read() >> (uint32_log2(m_dcache_words)+2); 4412 m_cpt_cc_cleanup_data++; 4366 4413 4367 4414 if ( r_dcache_in_itlb[way*m_dcache_sets+set] || r_dcache_in_dtlb[way*m_dcache_sets+set] ) … … 4392 4439 { 4393 4440 m_cost_write_frz++; 4441 m_cpt_dcache_data_write++; 4394 4442 size_t way = 0; 4395 4443 size_t set = 0; … … 4419 4467 if ( !r_dcache_dirty_save && (r_mmu_mode.read() & DATA_TLB_MASK) ) 4420 4468 { 4469 m_cpt_data_tlb_update_dirty++; 4470 m_cost_data_tlb_update_dirty_frz++; 4421 4471 if ( dcache_tlb.getpagesize(r_dcache_tlb_way_save, r_dcache_tlb_set_save) ) // 2M page size, one level page table 4422 { 4472 { 4423 4473 r_dcache_pte_update = dcache_tlb.getpte(r_dcache_tlb_way_save, r_dcache_tlb_set_save) | PTE_D_MASK; 4424 4474 r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2); 4425 4475 r_dcache_tlb_ll_dirty_req = true; 4426 r_dcache_fsm = DCACHE_LL_DIRTY_WAIT; 4427 m_cpt_data_tlb_write_dirty++; 4476 r_dcache_fsm = DCACHE_LL_DIRTY_WAIT; 4428 4477 } 4429 4478 else … … 4435 4484 r_dcache_tlb_ll_dirty_req = true; 4436 4485 r_dcache_fsm = DCACHE_LL_DIRTY_WAIT; 4437 m_cpt_data_tlb_write_dirty++;4438 4486 } 4439 4487 else … … 4457 4505 case DCACHE_WRITE_DIRTY: 4458 4506 { 4459 m_cost_data_tlb_miss_frz++;4507 m_cost_data_tlb_update_dirty_frz++; 4460 4508 4461 4509 // external cache invalidate request … … 4464 4512 r_dcache_fsm = DCACHE_CC_CHECK; 4465 4513 r_dcache_fsm_save = r_dcache_fsm; 4466 m_cost_data_waste_wait_frz++;4467 4514 break; 4468 4515 } … … 4482 4529 } 4483 4530 4531 m_cpt_dcache_data_write++; 4484 4532 r_dcache.write(r_dcache_tlb_paddr, r_dcache_pte_update); 4485 4533 dcache_tlb.setdirty(r_dcache_tlb_way_save, r_dcache_tlb_set_save); … … 4502 4550 case DCACHE_ITLB_READ: 4503 4551 { 4504 m_cost_data_waste_wait_frz++;4552 if ( dreq.valid ) m_cost_ins_tlb_occup_cache_frz++; 4505 4553 4506 4554 // external cache invalidate request … … 4509 4557 r_dcache_fsm = DCACHE_CC_CHECK; 4510 4558 r_dcache_fsm_save = r_dcache_fsm; 4511 m_cost_data_waste_wait_frz++;4512 4559 break; 4513 4560 } … … 4531 4578 r_dcache_cleanup_req = true; 4532 4579 r_dcache_cleanup_line = r_icache_paddr_save.read() >> (uint32_log2(m_dcache_words) + 2); 4580 m_cpt_cc_cleanup_data++; 4533 4581 r_dcache_fsm = DCACHE_IDLE; 4534 4582 r_dcache_inval_rsp = false; … … 4543 4591 case DCACHE_ITLB_UPDT: 4544 4592 { 4545 m_cost_data_waste_wait_frz++;4593 if ( dreq.valid ) m_cost_ins_tlb_occup_cache_frz++; 4546 4594 4547 4595 // external cache invalidate request … … 4550 4598 r_dcache_fsm = DCACHE_CC_CHECK; 4551 4599 r_dcache_fsm_save = r_dcache_fsm; 4552 m_cost_data_waste_wait_frz++;4553 4600 break; 4554 4601 } … … 4567 4614 r_dcache_cleanup_req = true; 4568 4615 r_dcache_cleanup_line = r_icache_paddr_save.read() >> (uint32_log2(m_dcache_words) + 2); 4616 m_cpt_cc_cleanup_data++; 4569 4617 r_dcache_fsm = DCACHE_IDLE; 4570 4618 r_dcache_inval_rsp = false; … … 4588 4636 r_dcache_cleanup_req = true; 4589 4637 r_dcache_cleanup_line = victim_index; 4638 m_cpt_cc_cleanup_data++; 4590 4639 if ( r_dcache_in_itlb[m_dcache_sets*way+set] || r_dcache_in_dtlb[m_dcache_sets*way+set] ) 4591 4640 { … … 4600 4649 r_dcache.setinbit(r_icache_paddr_save, r_dcache_in_itlb, true); 4601 4650 bool itlb_hit_dcache = r_dcache.read(r_icache_paddr_save, &rsp_itlb_miss); 4602 4651 m_cpt_ins_tlb_occup_cache++; 4652 4603 4653 if ( r_itlb_k_read_dcache && itlb_hit_dcache ) 4604 4654 { … … 4619 4669 case DCACHE_ITLB_LL_WAIT: 4620 4670 { 4671 if ( dreq.valid ) m_cost_ins_tlb_occup_cache_frz++; 4621 4672 // external cache invalidate request 4622 4673 if ( r_tgt_dcache_req ) … … 4624 4675 r_dcache_fsm = DCACHE_CC_CHECK; 4625 4676 r_dcache_fsm_save = r_dcache_fsm; 4626 m_cost_data_waste_wait_frz++;4627 4677 break; 4628 4678 } … … 4651 4701 r_dcache_inval_rsp = false; 4652 4702 r_dcache_fsm = DCACHE_IDLE; 4653 m_cost_data_tlb_miss_frz++;4654 4703 } 4655 4704 else … … 4666 4715 case DCACHE_ITLB_SC_WAIT: 4667 4716 { 4717 if ( dreq.valid ) m_cost_ins_tlb_occup_cache_frz++; 4668 4718 // external cache invalidate request 4669 4719 if ( r_tgt_dcache_req ) … … 4671 4721 r_dcache_fsm = DCACHE_CC_CHECK; 4672 4722 r_dcache_fsm_save = r_dcache_fsm; 4673 m_cost_data_waste_wait_frz++;4674 4723 break; 4675 4724 } … … 4692 4741 r_dcache_fsm = DCACHE_IDLE; 4693 4742 if (r_dcache_tlb_sc_fail) r_dcache_tlb_sc_fail = false; 4694 m_cost_data_tlb_miss_frz++;4695 4743 } 4696 4744 else if ( r_dcache_tlb_sc_fail ) … … 4712 4760 case DCACHE_CC_CHECK: // read directory in case of invalidate or update request 4713 4761 { 4714 if ( dreq.valid ) m_cost_data_waste_wait_frz++;4715 4716 4762 m_cpt_dcache_dir_read += m_dcache_ways; 4717 4763 m_cpt_dcache_data_read += m_dcache_ways; 4764 4765 /* activity counter */ 4766 if ( (( r_dcache_fsm_save == DCACHE_BIS ) ||( r_dcache_fsm_save == DCACHE_MISS_WAIT ) || ( r_dcache_fsm_save == DCACHE_MISS_UPDT ) ) && ( dreq.valid ) ) 4767 { 4768 m_cost_data_miss_frz++; 4769 } 4770 if( (( r_dcache_fsm_save == DCACHE_DTLB1_READ_CACHE ) || ( r_dcache_fsm_save == DCACHE_DTLB2_READ_CACHE ) || 4771 ( r_dcache_fsm_save == DCACHE_TLB1_READ ) || ( r_dcache_fsm_save == DCACHE_TLB2_READ ) || 4772 ( r_dcache_fsm_save == DCACHE_TLB1_LL_WAIT ) || ( r_dcache_fsm_save == DCACHE_TLB2_LL_WAIT ) || 4773 ( r_dcache_fsm_save == DCACHE_TLB1_SC_WAIT ) || ( r_dcache_fsm_save == DCACHE_TLB2_SC_WAIT ) || 4774 ( r_dcache_fsm_save == DCACHE_TLB1_READ_UPDT ) || ( r_dcache_fsm_save == DCACHE_TLB2_READ_UPDT ) || 4775 ( r_dcache_fsm_save == DCACHE_TLB1_UPDT ) || ( r_dcache_fsm_save == DCACHE_TLB2_UPDT )) && (dreq.valid) ) 4776 { 4777 m_cost_data_tlb_miss_frz++; 4778 } 4718 4779 4719 4780 // DCACHE_TLB1_LL_WAIT DCACHE_TLB1_SC_WAIT DCACHE_LL_DIRTY_WAIT DCACHE_WRITE_DIRTY DCACHE_ITLB_LL_WAIT DCACHE_ITLB_SC_WAIT … … 4792 4853 case DCACHE_CC_UPDT: // update directory and data cache 4793 4854 { 4794 if ( dreq.valid ) m_cost_data_waste_wait_frz++; 4855 /* activity counter */ 4856 if ( (( r_dcache_fsm_save == DCACHE_BIS ) ||( r_dcache_fsm_save == DCACHE_MISS_WAIT ) || ( r_dcache_fsm_save == DCACHE_MISS_UPDT ) ) && ( dreq.valid ) ) 4857 { 4858 m_cost_data_miss_frz++; 4859 } 4860 if( (( r_dcache_fsm_save == DCACHE_DTLB1_READ_CACHE ) || ( r_dcache_fsm_save == DCACHE_DTLB2_READ_CACHE ) || 4861 ( r_dcache_fsm_save == DCACHE_TLB1_READ ) || ( r_dcache_fsm_save == DCACHE_TLB2_READ ) || 4862 ( r_dcache_fsm_save == DCACHE_TLB1_LL_WAIT ) || ( r_dcache_fsm_save == DCACHE_TLB2_LL_WAIT ) || 4863 ( r_dcache_fsm_save == DCACHE_TLB1_SC_WAIT ) || ( r_dcache_fsm_save == DCACHE_TLB2_SC_WAIT ) || 4864 ( r_dcache_fsm_save == DCACHE_TLB1_READ_UPDT ) || ( r_dcache_fsm_save == DCACHE_TLB2_READ_UPDT ) || 4865 ( r_dcache_fsm_save == DCACHE_TLB1_UPDT ) || ( r_dcache_fsm_save == DCACHE_TLB2_UPDT )) && (dreq.valid) ) 4866 { 4867 m_cost_data_tlb_miss_frz++; 4868 } 4795 4869 4796 4870 m_cpt_dcache_dir_write++; … … 4810 4884 case DCACHE_CC_INVAL: // invalidate a cache line 4811 4885 { 4812 if ( dreq.valid ) m_cost_data_waste_wait_frz++; 4886 /* activity counter */ 4887 if ( (( r_dcache_fsm_save == DCACHE_BIS ) ||( r_dcache_fsm_save == DCACHE_MISS_WAIT ) || ( r_dcache_fsm_save == DCACHE_MISS_UPDT ) ) && ( dreq.valid ) ) 4888 { 4889 m_cost_data_miss_frz++; 4890 } 4891 if( (( r_dcache_fsm_save == DCACHE_DTLB1_READ_CACHE ) || ( r_dcache_fsm_save == DCACHE_DTLB2_READ_CACHE ) || 4892 ( r_dcache_fsm_save == DCACHE_TLB1_READ ) || ( r_dcache_fsm_save == DCACHE_TLB2_READ ) || 4893 ( r_dcache_fsm_save == DCACHE_TLB1_LL_WAIT ) || ( r_dcache_fsm_save == DCACHE_TLB2_LL_WAIT ) || 4894 ( r_dcache_fsm_save == DCACHE_TLB1_SC_WAIT ) || ( r_dcache_fsm_save == DCACHE_TLB2_SC_WAIT ) || 4895 ( r_dcache_fsm_save == DCACHE_TLB1_READ_UPDT ) || ( r_dcache_fsm_save == DCACHE_TLB2_READ_UPDT ) || 4896 ( r_dcache_fsm_save == DCACHE_TLB1_UPDT ) || ( r_dcache_fsm_save == DCACHE_TLB2_UPDT )) && (dreq.valid) ) 4897 { 4898 m_cost_data_tlb_miss_frz++; 4899 } 4813 4900 4814 4901 r_tgt_dcache_rsp = r_dcache.inval(r_tgt_addr.read()); … … 4820 4907 case DCACHE_CC_NOP: // no external hit 4821 4908 { 4822 if ( dreq.valid ) m_cost_data_waste_wait_frz++; 4909 /* activity counter */ 4910 if ( (( r_dcache_fsm_save == DCACHE_BIS ) ||( r_dcache_fsm_save == DCACHE_MISS_WAIT ) || ( r_dcache_fsm_save == DCACHE_MISS_UPDT ) ) && ( dreq.valid ) ) 4911 { 4912 m_cost_data_miss_frz++; 4913 } 4914 if( (( r_dcache_fsm_save == DCACHE_DTLB1_READ_CACHE ) || ( r_dcache_fsm_save == DCACHE_DTLB2_READ_CACHE ) || 4915 ( r_dcache_fsm_save == DCACHE_TLB1_READ ) || ( r_dcache_fsm_save == DCACHE_TLB2_READ ) || 4916 ( r_dcache_fsm_save == DCACHE_TLB1_LL_WAIT ) || ( r_dcache_fsm_save == DCACHE_TLB2_LL_WAIT ) || 4917 ( r_dcache_fsm_save == DCACHE_TLB1_SC_WAIT ) || ( r_dcache_fsm_save == DCACHE_TLB2_SC_WAIT ) || 4918 ( r_dcache_fsm_save == DCACHE_TLB1_READ_UPDT ) || ( r_dcache_fsm_save == DCACHE_TLB2_READ_UPDT ) || 4919 ( r_dcache_fsm_save == DCACHE_TLB1_UPDT ) || ( r_dcache_fsm_save == DCACHE_TLB2_UPDT )) && (dreq.valid) ) 4920 { 4921 m_cost_data_tlb_miss_frz++; 4922 } 4823 4923 4824 4924 r_tgt_dcache_req = false; … … 4838 4938 case DCACHE_TLB_CC_INVAL: 4839 4939 { 4840 if ( dreq.valid ) m_cost_data_waste_wait_frz++; 4940 /* activity counter */ 4941 if ( (( r_dcache_fsm_save == DCACHE_BIS ) ||( r_dcache_fsm_save == DCACHE_MISS_WAIT ) || ( r_dcache_fsm_save == DCACHE_MISS_UPDT ) ) && ( dreq.valid ) ) 4942 { 4943 m_cost_data_miss_frz++; 4944 } 4945 if( (( r_dcache_fsm_save == DCACHE_DTLB1_READ_CACHE ) || ( r_dcache_fsm_save == DCACHE_DTLB2_READ_CACHE ) || 4946 ( r_dcache_fsm_save == DCACHE_TLB1_READ ) || ( r_dcache_fsm_save == DCACHE_TLB2_READ ) || 4947 ( r_dcache_fsm_save == DCACHE_TLB1_LL_WAIT ) || ( r_dcache_fsm_save == DCACHE_TLB2_LL_WAIT ) || 4948 ( r_dcache_fsm_save == DCACHE_TLB1_SC_WAIT ) || ( r_dcache_fsm_save == DCACHE_TLB2_SC_WAIT ) || 4949 ( r_dcache_fsm_save == DCACHE_TLB1_READ_UPDT ) || ( r_dcache_fsm_save == DCACHE_TLB2_READ_UPDT ) || 4950 ( r_dcache_fsm_save == DCACHE_TLB1_UPDT ) || ( r_dcache_fsm_save == DCACHE_TLB2_UPDT )) && (dreq.valid) ) 4951 { 4952 m_cost_data_tlb_miss_frz++; 4953 } 4841 4954 4842 4955 if ( r_dcache_itlb_inval_req || r_dcache_dtlb_inval_req ) break; … … 4878 4991 case DCACHE_ITLB_CLEANUP: 4879 4992 { 4880 if ( dreq.valid ) m_cost_data_ waste_wait_frz++;4993 if ( dreq.valid ) m_cost_data_miss_frz++; 4881 4994 4882 4995 r_dcache.setinbit(((paddr_t)r_dcache_itlb_cleanup_line.read()*m_dcache_words*2), r_dcache_in_itlb, false); … … 4973 5086 m_cpt_frz_cycles++; 4974 5087 } 4975 5088 if ( dreq.valid && !drsp.valid ) 5089 { 5090 m_cpt_dcache_frz_cycles++; 5091 } 5092 for (size_t way = 0; way < m_dcache_ways; way++ ) 5093 { 5094 for (size_t set = 0; set < m_dcache_sets; set++ ) 5095 { 5096 if (r_dcache_in_itlb[way*m_dcache_sets+set] || r_dcache_in_dtlb[way*m_dcache_sets+set]) 5097 m_cpt_tlb_occup_dcache++; 5098 } 5099 } 4976 5100 //////////////////////////////////////////////////////////////////////////// 4977 5101 // VCI_CMD FSM … … 5006 5130 { 5007 5131 r_vci_cmd_fsm = CMD_INS_CLEANUP; 5132 m_cpt_icleanup_transaction++; 5008 5133 } 5009 5134 else if (r_dcache_cleanup_req) 5010 5135 { 5011 5136 r_vci_cmd_fsm = CMD_DATA_CLEANUP; 5137 m_cpt_dcleanup_transaction++; 5012 5138 } 5013 5139 else if (r_dcache_itlb_read_req) … … 5019 5145 { 5020 5146 r_vci_cmd_fsm = CMD_ITLB_ACC_LL; 5021 m_cpt_itlb_ write_transaction++;5147 m_cpt_itlb_ll_transaction++; 5022 5148 } 5023 5149 else if (r_dcache_itlb_sc_acc_req) 5024 5150 { 5025 5151 r_vci_cmd_fsm = CMD_ITLB_ACC_SC; 5026 m_cpt_itlb_ write_transaction++;5152 m_cpt_itlb_sc_transaction++; 5027 5153 } 5028 5154 else if (r_icache_miss_req) … … 5034 5160 { 5035 5161 r_vci_cmd_fsm = CMD_INS_UNC; 5036 m_cpt_i miss_transaction++;5162 m_cpt_icache_unc_transaction++; 5037 5163 } 5038 5164 else if (r_dcache_tlb_read_req) … … 5044 5170 { 5045 5171 r_vci_cmd_fsm = CMD_DTLB_ACC_LL; 5046 m_cpt_dtlb_ write_transaction++;5172 m_cpt_dtlb_ll_transaction++; 5047 5173 } 5048 5174 else if (r_dcache_tlb_sc_acc_req) 5049 5175 { 5050 5176 r_vci_cmd_fsm = CMD_DTLB_ACC_SC; 5051 m_cpt_dtlb_ write_transaction++;5177 m_cpt_dtlb_sc_transaction++; 5052 5178 } 5053 5179 else if (r_dcache_tlb_ll_dirty_req) 5054 5180 { 5055 5181 r_vci_cmd_fsm = CMD_DTLB_DIRTY_LL; 5056 m_cpt_dtlb_ write_transaction++;5182 m_cpt_dtlb_ll_dirty_transaction++; 5057 5183 } 5058 5184 else if (r_dcache_tlb_sc_dirty_req) 5059 5185 { 5060 5186 r_vci_cmd_fsm = CMD_DTLB_DIRTY_SC; 5061 m_cpt_dtlb_ write_transaction++;5187 m_cpt_dtlb_sc_dirty_transaction++; 5062 5188 } 5063 5189 else if (r_dcache_write_req) … … 5213 5339 5214 5340 case RSP_ITLB_ACC_LL: 5341 m_cost_itlb_ll_transaction++; 5215 5342 if ( ! p_vci_ini_rw.rspval.read() ) 5216 5343 break; … … 5232 5359 5233 5360 case RSP_ITLB_ACC_SC: 5361 m_cost_itlb_sc_transaction++; 5234 5362 if ( ! p_vci_ini_rw.rspval.read() ) 5235 5363 break; … … 5276 5404 5277 5405 case RSP_INS_UNC: 5278 m_cost_i miss_transaction++;5406 m_cost_icache_unc_transaction++; 5279 5407 if ( ! p_vci_ini_rw.rspval.read() ) 5280 5408 break; … … 5318 5446 5319 5447 case RSP_DTLB_ACC_LL: 5448 m_cost_dtlb_ll_transaction++; 5320 5449 if ( ! p_vci_ini_rw.rspval.read() ) 5321 5450 break; … … 5337 5466 5338 5467 case RSP_DTLB_ACC_SC: 5468 m_cost_dtlb_sc_transaction++; 5339 5469 if ( ! p_vci_ini_rw.rspval.read() ) 5340 5470 break; … … 5357 5487 5358 5488 case RSP_DTLB_DIRTY_LL: 5489 m_cost_dtlb_ll_dirty_transaction++; 5359 5490 if ( ! p_vci_ini_rw.rspval.read() ) 5360 5491 break; … … 5376 5507 5377 5508 case RSP_DTLB_DIRTY_SC: 5509 m_cost_dtlb_sc_dirty_transaction++; 5378 5510 if ( ! p_vci_ini_rw.rspval.read() ) 5379 5511 break; … … 5457 5589 case RSP_INS_CLEANUP: 5458 5590 case RSP_DATA_CLEANUP: 5591 if ( r_vci_rsp_fsm == RSP_INS_CLEANUP ) 5592 { 5593 m_cost_icleanup_transaction++; 5594 } 5595 else 5596 { 5597 m_cost_dcleanup_transaction++; 5598 } 5599 5459 5600 if ( ! p_vci_ini_c.rspval.read() ) 5460 5601 break;
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