Index: trunk/modules/vci_cc_vcache_wrapper2_v1/caba/source/include/vci_cc_vcache_wrapper2_v1.h
===================================================================
--- trunk/modules/vci_cc_vcache_wrapper2_v1/caba/source/include/vci_cc_vcache_wrapper2_v1.h	(revision 37)
+++ trunk/modules/vci_cc_vcache_wrapper2_v1/caba/source/include/vci_cc_vcache_wrapper2_v1.h	(revision 48)
@@ -440,5 +440,6 @@
 
     uint32_t m_cpt_frz_cycles;	            // number of cycles where the cpu is frozen
-    uint32_t m_cpt_total_cycles;	        // total number of cycles 
+    uint32_t m_cpt_total_cycles;	        // total number of cycles
+    uint32_t m_cpt_dcache_frz_cycles;       // number of cycles where the data cache is frozen    
 
     // Cache activity counters
@@ -460,4 +461,5 @@
     uint32_t m_cpt_unc_transaction;         // number of VCI uncached read transactions
     uint32_t m_cpt_write_transaction;       // number of VCI write transactions
+    uint32_t m_cpt_icache_unc_transaction;
 
     uint32_t m_cost_imiss_transaction;      // cumulated duration for VCI IMISS transactions
@@ -465,4 +467,5 @@
     uint32_t m_cost_unc_transaction;        // cumulated duration for VCI UNC transactions
     uint32_t m_cost_write_transaction;      // cumulated duration for VCI WRITE transactions
+    uint32_t m_cost_icache_unc_transaction; // cumulated duration for VCI IUNC transactions    
     uint32_t m_length_write_transaction;    // cumulated length for VCI WRITE transactions
 
@@ -470,36 +473,45 @@
     uint32_t m_cpt_ins_tlb_read;            // number of instruction tlb read
     uint32_t m_cpt_ins_tlb_miss;            // number of instruction tlb miss
-    uint32_t m_cpt_ins_tlb_write_et;        // number of instruction tlb write ET
-
+    uint32_t m_cpt_ins_tlb_update_acc;      // number of instruction tlb update acc
     uint32_t m_cpt_data_tlb_read;           // number of data tlb read
     uint32_t m_cpt_data_tlb_miss;           // number of data tlb miss
-    uint32_t m_cpt_data_tlb_write_et;       // number of data tlb write ET
-    uint32_t m_cpt_data_tlb_write_dirty;    // number of data tlb write dirty
+    uint32_t m_cpt_data_tlb_update_acc;     // number of data tlb update acc
+    uint32_t m_cpt_data_tlb_update_dirty;   // number of data tlb update dirty
+    uint32_t m_cpt_ins_tlb_hit_dcache;      // number of instruction tlb hit in data cache
+    uint32_t m_cpt_data_tlb_hit_dcache;     // number of data tlb hit in data cache
+    uint32_t m_cpt_ins_tlb_occup_cache;     // number of instruction tlb occupy data cache line 
+    uint32_t m_cpt_data_tlb_occup_cache;    // number of data tlb occupy data cache line
+    uint32_t m_cpt_tlb_occupy_dcache;
     
     uint32_t m_cost_ins_tlb_miss_frz;       // number of frozen cycles related to instruction tlb miss
     uint32_t m_cost_data_tlb_miss_frz;      // number of frozen cycles related to data tlb miss
-
-    uint32_t m_cost_ins_waste_wait_frz;     // number of frozen cycles related to ins wait coherence operate 
-    uint32_t m_cost_ins_tlb_sw_frz;         // number of frozen cycles related to ins context switch
-    uint32_t m_cost_ins_cache_flush_frz;    // number of frozen cycles related to ins cache flush 
-
-    uint32_t m_cpt_ins_tlb_cleanup;         // number of ins tlb cleanup 
-    uint32_t m_cost_data_waste_wait_frz;    // number of frozen cycles related to data wait coherence operate
-    uint32_t m_cost_data_tlb_sw_frz;        // number of frozen cycles related to data context switch
-    uint32_t m_cost_data_cache_flush_frz;   // number of frozen cycles related to data cache flush
-
-    uint32_t m_cpt_itlbmiss_transaction;    // number of itlb miss transactions
-    uint32_t m_cpt_itlb_write_transaction;  // number of itlb write ET transactions
-    uint32_t m_cpt_dtlbmiss_transaction;    // number of dtlb miss transactions
-    uint32_t m_cpt_dtlb_write_transaction;  // number of dtlb write ET and dirty transactions
-
-    uint32_t m_cost_itlbmiss_transaction;   // cumulated duration for VCI instruction TLB miss transactions
-    uint32_t m_cost_itlb_write_transaction; // cumulated duration for VCI instruction TLB write ET transactions
-    uint32_t m_cost_dtlbmiss_transaction;   // cumulated duration for VCI data TLB miss transactions
-    uint32_t m_cost_dtlb_write_transaction; // cumulated duration for VCI data TLB write transactions
-
-    uint32_t m_cpt_cc_update;               // number of coherence update packets 
-    uint32_t m_cpt_cc_inval;                // number of coherence inval packets
-    uint32_t m_cpt_cc_broadcast;            // number of coherence broadcast packets
+    uint32_t m_cost_ins_tlb_update_acc_frz;    // number of frozen cycles related to instruction tlb update acc
+    uint32_t m_cost_data_tlb_update_acc_frz;   // number of frozen cycles related to data tlb update acc
+    uint32_t m_cost_data_tlb_update_dirty_frz; // number of frozen cycles related to data tlb update dirty
+    uint32_t m_cost_ins_tlb_occup_cache_frz;   // number of frozen cycles related to instruction tlb miss operate in dcache
+    uint32_t m_cost_data_tlb_occup_cache_frz;  // number of frozen cycles related to data tlb miss operate in dcache
+
+    uint32_t m_cpt_itlbmiss_transaction;       // number of itlb miss transactions
+    uint32_t m_cpt_itlb_ll_transaction;        // number of itlb ll acc transactions
+    uint32_t m_cpt_itlb_sc_transaction;        // number of itlb sc acc transactions
+    uint32_t m_cpt_dtlbmiss_transaction;       // number of dtlb miss transactions
+    uint32_t m_cpt_dtlb_ll_transaction;        // number of dtlb ll acc transactions
+    uint32_t m_cpt_dtlb_sc_transaction;        // number of dtlb sc acc transactions
+    uint32_t m_cpt_dtlb_ll_dirty_transaction;  // number of dtlb ll dirty transactions
+    uint32_t m_cpt_dtlb_sc_dirty_transaction;  // number of dtlb sc dirty transactions
+
+    uint32_t m_cost_itlbmiss_transaction;     // cumulated duration for VCI instruction TLB miss transactions
+    uint32_t m_cost_itlb_ll_transaction;      // cumulated duration for VCI instruction TLB ll acc transactions
+    uint32_t m_cost_itlb_sc_transaction;      // cumulated duration for VCI instruction TLB sc acc transactions
+    uint32_t m_cost_dtlbmiss_transaction;     // cumulated duration for VCI data TLB miss transactions
+    uint32_t m_cost_dtlb_ll_transaction;      // cumulated duration for VCI data TLB ll acc transactions
+    uint32_t m_cost_dtlb_sc_transaction;      // cumulated duration for VCI data TLB sc acc transactions
+    uint32_t m_cost_dtlb_ll_dirty_transaction;// cumulated duration for VCI data TLB ll dirty transactions
+    uint32_t m_cost_dtlb_sc_dirty_transaction;// cumulated duration for VCI data TLB sc dirty transactions
+
+    uint32_t m_cpt_cc_update_data;              // number of coherence update data packets 
+    uint32_t m_cpt_cc_inval_ins;                // number of coherence inval instruction packets
+    uint32_t m_cpt_cc_inval_data;               // number of coherence inval data packets
+    uint32_t m_cpt_cc_broadcast;                // number of coherence broadcast packets
 
     uint32_t m_cost_ins_tlb_inval_frz;      // number of frozen cycles related to checking ins tlb invalidate
