Index: trunk/modules/vci_cc_vcache_wrapper_v1/caba/source/include/vci_cc_vcache_wrapper_v1.h
===================================================================
--- trunk/modules/vci_cc_vcache_wrapper_v1/caba/source/include/vci_cc_vcache_wrapper_v1.h	(revision 38)
+++ trunk/modules/vci_cc_vcache_wrapper_v1/caba/source/include/vci_cc_vcache_wrapper_v1.h	(revision 48)
@@ -313,5 +313,4 @@
     sc_signal<size_t>       r_dcache_way;
     sc_signal<size_t>       r_dcache_set;
-    sc_signal<bool>         r_dcache_cleanup_check_req;
     sc_signal<bool>         r_dcache_cleanup_req;
     sc_signal<data_t>       r_dcache_cleanup_line;
@@ -347,5 +346,4 @@
     sc_signal<size_t>       r_icache_way;
     sc_signal<size_t>       r_icache_set;
-    sc_signal<bool>         r_icache_cleanup_check_req;
     sc_signal<bool>         r_icache_cleanup_req;
     sc_signal<data_t>       r_icache_cleanup_line;
@@ -383,6 +381,4 @@
     sc_signal<bool>         r_tgt_icache_req;
     sc_signal<bool>         r_tgt_dcache_req;
-    sc_signal<bool>         r_tgt_icache_tlb_req;
-    sc_signal<bool>         r_tgt_dcache_tlb_req;
     sc_signal<bool>         r_tgt_icache_rsp;
     sc_signal<bool>         r_tgt_dcache_rsp;
@@ -440,5 +436,4 @@
     uint32_t m_cost_unc_read_frz;           // number of frozen cycles related to uncached read of cache
     uint32_t m_cost_ins_miss_frz;           // number of frozen cycles related to ins miss of cache
-    uint32_t m_cost_cc_wait_frz;            // number of frozen cycles related to cc check 
 
     uint32_t m_cpt_imiss_transaction;       // number of VCI instruction miss transactions
@@ -446,8 +441,10 @@
     uint32_t m_cpt_unc_transaction;         // number of VCI uncached read transactions
     uint32_t m_cpt_write_transaction;       // number of VCI write transactions
+    uint32_t m_cpt_icache_unc_transaction;  // number of VCI instruction uncached transactions
 
     uint32_t m_cost_imiss_transaction;      // cumulated duration for VCI IMISS transactions
     uint32_t m_cost_dmiss_transaction;      // cumulated duration for VCI DMISS transactions
     uint32_t m_cost_unc_transaction;        // cumulated duration for VCI UNC transactions
+    uint32_t m_cost_icache_unc_transaction; // cumulated duration for VCI IUNC transactions    
     uint32_t m_cost_write_transaction;      // cumulated duration for VCI WRITE transactions
     uint32_t m_length_write_transaction;    // cumulated length for VCI WRITE transactions
@@ -456,35 +453,45 @@
     uint32_t m_cpt_ins_tlb_read;            // number of instruction tlb read
     uint32_t m_cpt_ins_tlb_miss;            // number of instruction tlb miss
-    uint32_t m_cpt_ins_tlb_write_et;        // number of instruction tlb write ET
-
+    uint32_t m_cpt_ins_tlb_update_acc;      // number of instruction tlb update acc
     uint32_t m_cpt_data_tlb_read;           // number of data tlb read
     uint32_t m_cpt_data_tlb_miss;           // number of data tlb miss
-    uint32_t m_cpt_data_tlb_write_et;       // number of data tlb write ET
-    uint32_t m_cpt_data_tlb_write_dirty;    // number of data tlb write dirty
+    uint32_t m_cpt_data_tlb_update_acc;     // number of data tlb update acc
+    uint32_t m_cpt_data_tlb_update_dirty;   // number of data tlb update dirty
     
     uint32_t m_cost_ins_tlb_miss_frz;       // number of frozen cycles related to instruction tlb miss
     uint32_t m_cost_data_tlb_miss_frz;      // number of frozen cycles related to data tlb miss
-    uint32_t m_cost_ins_tlb_flush_frz;      // number of cycles for instruction tlb flush 
-    uint32_t m_cost_data_tlb_flush_frz;     // number of cycles for data tlb flush
-    uint32_t m_cost_ins_cache_flush_frz;    // number of cycles for instruction cache flush 
-    uint32_t m_cost_data_cache_flush_frz;   // number of cycles for data cache flush 
-    uint32_t m_cost_data_waste_wait_frz;
+    uint32_t m_cost_ins_tlb_update_acc_frz;      // number of cycles for instruction tlb flush 
+    uint32_t m_cost_data_tlb_update_acc_frz;     // number of cycles for data tlb flush
+    uint32_t m_cost_data_tlb_update_dirty_frz;    // number of cycles for instruction cache flush 
 
     uint32_t m_cpt_itlbmiss_transaction;    // number of itlb miss transactions
-    uint32_t m_cpt_itlb_write_transaction;  // number of itlb write ET transactions
+    uint32_t m_cpt_itlb_ll_transaction;        // number of itlb ll acc transactions
+    uint32_t m_cpt_itlb_sc_transaction;        // number of itlb sc acc transactions
     uint32_t m_cpt_dtlbmiss_transaction;    // number of dtlb miss transactions
-    uint32_t m_cpt_dtlb_write_transaction;  // number of dtlb write ET and dirty transactions
+    uint32_t m_cpt_dtlb_ll_transaction;        // number of dtlb ll acc transactions
+    uint32_t m_cpt_dtlb_sc_transaction;        // number of dtlb sc acc transactions
+    uint32_t m_cpt_dtlb_ll_dirty_transaction;  // number of dtlb ll dirty transactions
+    uint32_t m_cpt_dtlb_sc_dirty_transaction;  // number of dtlb sc dirty transactions    
 
     uint32_t m_cost_itlbmiss_transaction;   // cumulated duration for VCI instruction TLB miss transactions
-    uint32_t m_cost_itlb_write_transaction; // cumulated duration for VCI instruction TLB write ET transactions
+    uint32_t m_cost_itlb_ll_transaction;      // cumulated duration for VCI instruction TLB ll acc transactions
+    uint32_t m_cost_itlb_sc_transaction;      // cumulated duration for VCI instruction TLB sc acc transactions
     uint32_t m_cost_dtlbmiss_transaction;   // cumulated duration for VCI data TLB miss transactions
-    uint32_t m_cost_dtlb_write_transaction; // cumulated duration for VCI data TLB write transactions
-
-    uint32_t m_cpt_cc_update;               // number of coherence update packets 
-    uint32_t m_cpt_cc_inval;                // number of coherence inval packets
-    uint32_t m_cpt_cc_broadcast;            // number of coherence inval packets
-
-    uint32_t m_cost_cc_update_frz;          // number of waiting cycles for coherence update
-    uint32_t m_cost_cc_inval_frz;           // number of waiting cycles for coherence invalidate
+    uint32_t m_cost_dtlb_ll_transaction;      // cumulated duration for VCI data TLB ll acc transactions
+    uint32_t m_cost_dtlb_sc_transaction;      // cumulated duration for VCI data TLB sc acc transactions
+    uint32_t m_cost_dtlb_ll_dirty_transaction;// cumulated duration for VCI data TLB ll dirty transactions
+    uint32_t m_cost_dtlb_sc_dirty_transaction;// cumulated duration for VCI data TLB sc dirty transactions
+
+    uint32_t m_cpt_cc_cleanup_ins;
+    uint32_t m_cpt_cc_cleanup_data;
+    uint32_t m_cpt_icleanup_transaction;
+    uint32_t m_cpt_dcleanup_transaction;
+    uint32_t m_cost_icleanup_transaction;
+    uint32_t m_cost_dcleanup_transaction;
+
+    uint32_t m_cpt_cc_update_data;              // number of coherence update data packets 
+    uint32_t m_cpt_cc_inval_ins;                // number of coherence inval instruction packets
+    uint32_t m_cpt_cc_inval_data;               // number of coherence inval data packets
+    uint32_t m_cpt_cc_broadcast;                // number of coherence broadcast packets
 
 protected:
