Index: trunk/modules/vci_cc_vcache_wrapper2_v1/caba/source/include/vci_cc_vcache_wrapper2_v1.h =================================================================== --- trunk/modules/vci_cc_vcache_wrapper2_v1/caba/source/include/vci_cc_vcache_wrapper2_v1.h (revision 47) +++ trunk/modules/vci_cc_vcache_wrapper2_v1/caba/source/include/vci_cc_vcache_wrapper2_v1.h (revision 48) @@ -440,5 +440,6 @@ uint32_t m_cpt_frz_cycles; // number of cycles where the cpu is frozen - uint32_t m_cpt_total_cycles; // total number of cycles + uint32_t m_cpt_total_cycles; // total number of cycles + uint32_t m_cpt_dcache_frz_cycles; // number of cycles where the data cache is frozen // Cache activity counters @@ -460,4 +461,5 @@ uint32_t m_cpt_unc_transaction; // number of VCI uncached read transactions uint32_t m_cpt_write_transaction; // number of VCI write transactions + uint32_t m_cpt_icache_unc_transaction; uint32_t m_cost_imiss_transaction; // cumulated duration for VCI IMISS transactions @@ -465,4 +467,5 @@ uint32_t m_cost_unc_transaction; // cumulated duration for VCI UNC transactions uint32_t m_cost_write_transaction; // cumulated duration for VCI WRITE transactions + uint32_t m_cost_icache_unc_transaction; // cumulated duration for VCI IUNC transactions uint32_t m_length_write_transaction; // cumulated length for VCI WRITE transactions @@ -470,36 +473,45 @@ uint32_t m_cpt_ins_tlb_read; // number of instruction tlb read uint32_t m_cpt_ins_tlb_miss; // number of instruction tlb miss - uint32_t m_cpt_ins_tlb_write_et; // number of instruction tlb write ET - + uint32_t m_cpt_ins_tlb_update_acc; // number of instruction tlb update acc uint32_t m_cpt_data_tlb_read; // number of data tlb read uint32_t m_cpt_data_tlb_miss; // number of data tlb miss - uint32_t m_cpt_data_tlb_write_et; // number of data tlb write ET - uint32_t m_cpt_data_tlb_write_dirty; // number of data tlb write dirty + uint32_t m_cpt_data_tlb_update_acc; // number of data tlb update acc + uint32_t m_cpt_data_tlb_update_dirty; // number of data tlb update dirty + uint32_t m_cpt_ins_tlb_hit_dcache; // number of instruction tlb hit in data cache + uint32_t m_cpt_data_tlb_hit_dcache; // number of data tlb hit in data cache + uint32_t m_cpt_ins_tlb_occup_cache; // number of instruction tlb occupy data cache line + uint32_t m_cpt_data_tlb_occup_cache; // number of data tlb occupy data cache line + uint32_t m_cpt_tlb_occupy_dcache; uint32_t m_cost_ins_tlb_miss_frz; // number of frozen cycles related to instruction tlb miss uint32_t m_cost_data_tlb_miss_frz; // number of frozen cycles related to data tlb miss - - uint32_t m_cost_ins_waste_wait_frz; // number of frozen cycles related to ins wait coherence operate - uint32_t m_cost_ins_tlb_sw_frz; // number of frozen cycles related to ins context switch - uint32_t m_cost_ins_cache_flush_frz; // number of frozen cycles related to ins cache flush - - uint32_t m_cpt_ins_tlb_cleanup; // number of ins tlb cleanup - uint32_t m_cost_data_waste_wait_frz; // number of frozen cycles related to data wait coherence operate - uint32_t m_cost_data_tlb_sw_frz; // number of frozen cycles related to data context switch - uint32_t m_cost_data_cache_flush_frz; // number of frozen cycles related to data cache flush - - uint32_t m_cpt_itlbmiss_transaction; // number of itlb miss transactions - uint32_t m_cpt_itlb_write_transaction; // number of itlb write ET transactions - uint32_t m_cpt_dtlbmiss_transaction; // number of dtlb miss transactions - uint32_t m_cpt_dtlb_write_transaction; // number of dtlb write ET and dirty transactions - - uint32_t m_cost_itlbmiss_transaction; // cumulated duration for VCI instruction TLB miss transactions - uint32_t m_cost_itlb_write_transaction; // cumulated duration for VCI instruction TLB write ET transactions - uint32_t m_cost_dtlbmiss_transaction; // cumulated duration for VCI data TLB miss transactions - uint32_t m_cost_dtlb_write_transaction; // cumulated duration for VCI data TLB write transactions - - uint32_t m_cpt_cc_update; // number of coherence update packets - uint32_t m_cpt_cc_inval; // number of coherence inval packets - uint32_t m_cpt_cc_broadcast; // number of coherence broadcast packets + uint32_t m_cost_ins_tlb_update_acc_frz; // number of frozen cycles related to instruction tlb update acc + uint32_t m_cost_data_tlb_update_acc_frz; // number of frozen cycles related to data tlb update acc + uint32_t m_cost_data_tlb_update_dirty_frz; // number of frozen cycles related to data tlb update dirty + uint32_t m_cost_ins_tlb_occup_cache_frz; // number of frozen cycles related to instruction tlb miss operate in dcache + uint32_t m_cost_data_tlb_occup_cache_frz; // number of frozen cycles related to data tlb miss operate in dcache + + uint32_t m_cpt_itlbmiss_transaction; // number of itlb miss transactions + uint32_t m_cpt_itlb_ll_transaction; // number of itlb ll acc transactions + uint32_t m_cpt_itlb_sc_transaction; // number of itlb sc acc transactions + uint32_t m_cpt_dtlbmiss_transaction; // number of dtlb miss transactions + uint32_t m_cpt_dtlb_ll_transaction; // number of dtlb ll acc transactions + uint32_t m_cpt_dtlb_sc_transaction; // number of dtlb sc acc transactions + uint32_t m_cpt_dtlb_ll_dirty_transaction; // number of dtlb ll dirty transactions + uint32_t m_cpt_dtlb_sc_dirty_transaction; // number of dtlb sc dirty transactions + + uint32_t m_cost_itlbmiss_transaction; // cumulated duration for VCI instruction TLB miss transactions + uint32_t m_cost_itlb_ll_transaction; // cumulated duration for VCI instruction TLB ll acc transactions + uint32_t m_cost_itlb_sc_transaction; // cumulated duration for VCI instruction TLB sc acc transactions + uint32_t m_cost_dtlbmiss_transaction; // cumulated duration for VCI data TLB miss transactions + uint32_t m_cost_dtlb_ll_transaction; // cumulated duration for VCI data TLB ll acc transactions + uint32_t m_cost_dtlb_sc_transaction; // cumulated duration for VCI data TLB sc acc transactions + uint32_t m_cost_dtlb_ll_dirty_transaction;// cumulated duration for VCI data TLB ll dirty transactions + uint32_t m_cost_dtlb_sc_dirty_transaction;// cumulated duration for VCI data TLB sc dirty transactions + + uint32_t m_cpt_cc_update_data; // number of coherence update data packets + uint32_t m_cpt_cc_inval_ins; // number of coherence inval instruction packets + uint32_t m_cpt_cc_inval_data; // number of coherence inval data packets + uint32_t m_cpt_cc_broadcast; // number of coherence broadcast packets uint32_t m_cost_ins_tlb_inval_frz; // number of frozen cycles related to checking ins tlb invalidate Index: trunk/modules/vci_cc_vcache_wrapper2_v1/caba/source/src/vci_cc_vcache_wrapper2_v1.cpp =================================================================== --- trunk/modules/vci_cc_vcache_wrapper2_v1/caba/source/src/vci_cc_vcache_wrapper2_v1.cpp (revision 47) +++ trunk/modules/vci_cc_vcache_wrapper2_v1/caba/source/src/vci_cc_vcache_wrapper2_v1.cpp (revision 48) @@ -367,28 +367,39 @@ float run_cycles = (float)(m_cpt_total_cycles - m_cpt_frz_cycles); std::cout << name() << std::endl - << "- CPI = " << (float)m_cpt_total_cycles/run_cycles << std::endl - << "- READ RATE = " << (float)m_cpt_read/run_cycles << std::endl - << "- WRITE RATE = " << (float)m_cpt_write/run_cycles << std::endl - << "- UNCACHED READ RATE = " << (float)m_cpt_unc_read/m_cpt_read << std::endl - << "- CACHED WRITE RATE = " << (float)m_cpt_write_cached/m_cpt_write << std::endl - << "- IMISS_RATE = " << (float)m_cpt_ins_miss/m_cpt_ins_read << std::endl - << "- DMISS RATE = " << (float)m_cpt_data_miss/(m_cpt_read-m_cpt_unc_read) << std::endl - << "- INS MISS COST = " << (float)m_cost_ins_miss_frz/m_cpt_ins_miss << std::endl - << "- IMISS TRANSACTION = " << (float)m_cost_imiss_transaction/m_cpt_imiss_transaction << std::endl - << "- DMISS COST = " << (float)m_cost_data_miss_frz/m_cpt_data_miss << std::endl - << "- DMISS TRANSACTION = " << (float)m_cost_dmiss_transaction/m_cpt_dmiss_transaction << std::endl - << "- UNC COST = " << (float)m_cost_unc_read_frz/m_cpt_unc_read << std::endl - << "- UNC TRANSACTION = " << (float)m_cost_unc_transaction/m_cpt_unc_transaction << std::endl - << "- WRITE COST = " << (float)m_cost_write_frz/m_cpt_write << std::endl - << "- WRITE TRANSACTION = " << (float)m_cost_write_transaction/m_cpt_write_transaction << std::endl - << "- WRITE LENGTH = " << (float)m_length_write_transaction/m_cpt_write_transaction << std::endl - << "- INS TLB MISS RATE = " << (float)m_cpt_ins_tlb_miss/m_cpt_ins_tlb_read << std::endl - << "- DATA TLB MISS RATE = " << (float)m_cpt_data_tlb_miss/m_cpt_data_tlb_read << std::endl - << "- ITLB MISS TRANSACTION = " << (float)m_cost_itlbmiss_transaction/m_cpt_itlbmiss_transaction << std::endl - << "- ITLB WRITE TRANSACTION = " << (float)m_cost_itlb_write_transaction/m_cpt_itlb_write_transaction << std::endl - << "- ITLB MISS COST = " << (float)m_cost_ins_tlb_miss_frz/(m_cpt_ins_tlb_miss+m_cpt_ins_tlb_write_et) << std::endl - << "- DTLB MISS TRANSACTION = " << (float)m_cost_dtlbmiss_transaction/m_cpt_dtlbmiss_transaction << std::endl - << "- DTLB WRITE TRANSACTION = " << (float)m_cost_dtlb_write_transaction/m_cpt_dtlb_write_transaction << std::endl - << "- DTLB MISS COST = " << (float)m_cost_data_tlb_miss_frz/(m_cpt_data_tlb_miss+m_cpt_data_tlb_write_et+m_cpt_data_tlb_write_dirty) << std::endl; + << "- CPI = " << (float)m_cpt_total_cycles/run_cycles << std::endl + << "- READ RATE = " << (float)m_cpt_read/run_cycles << std::endl + << "- WRITE RATE = " << (float)m_cpt_write/run_cycles << std::endl + << "- IMISS_RATE = " << (float)m_cpt_ins_miss/m_cpt_ins_read << std::endl + << "- DMISS RATE = " << (float)m_cpt_data_miss/(m_cpt_read-m_cpt_unc_read) << std::endl + << "- INS MISS COST = " << (float)m_cost_ins_miss_frz/m_cpt_ins_miss << std::endl + << "- DATA MISS COST = " << (float)m_cost_data_miss_frz/m_cpt_data_miss << std::endl + << "- WRITE COST = " << (float)m_cost_write_frz/m_cpt_write << std::endl + << "- UNC COST = " << (float)m_cost_unc_read_frz/m_cpt_unc_read << std::endl + << "- UNCACHED READ RATE = " << (float)m_cpt_unc_read/m_cpt_read << std::endl + << "- CACHED WRITE RATE = " << (float)m_cpt_write_cached/m_cpt_write << std::endl + << "- INS TLB MISS RATE = " << (float)m_cpt_ins_tlb_miss/m_cpt_ins_tlb_read << std::endl + << "- DATA TLB MISS RATE = " << (float)m_cpt_data_tlb_miss/m_cpt_data_tlb_read << std::endl + << "- ITLB MISS COST = " << (float)m_cost_ins_tlb_miss_frz/m_cpt_ins_tlb_miss << std::endl + << "- DTLB MISS COST = " << (float)m_cost_data_tlb_miss_frz/m_cpt_data_tlb_miss << std::endl + << "- ITLB UPDATE ACC COST = " << (float)m_cost_ins_tlb_update_acc_frz/m_cpt_ins_tlb_update_acc << std::endl + << "- DTLB UPDATE ACC COST = " << (float)m_cost_data_tlb_update_acc_frz/m_cpt_data_tlb_update_acc << std::endl + << "- DTLB UPDATE DIRTY COST = " << (float)m_cost_data_tlb_update_dirty_frz/m_cpt_data_tlb_update_dirty << std::endl + << "- ITLB HIT IN DCACHE RATE= " << (float)m_cpt_ins_tlb_hit_dcache/m_cpt_ins_tlb_miss << std::endl + << "- DTLB HIT IN DCACHE RATE= " << (float)m_cpt_data_tlb_hit_dcache/m_cpt_data_tlb_miss << std::endl + << "- DCACHE FROZEN BY TLB OP= " << (float)(m_cost_ins_tlb_occup_cache_frz+m_cost_data_tlb_occup_cache_frz)/m_cpt_dcache_frz_cycles << std::endl + << "- DCACHE FOR TLB % = " << (float)m_cpt_tlb_occup_dcache/(m_dcache_ways*m_dcache_sets) << std::endl + << "- NB CC BROADCAST = " << m_cpt_cc_broadcast << std::endl + << "- NB CC UPDATE DATA = " << m_cpt_cc_update_data << std::endl + << "- NB CC INVAL DATA = " << m_cpt_cc_inval_data << std::endl + << "- NB CC INVAL INS = " << m_cpt_cc_inval_ins << std::endl + << "- NB CC CLEANUP DATA = " << m_cpt_cc_cleanup_data << std::endl + << "- NB CC CLEANUP INS = " << m_cpt_cc_cleanup_ins << std::endl + << "- IMISS TRANSACTION = " << (float)m_cost_imiss_transaction/m_cpt_imiss_transaction << std::endl + << "- DMISS TRANSACTION = " << (float)m_cost_dmiss_transaction/m_cpt_dmiss_transaction << std::endl + << "- UNC TRANSACTION = " << (float)m_cost_unc_transaction/m_cpt_unc_transaction << std::endl + << "- WRITE TRANSACTION = " << (float)m_cost_write_transaction/m_cpt_write_transaction << std::endl + << "- WRITE LENGTH = " << (float)m_length_write_transaction/m_cpt_write_transaction << std::endl + << "- ITLB MISS TRANSACTION = " << (float)m_cost_itlbmiss_transaction/m_cpt_itlbmiss_transaction << std::endl + << "- DTLB MISS TRANSACTION = " << (float)m_cost_dtlbmiss_transaction/m_cpt_dtlbmiss_transaction << std::endl; } @@ -464,4 +475,5 @@ r_dcache_dirty_save = false; r_dcache_hit_p_save = false; + r_dcache_cached_save = false; r_icache_buf_unc_valid = false; @@ -527,6 +539,7 @@ m_cpt_icache_dir_write = 0; - m_cpt_frz_cycles = 0; - m_cpt_total_cycles = 0; + m_cpt_frz_cycles = 0; + m_cpt_dcache_frz_cycles = 0; + m_cpt_total_cycles = 0; m_cpt_read = 0; @@ -543,36 +556,55 @@ m_cost_ins_miss_frz = 0; - m_cpt_imiss_transaction = 0; - m_cpt_dmiss_transaction = 0; - m_cpt_unc_transaction = 0; - m_cpt_write_transaction = 0; - - m_cost_imiss_transaction = 0; - m_cost_dmiss_transaction = 0; - m_cost_unc_transaction = 0; - m_cost_write_transaction = 0; - m_length_write_transaction = 0; - - m_cpt_ins_tlb_read = 0; - m_cpt_ins_tlb_miss = 0; - m_cpt_ins_tlb_write_et = 0; - - m_cpt_data_tlb_read = 0; - m_cpt_data_tlb_miss = 0; - m_cpt_data_tlb_write_et = 0; - m_cpt_data_tlb_write_dirty = 0; - - m_cost_ins_tlb_miss_frz = 0; - m_cost_data_tlb_miss_frz = 0; - - m_cpt_itlbmiss_transaction = 0; - m_cpt_itlb_write_transaction = 0; - m_cpt_dtlbmiss_transaction = 0; - m_cpt_dtlb_write_transaction = 0; + m_cpt_imiss_transaction = 0; + m_cpt_dmiss_transaction = 0; + m_cpt_unc_transaction = 0; + m_cpt_write_transaction = 0; + m_cpt_icache_unc_transaction = 0; + + m_cost_imiss_transaction = 0; + m_cost_dmiss_transaction = 0; + m_cost_unc_transaction = 0; + m_cost_write_transaction = 0; + m_cost_icache_unc_transaction = 0; + m_length_write_transaction = 0; + + m_cpt_ins_tlb_read = 0; + m_cpt_ins_tlb_miss = 0; + m_cpt_ins_tlb_update_acc = 0; + + m_cpt_data_tlb_read = 0; + m_cpt_data_tlb_miss = 0; + m_cpt_data_tlb_update_acc = 0; + m_cpt_data_tlb_update_dirty = 0; + m_cpt_ins_tlb_hit_dcache = 0; + m_cpt_data_tlb_hit_dcache = 0; + m_cpt_ins_tlb_occup_cache = 0; + m_cpt_data_tlb_occup_cache = 0; + + m_cost_ins_tlb_miss_frz = 0; + m_cost_data_tlb_miss_frz = 0; + m_cost_ins_tlb_update_acc_frz = 0; + m_cost_data_tlb_update_acc_frz = 0; + m_cost_data_tlb_update_dirty_frz = 0; + m_cost_ins_tlb_occup_cache_frz = 0; + m_cost_data_tlb_occup_cache_frz = 0; + + m_cpt_itlbmiss_transaction = 0; + m_cpt_itlb_ll_transaction = 0; + m_cpt_itlb_sc_transaction = 0; + m_cpt_dtlbmiss_transaction = 0; + m_cpt_dtlb_ll_transaction = 0; + m_cpt_dtlb_sc_transaction = 0; + m_cpt_dtlb_ll_dirty_transaction = 0; + m_cpt_dtlb_sc_dirty_transaction = 0; - m_cost_itlbmiss_transaction = 0; - m_cost_itlb_write_transaction = 0; - m_cost_dtlbmiss_transaction = 0; - m_cost_dtlb_write_transaction = 0; + m_cost_itlbmiss_transaction = 0; + m_cost_itlb_ll_transaction = 0; + m_cost_itlb_sc_transaction = 0; + m_cost_dtlbmiss_transaction = 0; + m_cost_dtlb_ll_transaction = 0; + m_cost_dtlb_sc_transaction = 0; + m_cost_dtlb_ll_dirty_transaction = 0; + m_cost_dtlb_sc_dirty_transaction = 0; return; } @@ -691,5 +723,5 @@ r_tgt_update = false; r_vci_tgt_fsm = TGT_REQ_DCACHE; - m_cpt_cc_inval++ ; + m_cpt_cc_inval_data++ ; } else if (cell == 4) // update @@ -703,5 +735,5 @@ r_tgt_update = true; r_vci_tgt_fsm = TGT_UPDT_WORD; - m_cpt_cc_update++ ; + m_cpt_cc_update_data++ ; } else if (cell == 8) @@ -715,5 +747,5 @@ r_tgt_update = false; r_vci_tgt_fsm = TGT_REQ_ICACHE; - m_cpt_cc_inval++ ; + m_cpt_cc_inval_ins++ ; } @@ -948,5 +980,4 @@ if ( r_tgt_icache_req ) { - if ( ireq.valid ) m_cost_ins_waste_wait_frz++; r_icache_fsm = ICACHE_CC_INVAL; r_icache_fsm_save = r_icache_fsm; @@ -957,5 +988,4 @@ if ( r_dcache_itlb_inval_req ) { - if ( ireq.valid ) m_cost_ins_waste_wait_frz++; r_itlb_inval_req = true; r_icache_fsm = ICACHE_TLB_CC_INVAL; @@ -1119,11 +1149,10 @@ case ICACHE_BIS: { - m_cost_ins_miss_frz++; // external cache invalidate request if ( r_tgt_icache_req ) { + if ( ireq.valid ) m_cost_ins_miss_frz++; r_icache_fsm = ICACHE_CC_INVAL; r_icache_fsm_save = r_icache_fsm; - m_cost_ins_waste_wait_frz++; break; } @@ -1132,8 +1161,8 @@ if ( r_dcache_itlb_inval_req ) { + if ( ireq.valid ) m_cost_ins_miss_frz++; r_itlb_inval_req = true; r_icache_fsm = ICACHE_TLB_CC_INVAL; r_icache_fsm_save = r_icache_fsm; - m_cost_ins_waste_wait_frz++; break; } @@ -1142,7 +1171,7 @@ if ( r_icache_inval_tlb_rsp ) { + if ( ireq.valid ) m_cost_ins_miss_frz++; r_icache_inval_tlb_rsp = false; r_icache_fsm = ICACHE_IDLE; - m_cost_ins_tlb_miss_frz++; break; } @@ -1167,4 +1196,5 @@ r_icache_fsm = ICACHE_MISS_WAIT; m_cpt_ins_miss++; + m_cost_ins_miss_frz++; } else @@ -1191,5 +1221,5 @@ case ICACHE_TLB1_READ: { - m_cost_ins_tlb_miss_frz++; + if ( ireq.valid ) m_cost_ins_tlb_miss_frz++; // external cache invalidate request @@ -1198,5 +1228,4 @@ r_icache_fsm = ICACHE_CC_INVAL; r_icache_fsm_save = r_icache_fsm; - m_cost_ins_waste_wait_frz++; break; } @@ -1208,5 +1237,4 @@ r_icache_fsm = ICACHE_TLB_CC_INVAL; r_icache_fsm_save = r_icache_fsm; - m_cost_ins_waste_wait_frz++; break; } @@ -1262,5 +1290,6 @@ r_itlb_acc_dcache_req = true; r_icache_fsm = ICACHE_TLB1_WRITE; - m_cpt_ins_tlb_write_et++; + m_cpt_ins_tlb_update_acc++; + m_cost_ins_tlb_update_acc_frz++; } } @@ -1277,5 +1306,6 @@ r_itlb_acc_dcache_req = true; r_icache_fsm = ICACHE_TLB1_WRITE; - m_cpt_ins_tlb_write_et++; + m_cpt_ins_tlb_update_acc++; + m_cost_ins_tlb_update_acc_frz++; } } @@ -1311,5 +1341,6 @@ case ICACHE_TLB1_WRITE: { - m_cost_ins_tlb_miss_frz++; + if ( ireq.valid ) m_cost_ins_tlb_miss_frz++; + m_cost_ins_tlb_update_acc_frz++; // external cache invalidate request @@ -1318,5 +1349,4 @@ r_icache_fsm = ICACHE_CC_INVAL; r_icache_fsm_save = r_icache_fsm; - m_cost_ins_waste_wait_frz++; break; } @@ -1327,5 +1357,4 @@ r_icache_fsm = ICACHE_TLB_CC_INVAL; r_icache_fsm_save = r_icache_fsm; - m_cost_ins_waste_wait_frz++; break; } @@ -1368,5 +1397,5 @@ case ICACHE_TLB1_UPDT: { - m_cost_ins_tlb_miss_frz++; + if ( ireq.valid ) m_cost_ins_tlb_miss_frz++; // external cache invalidate request @@ -1375,5 +1404,4 @@ r_icache_fsm = ICACHE_CC_INVAL; r_icache_fsm_save = r_icache_fsm; - m_cost_ins_waste_wait_frz++; break; } @@ -1385,5 +1413,4 @@ r_icache_fsm = ICACHE_TLB_CC_INVAL; r_icache_fsm_save = r_icache_fsm; - m_cost_ins_waste_wait_frz++; break; } @@ -1395,4 +1422,5 @@ r_dcache_itlb_cleanup_req = icache_tlb.update(r_icache_pte_update,r_icache_vaddr_req.read(),(r_icache_paddr_save.read() >> (uint32_log2(m_dcache_words)+2)),&victim_index); r_dcache_itlb_cleanup_line = victim_index; + m_cpt_cc_cleanup_ins++; r_icache_fsm = ICACHE_IDLE; } @@ -1409,5 +1437,5 @@ case ICACHE_TLB2_READ: { - m_cost_ins_tlb_miss_frz++; + if ( ireq.valid ) m_cost_ins_tlb_miss_frz++; // external cache invalidate request @@ -1416,5 +1444,4 @@ r_icache_fsm = ICACHE_CC_INVAL; r_icache_fsm_save = r_icache_fsm; - m_cost_ins_waste_wait_frz++; break; } @@ -1426,5 +1453,4 @@ r_icache_fsm = ICACHE_TLB_CC_INVAL; r_icache_fsm_save = r_icache_fsm; - m_cost_ins_waste_wait_frz++; break; } @@ -1466,5 +1492,6 @@ r_itlb_acc_dcache_req = true; r_icache_fsm = ICACHE_TLB2_WRITE; - m_cpt_ins_tlb_write_et++; + m_cpt_ins_tlb_update_acc++; + m_cost_ins_tlb_update_acc_frz++; } } @@ -1481,5 +1508,6 @@ r_itlb_acc_dcache_req = true; r_icache_fsm = ICACHE_TLB2_WRITE; - m_cpt_ins_tlb_write_et++; + m_cpt_ins_tlb_update_acc++; + m_cost_ins_tlb_update_acc_frz++; } } @@ -1515,5 +1543,6 @@ case ICACHE_TLB2_WRITE: { - m_cost_ins_tlb_miss_frz++; + if ( ireq.valid ) m_cost_ins_tlb_miss_frz++; + m_cost_ins_tlb_update_acc_frz++; // external cache invalidate request @@ -1522,5 +1551,4 @@ r_icache_fsm = ICACHE_CC_INVAL; r_icache_fsm_save = r_icache_fsm; - m_cost_ins_waste_wait_frz++; break; } @@ -1531,5 +1559,4 @@ r_icache_fsm = ICACHE_TLB_CC_INVAL; r_icache_fsm_save = r_icache_fsm; - m_cost_ins_waste_wait_frz++; break; } @@ -1572,5 +1599,5 @@ case ICACHE_TLB2_UPDT: { - m_cost_ins_tlb_miss_frz++; + if ( ireq.valid ) m_cost_ins_tlb_miss_frz++; // external cache invalidate request @@ -1579,5 +1606,4 @@ r_icache_fsm = ICACHE_CC_INVAL; r_icache_fsm_save = r_icache_fsm; - m_cost_ins_waste_wait_frz++; break; } @@ -1589,5 +1615,4 @@ r_icache_fsm = ICACHE_TLB_CC_INVAL; r_icache_fsm_save = r_icache_fsm; - m_cost_ins_waste_wait_frz++; break; } @@ -1599,4 +1624,5 @@ r_dcache_itlb_cleanup_req = icache_tlb.update(r_icache_pte_update,r_dcache_rsp_itlb_ppn,r_icache_vaddr_req.read(),(r_icache_paddr_save.read() >> (uint32_log2(m_dcache_words)+2)),&victim_index); r_dcache_itlb_cleanup_line = victim_index; + m_cpt_cc_cleanup_ins++; r_icache_fsm = ICACHE_IDLE; } @@ -1616,5 +1642,4 @@ bool clean = false; - if ( ireq.valid ) m_cost_ins_waste_wait_frz++; m_cost_ins_tlb_sw_frz++; @@ -1654,6 +1679,4 @@ case ICACHE_TLB_FLUSH: { - if ( ireq.valid ) m_cost_ins_waste_wait_frz++; - // data cache flush leads to ins tlb flush, flush all tlb entry icache_tlb.flush(true); // global entries are invalidated @@ -1672,5 +1695,4 @@ r_icache_fsm = ICACHE_CC_INVAL; r_icache_fsm_save = r_icache_fsm; - m_cost_ins_waste_wait_frz++; break; } @@ -1679,7 +1701,4 @@ size_t set = r_icache_set; bool clean = false; - - m_cost_ins_cache_flush_frz++; - if ( ireq.valid ) m_cost_ins_waste_wait_frz++; // cache flush and send cleanup to external @@ -1696,4 +1715,5 @@ r_icache_cleanup_req = true; r_icache_cleanup_line = victim_index; + m_cpt_cc_cleanup_ins++; r_icache_way = way + ((set+1)/m_icache_sets); r_icache_set = (set+1) % m_icache_sets; @@ -1715,5 +1735,4 @@ case ICACHE_TLB_INVAL: { - if ( ireq.valid ) m_cost_ins_waste_wait_frz++; paddr_t victim_index = 0; @@ -1722,4 +1741,5 @@ r_dcache_itlb_cleanup_req = icache_tlb.inval(r_dcache_wdata_save, &victim_index); r_dcache_itlb_cleanup_line = victim_index; + m_cpt_cc_cleanup_ins++; r_dcache_xtn_req = false; r_itlb_translation_valid = false; @@ -1732,5 +1752,4 @@ case ICACHE_CACHE_INVAL: { - if ( ireq.valid ) m_cost_ins_waste_wait_frz++; // external cache invalidate request if ( r_tgt_icache_req ) @@ -1738,5 +1757,4 @@ r_icache_fsm = ICACHE_CC_INVAL; r_icache_fsm_save = r_icache_fsm; - m_cost_ins_waste_wait_frz++; break; } @@ -1760,5 +1778,6 @@ // invalidate and cleanup if necessary r_icache_cleanup_req = r_icache.inval(ipaddr); - r_icache_cleanup_line = ipaddr >> (uint32_log2(m_icache_words) + 2); + r_icache_cleanup_line = ipaddr >> (uint32_log2(m_icache_words) + 2); + m_cpt_cc_cleanup_ins++; } r_dcache_xtn_req = false; @@ -1775,5 +1794,4 @@ r_icache_fsm = ICACHE_CC_INVAL; r_icache_fsm_save = r_icache_fsm; - m_cost_ins_waste_wait_frz++; break; } @@ -1785,5 +1803,6 @@ // invalidate and cleanup if necessary r_icache_cleanup_req = r_icache.inval(ipaddr); - r_icache_cleanup_line = ipaddr >> (uint32_log2(m_icache_words) + 2); + r_icache_cleanup_line = ipaddr >> (uint32_log2(m_icache_words) + 2); + m_cpt_cc_cleanup_ins++; r_dcache_xtn_req = false; r_icache_fsm = ICACHE_IDLE; @@ -1801,5 +1820,4 @@ r_icache_fsm = ICACHE_CC_INVAL; r_icache_fsm_save = r_icache_fsm; - m_cost_ins_waste_wait_frz++; break; } @@ -1811,5 +1829,4 @@ r_icache_fsm = ICACHE_TLB_CC_INVAL; r_icache_fsm_save = r_icache_fsm; - m_cost_ins_waste_wait_frz++; break; } @@ -1832,9 +1849,9 @@ if ( r_icache_cleanup_req ) break; r_icache_cleanup_req = true; - r_icache_cleanup_line = r_icache_paddr_save.read() >> (uint32_log2(m_icache_words) + 2); + r_icache_cleanup_line = r_icache_paddr_save.read() >> (uint32_log2(m_icache_words) + 2); + m_cpt_cc_cleanup_ins++; r_icache_fsm = ICACHE_IDLE; r_icache_inval_tlb_rsp = false; if ( r_icache_inval_rsp ) r_icache_inval_rsp = false; - m_cost_ins_tlb_miss_frz++; break; } @@ -1845,4 +1862,5 @@ r_icache_cleanup_req = true; r_icache_cleanup_line = r_icache_paddr_save.read() >> (uint32_log2(m_icache_words) + 2); + m_cpt_cc_cleanup_ins++; r_icache_fsm = ICACHE_IDLE; r_icache_inval_rsp = false; @@ -1856,6 +1874,4 @@ case ICACHE_UNC_WAIT: { - m_cost_ins_miss_frz++; - // external cache invalidate request if ( r_tgt_icache_req ) @@ -1863,5 +1879,4 @@ r_icache_fsm = ICACHE_CC_INVAL; r_icache_fsm_save = r_icache_fsm; - m_cost_ins_waste_wait_frz++; break; } @@ -1873,5 +1888,4 @@ r_icache_fsm = ICACHE_TLB_CC_INVAL; r_icache_fsm_save = r_icache_fsm; - m_cost_ins_waste_wait_frz++; break; } @@ -1913,5 +1927,4 @@ r_icache_fsm = ICACHE_CC_INVAL; r_icache_fsm_save = r_icache_fsm; - m_cost_ins_waste_wait_frz++; break; } @@ -1923,5 +1936,4 @@ r_icache_fsm = ICACHE_TLB_CC_INVAL; r_icache_fsm_save = r_icache_fsm; - m_cost_ins_waste_wait_frz++; break; } @@ -1931,9 +1943,9 @@ if ( r_icache_cleanup_req ) break; r_icache_cleanup_req = true; - r_icache_cleanup_line = r_icache_paddr_save.read() >> (uint32_log2(m_icache_words) + 2); + r_icache_cleanup_line = r_icache_paddr_save.read() >> (uint32_log2(m_icache_words) + 2); + m_cpt_cc_cleanup_ins++; r_icache_inval_tlb_rsp = false; if ( r_icache_inval_rsp ) r_icache_inval_rsp = false; r_icache_fsm = ICACHE_IDLE; - m_cost_ins_tlb_miss_frz++; break; } @@ -1944,5 +1956,6 @@ { r_icache_cleanup_req = true; - r_icache_cleanup_line = r_icache_paddr_save.read() >> (uint32_log2(m_icache_words) + 2); + r_icache_cleanup_line = r_icache_paddr_save.read() >> (uint32_log2(m_icache_words) + 2); + m_cpt_cc_cleanup_ins++; r_icache_fsm = ICACHE_IDLE; r_icache_inval_rsp = false; @@ -1956,6 +1969,5 @@ r_icache_cleanup_req = r_icache.update(r_icache_paddr_save.read(), buf, &victim_index); - r_icache_cleanup_line = victim_index; - + r_icache_cleanup_line = victim_index; m_cpt_cc_cleanup_ins++; r_icache_fsm = ICACHE_IDLE; } @@ -1977,6 +1989,16 @@ case ICACHE_CC_INVAL: { - if ( ireq.valid ) m_cost_ins_waste_wait_frz++; m_cpt_icache_dir_read += m_icache_ways; + /* activity counter */ + if ( (( r_icache_fsm_save == ICACHE_BIS ) ||( r_icache_fsm_save == ICACHE_MISS_WAIT ) || ( r_icache_fsm_save == ICACHE_MISS_UPDT ) ) && ( ireq.valid ) ) + { + m_cost_ins_miss_frz++; + } + if( (( r_icache_fsm_save == ICACHE_TLB1_READ ) || ( r_icache_fsm_save == ICACHE_TLB2_READ ) || + ( r_icache_fsm_save == ICACHE_TLB1_WRITR ) || ( r_icache_fsm_save == ICACHE_TLB2_WRITE ) || + ( r_icache_fsm_save == ICACHE_TLB1_UPDT ) || ( r_icache_fsm_save == ICACHE_TLB2_UPDT )) && (ireq.valid) ) + { + m_cost_ins_tlb_miss_frz++; + } // invalidate cache @@ -1999,5 +2021,15 @@ case ICACHE_TLB_CC_INVAL: { - if ( ireq.valid ) m_cost_ins_waste_wait_frz++; + /* activity counter */ + if ( (( r_icache_fsm_save == ICACHE_BIS ) ||( r_icache_fsm_save == ICACHE_MISS_WAIT ) || ( r_icache_fsm_save == ICACHE_MISS_UPDT ) ) && ( ireq.valid ) ) + { + m_cost_ins_miss_frz++; + } + if( (( r_icache_fsm_save == ICACHE_TLB1_READ ) || ( r_icache_fsm_save == ICACHE_TLB2_READ ) || + ( r_icache_fsm_save == ICACHE_TLB1_WRITR ) || ( r_icache_fsm_save == ICACHE_TLB2_WRITE ) || + ( r_icache_fsm_save == ICACHE_TLB1_UPDT ) || ( r_icache_fsm_save == ICACHE_TLB2_UPDT )) && (ireq.valid) ) + { + m_cost_ins_tlb_miss_frz++; + } if ( r_itlb_inval_req ) break; @@ -2148,5 +2180,4 @@ r_dcache_fsm = DCACHE_CC_CHECK; r_dcache_fsm_save = r_dcache_fsm; - if ( dreq.valid ) m_cost_data_waste_wait_frz++; break; } @@ -2194,5 +2225,4 @@ r_dcache_fsm = DCACHE_CC_CHECK; r_dcache_fsm_save = DCACHE_IDLE; - if ( dreq.valid ) m_cost_data_waste_wait_frz++; break; } @@ -2202,6 +2232,4 @@ { r_dcache_fsm = DCACHE_ITLB_CLEANUP; - m_cpt_ins_tlb_cleanup++; - if ( dreq.valid ) m_cost_data_waste_wait_frz++; break; } @@ -2209,4 +2237,5 @@ if ( r_itlb_read_dcache_req ) { + if ( dreq.valid ) m_cost_ins_tlb_occup_cache_frz++; data_t rsp_itlb_miss; data_t rsp_itlb_ppn; @@ -2225,4 +2254,5 @@ if ( itlb_hit_dcache ) // ins TLB request hits in data cache { + if (!((rsp_itlb_miss & PTE_T_MASK ) >> PTE_T_SHIFT)) m_cpt_ins_tlb_hit_dcache++; r_dcache_rsp_itlb_miss = rsp_itlb_miss; r_dcache_rsp_itlb_ppn = rsp_itlb_ppn; @@ -2241,5 +2271,4 @@ r_dcache_fsm = DCACHE_ITLB_READ; } - if ( dreq.valid ) m_cost_data_waste_wait_frz++; } else if ( r_itlb_acc_dcache_req ) // ins tlb write access bit @@ -2248,6 +2277,6 @@ assert(write_hit && "Write on miss ignores data"); r_dcache_itlb_ll_acc_req = true; - r_dcache_fsm = DCACHE_ITLB_LL_WAIT; - if ( dreq.valid ) m_cost_data_waste_wait_frz++; + r_dcache_fsm = DCACHE_ITLB_LL_WAIT; + m_cpt_dcache_data_write++; } else if (dreq.valid) @@ -2630,5 +2659,5 @@ r_dcache_hit_p_save = dcache_hit_p; r_dcache_fsm = DCACHE_BIS; - m_cost_data_miss_frz++; + m_cost_data_tlb_miss_frz++; } else // cached or uncached access with a correct speculative physical address @@ -2730,5 +2759,5 @@ m_cpt_write++; if ( dcache_cached ) m_cpt_write_cached++; - + m_cost_write_frz++; if ( dcache_hit_c && dcache_cached ) // cache update required { @@ -2737,4 +2766,6 @@ else if ( !dcache_pte_info.d && (r_mmu_mode.read() & DATA_TLB_MASK) ) // dirty bit update required { + m_cpt_data_tlb_update_dirty++; + m_cost_data_tlb_update_dirty_frz++; if ( dcache_tlb.getpagesize(dcache_tlb_way, dcache_tlb_set) ) // 2M page size, one level page table { @@ -2743,5 +2774,4 @@ r_dcache_tlb_ll_dirty_req = true; r_dcache_fsm = DCACHE_LL_DIRTY_WAIT; - m_cpt_data_tlb_write_dirty++; } else // 4k page size, two levels page table @@ -2753,5 +2783,4 @@ r_dcache_tlb_ll_dirty_req = true; r_dcache_fsm = DCACHE_LL_DIRTY_WAIT; - m_cpt_data_tlb_write_dirty++; } else // get PTBA to calculate the physical address of PTE @@ -2763,5 +2792,4 @@ } } - m_cost_data_tlb_miss_frz++; } else // no cache update, not dirty bit update @@ -2812,5 +2840,5 @@ r_dcache_fsm = DCACHE_CC_CHECK; r_dcache_fsm_save = r_dcache_fsm; - m_cost_data_waste_wait_frz++; + if ( dreq.valid ) m_cost_data_miss_frz++; break; } @@ -2821,5 +2849,5 @@ r_dcache_inval_tlb_rsp = false; r_dcache_fsm = DCACHE_IDLE; - m_cost_data_tlb_miss_frz++; + if ( dreq.valid ) m_cost_data_miss_frz++; break; } @@ -2866,4 +2894,6 @@ else if (!r_dcache_dirty_save && (r_mmu_mode.read() & DATA_TLB_MASK)) // dirty bit update required { + m_cpt_data_tlb_update_dirty++; + m_cost_data_tlb_update_dirty_frz++; if (dcache_tlb.getpagesize(r_dcache_tlb_way_save, r_dcache_tlb_set_save)) { @@ -2872,5 +2902,4 @@ r_dcache_tlb_ll_dirty_req = true; r_dcache_fsm = DCACHE_LL_DIRTY_WAIT; - m_cpt_data_tlb_write_dirty++; } else @@ -2882,5 +2911,4 @@ r_dcache_tlb_ll_dirty_req = true; r_dcache_fsm = DCACHE_LL_DIRTY_WAIT; - m_cpt_data_tlb_write_dirty++; } else @@ -2892,5 +2920,4 @@ } } - m_cost_data_tlb_miss_frz++; } else // no cache update, not dirty bit update @@ -2914,4 +2941,6 @@ case DCACHE_LL_DIRTY_WAIT: { + m_cost_data_tlb_update_dirty_frz++; + // external cache invalidate request if ( r_tgt_dcache_req ) @@ -2919,5 +2948,4 @@ r_dcache_fsm = DCACHE_CC_CHECK; r_dcache_fsm_save = r_dcache_fsm; - m_cost_data_waste_wait_frz++; break; } @@ -2963,5 +2991,4 @@ r_dcache_inval_tlb_rsp = false; r_dcache_fsm = DCACHE_IDLE; - m_cost_data_tlb_miss_frz++; } else if ( r_dcache_inval_rsp ) @@ -2983,4 +3010,5 @@ case DCACHE_SC_DIRTY_WAIT: { + m_cost_data_tlb_update_dirty_frz++; // external cache invalidate request if ( r_tgt_dcache_req ) @@ -2988,5 +3016,4 @@ r_dcache_fsm = DCACHE_CC_CHECK; r_dcache_fsm_save = r_dcache_fsm; - m_cost_data_waste_wait_frz++; break; } @@ -3018,5 +3045,4 @@ r_dcache_fsm = DCACHE_IDLE; if (r_dcache_tlb_sc_fail) r_dcache_tlb_sc_fail = false; - m_cost_data_tlb_miss_frz++; } else if ( r_dcache_inval_rsp ) @@ -3030,5 +3056,6 @@ r_dcache_tlb_ll_dirty_req = true; r_dcache_tlb_sc_fail = false; - r_dcache_fsm = DCACHE_LL_DIRTY_WAIT; + r_dcache_fsm = DCACHE_LL_DIRTY_WAIT; + m_cpt_data_tlb_update_dirty++; } else @@ -3050,5 +3077,4 @@ r_dcache_fsm = DCACHE_CC_CHECK; r_dcache_fsm_save = r_dcache_fsm; - m_cost_data_waste_wait_frz++; break; } @@ -3059,5 +3085,4 @@ r_dcache_inval_tlb_rsp = false; r_dcache_fsm = DCACHE_IDLE; - m_cost_data_tlb_miss_frz++; break; } @@ -3099,5 +3124,6 @@ r_dcache_tlb_ll_dirty_req = true; r_dcache_fsm = DCACHE_LL_DIRTY_WAIT; - m_cpt_data_tlb_write_dirty++; + m_cpt_dcache_data_write++; + m_cost_data_tlb_update_dirty_frz++; } else @@ -3108,4 +3134,5 @@ else // PTE { + m_cpt_data_tlb_hit_dcache++; r_dcache_ptba_ok = false; if ( (m_srcid_rw >> 4) == ((r_dcache_tlb_paddr.read() & ((1<<(m_paddr_nbits - PAGE_M_NBITS))-1)) >> (m_paddr_nbits - PAGE_M_NBITS -10)) ) // local @@ -3123,5 +3150,7 @@ assert(write_hit && "Write on miss ignores data"); r_dcache_fsm = DCACHE_TLB1_LL_WAIT; - m_cpt_ins_tlb_write_et++; + m_cpt_dcache_data_write++; + m_cpt_data_tlb_update_acc++; + m_cost_data_tlb_update_acc_frz++; } } @@ -3140,5 +3169,7 @@ assert(write_hit && "Write on miss ignores data"); r_dcache_fsm = DCACHE_TLB1_LL_WAIT; - m_cpt_ins_tlb_write_et++; + m_cpt_dcache_data_write++; + m_cpt_data_tlb_update_acc++; + m_cost_data_tlb_update_acc_frz++; } } @@ -3156,4 +3187,6 @@ case DCACHE_TLB1_LL_WAIT: { + if ( dreq.valid ) m_cost_data_tlb_miss_frz++; + m_cost_data_tlb_update_acc_frz++; // external cache invalidate request if ( r_tgt_dcache_req ) @@ -3161,5 +3194,4 @@ r_dcache_fsm = DCACHE_CC_CHECK; r_dcache_fsm_save = r_dcache_fsm; - m_cost_data_waste_wait_frz++; break; } @@ -3205,5 +3237,4 @@ r_dcache_inval_tlb_rsp = false; r_dcache_fsm = DCACHE_IDLE; - m_cost_data_tlb_miss_frz++; } else if ( r_dcache_inval_rsp ) @@ -3225,4 +3256,6 @@ case DCACHE_TLB1_SC_WAIT: { + if ( dreq.valid ) m_cost_data_tlb_miss_frz++; + m_cost_data_tlb_update_acc_frz++; // external cache invalidate request if ( r_tgt_dcache_req ) @@ -3230,5 +3263,4 @@ r_dcache_fsm = DCACHE_CC_CHECK; r_dcache_fsm_save = r_dcache_fsm; - m_cost_data_waste_wait_frz++; break; } @@ -3260,5 +3292,4 @@ r_dcache_fsm = DCACHE_IDLE; if (r_dcache_tlb_sc_fail) r_dcache_tlb_sc_fail = false; - m_cost_data_tlb_miss_frz++; } else if ( r_dcache_inval_rsp ) @@ -3272,5 +3303,6 @@ r_dcache_tlb_sc_fail = false; r_dcache_tlb_ll_acc_req = true; - r_dcache_fsm = DCACHE_TLB1_LL_WAIT; + r_dcache_fsm = DCACHE_TLB1_LL_WAIT; + m_cpt_data_tlb_update_acc++; } else @@ -3285,5 +3317,5 @@ case DCACHE_TLB1_READ: { - m_cost_data_tlb_miss_frz++; + if ( dreq.valid ) m_cost_data_tlb_miss_frz++; // external cache invalidate request @@ -3292,5 +3324,4 @@ r_dcache_fsm = DCACHE_CC_CHECK; r_dcache_fsm_save = r_dcache_fsm; - m_cost_data_waste_wait_frz++; break; } @@ -3328,4 +3359,5 @@ r_dcache_cleanup_req = true; r_dcache_cleanup_line = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words) + 2); + m_cpt_cc_cleanup_data++; r_dcache_fsm = DCACHE_IDLE; r_dcache_inval_rsp = false; @@ -3348,5 +3380,4 @@ r_dcache_fsm = DCACHE_CC_CHECK; r_dcache_fsm_save = r_dcache_fsm; - m_cost_data_waste_wait_frz++; break; } @@ -3357,5 +3388,4 @@ r_dcache_inval_tlb_rsp = false; r_dcache_fsm = DCACHE_IDLE; - m_cost_data_tlb_miss_frz++; break; } @@ -3374,5 +3404,6 @@ { r_dcache_cleanup_req = true; - r_dcache_cleanup_line = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words) + 2); + r_dcache_cleanup_line = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words) + 2); + m_cpt_cc_cleanup_data++; r_dcache_fsm = DCACHE_IDLE; r_dcache_inval_rsp = false; @@ -3396,4 +3427,5 @@ r_dcache_cleanup_req = true; r_dcache_cleanup_line = victim_index; + m_cpt_cc_cleanup_data++; r_dcache_fsm = DCACHE_TLB_CC_INVAL; r_dcache_fsm_save = r_dcache_fsm; @@ -3403,4 +3435,5 @@ r_dcache.update(r_dcache_tlb_paddr, way, set, r_dcache_miss_buf); r_dcache.read(r_dcache_tlb_paddr, &rsp_dtlb_miss); + m_cpt_data_tlb_occup_cache++; if ( !(rsp_dtlb_miss >> PTE_V_SHIFT) ) // unmapped @@ -3433,5 +3466,7 @@ r_dcache_tlb_ll_dirty_req = true; r_dcache_fsm = DCACHE_LL_DIRTY_WAIT; - m_cpt_data_tlb_write_dirty++; + m_cpt_dcache_data_write++; + m_cpt_data_tlb_update_dirty++; + m_cost_data_tlb_update_dirty_frz++; } else @@ -3457,5 +3492,7 @@ assert(write_hit && "Write on miss ignores data"); r_dcache_fsm = DCACHE_TLB1_LL_WAIT; - m_cpt_ins_tlb_write_et++; + m_cpt_dcache_data_write++; + m_cpt_data_tlb_update_acc++; + m_cost_data_tlb_update_acc_frz++; } } @@ -3474,5 +3511,7 @@ assert(write_hit && "Write on miss ignores data"); r_dcache_fsm = DCACHE_TLB1_LL_WAIT; - m_cpt_ins_tlb_write_et++; + m_cpt_dcache_data_write++; + m_cpt_data_tlb_update_acc++; + m_cost_data_tlb_update_acc_frz++; } } @@ -3491,5 +3530,4 @@ r_dcache_fsm = DCACHE_CC_CHECK; r_dcache_fsm_save = r_dcache_fsm; - m_cost_data_waste_wait_frz++; break; } @@ -3523,5 +3561,4 @@ r_dcache_fsm = DCACHE_CC_CHECK; r_dcache_fsm_save = r_dcache_fsm; - m_cost_data_waste_wait_frz++; break; } @@ -3532,5 +3569,4 @@ r_dcache_inval_tlb_rsp = false; r_dcache_fsm = DCACHE_IDLE; - m_cost_data_tlb_miss_frz++; break; } @@ -3571,4 +3607,5 @@ else { + m_cpt_data_tlb_hit_dcache++; if ( (m_srcid_rw >> 4) == ((r_dcache_tlb_paddr.read() & ((1<<(m_paddr_nbits - PAGE_M_NBITS))-1)) >> (m_paddr_nbits - PAGE_M_NBITS -10)) ) // local { @@ -3587,5 +3624,7 @@ assert(write_hit && "Write on miss ignores data"); r_dcache_fsm = DCACHE_TLB2_LL_WAIT; - m_cpt_ins_tlb_write_et++; + m_cpt_dcache_data_write++; + m_cpt_data_tlb_update_acc++; + m_cost_data_tlb_update_acc_frz++; } } @@ -3606,5 +3645,7 @@ assert(write_hit && "Write on miss ignores data"); r_dcache_fsm = DCACHE_TLB2_LL_WAIT; - m_cpt_ins_tlb_write_et++; + m_cpt_dcache_data_write++; + m_cpt_data_tlb_update_acc++; + m_cost_data_tlb_update_acc_frz++; } } @@ -3622,4 +3663,7 @@ case DCACHE_TLB2_LL_WAIT: { + if ( dreq.valid ) m_cost_data_tlb_miss_frz++; + m_cost_data_tlb_update_acc_frz++; + // external cache invalidate request if ( r_tgt_dcache_req ) @@ -3627,5 +3671,4 @@ r_dcache_fsm = DCACHE_CC_CHECK; r_dcache_fsm_save = r_dcache_fsm; - m_cost_data_waste_wait_frz++; break; } @@ -3671,5 +3714,4 @@ r_dcache_inval_tlb_rsp = false; r_dcache_fsm = DCACHE_IDLE; - m_cost_data_tlb_miss_frz++; } else if ( r_dcache_inval_rsp ) @@ -3691,4 +3733,6 @@ case DCACHE_TLB2_SC_WAIT: { + if ( dreq.valid ) m_cost_data_tlb_miss_frz++; + m_cost_data_tlb_update_acc_frz++; // external cache invalidate request if ( r_tgt_dcache_req ) @@ -3696,5 +3740,4 @@ r_dcache_fsm = DCACHE_CC_CHECK; r_dcache_fsm_save = r_dcache_fsm; - m_cost_data_waste_wait_frz++; break; } @@ -3726,5 +3769,4 @@ if (r_dcache_tlb_sc_fail) r_dcache_tlb_sc_fail = false; r_dcache_fsm = DCACHE_IDLE; - m_cost_data_tlb_miss_frz++; } else if ( r_dcache_inval_rsp ) @@ -3738,5 +3780,6 @@ r_dcache_tlb_ll_acc_req = true; r_dcache_tlb_sc_fail = false; - r_dcache_fsm = DCACHE_TLB2_LL_WAIT; + r_dcache_fsm = DCACHE_TLB2_LL_WAIT; + m_cpt_data_tlb_update_acc++; } else @@ -3758,5 +3801,4 @@ r_dcache_fsm = DCACHE_CC_CHECK; r_dcache_fsm_save = r_dcache_fsm; - m_cost_data_waste_wait_frz++; break; } @@ -3794,4 +3836,5 @@ r_dcache_cleanup_req = true; r_dcache_cleanup_line = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words) + 2); + m_cpt_cc_cleanup_data++; r_dcache_fsm = DCACHE_IDLE; r_dcache_inval_rsp = false; @@ -3814,5 +3857,4 @@ r_dcache_fsm = DCACHE_CC_CHECK; r_dcache_fsm_save = r_dcache_fsm; - m_cost_data_waste_wait_frz++; break; } @@ -3823,5 +3865,4 @@ r_dcache_inval_tlb_rsp = false; r_dcache_fsm = DCACHE_IDLE; - m_cost_data_tlb_miss_frz++; break; } @@ -3842,4 +3883,5 @@ r_dcache_cleanup_req = true; r_dcache_cleanup_line = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words) + 2); + m_cpt_cc_cleanup_data++; r_dcache_fsm = DCACHE_IDLE; r_dcache_inval_rsp = false; @@ -3863,4 +3905,5 @@ r_dcache_cleanup_req = true; r_dcache_cleanup_line = victim_index; + m_cpt_cc_cleanup_data++; r_dcache_fsm = DCACHE_TLB_CC_INVAL; r_dcache_fsm_save = r_dcache_fsm; @@ -3870,4 +3913,5 @@ r_dcache.update(r_dcache_tlb_paddr, way, set, r_dcache_miss_buf); r_dcache.read(r_dcache_tlb_paddr, &rsp_dtlb_miss); + m_cpt_data_tlb_occup_cache++; bool tlb_hit_ppn = r_dcache.read(r_dcache_tlb_paddr.read()+4, &tlb_data_ppn); @@ -3911,5 +3955,7 @@ assert(write_hit && "Write on miss ignores data"); r_dcache_fsm = DCACHE_TLB2_LL_WAIT; - m_cpt_ins_tlb_write_et++; + m_cpt_dcache_data_write++; + m_cpt_data_tlb_update_acc++; + m_cost_data_tlb_update_acc_frz++; } } @@ -3930,5 +3976,7 @@ assert(write_hit && "Write on miss ignores data"); r_dcache_fsm = DCACHE_TLB2_LL_WAIT; - m_cpt_ins_tlb_write_et++; + m_cpt_dcache_data_write++; + m_cpt_data_tlb_update_acc++; + m_cost_data_tlb_update_acc_frz++; } } @@ -3947,5 +3995,4 @@ r_dcache_fsm = DCACHE_CC_CHECK; r_dcache_fsm_save = r_dcache_fsm; - m_cost_data_waste_wait_frz++; break; } @@ -4026,5 +4073,4 @@ r_dcache_fsm = DCACHE_CC_CHECK; r_dcache_fsm_save = r_dcache_fsm; - m_cost_data_waste_wait_frz++; break; } @@ -4048,4 +4094,5 @@ r_dcache_cleanup_req = true; r_dcache_cleanup_line = victim_index; + m_cpt_cc_cleanup_data++; r_dcache_way = way + ((set+1)/m_dcache_sets); r_dcache_set = (set+1) % m_dcache_sets; @@ -4099,5 +4146,4 @@ r_dcache_fsm = DCACHE_CC_CHECK; r_dcache_fsm_save = r_dcache_fsm; - m_cost_data_waste_wait_frz++; break; } @@ -4126,4 +4172,5 @@ r_dcache_cleanup_req = r_dcache.inval(dpaddr, &way, &set); r_dcache_cleanup_line = dpaddr >> (uint32_log2(m_dcache_words)+2); + m_cpt_cc_cleanup_data++; if ( r_dcache_in_itlb[way*m_dcache_sets+set] || r_dcache_in_dtlb[way*m_dcache_sets+set] ) @@ -4156,5 +4203,4 @@ r_dcache_fsm = DCACHE_CC_CHECK; r_dcache_fsm_save = r_dcache_fsm; - m_cost_data_waste_wait_frz++; break; } @@ -4168,4 +4214,5 @@ r_dcache_cleanup_req = r_dcache.inval(dpaddr, &way, &set); r_dcache_cleanup_line = dpaddr >> (uint32_log2(m_dcache_words)+2); + m_cpt_cc_cleanup_data++; if ( r_dcache_in_itlb[way*m_dcache_sets+set] || r_dcache_in_dtlb[way*m_dcache_sets+set] ) @@ -4210,5 +4257,4 @@ r_dcache_fsm = DCACHE_CC_CHECK; r_dcache_fsm_save = r_dcache_fsm; - m_cost_data_waste_wait_frz++; break; } @@ -4232,4 +4278,5 @@ r_dcache_cleanup_req = true; r_dcache_cleanup_line = r_dcache_paddr_save.read() >> (uint32_log2(m_dcache_words) + 2); + m_cpt_cc_cleanup_data++; r_dcache_fsm = DCACHE_IDLE; r_dcache_inval_tlb_rsp = false; @@ -4243,4 +4290,5 @@ r_dcache_cleanup_req = true; r_dcache_cleanup_line = r_dcache_paddr_save.read() >> (uint32_log2(m_dcache_words) + 2); + m_cpt_cc_cleanup_data++; r_dcache_fsm = DCACHE_IDLE; r_dcache_inval_rsp = false; @@ -4262,5 +4310,4 @@ r_dcache_fsm = DCACHE_CC_CHECK; r_dcache_fsm_save = r_dcache_fsm; - m_cost_data_waste_wait_frz++; break; } @@ -4271,8 +4318,8 @@ r_dcache_cleanup_req = true; r_dcache_cleanup_line = r_dcache_paddr_save.read() >> (uint32_log2(m_dcache_words) + 2); + m_cpt_cc_cleanup_data++; r_dcache_inval_tlb_rsp = false; r_dcache_inval_rsp = false; r_dcache_fsm = DCACHE_IDLE; - m_cost_data_tlb_miss_frz++; break; } @@ -4284,7 +4331,4 @@ size_t set = 0; - m_cpt_dcache_data_write++; - m_cpt_dcache_dir_write++; - // Using tlb entry is in the invalidated cache line if ( r_dcache_inval_rsp ) @@ -4292,4 +4336,5 @@ r_dcache_cleanup_req = true; r_dcache_cleanup_line = r_dcache_paddr_save.read() >> (uint32_log2(m_dcache_words) + 2); + m_cpt_cc_cleanup_data++; r_dcache_fsm = DCACHE_IDLE; r_dcache_inval_rsp = false; @@ -4313,4 +4358,5 @@ r_dcache_cleanup_req = true; r_dcache_cleanup_line = victim_index; + m_cpt_cc_cleanup_data++; if ( r_dcache_in_itlb[m_dcache_sets*way+set] || r_dcache_in_dtlb[m_dcache_sets*way+set] ) { @@ -4320,5 +4366,6 @@ } } - + m_cpt_dcache_dir_write++; + m_cpt_dcache_data_write++; r_dcache.update(r_dcache_paddr_save.read(), way, set, r_dcache_miss_buf); r_dcache_fsm = DCACHE_IDLE; @@ -4336,5 +4383,4 @@ r_dcache_fsm = DCACHE_CC_CHECK; r_dcache_fsm_save = r_dcache_fsm; - m_cost_data_waste_wait_frz++; break; } @@ -4364,4 +4410,5 @@ r_dcache_cleanup_req = r_dcache.inval(r_dcache_paddr_save, &way, &set); r_dcache_cleanup_line = r_dcache_paddr_save.read() >> (uint32_log2(m_dcache_words)+2); + m_cpt_cc_cleanup_data++; if ( r_dcache_in_itlb[way*m_dcache_sets+set] || r_dcache_in_dtlb[way*m_dcache_sets+set] ) @@ -4392,4 +4439,5 @@ { m_cost_write_frz++; + m_cpt_dcache_data_write++; size_t way = 0; size_t set = 0; @@ -4419,11 +4467,12 @@ if ( !r_dcache_dirty_save && (r_mmu_mode.read() & DATA_TLB_MASK) ) { + m_cpt_data_tlb_update_dirty++; + m_cost_data_tlb_update_dirty_frz++; if ( dcache_tlb.getpagesize(r_dcache_tlb_way_save, r_dcache_tlb_set_save) ) // 2M page size, one level page table - { + { r_dcache_pte_update = dcache_tlb.getpte(r_dcache_tlb_way_save, r_dcache_tlb_set_save) | PTE_D_MASK; r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2); r_dcache_tlb_ll_dirty_req = true; - r_dcache_fsm = DCACHE_LL_DIRTY_WAIT; - m_cpt_data_tlb_write_dirty++; + r_dcache_fsm = DCACHE_LL_DIRTY_WAIT; } else @@ -4435,5 +4484,4 @@ r_dcache_tlb_ll_dirty_req = true; r_dcache_fsm = DCACHE_LL_DIRTY_WAIT; - m_cpt_data_tlb_write_dirty++; } else @@ -4457,5 +4505,5 @@ case DCACHE_WRITE_DIRTY: { - m_cost_data_tlb_miss_frz++; + m_cost_data_tlb_update_dirty_frz++; // external cache invalidate request @@ -4464,5 +4512,4 @@ r_dcache_fsm = DCACHE_CC_CHECK; r_dcache_fsm_save = r_dcache_fsm; - m_cost_data_waste_wait_frz++; break; } @@ -4482,4 +4529,5 @@ } + m_cpt_dcache_data_write++; r_dcache.write(r_dcache_tlb_paddr, r_dcache_pte_update); dcache_tlb.setdirty(r_dcache_tlb_way_save, r_dcache_tlb_set_save); @@ -4502,5 +4550,5 @@ case DCACHE_ITLB_READ: { - m_cost_data_waste_wait_frz++; + if ( dreq.valid ) m_cost_ins_tlb_occup_cache_frz++; // external cache invalidate request @@ -4509,5 +4557,4 @@ r_dcache_fsm = DCACHE_CC_CHECK; r_dcache_fsm_save = r_dcache_fsm; - m_cost_data_waste_wait_frz++; break; } @@ -4531,4 +4578,5 @@ r_dcache_cleanup_req = true; r_dcache_cleanup_line = r_icache_paddr_save.read() >> (uint32_log2(m_dcache_words) + 2); + m_cpt_cc_cleanup_data++; r_dcache_fsm = DCACHE_IDLE; r_dcache_inval_rsp = false; @@ -4543,5 +4591,5 @@ case DCACHE_ITLB_UPDT: { - m_cost_data_waste_wait_frz++; + if ( dreq.valid ) m_cost_ins_tlb_occup_cache_frz++; // external cache invalidate request @@ -4550,5 +4598,4 @@ r_dcache_fsm = DCACHE_CC_CHECK; r_dcache_fsm_save = r_dcache_fsm; - m_cost_data_waste_wait_frz++; break; } @@ -4567,4 +4614,5 @@ r_dcache_cleanup_req = true; r_dcache_cleanup_line = r_icache_paddr_save.read() >> (uint32_log2(m_dcache_words) + 2); + m_cpt_cc_cleanup_data++; r_dcache_fsm = DCACHE_IDLE; r_dcache_inval_rsp = false; @@ -4588,4 +4636,5 @@ r_dcache_cleanup_req = true; r_dcache_cleanup_line = victim_index; + m_cpt_cc_cleanup_data++; if ( r_dcache_in_itlb[m_dcache_sets*way+set] || r_dcache_in_dtlb[m_dcache_sets*way+set] ) { @@ -4600,5 +4649,6 @@ r_dcache.setinbit(r_icache_paddr_save, r_dcache_in_itlb, true); bool itlb_hit_dcache = r_dcache.read(r_icache_paddr_save, &rsp_itlb_miss); - + m_cpt_ins_tlb_occup_cache++; + if ( r_itlb_k_read_dcache && itlb_hit_dcache ) { @@ -4619,4 +4669,5 @@ case DCACHE_ITLB_LL_WAIT: { + if ( dreq.valid ) m_cost_ins_tlb_occup_cache_frz++; // external cache invalidate request if ( r_tgt_dcache_req ) @@ -4624,5 +4675,4 @@ r_dcache_fsm = DCACHE_CC_CHECK; r_dcache_fsm_save = r_dcache_fsm; - m_cost_data_waste_wait_frz++; break; } @@ -4651,5 +4701,4 @@ r_dcache_inval_rsp = false; r_dcache_fsm = DCACHE_IDLE; - m_cost_data_tlb_miss_frz++; } else @@ -4666,4 +4715,5 @@ case DCACHE_ITLB_SC_WAIT: { + if ( dreq.valid ) m_cost_ins_tlb_occup_cache_frz++; // external cache invalidate request if ( r_tgt_dcache_req ) @@ -4671,5 +4721,4 @@ r_dcache_fsm = DCACHE_CC_CHECK; r_dcache_fsm_save = r_dcache_fsm; - m_cost_data_waste_wait_frz++; break; } @@ -4692,5 +4741,4 @@ r_dcache_fsm = DCACHE_IDLE; if (r_dcache_tlb_sc_fail) r_dcache_tlb_sc_fail = false; - m_cost_data_tlb_miss_frz++; } else if ( r_dcache_tlb_sc_fail ) @@ -4712,8 +4760,21 @@ case DCACHE_CC_CHECK: // read directory in case of invalidate or update request { - if ( dreq.valid ) m_cost_data_waste_wait_frz++; - m_cpt_dcache_dir_read += m_dcache_ways; m_cpt_dcache_data_read += m_dcache_ways; + + /* activity counter */ + if ( (( r_dcache_fsm_save == DCACHE_BIS ) ||( r_dcache_fsm_save == DCACHE_MISS_WAIT ) || ( r_dcache_fsm_save == DCACHE_MISS_UPDT ) ) && ( dreq.valid ) ) + { + m_cost_data_miss_frz++; + } + if( (( r_dcache_fsm_save == DCACHE_DTLB1_READ_CACHE ) || ( r_dcache_fsm_save == DCACHE_DTLB2_READ_CACHE ) || + ( r_dcache_fsm_save == DCACHE_TLB1_READ ) || ( r_dcache_fsm_save == DCACHE_TLB2_READ ) || + ( r_dcache_fsm_save == DCACHE_TLB1_LL_WAIT ) || ( r_dcache_fsm_save == DCACHE_TLB2_LL_WAIT ) || + ( r_dcache_fsm_save == DCACHE_TLB1_SC_WAIT ) || ( r_dcache_fsm_save == DCACHE_TLB2_SC_WAIT ) || + ( r_dcache_fsm_save == DCACHE_TLB1_READ_UPDT ) || ( r_dcache_fsm_save == DCACHE_TLB2_READ_UPDT ) || + ( r_dcache_fsm_save == DCACHE_TLB1_UPDT ) || ( r_dcache_fsm_save == DCACHE_TLB2_UPDT )) && (dreq.valid) ) + { + m_cost_data_tlb_miss_frz++; + } // DCACHE_TLB1_LL_WAIT DCACHE_TLB1_SC_WAIT DCACHE_LL_DIRTY_WAIT DCACHE_WRITE_DIRTY DCACHE_ITLB_LL_WAIT DCACHE_ITLB_SC_WAIT @@ -4792,5 +4853,18 @@ case DCACHE_CC_UPDT: // update directory and data cache { - if ( dreq.valid ) m_cost_data_waste_wait_frz++; + /* activity counter */ + if ( (( r_dcache_fsm_save == DCACHE_BIS ) ||( r_dcache_fsm_save == DCACHE_MISS_WAIT ) || ( r_dcache_fsm_save == DCACHE_MISS_UPDT ) ) && ( dreq.valid ) ) + { + m_cost_data_miss_frz++; + } + if( (( r_dcache_fsm_save == DCACHE_DTLB1_READ_CACHE ) || ( r_dcache_fsm_save == DCACHE_DTLB2_READ_CACHE ) || + ( r_dcache_fsm_save == DCACHE_TLB1_READ ) || ( r_dcache_fsm_save == DCACHE_TLB2_READ ) || + ( r_dcache_fsm_save == DCACHE_TLB1_LL_WAIT ) || ( r_dcache_fsm_save == DCACHE_TLB2_LL_WAIT ) || + ( r_dcache_fsm_save == DCACHE_TLB1_SC_WAIT ) || ( r_dcache_fsm_save == DCACHE_TLB2_SC_WAIT ) || + ( r_dcache_fsm_save == DCACHE_TLB1_READ_UPDT ) || ( r_dcache_fsm_save == DCACHE_TLB2_READ_UPDT ) || + ( r_dcache_fsm_save == DCACHE_TLB1_UPDT ) || ( r_dcache_fsm_save == DCACHE_TLB2_UPDT )) && (dreq.valid) ) + { + m_cost_data_tlb_miss_frz++; + } m_cpt_dcache_dir_write++; @@ -4810,5 +4884,18 @@ case DCACHE_CC_INVAL: // invalidate a cache line { - if ( dreq.valid ) m_cost_data_waste_wait_frz++; + /* activity counter */ + if ( (( r_dcache_fsm_save == DCACHE_BIS ) ||( r_dcache_fsm_save == DCACHE_MISS_WAIT ) || ( r_dcache_fsm_save == DCACHE_MISS_UPDT ) ) && ( dreq.valid ) ) + { + m_cost_data_miss_frz++; + } + if( (( r_dcache_fsm_save == DCACHE_DTLB1_READ_CACHE ) || ( r_dcache_fsm_save == DCACHE_DTLB2_READ_CACHE ) || + ( r_dcache_fsm_save == DCACHE_TLB1_READ ) || ( r_dcache_fsm_save == DCACHE_TLB2_READ ) || + ( r_dcache_fsm_save == DCACHE_TLB1_LL_WAIT ) || ( r_dcache_fsm_save == DCACHE_TLB2_LL_WAIT ) || + ( r_dcache_fsm_save == DCACHE_TLB1_SC_WAIT ) || ( r_dcache_fsm_save == DCACHE_TLB2_SC_WAIT ) || + ( r_dcache_fsm_save == DCACHE_TLB1_READ_UPDT ) || ( r_dcache_fsm_save == DCACHE_TLB2_READ_UPDT ) || + ( r_dcache_fsm_save == DCACHE_TLB1_UPDT ) || ( r_dcache_fsm_save == DCACHE_TLB2_UPDT )) && (dreq.valid) ) + { + m_cost_data_tlb_miss_frz++; + } r_tgt_dcache_rsp = r_dcache.inval(r_tgt_addr.read()); @@ -4820,5 +4907,18 @@ case DCACHE_CC_NOP: // no external hit { - if ( dreq.valid ) m_cost_data_waste_wait_frz++; + /* activity counter */ + if ( (( r_dcache_fsm_save == DCACHE_BIS ) ||( r_dcache_fsm_save == DCACHE_MISS_WAIT ) || ( r_dcache_fsm_save == DCACHE_MISS_UPDT ) ) && ( dreq.valid ) ) + { + m_cost_data_miss_frz++; + } + if( (( r_dcache_fsm_save == DCACHE_DTLB1_READ_CACHE ) || ( r_dcache_fsm_save == DCACHE_DTLB2_READ_CACHE ) || + ( r_dcache_fsm_save == DCACHE_TLB1_READ ) || ( r_dcache_fsm_save == DCACHE_TLB2_READ ) || + ( r_dcache_fsm_save == DCACHE_TLB1_LL_WAIT ) || ( r_dcache_fsm_save == DCACHE_TLB2_LL_WAIT ) || + ( r_dcache_fsm_save == DCACHE_TLB1_SC_WAIT ) || ( r_dcache_fsm_save == DCACHE_TLB2_SC_WAIT ) || + ( r_dcache_fsm_save == DCACHE_TLB1_READ_UPDT ) || ( r_dcache_fsm_save == DCACHE_TLB2_READ_UPDT ) || + ( r_dcache_fsm_save == DCACHE_TLB1_UPDT ) || ( r_dcache_fsm_save == DCACHE_TLB2_UPDT )) && (dreq.valid) ) + { + m_cost_data_tlb_miss_frz++; + } r_tgt_dcache_req = false; @@ -4838,5 +4938,18 @@ case DCACHE_TLB_CC_INVAL: { - if ( dreq.valid ) m_cost_data_waste_wait_frz++; + /* activity counter */ + if ( (( r_dcache_fsm_save == DCACHE_BIS ) ||( r_dcache_fsm_save == DCACHE_MISS_WAIT ) || ( r_dcache_fsm_save == DCACHE_MISS_UPDT ) ) && ( dreq.valid ) ) + { + m_cost_data_miss_frz++; + } + if( (( r_dcache_fsm_save == DCACHE_DTLB1_READ_CACHE ) || ( r_dcache_fsm_save == DCACHE_DTLB2_READ_CACHE ) || + ( r_dcache_fsm_save == DCACHE_TLB1_READ ) || ( r_dcache_fsm_save == DCACHE_TLB2_READ ) || + ( r_dcache_fsm_save == DCACHE_TLB1_LL_WAIT ) || ( r_dcache_fsm_save == DCACHE_TLB2_LL_WAIT ) || + ( r_dcache_fsm_save == DCACHE_TLB1_SC_WAIT ) || ( r_dcache_fsm_save == DCACHE_TLB2_SC_WAIT ) || + ( r_dcache_fsm_save == DCACHE_TLB1_READ_UPDT ) || ( r_dcache_fsm_save == DCACHE_TLB2_READ_UPDT ) || + ( r_dcache_fsm_save == DCACHE_TLB1_UPDT ) || ( r_dcache_fsm_save == DCACHE_TLB2_UPDT )) && (dreq.valid) ) + { + m_cost_data_tlb_miss_frz++; + } if ( r_dcache_itlb_inval_req || r_dcache_dtlb_inval_req ) break; @@ -4878,5 +4991,5 @@ case DCACHE_ITLB_CLEANUP: { - if ( dreq.valid ) m_cost_data_waste_wait_frz++; + if ( dreq.valid ) m_cost_data_miss_frz++; r_dcache.setinbit(((paddr_t)r_dcache_itlb_cleanup_line.read()*m_dcache_words*2), r_dcache_in_itlb, false); @@ -4973,5 +5086,16 @@ m_cpt_frz_cycles++; } - + if ( dreq.valid && !drsp.valid ) + { + m_cpt_dcache_frz_cycles++; + } + for (size_t way = 0; way < m_dcache_ways; way++ ) + { + for (size_t set = 0; set < m_dcache_sets; set++ ) + { + if (r_dcache_in_itlb[way*m_dcache_sets+set] || r_dcache_in_dtlb[way*m_dcache_sets+set]) + m_cpt_tlb_occup_dcache++; + } + } //////////////////////////////////////////////////////////////////////////// // VCI_CMD FSM @@ -5006,8 +5130,10 @@ { r_vci_cmd_fsm = CMD_INS_CLEANUP; + m_cpt_icleanup_transaction++; } else if (r_dcache_cleanup_req) { r_vci_cmd_fsm = CMD_DATA_CLEANUP; + m_cpt_dcleanup_transaction++; } else if (r_dcache_itlb_read_req) @@ -5019,10 +5145,10 @@ { r_vci_cmd_fsm = CMD_ITLB_ACC_LL; - m_cpt_itlb_write_transaction++; + m_cpt_itlb_ll_transaction++; } else if (r_dcache_itlb_sc_acc_req) { r_vci_cmd_fsm = CMD_ITLB_ACC_SC; - m_cpt_itlb_write_transaction++; + m_cpt_itlb_sc_transaction++; } else if (r_icache_miss_req) @@ -5034,5 +5160,5 @@ { r_vci_cmd_fsm = CMD_INS_UNC; - m_cpt_imiss_transaction++; + m_cpt_icache_unc_transaction++; } else if (r_dcache_tlb_read_req) @@ -5044,20 +5170,20 @@ { r_vci_cmd_fsm = CMD_DTLB_ACC_LL; - m_cpt_dtlb_write_transaction++; + m_cpt_dtlb_ll_transaction++; } else if (r_dcache_tlb_sc_acc_req) { r_vci_cmd_fsm = CMD_DTLB_ACC_SC; - m_cpt_dtlb_write_transaction++; + m_cpt_dtlb_sc_transaction++; } else if (r_dcache_tlb_ll_dirty_req) { r_vci_cmd_fsm = CMD_DTLB_DIRTY_LL; - m_cpt_dtlb_write_transaction++; + m_cpt_dtlb_ll_dirty_transaction++; } else if (r_dcache_tlb_sc_dirty_req) { r_vci_cmd_fsm = CMD_DTLB_DIRTY_SC; - m_cpt_dtlb_write_transaction++; + m_cpt_dtlb_sc_dirty_transaction++; } else if (r_dcache_write_req) @@ -5213,4 +5339,5 @@ case RSP_ITLB_ACC_LL: + m_cost_itlb_ll_transaction++; if ( ! p_vci_ini_rw.rspval.read() ) break; @@ -5232,4 +5359,5 @@ case RSP_ITLB_ACC_SC: + m_cost_itlb_sc_transaction++; if ( ! p_vci_ini_rw.rspval.read() ) break; @@ -5276,5 +5404,5 @@ case RSP_INS_UNC: - m_cost_imiss_transaction++; + m_cost_icache_unc_transaction++; if ( ! p_vci_ini_rw.rspval.read() ) break; @@ -5318,4 +5446,5 @@ case RSP_DTLB_ACC_LL: + m_cost_dtlb_ll_transaction++; if ( ! p_vci_ini_rw.rspval.read() ) break; @@ -5337,4 +5466,5 @@ case RSP_DTLB_ACC_SC: + m_cost_dtlb_sc_transaction++; if ( ! p_vci_ini_rw.rspval.read() ) break; @@ -5357,4 +5487,5 @@ case RSP_DTLB_DIRTY_LL: + m_cost_dtlb_ll_dirty_transaction++; if ( ! p_vci_ini_rw.rspval.read() ) break; @@ -5376,4 +5507,5 @@ case RSP_DTLB_DIRTY_SC: + m_cost_dtlb_sc_dirty_transaction++; if ( ! p_vci_ini_rw.rspval.read() ) break; @@ -5457,4 +5589,13 @@ case RSP_INS_CLEANUP: case RSP_DATA_CLEANUP: + if ( r_vci_rsp_fsm == RSP_INS_CLEANUP ) + { + m_cost_icleanup_transaction++; + } + else + { + m_cost_dcleanup_transaction++; + } + if ( ! p_vci_ini_c.rspval.read() ) break; Index: trunk/modules/vci_cc_vcache_wrapper_v1/caba/source/include/vci_cc_vcache_wrapper_v1.h =================================================================== --- trunk/modules/vci_cc_vcache_wrapper_v1/caba/source/include/vci_cc_vcache_wrapper_v1.h (revision 47) +++ trunk/modules/vci_cc_vcache_wrapper_v1/caba/source/include/vci_cc_vcache_wrapper_v1.h (revision 48) @@ -313,5 +313,4 @@ sc_signal r_dcache_way; sc_signal r_dcache_set; - sc_signal r_dcache_cleanup_check_req; sc_signal r_dcache_cleanup_req; sc_signal r_dcache_cleanup_line; @@ -347,5 +346,4 @@ sc_signal r_icache_way; sc_signal r_icache_set; - sc_signal r_icache_cleanup_check_req; sc_signal r_icache_cleanup_req; sc_signal r_icache_cleanup_line; @@ -383,6 +381,4 @@ sc_signal r_tgt_icache_req; sc_signal r_tgt_dcache_req; - sc_signal r_tgt_icache_tlb_req; - sc_signal r_tgt_dcache_tlb_req; sc_signal r_tgt_icache_rsp; sc_signal r_tgt_dcache_rsp; @@ -440,5 +436,4 @@ uint32_t m_cost_unc_read_frz; // number of frozen cycles related to uncached read of cache uint32_t m_cost_ins_miss_frz; // number of frozen cycles related to ins miss of cache - uint32_t m_cost_cc_wait_frz; // number of frozen cycles related to cc check uint32_t m_cpt_imiss_transaction; // number of VCI instruction miss transactions @@ -446,8 +441,10 @@ uint32_t m_cpt_unc_transaction; // number of VCI uncached read transactions uint32_t m_cpt_write_transaction; // number of VCI write transactions + uint32_t m_cpt_icache_unc_transaction; // number of VCI instruction uncached transactions uint32_t m_cost_imiss_transaction; // cumulated duration for VCI IMISS transactions uint32_t m_cost_dmiss_transaction; // cumulated duration for VCI DMISS transactions uint32_t m_cost_unc_transaction; // cumulated duration for VCI UNC transactions + uint32_t m_cost_icache_unc_transaction; // cumulated duration for VCI IUNC transactions uint32_t m_cost_write_transaction; // cumulated duration for VCI WRITE transactions uint32_t m_length_write_transaction; // cumulated length for VCI WRITE transactions @@ -456,35 +453,45 @@ uint32_t m_cpt_ins_tlb_read; // number of instruction tlb read uint32_t m_cpt_ins_tlb_miss; // number of instruction tlb miss - uint32_t m_cpt_ins_tlb_write_et; // number of instruction tlb write ET - + uint32_t m_cpt_ins_tlb_update_acc; // number of instruction tlb update acc uint32_t m_cpt_data_tlb_read; // number of data tlb read uint32_t m_cpt_data_tlb_miss; // number of data tlb miss - uint32_t m_cpt_data_tlb_write_et; // number of data tlb write ET - uint32_t m_cpt_data_tlb_write_dirty; // number of data tlb write dirty + uint32_t m_cpt_data_tlb_update_acc; // number of data tlb update acc + uint32_t m_cpt_data_tlb_update_dirty; // number of data tlb update dirty uint32_t m_cost_ins_tlb_miss_frz; // number of frozen cycles related to instruction tlb miss uint32_t m_cost_data_tlb_miss_frz; // number of frozen cycles related to data tlb miss - uint32_t m_cost_ins_tlb_flush_frz; // number of cycles for instruction tlb flush - uint32_t m_cost_data_tlb_flush_frz; // number of cycles for data tlb flush - uint32_t m_cost_ins_cache_flush_frz; // number of cycles for instruction cache flush - uint32_t m_cost_data_cache_flush_frz; // number of cycles for data cache flush - uint32_t m_cost_data_waste_wait_frz; + uint32_t m_cost_ins_tlb_update_acc_frz; // number of cycles for instruction tlb flush + uint32_t m_cost_data_tlb_update_acc_frz; // number of cycles for data tlb flush + uint32_t m_cost_data_tlb_update_dirty_frz; // number of cycles for instruction cache flush uint32_t m_cpt_itlbmiss_transaction; // number of itlb miss transactions - uint32_t m_cpt_itlb_write_transaction; // number of itlb write ET transactions + uint32_t m_cpt_itlb_ll_transaction; // number of itlb ll acc transactions + uint32_t m_cpt_itlb_sc_transaction; // number of itlb sc acc transactions uint32_t m_cpt_dtlbmiss_transaction; // number of dtlb miss transactions - uint32_t m_cpt_dtlb_write_transaction; // number of dtlb write ET and dirty transactions + uint32_t m_cpt_dtlb_ll_transaction; // number of dtlb ll acc transactions + uint32_t m_cpt_dtlb_sc_transaction; // number of dtlb sc acc transactions + uint32_t m_cpt_dtlb_ll_dirty_transaction; // number of dtlb ll dirty transactions + uint32_t m_cpt_dtlb_sc_dirty_transaction; // number of dtlb sc dirty transactions uint32_t m_cost_itlbmiss_transaction; // cumulated duration for VCI instruction TLB miss transactions - uint32_t m_cost_itlb_write_transaction; // cumulated duration for VCI instruction TLB write ET transactions + uint32_t m_cost_itlb_ll_transaction; // cumulated duration for VCI instruction TLB ll acc transactions + uint32_t m_cost_itlb_sc_transaction; // cumulated duration for VCI instruction TLB sc acc transactions uint32_t m_cost_dtlbmiss_transaction; // cumulated duration for VCI data TLB miss transactions - uint32_t m_cost_dtlb_write_transaction; // cumulated duration for VCI data TLB write transactions - - uint32_t m_cpt_cc_update; // number of coherence update packets - uint32_t m_cpt_cc_inval; // number of coherence inval packets - uint32_t m_cpt_cc_broadcast; // number of coherence inval packets - - uint32_t m_cost_cc_update_frz; // number of waiting cycles for coherence update - uint32_t m_cost_cc_inval_frz; // number of waiting cycles for coherence invalidate + uint32_t m_cost_dtlb_ll_transaction; // cumulated duration for VCI data TLB ll acc transactions + uint32_t m_cost_dtlb_sc_transaction; // cumulated duration for VCI data TLB sc acc transactions + uint32_t m_cost_dtlb_ll_dirty_transaction;// cumulated duration for VCI data TLB ll dirty transactions + uint32_t m_cost_dtlb_sc_dirty_transaction;// cumulated duration for VCI data TLB sc dirty transactions + + uint32_t m_cpt_cc_cleanup_ins; + uint32_t m_cpt_cc_cleanup_data; + uint32_t m_cpt_icleanup_transaction; + uint32_t m_cpt_dcleanup_transaction; + uint32_t m_cost_icleanup_transaction; + uint32_t m_cost_dcleanup_transaction; + + uint32_t m_cpt_cc_update_data; // number of coherence update data packets + uint32_t m_cpt_cc_inval_ins; // number of coherence inval instruction packets + uint32_t m_cpt_cc_inval_data; // number of coherence inval data packets + uint32_t m_cpt_cc_broadcast; // number of coherence broadcast packets protected: Index: trunk/modules/vci_cc_vcache_wrapper_v1/caba/source/src/vci_cc_vcache_wrapper_v1.cpp =================================================================== --- trunk/modules/vci_cc_vcache_wrapper_v1/caba/source/src/vci_cc_vcache_wrapper_v1.cpp (revision 47) +++ trunk/modules/vci_cc_vcache_wrapper_v1/caba/source/src/vci_cc_vcache_wrapper_v1.cpp (revision 48) @@ -320,25 +320,27 @@ << "- READ RATE = " << (float)m_cpt_read/run_cycles << std::endl << "- WRITE RATE = " << (float)m_cpt_write/run_cycles << std::endl - << "- UNCACHED READ RATE = " << (float)m_cpt_unc_read/m_cpt_read << std::endl - << "- CACHED WRITE RATE = " << (float)m_cpt_write_cached/m_cpt_write << std::endl << "- IMISS_RATE = " << (float)m_cpt_ins_miss/m_cpt_ins_read << std::endl << "- DMISS RATE = " << (float)m_cpt_data_miss/(m_cpt_read-m_cpt_unc_read) << std::endl << "- INS MISS COST = " << (float)m_cost_ins_miss_frz/m_cpt_ins_miss << std::endl - << "- IMISS TRANSACTION = " << (float)m_cost_imiss_transaction/m_cpt_imiss_transaction << std::endl - << "- DMISS COST = " << (float)m_cost_data_miss_frz/m_cpt_data_miss << std::endl - << "- DMISS TRANSACTION = " << (float)m_cost_dmiss_transaction/m_cpt_dmiss_transaction << std::endl + << "- DATA MISS COST = " << (float)m_cost_data_miss_frz/m_cpt_data_miss << std::endl + << "- WRITE COST = " << (float)m_cost_write_frz/m_cpt_write << std::endl << "- UNC COST = " << (float)m_cost_unc_read_frz/m_cpt_unc_read << std::endl - << "- UNC TRANSACTION = " << (float)m_cost_unc_transaction/m_cpt_unc_transaction << std::endl - << "- WRITE COST = " << (float)m_cost_write_frz/m_cpt_write << std::endl - << "- WRITE TRANSACTION = " << (float)m_cost_write_transaction/m_cpt_write_transaction << std::endl - << "- WRITE LENGTH = " << (float)m_length_write_transaction/m_cpt_write_transaction << std::endl + << "- UNCACHED READ RATE = " << (float)m_cpt_unc_read/m_cpt_read << std::endl + << "- CACHED WRITE RATE = " << (float)m_cpt_write_cached/m_cpt_write << std::endl << "- INS TLB MISS RATE = " << (float)m_cpt_ins_tlb_miss/m_cpt_ins_tlb_read << std::endl << "- DATA TLB MISS RATE = " << (float)m_cpt_data_tlb_miss/m_cpt_data_tlb_read << std::endl + << "- ITLB MISS COST = " << (float)m_cost_ins_tlb_miss_frz/m_cpt_ins_tlb_miss << std::endl + << "- DTLB MISS COST = " << (float)m_cost_data_tlb_miss_frz/m_cpt_data_tlb_miss << std::endl + << "- ITLB UPDATE ACC COST = " << (float)m_cost_ins_tlb_update_acc_frz/m_cpt_ins_tlb_update_acc << std::endl + << "- DTLB UPDATE ACC COST = " << (float)m_cost_data_tlb_update_acc_frz/m_cpt_data_tlb_update_acc << std::endl + << "- DTLB UPDATE DIRTY COST = " << (float)m_cost_data_tlb_update_dirty_frz/m_cpt_data_tlb_update_dirty << std::endl + << "- NB CC BROADCAST = " << m_cpt_cc_broadcast << std::endl + << "- NB CC UPDATE DATA = " << m_cpt_cc_update_data << std::endl + << "- NB CC INVAL DATA = " << m_cpt_cc_inval_data << std::endl + << "- NB CC INVAL INS = " << m_cpt_cc_inval_ins << std::endl + << "- NB CC CLEANUP DATA = " << m_cpt_cc_cleanup_data << std::endl + << "- NB CC CLEANUP INS = " << m_cpt_cc_cleanup_ins << std::endl << "- ITLB MISS TRANSACTION = " << (float)m_cost_itlbmiss_transaction/m_cpt_itlbmiss_transaction << std::endl - << "- ITLB WRITE TRANSACTION = " << (float)m_cost_itlb_write_transaction/m_cpt_itlb_write_transaction << std::endl - << "- ITLB MISS COST = " << (float)m_cost_ins_tlb_miss_frz/(m_cpt_ins_tlb_miss+m_cpt_ins_tlb_write_et) << std::endl - << "- DTLB MISS TRANSACTION = " << (float)m_cost_dtlbmiss_transaction/m_cpt_dtlbmiss_transaction << std::endl - << "- DTLB WRITE TRANSACTION = " << (float)m_cost_dtlb_write_transaction/m_cpt_dtlb_write_transaction << std::endl - << "- DTLB MISS COST = " << (float)m_cost_data_tlb_miss_frz/(m_cpt_data_tlb_miss+m_cpt_data_tlb_write_et+m_cpt_data_tlb_write_dirty) << std::endl; + << "- DTLB MISS TRANSACTION = " << (float)m_cost_dtlbmiss_transaction/m_cpt_dtlbmiss_transaction << std::endl; } @@ -396,9 +398,33 @@ r_dcache_xtn_req = false; - r_icache_cleanup_check_req = false; + r_dcache_dirty_save = false; + r_dcache_hit_p_save = false; + r_dcache_cached_save = false; + + r_icache_buf_unc_valid = false; + r_dcache_buf_unc_valid = false; + + r_vci_rsp_ins_error = false; + r_vci_rsp_data_error = false; + + r_icache_id1_save = 0; + r_icache_ppn_save = 0; + r_icache_vpn_save = 0; + r_itlb_translation_valid = false; + + r_dcache_id1_save = 0; + r_dcache_ppn_save = 0; + r_dcache_vpn_save = 0; + r_dtlb_translation_valid = false; + + r_icache_ptba_ok = false; + r_dcache_ptba_ok = false; + + r_icache_error_type = MMU_NONE; + r_dcache_error_type = MMU_NONE; + r_icache_cleanup_req = false; r_icache_cleanup_type = NONE; - r_dcache_cleanup_check_req = false; r_dcache_cleanup_req = false; r_dcache_cleanup_type = NONE; @@ -428,29 +454,4 @@ r_dcache_inval_tlb_rsp = false; - r_dcache_dirty_save = false; - r_dcache_hit_p_save = false; - - r_icache_buf_unc_valid = false; - r_dcache_buf_unc_valid = false; - - r_vci_rsp_ins_error = false; - r_vci_rsp_data_error = false; - - r_icache_id1_save = 0; - r_icache_ppn_save = 0; - r_icache_vpn_save = 0; - r_itlb_translation_valid = false; - - r_dcache_id1_save = 0; - r_dcache_ppn_save = 0; - r_dcache_vpn_save = 0; - r_dtlb_translation_valid = false; - - r_icache_ptba_ok = false; - r_dcache_ptba_ok = false; - - r_icache_error_type = MMU_NONE; - r_dcache_error_type = MMU_NONE; - // activity counters m_cpt_dcache_data_read = 0; @@ -479,36 +480,61 @@ m_cost_ins_miss_frz = 0; - m_cpt_imiss_transaction = 0; - m_cpt_dmiss_transaction = 0; - m_cpt_unc_transaction = 0; - m_cpt_write_transaction = 0; - - m_cost_imiss_transaction = 0; - m_cost_dmiss_transaction = 0; - m_cost_unc_transaction = 0; - m_cost_write_transaction = 0; - m_length_write_transaction = 0; + m_cpt_imiss_transaction = 0; + m_cpt_dmiss_transaction = 0; + m_cpt_unc_transaction = 0; + m_cpt_write_transaction = 0; + m_cpt_icache_unc_transaction = 0; + + m_cost_imiss_transaction = 0; + m_cost_dmiss_transaction = 0; + m_cost_unc_transaction = 0; + m_cost_write_transaction = 0; + m_cost_icache_unc_transaction = 0; + m_length_write_transaction = 0; m_cpt_ins_tlb_read = 0; m_cpt_ins_tlb_miss = 0; - m_cpt_ins_tlb_write_et = 0; - - m_cpt_data_tlb_read = 0; - m_cpt_data_tlb_miss = 0; - m_cpt_data_tlb_write_et = 0; - m_cpt_data_tlb_write_dirty = 0; - - m_cost_ins_tlb_miss_frz = 0; - m_cost_data_tlb_miss_frz = 0; - - m_cpt_itlbmiss_transaction = 0; - m_cpt_itlb_write_transaction = 0; - m_cpt_dtlbmiss_transaction = 0; - m_cpt_dtlb_write_transaction = 0; + m_cpt_ins_tlb_update_acc = 0; + + m_cpt_data_tlb_read = 0; + m_cpt_data_tlb_miss = 0; + m_cpt_data_tlb_update_acc = 0; + m_cpt_data_tlb_update_dirty = 0; + + m_cost_ins_tlb_miss_frz = 0; + m_cost_data_tlb_miss_frz = 0; + m_cost_ins_tlb_update_acc_frz = 0; + m_cost_data_tlb_update_acc_frz = 0; + m_cost_data_tlb_update_dirty_frz = 0; + + m_cpt_itlbmiss_transaction = 0; + m_cpt_itlb_ll_transaction = 0; + m_cpt_itlb_sc_transaction = 0; + m_cpt_dtlbmiss_transaction = 0; + m_cpt_dtlb_ll_transaction = 0; + m_cpt_dtlb_sc_transaction = 0; + m_cpt_dtlb_ll_dirty_transaction = 0; + m_cpt_dtlb_sc_dirty_transaction = 0; - m_cost_itlbmiss_transaction = 0; - m_cost_itlb_write_transaction = 0; - m_cost_dtlbmiss_transaction = 0; - m_cost_dtlb_write_transaction = 0; + m_cost_itlbmiss_transaction = 0; + m_cost_itlb_ll_transaction = 0; + m_cost_itlb_sc_transaction = 0; + m_cost_dtlbmiss_transaction = 0; + m_cost_dtlb_ll_transaction = 0; + m_cost_dtlb_sc_transaction = 0; + m_cost_dtlb_ll_dirty_transaction = 0; + m_cost_dtlb_sc_dirty_transaction = 0; + + m_cpt_cc_cleanup_ins = 0; + m_cpt_cc_cleanup_data = 0; + m_cpt_icleanup_transaction = 0; + m_cpt_dcleanup_transaction = 0; + m_cost_icleanup_transaction = 0; + m_cost_dcleanup_transaction = 0; + + m_cpt_cc_update_data = 0; + m_cpt_cc_inval_ins = 0; + m_cpt_cc_inval_data = 0; + m_cpt_cc_broadcast = 0; return; } @@ -630,5 +656,5 @@ r_tgt_update = false; r_vci_tgt_fsm = TGT_REQ_DCACHE; - m_cpt_cc_inval++ ; + m_cpt_cc_inval_data++ ; } else if (cell == 4) // update @@ -642,5 +668,5 @@ r_tgt_update = true; r_vci_tgt_fsm = TGT_UPDT_WORD; - m_cpt_cc_update++ ; + m_cpt_cc_update_data++ ; } else if (cell == 8) @@ -654,5 +680,5 @@ r_tgt_update = false; r_vci_tgt_fsm = TGT_REQ_ICACHE; - m_cpt_cc_inval++ ; + m_cpt_cc_inval_ins++ ; } } // end if address @@ -853,6 +879,4 @@ if (r_dcache_xtn_req) { - if ( ireq.valid ) m_cost_ins_miss_frz++; - if ((int)r_dcache_type_save == (int)iss_t::XTN_PTPR) { @@ -889,5 +913,4 @@ if ( r_tgt_icache_req ) { - if ( ireq.valid ) m_cost_ins_miss_frz++; r_icache_fsm = ICACHE_CC_INVAL; r_icache_fsm_save = r_icache_fsm; @@ -1011,5 +1034,5 @@ r_icache_vaddr_req = ireq.addr; r_icache_fsm = ICACHE_BIS; - m_cost_ins_miss_frz++; + m_cost_ins_tlb_miss_frz++; } else // cached or uncached access with a correct speculative physical address @@ -1089,5 +1112,4 @@ r_icache_fsm = ICACHE_MISS_WAIT; m_cpt_ins_miss++; - m_cost_ins_miss_frz++; } else @@ -1116,5 +1138,4 @@ { if ( ireq.valid ) m_cost_ins_tlb_miss_frz++; - // external cache invalidate request if ( r_tgt_icache_req ) @@ -1166,4 +1187,5 @@ r_icache_cleanup_line = r_icache_paddr_save.read() >> (uint32_log2(m_icache_words) + 2); r_icache_cleanup_type = TLB_CLEANUP; + m_cpt_cc_cleanup_ins++; } else // PTE @@ -1183,5 +1205,6 @@ r_icache_tlb_ll_req = true; r_icache_fsm = ICACHE_TLB1_LL_WAIT; - m_cpt_ins_tlb_write_et++; + m_cpt_ins_tlb_update_acc++; + m_cost_ins_tlb_update_acc_frz++; } } @@ -1198,5 +1221,6 @@ r_icache_tlb_ll_req = true; r_icache_fsm = ICACHE_TLB1_LL_WAIT; - m_cpt_ins_tlb_write_et++; + m_cpt_ins_tlb_update_acc++; + m_cost_ins_tlb_update_acc_frz++; } } @@ -1226,4 +1250,5 @@ r_icache_cleanup_line = r_icache_paddr_save.read() >> (uint32_log2(m_icache_words) + 2); r_icache_cleanup_type = TLB_CLEANUP; + m_cpt_cc_cleanup_ins++; r_icache_fsm = ICACHE_IDLE; } @@ -1235,4 +1260,7 @@ case ICACHE_TLB1_LL_WAIT: { + if ( ireq.valid ) m_cost_ins_tlb_miss_frz++; + m_cost_ins_tlb_update_acc_frz++; + // external cache invalidate request if ( r_tgt_icache_req ) @@ -1281,4 +1309,7 @@ case ICACHE_TLB1_SC_WAIT: { + if ( ireq.valid ) m_cost_ins_tlb_miss_frz++; + m_cost_ins_tlb_update_acc_frz++; + // external cache invalidate request if ( r_tgt_icache_req ) @@ -1341,4 +1372,5 @@ r_icache_cleanup_line = victim_index; r_icache_cleanup_type = TLB_CLEANUP; + m_cpt_cc_cleanup_ins++; r_icache_fsm = ICACHE_IDLE; } @@ -1401,5 +1433,6 @@ r_icache_tlb_ll_req = true; r_icache_fsm = ICACHE_TLB2_LL_WAIT; - m_cpt_ins_tlb_write_et++; + m_cpt_ins_tlb_update_acc++; + m_cost_ins_tlb_update_acc_frz++; } } @@ -1416,5 +1449,6 @@ r_icache_tlb_ll_req = true; r_icache_fsm = ICACHE_TLB2_LL_WAIT; - m_cpt_ins_tlb_write_et++; + m_cpt_ins_tlb_update_acc++; + m_cost_ins_tlb_update_acc_frz++; } } @@ -1445,4 +1479,5 @@ r_icache_cleanup_line = r_icache_paddr_save.read() >> (uint32_log2(m_icache_words) + 2); r_icache_cleanup_type = TLB_CLEANUP; + m_cpt_cc_cleanup_ins++; r_icache_fsm = ICACHE_IDLE; } @@ -1454,4 +1489,7 @@ case ICACHE_TLB2_LL_WAIT: { + if ( ireq.valid ) m_cost_ins_tlb_miss_frz++; + m_cost_ins_tlb_update_acc_frz++; + // external cache invalidate request if ( r_tgt_icache_req ) @@ -1500,4 +1538,7 @@ case ICACHE_TLB2_SC_WAIT: { + if ( ireq.valid ) m_cost_ins_tlb_miss_frz++; + m_cost_ins_tlb_update_acc_frz++; + // external cache invalidate request if ( r_tgt_icache_req ) @@ -1561,4 +1602,5 @@ r_icache_cleanup_line = victim_index; r_icache_cleanup_type = TLB_CLEANUP; + m_cpt_cc_cleanup_ins++; r_icache_fsm = ICACHE_IDLE; } @@ -1594,4 +1636,5 @@ r_icache_cleanup_line = victim_index; r_icache_cleanup_type = TLB_CLEANUP; + m_cpt_cc_cleanup_ins++; r_icache_way = way + ((set+1)/m_itlb_sets); r_icache_set = (set+1) % m_itlb_sets; @@ -1627,6 +1670,4 @@ size_t set = r_icache_set; bool clean = false; - - m_cost_ins_cache_flush_frz++; // cache flush and send cleanup to external @@ -1644,4 +1685,5 @@ r_icache_cleanup_line = victim_index; r_icache_cleanup_type = CACHE_CLEANUP; + m_cpt_cc_cleanup_ins++; r_icache_way = way + ((set+1)/m_icache_sets); r_icache_set = (set+1) % m_icache_sets; @@ -1670,4 +1712,5 @@ r_icache_cleanup_type = TLB_CLEANUP; r_icache_cleanup_line = victim_index; + m_cpt_cc_cleanup_ins++; r_dcache_xtn_req = false; r_itlb_translation_valid = false; @@ -1708,4 +1751,5 @@ r_icache_cleanup_line = ipaddr >> (uint32_log2(m_icache_words) + 2); r_icache_cleanup_type = CACHE_CLEANUP; + m_cpt_cc_cleanup_ins++; } r_dcache_xtn_req = false; @@ -1733,4 +1777,5 @@ r_icache_cleanup_line = ipaddr >> (uint32_log2(m_icache_words) + 2); r_icache_cleanup_type = CACHE_CLEANUP; + m_cpt_cc_cleanup_ins++; r_dcache_xtn_req = false; r_icache_fsm = ICACHE_IDLE; @@ -1770,8 +1815,8 @@ r_icache_cleanup_line = r_icache_paddr_save.read() >> (uint32_log2(m_icache_words) + 2); r_icache_cleanup_type = CACHE_CLEANUP; + m_cpt_cc_cleanup_ins++; r_icache_fsm = ICACHE_IDLE; r_icache_inval_tlb_rsp = false; if ( r_icache_inval_rsp ) r_icache_inval_rsp = false; - m_cost_ins_tlb_miss_frz++; break; } @@ -1783,4 +1828,5 @@ r_icache_cleanup_line = r_icache_paddr_save.read() >> (uint32_log2(m_icache_words) + 2); r_icache_cleanup_type = CACHE_CLEANUP; + m_cpt_cc_cleanup_ins++; r_icache_fsm = ICACHE_IDLE; r_icache_inval_rsp = false; @@ -1794,5 +1840,4 @@ case ICACHE_UNC_WAIT: { - m_cost_ins_miss_frz++; // external cache invalidate request if ( r_tgt_icache_req ) @@ -1846,4 +1891,5 @@ r_icache_cleanup_line = r_icache_paddr_save.read() >> (uint32_log2(m_icache_words) + 2); r_icache_cleanup_type = CACHE_CLEANUP; + m_cpt_cc_cleanup_ins++; r_icache_inval_tlb_rsp = false; if ( r_icache_inval_rsp ) r_icache_inval_rsp = false; @@ -1859,4 +1905,5 @@ r_icache_cleanup_line = r_icache_paddr_save.read() >> (uint32_log2(m_icache_words) + 2); r_icache_cleanup_type = CACHE_CLEANUP; + m_cpt_cc_cleanup_ins++; r_icache_inval_rsp = false; r_icache_fsm = ICACHE_IDLE; @@ -1871,5 +1918,6 @@ r_icache_cleanup_req = r_icache.update(r_icache_paddr_save.read(), buf, &victim_index); r_icache_cleanup_line = victim_index; - r_icache_cleanup_type = CACHE_CLEANUP; + r_icache_cleanup_type = CACHE_CLEANUP; + m_cpt_cc_cleanup_ins++; r_icache_fsm = ICACHE_IDLE; } @@ -1890,8 +1938,19 @@ case ICACHE_CC_INVAL: { - if ( ireq.valid ) m_cost_ins_miss_frz++; m_cpt_icache_dir_read += m_icache_ways; - // invalidate cache + /* activity counter */ + if ( (( r_icache_fsm_save == ICACHE_BIS ) ||( r_icache_fsm_save == ICACHE_MISS_WAIT ) || ( r_icache_fsm_save == ICACHE_MISS_UPDT ) ) && ( ireq.valid ) ) + { + m_cost_ins_miss_frz++; + } + if( (( r_icache_fsm_save == ICACHE_TLB1_READ ) || ( r_icache_fsm_save == ICACHE_TLB2_READ ) || + ( r_icache_fsm_save == ICACHE_TLB1_LL_WAIT )|| ( r_icache_fsm_save == ICACHE_TLB2_LL_WAIT ) || + ( r_icache_fsm_save == ICACHE_TLB1_SC_WAIT )|| ( r_icache_fsm_save == ICACHE_TLB2_SC_WAIT ) || + ( r_icache_fsm_save == ICACHE_TLB1_UPDT ) || ( r_icache_fsm_save == ICACHE_TLB2_UPDT )) && (ireq.valid) ) + { + m_cost_ins_tlb_miss_frz++; + } + if( (( r_icache_fsm_save == ICACHE_MISS_WAIT ) || ( r_icache_fsm_save == ICACHE_MISS_UPDT ) ) && ((r_icache_paddr_save.read() & ~((m_icache_words<<2)-1)) == (r_tgt_addr.read() & ~((m_icache_words<<2)-1))) ) @@ -1921,5 +1980,17 @@ case ICACHE_TLB_CC_INVAL: { - if ( ireq.valid ) m_cost_ins_miss_frz++; + /* activity counter */ + if ( (( r_icache_fsm_save == ICACHE_BIS ) ||( r_icache_fsm_save == ICACHE_MISS_WAIT ) || ( r_icache_fsm_save == ICACHE_MISS_UPDT ) ) && ( ireq.valid ) ) + { + m_cost_ins_miss_frz++; + } + + if( (( r_icache_fsm_save == ICACHE_TLB1_READ ) || ( r_icache_fsm_save == ICACHE_TLB2_READ ) || + ( r_icache_fsm_save == ICACHE_TLB1_LL_WAIT )|| ( r_icache_fsm_save == ICACHE_TLB2_LL_WAIT ) || + ( r_icache_fsm_save == ICACHE_TLB1_SC_WAIT )|| ( r_icache_fsm_save == ICACHE_TLB2_SC_WAIT ) || + ( r_icache_fsm_save == ICACHE_TLB1_UPDT ) || ( r_icache_fsm_save == ICACHE_TLB2_UPDT )) && (ireq.valid) ) + { + m_cost_ins_tlb_miss_frz++; + } if ( r_icache_tlb_inval_req ) break; @@ -1988,6 +2059,5 @@ // r_tgt_addr is number of line - bool tlb_hit = icache_tlb.cccheck((r_tgt_addr.read() >> (uint32_log2(m_icache_words)+2)),way, set, &way, &set, &end); - + bool tlb_hit = icache_tlb.cccheck((r_tgt_addr.read() >> (uint32_log2(m_icache_words)+2)),way, set, &way, &set, &end); if ( tlb_hit ) { @@ -2007,6 +2077,4 @@ case INVAL_ITLB_INVAL: { - //m_cost_ins_tlb_inval_frz++; - icache_tlb.ccinval(r_ccinval_itlb_way, r_ccinval_itlb_set); @@ -2128,5 +2196,4 @@ r_dcache_fsm = DCACHE_CC_CHECK; r_dcache_fsm_save = DCACHE_IDLE; - if ( dreq.valid ) m_cost_data_miss_frz++; break; } @@ -2509,5 +2576,5 @@ r_dcache_hit_p_save = dcache_hit_p; r_dcache_fsm = DCACHE_BIS; - m_cost_data_miss_frz++; + m_cost_data_tlb_miss_frz++; } else // cached or uncached access with a correct speculative physical address @@ -2545,4 +2612,5 @@ m_cpt_write++; if ( dcache_cached ) m_cpt_write_cached++; + m_cost_write_frz++; if ( dcache_hit_c && dcache_cached ) // cache update required @@ -2553,4 +2621,6 @@ else if ( !dcache_pte_info.d && (r_mmu_mode.read() & DATA_TLB_MASK) ) // dirty bit update required { + m_cpt_data_tlb_update_dirty++; + m_cost_data_tlb_update_dirty_frz++; if (dcache_tlb.getpagesize(dcache_tlb_way, dcache_tlb_set)) { @@ -2559,5 +2629,4 @@ r_dcache_tlb_ll_dirty_req = true; r_dcache_fsm = DCACHE_LL_DIRTY_WAIT; - m_cpt_data_tlb_write_dirty++; } else @@ -2569,5 +2638,4 @@ r_dcache_tlb_ll_dirty_req = true; r_dcache_fsm = DCACHE_LL_DIRTY_WAIT; - m_cpt_data_tlb_write_dirty++; } else // get PTBA to calculate the physical address of PTE @@ -2581,5 +2649,4 @@ } } - m_cost_data_tlb_miss_frz++; } else // no cache update, not dirty bit update @@ -2685,4 +2752,6 @@ else if ( !r_dcache_dirty_save && (r_mmu_mode.read() & DATA_TLB_MASK) ) // dirty bit update required { + m_cpt_data_tlb_update_dirty++; + m_cost_data_tlb_update_dirty_frz++; if (dcache_tlb.getpagesize(r_dcache_tlb_way_save, r_dcache_tlb_set_save)) { @@ -2691,5 +2760,4 @@ r_dcache_tlb_ll_dirty_req = true; r_dcache_fsm = DCACHE_LL_DIRTY_WAIT; - m_cpt_data_tlb_write_dirty++; } else @@ -2701,5 +2769,4 @@ r_dcache_tlb_ll_dirty_req = true; r_dcache_fsm = DCACHE_LL_DIRTY_WAIT; - m_cpt_data_tlb_write_dirty++; } else @@ -2713,5 +2780,4 @@ } } - m_cost_data_tlb_miss_frz++; } else // no cache update, not dirty bit update @@ -2735,4 +2801,6 @@ case DCACHE_LL_DIRTY_WAIT: { + m_cost_data_tlb_update_dirty_frz++; + // external cache invalidate request if ( r_tgt_dcache_req ) @@ -2740,5 +2808,4 @@ r_dcache_fsm = DCACHE_CC_CHECK; r_dcache_fsm_save = r_dcache_fsm; - //m_cost_data_waste_wait_frz++; break; } @@ -2784,5 +2851,4 @@ r_dcache_inval_tlb_rsp = false; r_dcache_fsm = DCACHE_IDLE; - m_cost_data_tlb_miss_frz++; } else if ( r_dcache_inval_rsp ) @@ -2804,4 +2870,5 @@ case DCACHE_SC_DIRTY_WAIT: { + m_cost_data_tlb_update_dirty_frz++; // external cache invalidate request if ( r_tgt_dcache_req ) @@ -2809,5 +2876,4 @@ r_dcache_fsm = DCACHE_CC_CHECK; r_dcache_fsm_save = r_dcache_fsm; - //m_cost_data_waste_wait_frz++; break; } @@ -2839,5 +2905,4 @@ if (r_dcache_tlb_sc_fail) r_dcache_tlb_sc_fail = false; r_dcache_fsm = DCACHE_IDLE; - m_cost_data_tlb_miss_frz++; } else if ( r_dcache_inval_rsp ) @@ -2902,4 +2967,5 @@ r_dcache_cleanup_line = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words) + 2); r_dcache_cleanup_type = TLB_CLEANUP; + m_cpt_cc_cleanup_data++; r_dcache_inval_tlb_rsp = false; break; @@ -2932,5 +2998,5 @@ r_dcache_tlb_ll_dirty_req = true; r_dcache_fsm = DCACHE_LL_DIRTY_WAIT; - m_cpt_data_tlb_write_dirty++; + m_cpt_data_tlb_update_dirty_frz++; } else @@ -2945,4 +3011,5 @@ r_dcache_cleanup_line = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words) + 2); r_dcache_cleanup_type = TLB_CLEANUP; + m_cpt_cc_cleanup_data++; } @@ -2962,5 +3029,6 @@ r_dcache_tlb_ll_acc_req = true; r_dcache_fsm = DCACHE_TLB1_LL_WAIT; - m_cpt_ins_tlb_write_et++; + m_cpt_data_tlb_update_acc++; + m_cost_data_tlb_update_acc_frz++; } } @@ -2977,5 +3045,6 @@ r_dcache_tlb_ll_acc_req = true; r_dcache_fsm = DCACHE_TLB1_LL_WAIT; - m_cpt_ins_tlb_write_et++; + m_cpt_data_tlb_update_acc++; + m_cost_data_tlb_update_acc_frz++; } } @@ -2987,4 +3056,7 @@ case DCACHE_TLB1_LL_WAIT: { + if ( dreq.valid ) m_cost_data_tlb_miss_frz++; + m_cost_data_tlb_update_acc_frz++; + // external cache invalidate request if ( r_tgt_dcache_req ) @@ -3033,5 +3105,4 @@ r_dcache_inval_tlb_rsp = false; r_dcache_fsm = DCACHE_IDLE; - m_cost_data_tlb_miss_frz++; } else @@ -3048,4 +3119,7 @@ case DCACHE_TLB1_SC_WAIT: { + if ( dreq.valid ) m_cost_data_tlb_miss_frz++; + m_cost_data_tlb_update_acc_frz++; + // external cache invalidate request if ( r_tgt_dcache_req ) @@ -3081,5 +3155,4 @@ if (r_dcache_tlb_sc_fail) r_dcache_tlb_sc_fail = false; r_dcache_fsm = DCACHE_IDLE; - m_cost_data_tlb_miss_frz++; } else if ( r_dcache_tlb_sc_fail ) @@ -3107,5 +3180,4 @@ r_dcache_fsm = DCACHE_CC_CHECK; r_dcache_fsm_save = r_dcache_fsm; - //m_cost_data_waste_wait_frz++; break; } @@ -3118,4 +3190,5 @@ r_dcache_cleanup_line = victim_index; r_dcache_cleanup_type = TLB_CLEANUP; + m_cpt_cc_cleanup_data++; r_dcache_fsm = DCACHE_IDLE; } @@ -3169,4 +3242,5 @@ r_dcache_cleanup_line = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words) + 2); r_dcache_cleanup_type = TLB_CLEANUP; + m_cpt_cc_cleanup_data++; r_dcache_inval_tlb_rsp = false; break; @@ -3205,5 +3279,6 @@ r_dcache_tlb_ll_acc_req = true; r_dcache_fsm = DCACHE_TLB2_LL_WAIT; - m_cpt_ins_tlb_write_et++; + m_cpt_data_tlb_update_acc++; + m_cost_data_tlb_update_acc_frz++; } } @@ -3220,5 +3295,6 @@ r_dcache_tlb_ll_acc_req = true; r_dcache_fsm = DCACHE_TLB2_LL_WAIT; - m_cpt_ins_tlb_write_et++; + m_cpt_data_tlb_update_acc++; + m_cost_data_tlb_update_acc_frz++; } } @@ -3230,4 +3306,7 @@ case DCACHE_TLB2_LL_WAIT: { + if ( dreq.valid ) m_cost_data_tlb_miss_frz++; + m_cost_data_tlb_update_acc_frz++; + // external cache invalidate request if ( r_tgt_dcache_req ) @@ -3276,5 +3355,4 @@ r_dcache_inval_tlb_rsp = false; r_dcache_fsm = DCACHE_IDLE; - m_cost_data_tlb_miss_frz++; } else @@ -3291,4 +3369,7 @@ case DCACHE_TLB2_SC_WAIT: { + if ( dreq.valid ) m_cost_data_tlb_miss_frz++; + m_cost_data_tlb_update_acc_frz++; + // external cache invalidate request if ( r_tgt_dcache_req ) @@ -3324,5 +3405,4 @@ if (r_dcache_tlb_sc_fail) r_dcache_tlb_sc_fail = false; r_dcache_fsm = DCACHE_IDLE; - m_cost_data_tlb_miss_frz++; } else if ( r_dcache_tlb_sc_fail ) @@ -3360,4 +3440,5 @@ r_dcache_cleanup_line = victim_index; r_dcache_cleanup_type = TLB_CLEANUP; + m_cpt_cc_cleanup_data++; r_dcache_fsm = DCACHE_IDLE; } @@ -3377,6 +3458,4 @@ size_t set = r_dcache_set; bool clean = false; - - m_cost_data_tlb_flush_frz++; // 4K page size TLB flush leads to cleanup req @@ -3394,4 +3473,5 @@ r_dcache_cleanup_line = victim_index; r_dcache_cleanup_type = TLB_CLEANUP; + m_cpt_cc_cleanup_data++; r_dcache_way = way + ((set+1)/m_dtlb_sets); r_dcache_set = (set+1) % m_dtlb_sets; @@ -3435,5 +3515,4 @@ r_dcache_fsm = DCACHE_CC_CHECK; r_dcache_fsm_save = r_dcache_fsm; - m_cost_data_waste_wait_frz++; break; } @@ -3456,4 +3535,5 @@ r_dcache_cleanup_line = victim_index; r_dcache_cleanup_type = CACHE_CLEANUP; + m_cpt_cc_cleanup_data++; r_dcache_way = way + ((set+1)/m_dcache_sets); r_dcache_set = (set+1) % m_dcache_sets; @@ -3482,4 +3562,5 @@ r_dcache_cleanup_req = dcache_tlb.inval1(r_dcache_wdata_save, &victim_index); r_dcache_cleanup_type = TLB_CLEANUP; + m_cpt_cc_cleanup_data++; r_dcache_cleanup_line = victim_index; r_dtlb_translation_valid = false; @@ -3498,5 +3579,4 @@ r_dcache_fsm = DCACHE_CC_CHECK; r_dcache_fsm_save = r_dcache_fsm; - m_cost_data_waste_wait_frz++; break; } @@ -3523,4 +3603,5 @@ r_dcache_cleanup_req = r_dcache.inval(dpaddr); r_dcache_cleanup_type = CACHE_CLEANUP; + m_cpt_cc_cleanup_data++; r_dcache_cleanup_line = dpaddr >> (uint32_log2(m_dcache_words)+2); } @@ -3538,5 +3619,4 @@ r_dcache_fsm = DCACHE_CC_CHECK; r_dcache_fsm_save = r_dcache_fsm; - m_cost_data_waste_wait_frz++; break; } @@ -3549,4 +3629,5 @@ r_dcache_cleanup_req = r_dcache.inval(dpaddr); r_dcache_cleanup_type = CACHE_CLEANUP; + m_cpt_cc_cleanup_data++; r_dcache_cleanup_line = dpaddr >> (uint32_log2(m_dcache_words)+2); r_dcache_fsm = DCACHE_IDLE; @@ -3569,4 +3650,5 @@ case DCACHE_MISS_WAIT: { + if (dreq.valid) m_cost_data_miss_frz++; // external cache invalidate request if ( r_tgt_dcache_req ) @@ -3574,5 +3656,4 @@ r_dcache_fsm = DCACHE_CC_CHECK; r_dcache_fsm_save = r_dcache_fsm; - m_cost_cc_wait_frz++; break; } @@ -3596,4 +3677,5 @@ r_dcache_cleanup_req = true; r_dcache_cleanup_type = CACHE_CLEANUP; + m_cpt_cc_cleanup_data++; r_dcache_cleanup_line = r_dcache_paddr_save.read() >> (uint32_log2(m_dcache_words) + 2); r_dcache_fsm = DCACHE_IDLE; @@ -3608,4 +3690,5 @@ r_dcache_cleanup_req = true; r_dcache_cleanup_type = CACHE_CLEANUP; + m_cpt_cc_cleanup_data++; r_dcache_cleanup_line = r_dcache_paddr_save.read() >> (uint32_log2(m_dcache_words) + 2); r_dcache_fsm = DCACHE_IDLE; @@ -3621,4 +3704,5 @@ case DCACHE_MISS_UPDT: { + if (dreq.valid) m_cost_data_miss_frz++; // external cache invalidate request if ( r_tgt_dcache_req ) @@ -3634,4 +3718,5 @@ r_dcache_cleanup_req = true; r_dcache_cleanup_type = CACHE_CLEANUP; + m_cpt_cc_cleanup_data++; r_dcache_cleanup_line = r_dcache_paddr_save.read() >> (uint32_log2(m_dcache_words) + 2); r_dcache_inval_tlb_rsp = false; @@ -3647,8 +3732,8 @@ r_dcache_cleanup_req = true; r_dcache_cleanup_type = CACHE_CLEANUP; + m_cpt_cc_cleanup_data++; r_dcache_cleanup_line = r_dcache_paddr_save.read() >> (uint32_log2(m_dcache_words) + 2); r_dcache_inval_rsp = false; r_dcache_fsm = DCACHE_IDLE; - m_cost_data_tlb_miss_frz++; break; } @@ -3657,7 +3742,10 @@ { paddr_t victim_index = 0; + m_cpt_dcache_data_write++; + m_cpt_dcache_dir_write++; r_dcache_cleanup_req = r_dcache.update(r_dcache_paddr_save.read(), r_dcache_miss_buf, &victim_index); r_dcache_cleanup_line = victim_index; r_dcache_cleanup_type = CACHE_CLEANUP; + m_cpt_cc_cleanup_data++; r_dcache_fsm = DCACHE_IDLE; } @@ -3667,4 +3755,5 @@ case DCACHE_UNC_WAIT: { + if ( dreq.valid ) m_cost_unc_read_frz++; // external cache invalidate request if ( r_tgt_dcache_req ) @@ -3697,4 +3786,5 @@ r_dcache_cleanup_req = r_dcache.inval(r_dcache_paddr_save); r_dcache_cleanup_type = CACHE_CLEANUP; + m_cpt_cc_cleanup_data++; r_dcache_cleanup_line = r_dcache_paddr_save.read() >> (uint32_log2(m_dcache_words)+2); } @@ -3708,4 +3798,5 @@ case DCACHE_WRITE_UPDT: { + m_cpt_dcache_data_write++; bool write_hit = false; data_t mask = vci_param::be2mask(r_dcache_be_save.read()); @@ -3716,4 +3807,6 @@ if ( !r_dcache_dirty_save && (r_mmu_mode.read() & DATA_TLB_MASK) ) { + m_cpt_data_tlb_update_dirty++; + m_cost_data_tlb_update_dirty_frz++; if ( dcache_tlb.getpagesize(r_dcache_tlb_way_save, r_dcache_tlb_set_save) ) // 2M page size, one level page table { @@ -3722,5 +3815,4 @@ r_dcache_tlb_ll_dirty_req = true; r_dcache_fsm = DCACHE_LL_DIRTY_WAIT; - m_cpt_data_tlb_write_dirty++; } else @@ -3732,5 +3824,4 @@ r_dcache_tlb_ll_dirty_req = true; r_dcache_fsm = DCACHE_LL_DIRTY_WAIT; - m_cpt_data_tlb_write_dirty++; } else @@ -3756,5 +3847,5 @@ case DCACHE_WRITE_DIRTY: { - m_cost_data_tlb_miss_frz++; + m_cost_data_tlb_update_dirty_frz++; // external cache invalidate request @@ -3763,5 +3854,4 @@ r_dcache_fsm = DCACHE_CC_CHECK; r_dcache_fsm_save = r_dcache_fsm; - //m_cost_data_waste_wait_frz++; break; } @@ -3795,5 +3885,16 @@ m_cpt_dcache_data_read += m_dcache_ways; - m_cost_cc_wait_frz++; + /* activity counter */ + if ( (( r_dcache_fsm_save == DCACHE_BIS ) ||( r_dcache_fsm_save == DCACHE_MISS_WAIT ) || ( r_dcache_fsm_save == DCACHE_MISS_UPDT ) ) && ( dreq.valid ) ) + { + m_cost_data_miss_frz++; + } + if( (( r_dcache_fsm_save == DCACHE_TLB1_READ ) || ( r_dcache_fsm_save == DCACHE_TLB2_READ ) || + ( r_dcache_fsm_save == DCACHE_TLB1_LL_WAIT )|| ( r_dcache_fsm_save == DCACHE_TLB2_LL_WAIT ) || + ( r_dcache_fsm_save == DCACHE_TLB1_SC_WAIT )|| ( r_dcache_fsm_save == DCACHE_TLB2_SC_WAIT ) || + ( r_dcache_fsm_save == DCACHE_TLB1_UPDT ) || ( r_dcache_fsm_save == DCACHE_TLB2_UPDT )) && (dreq.valid) ) + { + m_cost_data_tlb_miss_frz++; + } if(( /*( r_dcache_fsm_save == DCACHE_UNC_WAIT ) ||*/ @@ -3841,7 +3942,19 @@ case DCACHE_CC_UPDT: // update directory and data cache { + /* activity counter */ + if ( (( r_dcache_fsm_save == DCACHE_BIS ) ||( r_dcache_fsm_save == DCACHE_MISS_WAIT ) || ( r_dcache_fsm_save == DCACHE_MISS_UPDT ) ) && ( dreq.valid ) ) + { + m_cost_data_miss_frz++; + } + if( (( r_dcache_fsm_save == DCACHE_TLB1_READ ) || ( r_dcache_fsm_save == DCACHE_TLB2_READ ) || + ( r_dcache_fsm_save == DCACHE_TLB1_LL_WAIT )|| ( r_dcache_fsm_save == DCACHE_TLB2_LL_WAIT ) || + ( r_dcache_fsm_save == DCACHE_TLB1_SC_WAIT )|| ( r_dcache_fsm_save == DCACHE_TLB2_SC_WAIT ) || + ( r_dcache_fsm_save == DCACHE_TLB1_UPDT ) || ( r_dcache_fsm_save == DCACHE_TLB2_UPDT )) && (dreq.valid) ) + { + m_cost_data_tlb_miss_frz++; + } + m_cpt_dcache_dir_write++; m_cpt_dcache_data_write++; - m_cost_cc_wait_frz++; data_t* buf = r_tgt_buf; @@ -3858,5 +3971,17 @@ case DCACHE_CC_INVAL: // invalidate a cache line { - m_cost_cc_wait_frz++; + /* activity counter */ + if ( (( r_dcache_fsm_save == DCACHE_BIS ) ||( r_dcache_fsm_save == DCACHE_MISS_WAIT ) || ( r_dcache_fsm_save == DCACHE_MISS_UPDT ) ) && ( dreq.valid ) ) + { + m_cost_data_miss_frz++; + } + if( (( r_dcache_fsm_save == DCACHE_TLB1_READ ) || ( r_dcache_fsm_save == DCACHE_TLB2_READ ) || + ( r_dcache_fsm_save == DCACHE_TLB1_LL_WAIT )|| ( r_dcache_fsm_save == DCACHE_TLB2_LL_WAIT ) || + ( r_dcache_fsm_save == DCACHE_TLB1_SC_WAIT )|| ( r_dcache_fsm_save == DCACHE_TLB2_SC_WAIT ) || + ( r_dcache_fsm_save == DCACHE_TLB1_UPDT ) || ( r_dcache_fsm_save == DCACHE_TLB2_UPDT )) && (dreq.valid) ) + { + m_cost_data_tlb_miss_frz++; + } + r_tgt_dcache_rsp = r_dcache.inval(r_tgt_addr.read()); if ( r_tgt_broadcast ) @@ -3875,5 +4000,17 @@ case DCACHE_CC_NOP: // no external hit { - m_cost_cc_wait_frz++; + /* activity counter */ + if ( (( r_dcache_fsm_save == DCACHE_BIS ) ||( r_dcache_fsm_save == DCACHE_MISS_WAIT ) || ( r_dcache_fsm_save == DCACHE_MISS_UPDT ) ) && ( dreq.valid ) ) + { + m_cost_data_miss_frz++; + } + if( (( r_dcache_fsm_save == DCACHE_TLB1_READ ) || ( r_dcache_fsm_save == DCACHE_TLB2_READ ) || + ( r_dcache_fsm_save == DCACHE_TLB1_LL_WAIT )|| ( r_dcache_fsm_save == DCACHE_TLB2_LL_WAIT ) || + ( r_dcache_fsm_save == DCACHE_TLB1_SC_WAIT )|| ( r_dcache_fsm_save == DCACHE_TLB2_SC_WAIT ) || + ( r_dcache_fsm_save == DCACHE_TLB1_UPDT ) || ( r_dcache_fsm_save == DCACHE_TLB2_UPDT )) && (dreq.valid) ) + { + m_cost_data_tlb_miss_frz++; + } + r_tgt_dcache_rsp = r_tgt_update; if ( r_tgt_broadcast ) @@ -3892,6 +4029,18 @@ case DCACHE_TLB_CC_INVAL: { + /* activity counter */ + if ( (( r_dcache_fsm_save == DCACHE_BIS ) ||( r_dcache_fsm_save == DCACHE_MISS_WAIT ) || ( r_dcache_fsm_save == DCACHE_MISS_UPDT ) ) && ( dreq.valid ) ) + { + m_cost_data_miss_frz++; + } + if( (( r_dcache_fsm_save == DCACHE_TLB1_READ ) || ( r_dcache_fsm_save == DCACHE_TLB2_READ ) || + ( r_dcache_fsm_save == DCACHE_TLB1_LL_WAIT )|| ( r_dcache_fsm_save == DCACHE_TLB2_LL_WAIT ) || + ( r_dcache_fsm_save == DCACHE_TLB1_SC_WAIT )|| ( r_dcache_fsm_save == DCACHE_TLB2_SC_WAIT ) || + ( r_dcache_fsm_save == DCACHE_TLB1_UPDT ) || ( r_dcache_fsm_save == DCACHE_TLB2_UPDT )) && (dreq.valid) ) + { + m_cost_data_tlb_miss_frz++; + } + paddr_t dcache_tlb_nline = 0; - if ( dreq.valid ) m_cost_data_tlb_miss_frz++; if ( r_dcache_tlb_inval_req ) break; @@ -4052,8 +4201,10 @@ { r_vci_cmd_fsm = CMD_INS_CLEANUP; + m_cpt_icleanup_transaction++; } else if (r_dcache_cleanup_req) { r_vci_cmd_fsm = CMD_DATA_CLEANUP; + m_cpt_dcleanup_transaction++; } else if (r_icache_tlb_read_req) @@ -4065,10 +4216,10 @@ { r_vci_cmd_fsm = CMD_ITLB_ACC_LL; - //m_cpt_itlb_write_transaction++; + m_cpt_itlb_ll_transaction++; } else if (r_icache_tlb_sc_req) { r_vci_cmd_fsm = CMD_ITLB_ACC_SC; - //m_cpt_itlb_write_transaction++; + m_cpt_itlb_sc_transaction++; } else if (r_icache_miss_req) @@ -4080,5 +4231,5 @@ { r_vci_cmd_fsm = CMD_INS_UNC; - m_cpt_imiss_transaction++; + m_cpt_icache_unc_transaction++; } else if (r_dcache_tlb_read_req) @@ -4090,20 +4241,20 @@ { r_vci_cmd_fsm = CMD_DTLB_ACC_LL; - m_cpt_dtlb_write_transaction++; + m_cpt_dtlb_ll_transaction++; } else if (r_dcache_tlb_sc_acc_req) { r_vci_cmd_fsm = CMD_DTLB_ACC_SC; - m_cpt_dtlb_write_transaction++; + m_cpt_dtlb_sc_transaction++; } else if (r_dcache_tlb_ll_dirty_req) { r_vci_cmd_fsm = CMD_DTLB_DIRTY_LL; - m_cpt_dtlb_write_transaction++; + m_cpt_dtlb_ll_dirty_transaction++; } else if (r_dcache_tlb_sc_dirty_req) { r_vci_cmd_fsm = CMD_DTLB_DIRTY_SC; - m_cpt_dtlb_write_transaction++; + m_cpt_dtlb_sc_dirty_transaction++; } else if (r_dcache_write_req) @@ -4249,5 +4400,4 @@ "illegal VCI response packet for data read uncached"); } -/* else { @@ -4255,5 +4405,5 @@ "The VCI response packet for instruction miss is too short"); } -*/ + r_icache_tlb_read_req = false; r_icache_tlb_first_req = false; @@ -4267,4 +4417,5 @@ case RSP_ITLB_ACC_LL: + m_cost_itlb_ll_transaction++; if ( ! p_vci_ini_rw.rspval.read() ) break; @@ -4286,4 +4437,5 @@ case RSP_ITLB_ACC_SC: + m_cost_itlb_sc_transaction++; if ( ! p_vci_ini_rw.rspval.read() ) break; @@ -4328,5 +4480,5 @@ case RSP_INS_UNC: - m_cost_imiss_transaction++; + m_cost_icache_unc_transaction++; if ( ! p_vci_ini_rw.rspval.read() ) break; @@ -4360,5 +4512,4 @@ "illegal VCI response packet for data read uncached"); } -/* else { @@ -4366,5 +4517,5 @@ "The VCI response packet for instruction miss is too short"); } -*/ + r_dcache_tlb_read_req = false; r_dcache_tlb_first_req = false; @@ -4378,4 +4529,5 @@ case RSP_DTLB_ACC_LL: + m_cost_dtlb_ll_transaction++; if ( ! p_vci_ini_rw.rspval.read() ) break; @@ -4397,4 +4549,5 @@ case RSP_DTLB_ACC_SC: + m_cost_dtlb_sc_transaction++; if ( ! p_vci_ini_rw.rspval.read() ) break; @@ -4416,4 +4569,5 @@ case RSP_DTLB_DIRTY_LL: + m_cost_dtlb_ll_dirty_transaction++; if ( ! p_vci_ini_rw.rspval.read() ) break; @@ -4435,4 +4589,5 @@ case RSP_DTLB_DIRTY_SC: + m_cost_dtlb_sc_dirty_transaction++; if ( ! p_vci_ini_rw.rspval.read() ) break; @@ -4515,4 +4670,13 @@ case RSP_INS_CLEANUP: case RSP_DATA_CLEANUP: + if ( r_vci_rsp_fsm == RSP_INS_CLEANUP ) + { + m_cost_icleanup_transaction++; + } + else + { + m_cost_dcleanup_transaction++; + } + if ( ! p_vci_ini_c.rspval.read() ) break;