Changeset 483
- Timestamp:
- Aug 5, 2013, 5:40:31 PM (11 years ago)
- Location:
- trunk/modules/vci_mem_cache/caba/source
- Files:
-
- 2 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h
r481 r483 104 104 TGT_RSP_XRAM, 105 105 TGT_RSP_MULTI_ACK, 106 TGT_RSP_CLEANUP, 107 TGT_RSP_UPT_LOCK, 108 TGT_RSP_IVT_LOCK 106 TGT_RSP_CLEANUP 109 107 }; 110 108 … … 335 333 ALLOC_UPT_WRITE, 336 334 ALLOC_UPT_CAS, 337 ALLOC_UPT_MULTI_ACK, 338 ALLOC_UPT_TGT_RSP 335 ALLOC_UPT_MULTI_ACK 339 336 }; 340 337 … … 346 343 ALLOC_IVT_CLEANUP, 347 344 ALLOC_IVT_CAS, 348 ALLOC_IVT_CONFIG, 349 ALLOC_IVT_TGT_RSP 345 ALLOC_IVT_CONFIG 350 346 }; 351 347 … … 496 492 void genMoore(); 497 493 void check_monitor(addr_t addr, data_t data, bool read); 498 bool hit_cleanup_req(size_t *index);499 bool hit_multi_ack_req(size_t *index);500 494 501 495 // Component attributes … … 516 510 TransactionTab m_trt; // xram transaction table 517 511 uint32_t m_upt_lines; 518 uint32_t m_ivt_lines;519 512 UpdateTab m_upt; // pending update 520 513 UpdateTab m_ivt; // pending invalidate … … 743 736 744 737 // Buffer between MULTI_ACK fsm and TGT_RSP fsm (complete write/update transaction) 745 sc_signal<bool> *r_multi_ack_to_tgt_rsp_req;// valid request738 sc_signal<bool> r_multi_ack_to_tgt_rsp_req; // valid request 746 739 sc_signal<size_t> r_multi_ack_to_tgt_rsp_srcid; // Transaction srcid 747 740 sc_signal<size_t> r_multi_ack_to_tgt_rsp_trdid; // Transaction trdid … … 791 784 792 785 // Buffer between CLEANUP fsm and TGT_RSP fsm (acknowledge a write command from L1) 793 sc_signal<bool> *r_cleanup_to_tgt_rsp_req; // valid request786 sc_signal<bool> r_cleanup_to_tgt_rsp_req; // valid request 794 787 sc_signal<size_t> r_cleanup_to_tgt_rsp_srcid; // transaction srcid 795 788 sc_signal<size_t> r_cleanup_to_tgt_rsp_trdid; // transaction trdid … … 926 919 sc_signal<int> r_tgt_rsp_fsm; 927 920 sc_signal<size_t> r_tgt_rsp_cpt; 928 sc_signal<size_t> r_tgt_rsp_prio_multi_ack;929 sc_signal<size_t> r_tgt_rsp_prio_cleanup;930 921 sc_signal<bool> r_tgt_rsp_key_sent; 931 922 -
trunk/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp
r482 r483 84 84 "TGT_RSP_XRAM", 85 85 "TGT_RSP_MULTI_ACK", 86 "TGT_RSP_CLEANUP", 87 "TGT_RSP_UPT_LOCK", 88 "TGT_RSP_IVT_LOCK" 86 "TGT_RSP_CLEANUP" 89 87 }; 90 88 const char *cc_receive_fsm_str[] = … … 287 285 "ALLOC_UPT_WRITE", 288 286 "ALLOC_UPT_CAS", 289 "ALLOC_UPT_MULTI_ACK", 290 "ALLOC_UPT_TGT_RSP" 287 "ALLOC_UPT_MULTI_ACK" 291 288 }; 292 289 const char *alloc_ivt_fsm_str[] = … … 296 293 "ALLOC_IVT_CLEANUP", 297 294 "ALLOC_IVT_CAS", 298 "ALLOC_IVT_CONFIG", 299 "ALLOC_IVT_TGT_RSP" 295 "ALLOC_IVT_CONFIG" 300 296 }; 301 297 const char *alloc_heap_fsm_str[] = … … 365 361 m_trt(this->name(), trt_lines, nwords), 366 362 m_upt_lines(upt_lines), 367 m_ivt_lines(ivt_lines),368 363 m_upt(upt_lines), 369 364 m_ivt(ivt_lines), … … 507 502 i++; 508 503 } 509 // Allocation for MULTI_ACK FSM510 r_multi_ack_to_tgt_rsp_req = new sc_signal<bool>[m_upt_lines];511 r_cleanup_to_tgt_rsp_req = new sc_signal<bool>[m_ivt_lines];512 504 513 505 // Allocation for IXR_RSP FSM … … 579 571 << " at cycle " << std::dec << m_cpt_cycles << std::endl; 580 572 } 581 }582 // Index is the value of the current priority583 ///////////////////////////////////////////////////////////////////////584 tmpl(bool) ::hit_cleanup_req(size_t *index)585 ///////////////////////////////////////////////////////////////////////586 {587 size_t i = *index;588 do589 {590 if(r_cleanup_to_tgt_rsp_req[i].read())591 {592 *index = i;593 return true;594 }595 i = (i + 1) % m_ivt_lines;596 } while (i != *index);597 return false;598 }599 600 // Index is the value of the current priority601 ///////////////////////////////////////////////////////////////////////602 tmpl(bool) ::hit_multi_ack_req(size_t *index)603 ///////////////////////////////////////////////////////////////////////604 {605 size_t i = *index;606 do607 {608 if(r_multi_ack_to_tgt_rsp_req[i].read())609 {610 *index = i;611 return true;612 }613 i = (i + 1) % m_upt_lines;614 } while (i != *index);615 return false;616 573 } 617 574 … … 717 674 { 718 675 delete [] r_ixr_rsp_to_xram_rsp_rok; 719 delete [] r_multi_ack_to_tgt_rsp_req; 720 delete [] r_cleanup_to_tgt_rsp_req; 676 721 677 delete [] r_xram_rsp_victim_data; 722 678 delete [] r_xram_rsp_to_tgt_rsp_data; … … 820 776 #endif 821 777 778 r_cleanup_to_tgt_rsp_req = false; 779 822 780 m_cc_receive_to_cleanup_fifo.init(); 823 for(size_t i = 0; i < m_upt_lines; i++) 824 { 825 r_multi_ack_to_tgt_rsp_req[i] = false; 826 } 827 for(size_t i = 0; i < m_ivt_lines; i++) 828 { 829 r_cleanup_to_tgt_rsp_req[i] = false; 830 } 781 782 r_multi_ack_to_tgt_rsp_req = false; 831 783 832 784 m_cc_receive_to_multi_ack_fifo.init(); … … 866 818 r_alloc_heap_reset_cpt = 0; 867 819 868 r_tgt_rsp_key_sent = false; 869 r_tgt_rsp_prio_multi_ack = 0; 870 r_tgt_rsp_prio_cleanup = 0; 820 r_tgt_rsp_key_sent = false; 871 821 872 822 // Activity counters … … 1387 1337 size_t count = 0; 1388 1338 bool valid = m_upt.decrement(r_multi_ack_upt_index.read(), count); 1389 1390 bool need_rsp = m_upt.need_rsp(r_multi_ack_upt_index.read());1391 1339 1392 1340 if(not valid) … … 1398 1346 } 1399 1347 1400 if(count == 0 and need_rsp) 1401 { 1402 r_multi_ack_fsm = MULTI_ACK_WRITE_RSP; 1403 } 1404 else if(count == 0) 1348 if(count == 0) 1405 1349 { 1406 1350 r_multi_ack_fsm = MULTI_ACK_UPT_CLEAR; … … 1436 1380 r_multi_ack_pktid = m_upt.pktid(r_multi_ack_upt_index.read()); 1437 1381 r_multi_ack_nline = m_upt.nline(r_multi_ack_upt_index.read()); 1382 bool need_rsp = m_upt.need_rsp(r_multi_ack_upt_index.read()); 1438 1383 bool need_ack = m_upt.need_ack(r_multi_ack_upt_index.read()); 1439 1384 … … 1441 1386 m_upt.clear(r_multi_ack_upt_index.read()); 1442 1387 1443 if ( need_ack ) r_multi_ack_fsm = MULTI_ACK_CONFIG_ACK; 1388 if ( need_rsp ) r_multi_ack_fsm = MULTI_ACK_WRITE_RSP; 1389 else if ( need_ack ) r_multi_ack_fsm = MULTI_ACK_CONFIG_ACK; 1444 1390 else r_multi_ack_fsm = MULTI_ACK_IDLE; 1445 1391 … … 1454 1400 ///////////////////////// 1455 1401 case MULTI_ACK_WRITE_RSP: // Post a response request to TGT_RSP FSM 1456 { 1457 r_multi_ack_to_tgt_rsp_req[r_multi_ack_upt_index.read()] = true; 1458 r_multi_ack_fsm = MULTI_ACK_IDLE; 1402 // Wait if pending request 1403 { 1404 if ( r_multi_ack_to_tgt_rsp_req.read() ) break; 1405 1406 r_multi_ack_to_tgt_rsp_req = true; 1407 r_multi_ack_to_tgt_rsp_srcid = r_multi_ack_srcid.read(); 1408 r_multi_ack_to_tgt_rsp_trdid = r_multi_ack_trdid.read(); 1409 r_multi_ack_to_tgt_rsp_pktid = r_multi_ack_pktid.read(); 1410 r_multi_ack_fsm = MULTI_ACK_IDLE; 1459 1411 1460 1412 #if DEBUG_MEMC_MULTI_ACK 1461 1413 if(m_debug) 1462 1414 std::cout << " <MEMC " << name() << " MULTI_ACK_WRITE_RSP>" 1463 << " Request TGT_RSP FSM to send a response "1464 << " / Request for upt index " << r_multi_ack_upt_index.read() << std::endl;1415 << " Request TGT_RSP FSM to send a response to srcid " 1416 << std::hex << r_multi_ack_srcid.read() << std::endl; 1465 1417 #endif 1466 1418 break; … … 4961 4913 size_t count = 0; 4962 4914 m_ivt.decrement(r_cleanup_index.read(), count); 4963 4964 if((count == 0) and r_cleanup_need_rsp.read()) // multi inval transaction completed 4965 { 4966 r_cleanup_fsm = CLEANUP_WRITE_RSP; 4967 } 4968 else if(count == 0) // multi inval transaction completed 4915 4916 if(count == 0) // multi inval transaction completed 4969 4917 { 4970 4918 r_cleanup_fsm = CLEANUP_IVT_CLEAR; … … 5000 4948 m_ivt.clear(r_cleanup_index.read()); 5001 4949 5002 if ( r_cleanup_need_ack.read() ) r_cleanup_fsm = CLEANUP_CONFIG_ACK; 4950 if ( r_cleanup_need_rsp.read() ) r_cleanup_fsm = CLEANUP_WRITE_RSP; 4951 else if ( r_cleanup_need_ack.read() ) r_cleanup_fsm = CLEANUP_CONFIG_ACK; 5003 4952 else r_cleanup_fsm = CLEANUP_SEND_CLACK; 5004 4953 … … 5015 4964 // wait if pending request to the TGT_RSP FSM 5016 4965 { 4966 if(r_cleanup_to_tgt_rsp_req.read()) break; 5017 4967 5018 4968 // no pending request 5019 r_cleanup_to_tgt_rsp_req[r_cleanup_index.read()] = true; 4969 r_cleanup_to_tgt_rsp_req = true; 4970 r_cleanup_to_tgt_rsp_srcid = r_cleanup_write_srcid.read(); 4971 r_cleanup_to_tgt_rsp_trdid = r_cleanup_write_trdid.read(); 4972 r_cleanup_to_tgt_rsp_pktid = r_cleanup_write_pktid.read(); 5020 4973 5021 4974 r_cleanup_fsm = CLEANUP_SEND_CLACK; … … 5024 4977 if(m_debug) 5025 4978 std::cout << " <MEMC " << name() << " CLEANUP_WRITE_RSP>" 5026 << " Send a response to a previous write request" 5027 << std::endl; 4979 << " Send a response to a previous write request: " 4980 << " rsrcid = " << std::hex << r_cleanup_write_srcid.read() 4981 << " / rtrdid = " << r_cleanup_write_trdid.read() 4982 << " / rpktid = " << r_cleanup_write_pktid.read() << std::endl; 5028 4983 #endif 5029 4984 break; … … 6530 6485 case TGT_RSP_CONFIG_IDLE: // tgt_cmd requests have the highest priority 6531 6486 { 6532 size_t prio_multi_ack = r_tgt_rsp_prio_multi_ack.read();6533 size_t prio_cleanup = r_tgt_rsp_prio_cleanup.read();6534 6487 if(r_tgt_cmd_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_TGT_CMD; 6535 6488 else if(r_read_to_tgt_rsp_req) … … 6545 6498 r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read(); 6546 6499 } 6547 else if(hit_multi_ack_req(&prio_multi_ack)) 6548 { 6549 r_tgt_rsp_fsm = TGT_RSP_UPT_LOCK; 6550 // update rr priority 6551 r_tgt_rsp_prio_multi_ack = prio_multi_ack; 6552 } 6553 else if(hit_cleanup_req(&prio_cleanup)) 6554 { 6555 r_tgt_rsp_fsm = TGT_RSP_IVT_LOCK; 6556 r_tgt_rsp_prio_cleanup = prio_cleanup; 6557 } 6500 else if(r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK; 6501 else if(r_cleanup_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CLEANUP; 6558 6502 else if(r_config_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CONFIG; 6559 6503 break; … … 6562 6506 case TGT_RSP_TGT_CMD_IDLE: // read requests have the highest priority 6563 6507 { 6564 size_t prio_multi_ack = r_tgt_rsp_prio_multi_ack.read();6565 size_t prio_cleanup = r_tgt_rsp_prio_cleanup.read();6566 6508 if(r_read_to_tgt_rsp_req) 6567 6509 { … … 6576 6518 r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read(); 6577 6519 } 6578 else if(hit_multi_ack_req(&prio_multi_ack)) 6579 { 6580 r_tgt_rsp_fsm = TGT_RSP_UPT_LOCK; 6581 // update rr priority 6582 r_tgt_rsp_prio_multi_ack = prio_multi_ack; 6583 } 6584 else if(hit_cleanup_req(&prio_cleanup)) 6585 { 6586 r_tgt_rsp_fsm = TGT_RSP_IVT_LOCK; 6587 r_tgt_rsp_prio_cleanup = prio_cleanup; 6588 } 6520 else if(r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK; 6521 else if(r_cleanup_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CLEANUP; 6589 6522 else if(r_config_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CONFIG; 6590 6523 else if(r_tgt_cmd_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_TGT_CMD; … … 6594 6527 case TGT_RSP_READ_IDLE: // write requests have the highest priority 6595 6528 { 6596 size_t prio_multi_ack = r_tgt_rsp_prio_multi_ack.read();6597 size_t prio_cleanup = r_tgt_rsp_prio_cleanup.read();6598 6529 if(r_write_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_WRITE; 6599 6530 else if(r_cas_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CAS; … … 6603 6534 r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read(); 6604 6535 } 6605 else if(hit_multi_ack_req(&prio_multi_ack)) 6606 { 6607 r_tgt_rsp_fsm = TGT_RSP_UPT_LOCK; 6608 // update rr priority 6609 r_tgt_rsp_prio_multi_ack = prio_multi_ack; 6610 } 6611 else if(hit_cleanup_req(&prio_cleanup)) 6612 { 6613 r_tgt_rsp_fsm = TGT_RSP_IVT_LOCK; 6614 r_tgt_rsp_prio_cleanup = prio_cleanup; 6615 } 6536 else if(r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK; 6537 else if(r_cleanup_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CLEANUP; 6616 6538 else if(r_config_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CONFIG; 6617 6539 else if(r_tgt_cmd_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_TGT_CMD; … … 6626 6548 case TGT_RSP_WRITE_IDLE: // cas requests have the highest priority 6627 6549 { 6628 size_t prio_multi_ack = r_tgt_rsp_prio_multi_ack.read();6629 size_t prio_cleanup = r_tgt_rsp_prio_cleanup.read();6630 6550 if(r_cas_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CAS; 6631 6551 else if(r_xram_rsp_to_tgt_rsp_req) … … 6634 6554 r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read(); 6635 6555 } 6636 else if(hit_multi_ack_req(&prio_multi_ack)) 6637 { 6638 r_tgt_rsp_fsm = TGT_RSP_UPT_LOCK; 6639 // update rr priority 6640 r_tgt_rsp_prio_multi_ack = prio_multi_ack; 6641 } 6642 else if(hit_cleanup_req(&prio_cleanup)) 6643 { 6644 r_tgt_rsp_fsm = TGT_RSP_IVT_LOCK; 6645 r_tgt_rsp_prio_cleanup = prio_cleanup; 6646 } 6556 else if(r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK; 6557 else if(r_cleanup_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CLEANUP; 6647 6558 else if(r_config_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CONFIG; 6648 6559 else if(r_tgt_cmd_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_TGT_CMD; … … 6658 6569 case TGT_RSP_CAS_IDLE: // xram_rsp requests have the highest priority 6659 6570 { 6660 size_t prio_multi_ack = r_tgt_rsp_prio_multi_ack.read();6661 size_t prio_cleanup = r_tgt_rsp_prio_cleanup.read();6662 6571 if(r_xram_rsp_to_tgt_rsp_req) 6663 6572 { … … 6665 6574 r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read(); 6666 6575 } 6667 else if(hit_multi_ack_req(&prio_multi_ack)) 6668 { 6669 r_tgt_rsp_fsm = TGT_RSP_UPT_LOCK; 6670 // update rr priority 6671 r_tgt_rsp_prio_multi_ack = prio_multi_ack; 6672 } 6673 else if(hit_cleanup_req(&prio_cleanup)) 6674 { 6675 r_tgt_rsp_fsm = TGT_RSP_IVT_LOCK; 6676 r_tgt_rsp_prio_cleanup = prio_cleanup; 6677 } 6576 else if(r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK ; 6577 else if(r_cleanup_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CLEANUP; 6678 6578 else if(r_config_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CONFIG; 6679 6579 else if(r_tgt_cmd_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_TGT_CMD; … … 6690 6590 case TGT_RSP_XRAM_IDLE: // multi ack requests have the highest priority 6691 6591 { 6692 size_t prio_multi_ack = r_tgt_rsp_prio_multi_ack.read(); 6693 size_t prio_cleanup = r_tgt_rsp_prio_cleanup.read(); 6694 6695 if(hit_multi_ack_req(&prio_multi_ack)) 6696 { 6697 r_tgt_rsp_fsm = TGT_RSP_UPT_LOCK; 6698 // update rr priority 6699 r_tgt_rsp_prio_multi_ack = prio_multi_ack; 6700 } 6701 else if(hit_cleanup_req(&prio_cleanup)) 6702 { 6703 r_tgt_rsp_fsm = TGT_RSP_IVT_LOCK; 6704 r_tgt_rsp_prio_cleanup = prio_cleanup; 6705 } 6592 6593 if(r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK ; 6594 else if(r_cleanup_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CLEANUP; 6706 6595 else if(r_config_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CONFIG; 6707 6596 else if(r_tgt_cmd_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_TGT_CMD; … … 6723 6612 case TGT_RSP_MULTI_ACK_IDLE: // cleanup requests have the highest priority 6724 6613 { 6725 size_t prio_multi_ack = r_tgt_rsp_prio_multi_ack.read(); 6726 size_t prio_cleanup = r_tgt_rsp_prio_cleanup.read(); 6727 if(hit_cleanup_req(&prio_cleanup)) 6728 { 6729 r_tgt_rsp_fsm = TGT_RSP_IVT_LOCK; 6730 r_tgt_rsp_prio_cleanup = prio_cleanup; 6731 } 6614 if(r_cleanup_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CLEANUP; 6732 6615 else if(r_config_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CONFIG; 6733 6616 else if(r_tgt_cmd_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_TGT_CMD; … … 6744 6627 r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read(); 6745 6628 } 6746 else if(hit_multi_ack_req(&prio_multi_ack)) 6747 { 6748 r_tgt_rsp_fsm = TGT_RSP_UPT_LOCK; 6749 // update rr priority 6750 r_tgt_rsp_prio_multi_ack = prio_multi_ack; 6751 } 6629 else if(r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK; 6752 6630 break; 6753 6631 } … … 6755 6633 case TGT_RSP_CLEANUP_IDLE: // tgt cmd requests have the highest priority 6756 6634 { 6757 size_t prio_multi_ack = r_tgt_rsp_prio_multi_ack.read();6758 size_t prio_cleanup = r_tgt_rsp_prio_cleanup.read();6759 6635 if(r_config_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CONFIG; 6760 6636 else if(r_tgt_cmd_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_TGT_CMD; … … 6771 6647 r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read(); 6772 6648 } 6773 else if(hit_multi_ack_req(&prio_multi_ack)) 6774 { 6775 r_tgt_rsp_fsm = TGT_RSP_UPT_LOCK; 6776 // update rr priority 6777 r_tgt_rsp_prio_multi_ack = prio_multi_ack; 6778 } 6779 else if(hit_cleanup_req(&prio_cleanup)) 6780 { 6781 r_tgt_rsp_fsm = TGT_RSP_IVT_LOCK; 6782 r_tgt_rsp_prio_cleanup = prio_cleanup; 6783 } 6649 else if(r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK ; 6650 else if(r_cleanup_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CLEANUP; 6784 6651 break; 6785 6652 } … … 6894 6761 break; 6895 6762 } 6896 6897 ///////////////////////6898 case TGT_RSP_IVT_LOCK: // Clear IVT entry6899 {6900 if (r_alloc_ivt_fsm.read() != ALLOC_IVT_TGT_RSP) break;6901 6902 r_cleanup_to_tgt_rsp_srcid = m_ivt.srcid(r_tgt_rsp_prio_cleanup.read());6903 r_cleanup_to_tgt_rsp_trdid = m_ivt.trdid(r_tgt_rsp_prio_cleanup.read());6904 r_cleanup_to_tgt_rsp_pktid = m_ivt.pktid(r_tgt_rsp_prio_cleanup.read());6905 6906 m_ivt.clear(r_tgt_rsp_prio_cleanup.read());6907 6908 r_tgt_rsp_fsm = TGT_RSP_CLEANUP;6909 break;6910 }6911 6912 6763 ///////////////////// 6913 6764 case TGT_RSP_CLEANUP: // pas clair pour moi (AG) … … 6924 6775 #endif 6925 6776 r_tgt_rsp_fsm = TGT_RSP_CLEANUP_IDLE; 6926 r_cleanup_to_tgt_rsp_req[r_tgt_rsp_prio_cleanup.read()] = false; 6927 r_tgt_rsp_prio_cleanup = (r_tgt_rsp_prio_cleanup.read() + 1) % m_ivt_lines; 6777 r_cleanup_to_tgt_rsp_req = false; 6928 6778 } 6929 6779 break; … … 6991 6841 } 6992 6842 /////////////////////// 6993 case TGT_RSP_UPT_LOCK: // Clear UPT entry6994 {6995 if (r_alloc_upt_fsm.read() != ALLOC_UPT_TGT_RSP) break;6996 6997 r_multi_ack_to_tgt_rsp_srcid = m_upt.srcid(r_tgt_rsp_prio_multi_ack.read());6998 r_multi_ack_to_tgt_rsp_trdid = m_upt.trdid(r_tgt_rsp_prio_multi_ack.read());6999 r_multi_ack_to_tgt_rsp_pktid = m_upt.pktid(r_tgt_rsp_prio_multi_ack.read());7000 7001 m_upt.clear(r_tgt_rsp_prio_multi_ack.read());7002 7003 r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK;7004 break;7005 }7006 7007 ///////////////////////7008 6843 case TGT_RSP_MULTI_ACK: // send the write response after coherence transaction 7009 6844 { … … 7019 6854 #endif 7020 6855 r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK_IDLE; 7021 r_multi_ack_to_tgt_rsp_req[r_tgt_rsp_prio_multi_ack.read()] = false; 7022 r_tgt_rsp_prio_multi_ack = (r_tgt_rsp_prio_multi_ack.read() + 1) % m_upt_lines; 6856 r_multi_ack_to_tgt_rsp_req = false; 7023 6857 } 7024 6858 break; … … 7048 6882 else if (r_multi_ack_fsm.read() == MULTI_ACK_UPT_LOCK) 7049 6883 r_alloc_upt_fsm = ALLOC_UPT_MULTI_ACK; 7050 7051 else if (r_tgt_rsp_fsm.read() == TGT_RSP_UPT_LOCK)7052 r_alloc_upt_fsm = ALLOC_UPT_TGT_RSP;7053 6884 } 7054 6885 break; … … 7060 6891 if (r_multi_ack_fsm.read() == MULTI_ACK_UPT_LOCK) 7061 6892 r_alloc_upt_fsm = ALLOC_UPT_MULTI_ACK; 7062 7063 else if (r_tgt_rsp_fsm.read() == TGT_RSP_UPT_LOCK)7064 r_alloc_upt_fsm = ALLOC_UPT_TGT_RSP;7065 6893 7066 6894 else if (r_write_fsm.read() == WRITE_UPT_LOCK) … … 7074 6902 (r_multi_ack_fsm.read() != MULTI_ACK_UPT_CLEAR)) 7075 6903 { 7076 if (r_tgt_rsp_fsm.read() == TGT_RSP_UPT_LOCK) 7077 r_alloc_upt_fsm = ALLOC_UPT_TGT_RSP; 7078 7079 else if (r_write_fsm.read() == WRITE_UPT_LOCK) 6904 if (r_write_fsm.read() == WRITE_UPT_LOCK) 7080 6905 r_alloc_upt_fsm = ALLOC_UPT_WRITE; 7081 6906 7082 6907 else if (r_cas_fsm.read() == CAS_UPT_LOCK) 7083 6908 r_alloc_upt_fsm = ALLOC_UPT_CAS; 7084 }7085 break;7086 7087 /////////////////////////7088 case ALLOC_UPT_TGT_RSP: // allocated to TGT_RSP FSM7089 if (r_tgt_rsp_fsm.read() != TGT_RSP_UPT_LOCK )7090 {7091 if (r_write_fsm.read() == WRITE_UPT_LOCK)7092 r_alloc_upt_fsm = ALLOC_UPT_WRITE;7093 7094 else if (r_cas_fsm.read() == CAS_UPT_LOCK)7095 r_alloc_upt_fsm = ALLOC_UPT_CAS;7096 7097 else if (r_multi_ack_fsm.read() == MULTI_ACK_UPT_LOCK)7098 r_alloc_upt_fsm = ALLOC_UPT_MULTI_ACK;7099 7100 6909 } 7101 6910 break; … … 7134 6943 else if (r_config_fsm.read() == CONFIG_DIR_IVT_LOCK) 7135 6944 r_alloc_ivt_fsm = ALLOC_IVT_CONFIG; 7136 7137 else if (r_tgt_rsp_fsm.read() == TGT_RSP_IVT_LOCK)7138 r_alloc_ivt_fsm = ALLOC_IVT_TGT_RSP;7139 6945 } 7140 6946 break; … … 7152 6958 else if (r_config_fsm.read() == CONFIG_DIR_IVT_LOCK) 7153 6959 r_alloc_ivt_fsm = ALLOC_IVT_CONFIG; 7154 7155 else if (r_tgt_rsp_fsm.read() == TGT_RSP_IVT_LOCK)7156 r_alloc_ivt_fsm = ALLOC_IVT_TGT_RSP;7157 6960 7158 6961 else if (r_write_fsm.read() == WRITE_BC_IVT_LOCK) … … 7171 6974 else if (r_config_fsm.read() == CONFIG_DIR_IVT_LOCK) 7172 6975 r_alloc_ivt_fsm = ALLOC_IVT_CONFIG; 7173 7174 else if (r_tgt_rsp_fsm.read() == TGT_RSP_IVT_LOCK)7175 r_alloc_ivt_fsm = ALLOC_IVT_TGT_RSP;7176 6976 7177 6977 else if (r_write_fsm.read() == WRITE_BC_IVT_LOCK) … … 7189 6989 if (r_config_fsm.read() == CONFIG_DIR_IVT_LOCK) 7190 6990 r_alloc_ivt_fsm = ALLOC_IVT_CONFIG; 7191 7192 else if (r_tgt_rsp_fsm.read() == TGT_RSP_IVT_LOCK)7193 r_alloc_ivt_fsm = ALLOC_IVT_TGT_RSP;7194 6991 7195 6992 else if (r_write_fsm.read() == WRITE_BC_IVT_LOCK) … … 7207 7004 case ALLOC_IVT_CONFIG: // allocated to CONFIG FSM 7208 7005 if (r_config_fsm.read() != CONFIG_DIR_IVT_LOCK) 7209 { 7210 if (r_tgt_rsp_fsm.read() == TGT_RSP_IVT_LOCK) 7211 r_alloc_ivt_fsm = ALLOC_IVT_TGT_RSP; 7212 7213 else if (r_write_fsm.read() == WRITE_BC_IVT_LOCK) 7006 { 7007 if (r_write_fsm.read() == WRITE_BC_IVT_LOCK) 7214 7008 r_alloc_ivt_fsm = ALLOC_IVT_WRITE; 7215 7009 … … 7222 7016 else if (r_cas_fsm.read() == CAS_BC_IVT_LOCK) 7223 7017 r_alloc_ivt_fsm = ALLOC_IVT_CAS; 7224 }7225 break;7226 7227 //////////////////////////7228 case ALLOC_IVT_TGT_RSP: // allocated to TGT RSP FSM7229 if (r_tgt_rsp_fsm.read() != TGT_RSP_IVT_LOCK)7230 {7231 if (r_write_fsm.read() == WRITE_BC_IVT_LOCK)7232 r_alloc_ivt_fsm = ALLOC_IVT_WRITE;7233 7234 else if (r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK)7235 r_alloc_ivt_fsm = ALLOC_IVT_XRAM_RSP;7236 7237 else if (r_cleanup_fsm.read() == CLEANUP_IVT_LOCK)7238 r_alloc_ivt_fsm = ALLOC_IVT_CLEANUP;7239 7240 else if (r_cas_fsm.read() == CAS_BC_IVT_LOCK)7241 r_alloc_ivt_fsm = ALLOC_IVT_CAS;7242 7243 else if (r_config_fsm.read() == CONFIG_DIR_IVT_LOCK)7244 r_alloc_ivt_fsm = ALLOC_IVT_CONFIG;7245 7018 } 7246 7019 break;
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