Index: trunk/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp =================================================================== --- trunk/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp (revision 483) +++ trunk/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp (revision 484) @@ -1030,5 +1030,5 @@ // coherence interrupt - if ( r_cc_receive_icache_req.read() ) + if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read()) { r_icache_fsm = ICACHE_CC_CHECK; @@ -1266,5 +1266,5 @@ // coherence interrupt - if ( r_cc_receive_icache_req.read() ) + if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read()) { r_icache_fsm = ICACHE_CC_CHECK; @@ -1318,5 +1318,5 @@ // coherence request (from CC_RECEIVE FSM) - if ( r_cc_receive_icache_req.read() ) + if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read()) { r_icache_fsm = ICACHE_CC_CHECK; @@ -1525,5 +1525,5 @@ // coherence interrupt - if ( r_cc_receive_icache_req.read() ) + if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read()) { r_icache_fsm = ICACHE_CC_CHECK; @@ -1622,5 +1622,5 @@ // coherence interrupt - if ( r_cc_receive_icache_req.read() ) + if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read()) { r_icache_fsm = ICACHE_CC_CHECK; @@ -1701,5 +1701,5 @@ // coherence interrupt - if ( r_cc_receive_icache_req.read() ) + if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read()) { r_icache_fsm = ICACHE_CC_CHECK; @@ -1780,5 +1780,5 @@ // coherence interrupt - if ( r_cc_receive_icache_req.read() ) + if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read()) { r_icache_fsm = ICACHE_CC_CHECK; @@ -1819,4 +1819,44 @@ paddr_t mask = ~((m_icache_words<<2)-1); + // CLACK handler + // We switch the directory slot to EMPTY state + // and reset r_icache_miss_clack if the cleanup ack + // is matching a pending miss. + if ( r_icache_clack_req.read() ) + { + + if ( m_ireq.valid ) m_cost_ins_miss_frz++; + +#ifdef INSTRUMENTATION +m_cpt_icache_dir_write++; +#endif + r_icache.write_dir( 0, + r_icache_clack_way.read(), + r_icache_clack_set.read(), + CACHE_SLOT_STATE_EMPTY); + + if ( (r_icache_miss_set.read() == r_icache_clack_set.read()) and + (r_icache_miss_way.read() == r_icache_clack_way.read()) ) + { + r_icache_miss_clack = false; + } + + r_icache_clack_req = false; + + // return to cc_save state + r_icache_fsm = r_icache_fsm_save.read(); + +#if DEBUG_ICACHE +if ( m_debug_activated ) +{ + std::cout << " CC_TYPE_CLACK slot returns to empty state" + << " set = " << r_icache_clack_set.read() + << " / way = " << r_icache_clack_way.read() << std::endl; +} +#endif + + break; + } // Match between MISS address and CC address @@ -1858,50 +1898,5 @@ } - // CLACK handler - // We switch the directory slot to EMPTY state - // and reset r_icache_miss_clack if the cleanup ack - // is matching a pending miss. - if ( r_icache_clack_req.read() ) - { - - if ( m_ireq.valid ) m_cost_ins_miss_frz++; - -#ifdef INSTRUMENTATION -m_cpt_icache_dir_write++; -#endif - r_icache.write_dir( 0, - r_icache_clack_way.read(), - r_icache_clack_set.read(), - CACHE_SLOT_STATE_EMPTY); - - if ( (r_icache_miss_set.read() == r_icache_clack_set.read()) and - (r_icache_miss_way.read() == r_icache_clack_way.read()) ) - { - r_icache_miss_clack = false; - } - - r_icache_clack_req = false; - - // return to cc_save state if no pending CC request - if ( not r_cc_receive_icache_req.read() ) - r_icache_fsm = r_icache_fsm_save.read(); - -#if DEBUG_ICACHE -if ( m_debug_activated ) -{ - std::cout << " CC_TYPE_CLACK slot returns to empty state" - << " set = " << r_icache_clack_set.read() - << " / way = " << r_icache_clack_way.read() << std::endl; -} -#endif - - break; - } - - // wait if pending request to CC_SEND. This way if there are pending - // CLACK they can be treated in this state and then a deadlock - // situation is avoided - if ( r_icache_cc_send_req.read() ) break; + assert ( not r_icache_cc_send_req.read() and "CC_SEND must be available in ICACHE_CC_CHECK"); // CC request handler @@ -2344,5 +2339,5 @@ } // coherence request (from CC_RECEIVE FSM) - else if ( r_cc_receive_dcache_req.read() ) + else if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) { r_dcache_fsm = DCACHE_CC_CHECK; @@ -2956,5 +2951,5 @@ // coherence request (from CC_RECEIVE FSM) - if ( r_cc_receive_dcache_req.read() ) + if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) { r_dcache_fsm = DCACHE_CC_CHECK; @@ -3261,5 +3256,5 @@ // coherence request (from CC_RECEIVE FSM) - if ( r_cc_receive_dcache_req.read() ) + if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) { r_dcache_fsm = DCACHE_CC_CHECK; @@ -3566,5 +3561,5 @@ // coherence request (from CC_RECEIVE FSM) - if ( r_cc_receive_dcache_req.read() ) + if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) { r_dcache_fsm = DCACHE_CC_CHECK; @@ -3645,5 +3640,5 @@ // coherence request (from CC_RECEIVE FSM) - if ( r_cc_receive_dcache_req.read() ) + if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) { r_dcache_fsm = DCACHE_CC_CHECK; @@ -3675,5 +3670,5 @@ // coherence request (from CC_RECEIVE FSM) - if ( r_cc_receive_dcache_req.read() ) + if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) { r_dcache_fsm = DCACHE_CC_CHECK; @@ -3718,5 +3713,5 @@ // coherence request (from CC_RECEIVE FSM) - if ( r_cc_receive_dcache_req.read() ) + if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) { r_dcache_fsm = DCACHE_CC_CHECK; @@ -3987,5 +3982,5 @@ // coherence request (from CC_RECEIVE FSM) - if ( r_cc_receive_dcache_req.read() ) + if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) { r_dcache_fsm = DCACHE_CC_CHECK; @@ -4111,5 +4106,5 @@ // coherence request (from CC_RECEIVE FSM) - if ( r_cc_receive_dcache_req.read() ) + if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) { r_dcache_fsm = DCACHE_CC_CHECK; @@ -4234,5 +4229,5 @@ // coherence request (from CC_RECEIVE FSM) - if ( r_cc_receive_dcache_req.read() ) + if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) { r_dcache_fsm = DCACHE_CC_CHECK; @@ -4316,5 +4311,5 @@ // coherence request (from CC_RECEIVE FSM) - if ( r_cc_receive_dcache_req.read() ) + if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) { r_dcache_fsm = DCACHE_CC_CHECK; @@ -4361,5 +4356,5 @@ // coherence request (from CC_RECEIVE FSM) - if ( r_cc_receive_dcache_req.read() ) + if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) { r_dcache_fsm = DCACHE_CC_CHECK; @@ -4415,5 +4410,5 @@ // coherence request (from CC_RECEIVE FSM) - if ( r_cc_receive_dcache_req.read() ) + if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) { r_dcache_fsm = DCACHE_CC_CHECK; @@ -4515,5 +4510,5 @@ // coherence request (from CC_RECEIVE FSM) - if ( r_cc_receive_dcache_req.read() ) + if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) { r_dcache_fsm = DCACHE_CC_CHECK; @@ -4571,4 +4566,41 @@ } #endif + // CLACK handler + // We switch the directory slot to EMPTY state and reset + // r_dcache_miss_clack if the cleanup ack is matching a pending miss. + if ( r_dcache_clack_req.read() ) + { + if ( m_dreq.valid ) m_cost_data_miss_frz++; + +#ifdef INSTRUMENTATION +m_cpt_dcache_dir_write++; +#endif + r_dcache.write_dir( 0, + r_dcache_clack_way.read(), + r_dcache_clack_set.read(), + CACHE_SLOT_STATE_EMPTY); + + if ( (r_dcache_miss_set.read() == r_dcache_clack_set.read()) and + (r_dcache_miss_way.read() == r_dcache_clack_way.read()) ) + { + r_dcache_miss_clack = false; + } + + r_dcache_clack_req = false; + + // return to cc_save state + r_dcache_fsm = r_dcache_fsm_cc_save.read() ; + +#if DEBUG_DCACHE +if ( m_debug_activated ) +{ + std::cout << " CC_TYPE_CLACK Switch slot to EMPTY state" + << " set = " << r_dcache_clack_set.read() + << " / way = " << r_dcache_clack_way.read() << std::endl; +} +#endif + break; + } @@ -4612,49 +4644,6 @@ } - // CLACK handler - // We switch the directory slot to EMPTY state and reset - // r_dcache_miss_clack if the cleanup ack is matching a pending miss. - if ( r_dcache_clack_req.read() ) - { - if ( m_dreq.valid ) m_cost_data_miss_frz++; - -#ifdef INSTRUMENTATION -m_cpt_dcache_dir_write++; -#endif - r_dcache.write_dir( 0, - r_dcache_clack_way.read(), - r_dcache_clack_set.read(), - CACHE_SLOT_STATE_EMPTY); - - if ( (r_dcache_miss_set.read() == r_dcache_clack_set.read()) and - (r_dcache_miss_way.read() == r_dcache_clack_way.read()) ) - { - r_dcache_miss_clack = false; - } - - r_dcache_clack_req = false; - - // return to cc_save state if no pending CC request - if ( not r_cc_receive_dcache_req.read() ) - { - r_dcache_fsm = r_dcache_fsm_cc_save.read() ; - } - -#if DEBUG_DCACHE -if ( m_debug_activated ) -{ - std::cout << " CC_TYPE_CLACK Switch slot to EMPTY state" - << " set = " << r_dcache_clack_set.read() - << " / way = " << r_dcache_clack_way.read() << std::endl; -} -#endif - break; - } - - // wait if pending request to CC_SEND. This way if there are pending - // CLACK they can be treated in this state and then a deadlock - // situation is avoided - if ( r_dcache_cc_send_req.read() ) break; + + assert ( not r_dcache_cc_send_req.read() and "CC_SEND must be available in DCACHE_CC_CHECK" ); // CC request handler @@ -5573,5 +5562,5 @@ // flip_flop to check that ? if (not (r_cc_receive_icache_req.read()) and - not (r_cc_receive_dcache_req.read()) and + not (r_cc_receive_dcache_req.read()) and (p_dspin_m2p.write.read())) { @@ -5613,5 +5602,6 @@ uint64_t receive_data = p_dspin_m2p.data.read(); // for data INVAL, wait for dcache to take the request - if (p_dspin_m2p.write.read() and not r_cc_receive_dcache_req.read()) + if (p_dspin_m2p.write.read() and + not r_cc_receive_dcache_req.read() ) { // request dcache to handle the INVAL @@ -5631,5 +5621,6 @@ uint64_t receive_data = p_dspin_m2p.data.read(); // for ins INVAL, wait for icache to take the request - if (p_dspin_m2p.write.read() and not r_cc_receive_icache_req.read()) + if (p_dspin_m2p.write.read() and + not r_cc_receive_icache_req.read() ) { // request icache to handle the INVAL @@ -5681,5 +5672,5 @@ // for data INVAL, wait for dcache to take the request and fifo to // be empty - if ( r_cc_receive_updt_fifo_be.empty() and + if ( r_cc_receive_updt_fifo_be.empty() and p_dspin_m2p.write.read() ) { @@ -5701,5 +5692,5 @@ // for ins INVAL, wait for icache to take the request and fifo to be // empty - if ( r_cc_receive_updt_fifo_be.empty() and + if ( r_cc_receive_updt_fifo_be.empty() and p_dspin_m2p.write.read() ) {