Changeset 489 for trunk/modules/vci_mem_cache/caba/source/include
- Timestamp:
- Aug 9, 2013, 11:00:05 AM (11 years ago)
- Location:
- trunk/modules/vci_mem_cache/caba/source/include
- Files:
-
- 3 edited
-
mem_cache_directory.h (modified) (12 diffs)
-
vci_mem_cache.h (modified) (24 diffs)
-
xram_transaction.h (modified) (26 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/modules/vci_mem_cache/caba/source/include/mem_cache_directory.h
r449 r489 6 6 #include <cassert> 7 7 #include "arithmetics.h" 8 9 // !!!10 // The L1_MULTI_CACHE mechanism does no longer work with the new pktid encoding11 // of TSAR. Turning the define below to a non null value will cause the memcache12 // to behave in an unpredicted way.13 // TODO Either remove the mechanism from the mem cache or update its behaviour.14 15 #define L1_MULTI_CACHE 016 8 17 9 //#define RANDOM_EVICTION … … 46 38 bool inst; // Is the owner an ICache ? 47 39 size_t srcid; // The SRCID of the owner 48 #if L1_MULTI_CACHE49 size_t cache_id; // In multi_cache configuration50 #endif51 40 52 41 //////////////////////// 53 42 // Constructors 54 43 //////////////////////// 55 Owner(bool i_inst 56 ,size_t i_srcid 57 #if L1_MULTI_CACHE 58 ,size_t i_cache_id 59 #endif 60 ){ 44 Owner(bool i_inst, 45 size_t i_srcid) 46 { 61 47 inst = i_inst; 62 48 srcid = i_srcid; 63 #if L1_MULTI_CACHE 64 cache_id= i_cache_id; 65 #endif 66 } 67 68 Owner(const Owner &a){ 49 } 50 51 Owner(const Owner &a) 52 { 69 53 inst = a.inst; 70 54 srcid = a.srcid; 71 #if L1_MULTI_CACHE 72 cache_id= a.cache_id; 73 #endif 74 } 75 76 Owner(){ 55 } 56 57 Owner() 58 { 77 59 inst = false; 78 60 srcid = 0; 79 #if L1_MULTI_CACHE80 cache_id= 0;81 #endif82 61 } 83 62 // end constructors … … 114 93 owner.inst = 0; 115 94 owner.srcid = 0; 116 #if L1_MULTI_CACHE117 owner.cache_id= 0;118 #endif119 95 ptr = 0; 120 96 } … … 171 147 << " ; Count = " << count 172 148 << " ; Owner = " << owner.srcid 173 #if L1_MULTI_CACHE174 << "." << owner.cache_id175 #endif176 149 << " " << owner.inst 177 150 << " ; Pointer = " << ptr << std::endl; … … 322 295 // - entry : the entry value 323 296 ///////////////////////////////////////////////////////////////////// 324 void write(const size_t &set, const size_t &way, const DirectoryEntry &entry) 297 void write( const size_t &set, 298 const size_t &way, 299 const DirectoryEntry &entry) 325 300 { 326 301 assert( (set<m_sets) … … 368 343 DirectoryEntry select(const size_t &set, size_t &way) 369 344 { 370 assert( (set < m_sets)345 assert( (set < m_sets) 371 346 && "Cache Directory : (select) The set index is invalid"); 372 347 373 for(size_t i=0; i<m_ways; i++){ 374 if(!m_dir_tab[set][i].valid){ 375 way=i; 376 return DirectoryEntry(m_dir_tab[set][way]); 348 // looking for an empty slot 349 for(size_t i=0; i<m_ways; i++) 350 { 351 if( not m_dir_tab[set][i].valid ) 352 { 353 way=i; 354 return DirectoryEntry(m_dir_tab[set][way]); 355 } 377 356 } 378 }379 357 380 358 #ifdef RANDOM_EVICTION 381 lfsr = (lfsr >> 1) ^ ((-(lfsr & 1)) & 0xd0000001);382 way = lfsr % m_ways;383 return DirectoryEntry(m_dir_tab[set][way]);359 lfsr = (lfsr >> 1) ^ ((-(lfsr & 1)) & 0xd0000001); 360 way = lfsr % m_ways; 361 return DirectoryEntry(m_dir_tab[set][way]); 384 362 #endif 385 363 386 for(size_t i=0; i<m_ways; i++){ 387 if(!(m_lru_tab[set][i].recent) && !(m_dir_tab[set][i].lock)){ 388 way=i; 389 return DirectoryEntry(m_dir_tab[set][way]); 364 // looking for a not locked and not recently used entry 365 for(size_t i=0; i<m_ways; i++) 366 { 367 if((not m_lru_tab[set][i].recent) && (not m_dir_tab[set][i].lock) ) 368 { 369 way=i; 370 return DirectoryEntry(m_dir_tab[set][way]); 371 } 390 372 } 391 } 392 for(size_t i=0; i<m_ways; i++){ 393 if( !(m_lru_tab[set][i].recent) && (m_dir_tab[set][i].lock)){ 394 way=i; 395 return DirectoryEntry(m_dir_tab[set][way]); 373 374 // looking for a locked not recently used entry 375 for(size_t i=0; i<m_ways; i++) 376 { 377 if( (not m_lru_tab[set][i].recent) && (m_dir_tab[set][i].lock)) 378 { 379 way=i; 380 return DirectoryEntry(m_dir_tab[set][way]); 381 } 396 382 } 397 } 398 for(size_t i=0; i<m_ways; i++){ 399 if( (m_lru_tab[set][i].recent) && !(m_dir_tab[set][i].lock)){ 400 way=i; 401 return DirectoryEntry(m_dir_tab[set][way]); 383 384 // looking for a recently used entry not locked 385 for(size_t i=0; i<m_ways; i++) 386 { 387 if( (m_lru_tab[set][i].recent) && (not m_dir_tab[set][i].lock)) 388 { 389 way=i; 390 return DirectoryEntry(m_dir_tab[set][way]); 391 } 402 392 } 403 } 404 way = 0; 405 return DirectoryEntry(m_dir_tab[set][0]); 393 394 // select way 0 (even if entry is locked and recently used) 395 way = 0; 396 return DirectoryEntry(m_dir_tab[set][0]); 406 397 } // end select() 407 398 … … 437 428 //////////////////////// 438 429 HeapEntry() 439 :owner(false,0 440 #if L1_MULTI_CACHE 441 ,0 442 #endif 443 ) 430 :owner(false,0) 444 431 { 445 432 next = 0; … … 449 436 // Constructor 450 437 //////////////////////// 451 HeapEntry(const HeapEntry &entry){ 438 HeapEntry(const HeapEntry &entry) 439 { 452 440 owner.inst = entry.owner.inst; 453 441 owner.srcid = entry.owner.srcid; 454 #if L1_MULTI_CACHE455 owner.cache_id = entry.owner.cache_id;456 #endif457 442 next = entry.next; 458 443 } // end constructor … … 461 446 // The copy() function copies an existing source entry to a target 462 447 ///////////////////////////////////////////////////////////////////// 463 void copy(const HeapEntry &entry){ 448 void copy(const HeapEntry &entry) 449 { 464 450 owner.inst = entry.owner.inst; 465 451 owner.srcid = entry.owner.srcid; 466 #if L1_MULTI_CACHE467 owner.cache_id = entry.owner.cache_id;468 #endif469 452 next = entry.next; 470 453 } // end copy() … … 477 460 << " -- owner.inst : " << std::dec << owner.inst << std::endl 478 461 << " -- owner.srcid : " << std::dec << owner.srcid << std::endl 479 #if L1_MULTI_CACHE480 << " -- owner.cache_id : " << std::dec << owner.cache_id << std::endl481 #endif482 462 << " -- next : " << std::dec << next << std::endl; 483 463 … … 640 620 // Cache Data 641 621 //////////////////////////////////////////////////////////////////////// 642 class CacheData { 622 class CacheData 623 { 643 624 private: 644 625 const uint32_t m_sets; … … 650 631 public: 651 632 633 /////////////////////////////////////////////////////// 652 634 CacheData(uint32_t ways, uint32_t sets, uint32_t words) 653 : m_sets(sets), m_ways(ways), m_words(words) {654 635 : m_sets(sets), m_ways(ways), m_words(words) 636 { 655 637 m_cache_data = new uint32_t ** [ways]; 656 for ( size_t i=0 ; i < ways ; i++ ) { 657 m_cache_data[i] = new uint32_t * [sets]; 638 for ( size_t i=0 ; i < ways ; i++ ) 639 { 640 m_cache_data[i] = new uint32_t * [sets]; 658 641 } 659 for ( size_t i=0; i<ways; i++ ) { 660 for ( size_t j=0; j<sets; j++ ) { 661 m_cache_data[i][j] = new uint32_t [words]; 662 } 642 for ( size_t i=0; i<ways; i++ ) 643 { 644 for ( size_t j=0; j<sets; j++ ) 645 { 646 m_cache_data[i][j] = new uint32_t [words]; 647 } 663 648 } 664 } 665 666 ~CacheData() { 667 for(size_t i=0; i<m_ways ; i++){ 668 for(size_t j=0; j<m_sets ; j++){ 649 } 650 //////////// 651 ~CacheData() 652 { 653 for(size_t i=0; i<m_ways ; i++) 654 { 655 for(size_t j=0; j<m_sets ; j++) 656 { 669 657 delete [] m_cache_data[i][j]; 670 658 } 671 659 } 672 for(size_t i=0; i<m_ways ; i++){ 660 for(size_t i=0; i<m_ways ; i++) 661 { 673 662 delete [] m_cache_data[i]; 674 663 } 675 664 delete [] m_cache_data; 676 665 } 677 678 uint32_t read ( 679 const uint32_t &way, 680 const uint32_t &set, 681 const uint32_t &word) const { 682 683 assert((set < m_sets ) && "Cache data error: Trying to read a wrong set" ); 684 assert((way < m_ways ) && "Cache data error: Trying to read a wrong way" ); 685 assert((word < m_words) && "Cache data error: Trying to read a wrong word"); 686 687 return m_cache_data[way][set][word]; 688 } 689 690 void read_line( 691 const uint32_t &way, 692 const uint32_t &set, 693 sc_core::sc_signal<uint32_t> * cache_line) 694 { 695 assert((set < m_sets ) && "Cache data error: Trying to read a wrong set" ); 696 assert((way < m_ways ) && "Cache data error: Trying to read a wrong way" ); 697 698 for (uint32_t word=0; word<m_words; word++) 699 cache_line[word].write(m_cache_data[way][set][word]); 700 } 701 702 void write ( 703 const uint32_t &way, 704 const uint32_t &set, 705 const uint32_t &word, 706 const uint32_t &data, 707 const uint32_t &be = 0xF) { 708 709 assert((set < m_sets ) && "Cache data error: Trying to write a wrong set" ); 710 assert((way < m_ways ) && "Cache data error: Trying to write a wrong way" ); 711 assert((word < m_words) && "Cache data error: Trying to write a wrong word"); 712 assert((be <= 0xF ) && "Cache data error: Trying to write a wrong word cell"); 713 714 if (be == 0x0) return; 715 716 if (be == 0xF) { 717 m_cache_data[way][set][word] = data; 718 return; 719 } 720 721 uint32_t mask = 0; 722 if (be & 0x1) mask = mask | 0x000000FF; 723 if (be & 0x2) mask = mask | 0x0000FF00; 724 if (be & 0x4) mask = mask | 0x00FF0000; 725 if (be & 0x8) mask = mask | 0xFF000000; 726 727 m_cache_data[way][set][word] = 728 (data & mask) | (m_cache_data[way][set][word] & ~mask); 666 ////////////////////////////////////////// 667 uint32_t read ( const uint32_t &way, 668 const uint32_t &set, 669 const uint32_t &word) const 670 { 671 assert((set < m_sets ) && "Cache data error: Trying to read a wrong set" ); 672 assert((way < m_ways ) && "Cache data error: Trying to read a wrong way" ); 673 assert((word < m_words) && "Cache data error: Trying to read a wrong word"); 674 675 return m_cache_data[way][set][word]; 676 } 677 ////////////////////////////////////////// 678 void read_line( const uint32_t &way, 679 const uint32_t &set, 680 sc_core::sc_signal<uint32_t> * cache_line) 681 { 682 assert((set < m_sets ) && "Cache data error: Trying to read a wrong set" ); 683 assert((way < m_ways ) && "Cache data error: Trying to read a wrong way" ); 684 685 for (uint32_t word=0; word<m_words; word++) 686 cache_line[word].write(m_cache_data[way][set][word]); 687 } 688 ///////////////////////////////////////// 689 void write ( const uint32_t &way, 690 const uint32_t &set, 691 const uint32_t &word, 692 const uint32_t &data, 693 const uint32_t &be = 0xF) 694 { 695 696 assert((set < m_sets ) && "Cache data error: Trying to write a wrong set" ); 697 assert((way < m_ways ) && "Cache data error: Trying to write a wrong way" ); 698 assert((word < m_words) && "Cache data error: Trying to write a wrong word"); 699 assert((be <= 0xF ) && "Cache data error: Trying to write a wrong be"); 700 701 if (be == 0x0) return; 702 703 if (be == 0xF) 704 { 705 m_cache_data[way][set][word] = data; 706 return; 707 } 708 709 uint32_t mask = 0; 710 if (be & 0x1) mask = mask | 0x000000FF; 711 if (be & 0x2) mask = mask | 0x0000FF00; 712 if (be & 0x4) mask = mask | 0x00FF0000; 713 if (be & 0x8) mask = mask | 0xFF000000; 714 715 m_cache_data[way][set][word] = 716 (data & mask) | (m_cache_data[way][set][word] & ~mask); 729 717 } 730 718 }; // end class CacheData -
trunk/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h
r483 r489 25 25 * SOCLIB_LGPL_HEADER_END 26 26 * 27 * Maintainers: alain eric.guthmuller@polytechnique.edu 27 * Maintainers: alain.greiner@lip6.fr 28 * eric.guthmuller@polytechnique.edu 28 29 * cesar.fuguet-tortolero@lip6.fr 29 30 * alexandre.joannou@lip6.fr … … 150 151 MULTI_ACK_UPT_LOCK, 151 152 MULTI_ACK_UPT_CLEAR, 152 MULTI_ACK_WRITE_RSP, 153 MULTI_ACK_CONFIG_ACK 153 MULTI_ACK_WRITE_RSP 154 154 }; 155 155 … … 159 159 CONFIG_IDLE, 160 160 CONFIG_LOOP, 161 CONFIG_WAIT, 161 162 CONFIG_RSP, 162 163 CONFIG_DIR_REQ, 163 164 CONFIG_DIR_ACCESS, 164 CONFIG_ DIR_IVT_LOCK,165 CONFIG_IVT_LOCK, 165 166 CONFIG_BC_SEND, 166 CONFIG_BC_WAIT, 167 CONFIG_INV_SEND, 167 CONFIG_INVAL_SEND, 168 168 CONFIG_HEAP_REQ, 169 169 CONFIG_HEAP_SCAN, 170 170 CONFIG_HEAP_LAST, 171 CONFIG_INV_WAIT 171 CONFIG_TRT_LOCK, 172 CONFIG_TRT_SET, 173 CONFIG_PUT_REQ 172 174 }; 173 175 … … 197 199 WRITE_DIR_REQ, 198 200 WRITE_DIR_LOCK, 199 WRITE_DIR_READ,200 201 WRITE_DIR_HIT, 201 202 WRITE_UPT_LOCK, … … 209 210 WRITE_MISS_TRT_SET, 210 211 WRITE_MISS_XRAM_REQ, 212 WRITE_BC_DIR_READ, 211 213 WRITE_BC_TRT_LOCK, 212 214 WRITE_BC_IVT_LOCK, … … 221 223 { 222 224 IXR_RSP_IDLE, 223 IXR_RSP_ACK,224 225 IXR_RSP_TRT_ERASE, 225 226 IXR_RSP_TRT_READ … … 235 236 XRAM_RSP_DIR_UPDT, 236 237 XRAM_RSP_DIR_RSP, 237 XRAM_RSP_I NVAL_LOCK,238 XRAM_RSP_IVT_LOCK, 238 239 XRAM_RSP_INVAL_WAIT, 239 240 XRAM_RSP_INVAL, … … 253 254 IXR_CMD_CAS_IDLE, 254 255 IXR_CMD_XRAM_IDLE, 255 IXR_CMD_READ, 256 IXR_CMD_WRITE, 257 IXR_CMD_CAS, 258 IXR_CMD_XRAM 256 IXR_CMD_CONFIG_IDLE, 257 IXR_CMD_READ_TRT, 258 IXR_CMD_WRITE_TRT, 259 IXR_CMD_CAS_TRT, 260 IXR_CMD_XRAM_TRT, 261 IXR_CMD_CONFIG_TRT, 262 IXR_CMD_READ_SEND, 263 IXR_CMD_WRITE_SEND, 264 IXR_CMD_CAS_SEND, 265 IXR_CMD_XRAM_SEND, 266 IXR_CMD_CONFIG_SEND 259 267 }; 260 268 … … 302 310 CLEANUP_IVT_CLEAR, 303 311 CLEANUP_WRITE_RSP, 304 CLEANUP_CONFIG_ACK,305 312 CLEANUP_SEND_CLACK 306 313 }; … … 325 332 ALLOC_TRT_CAS, 326 333 ALLOC_TRT_XRAM_RSP, 327 ALLOC_TRT_IXR_RSP 334 ALLOC_TRT_IXR_RSP, 335 ALLOC_TRT_CONFIG, 336 ALLOC_TRT_IXR_CMD 328 337 }; 329 338 … … 386 395 }; 387 396 388 /* Configuration commands */ 389 enum cmd_config_type_e 390 { 391 CMD_CONFIG_INVAL = 0, 392 CMD_CONFIG_SYNC = 1 393 }; 394 395 // debug variables (for each FSM) 397 // debug variables 396 398 bool m_debug; 397 399 bool m_debug_previous_valid; 398 400 size_t m_debug_previous_count; 399 401 bool m_debug_previous_dirty; 400 sc_signal<data_t>* m_debug_previous_data; 401 sc_signal<data_t>* m_debug_data; 402 403 bool m_monitor_ok; 404 addr_t m_monitor_base; 405 addr_t m_monitor_length; 402 data_t * m_debug_previous_data; 403 data_t * m_debug_data; 406 404 407 405 // instrumentation counters … … 531 529 uint32_t m_broadcast_boundaries; 532 530 533 //////////////////////////////////////////////////534 // Registers controlled by the TGT_CMD fsm535 //////////////////////////////////////////////////536 537 sc_signal<int> r_tgt_cmd_fsm;538 539 531 // Fifo between TGT_CMD fsm and READ fsm 540 532 GenericFifo<addr_t> m_cmd_read_addr_fifo; … … 580 572 sc_signal<size_t> r_tgt_cmd_config_cmd; 581 573 574 ////////////////////////////////////////////////// 575 // Registers controlled by the TGT_CMD fsm 576 ////////////////////////////////////////////////// 577 578 sc_signal<int> r_tgt_cmd_fsm; 579 sc_signal<size_t> r_tgt_cmd_srcid; // srcid for response to config 580 sc_signal<size_t> r_tgt_cmd_trdid; // trdid for response to config 581 sc_signal<size_t> r_tgt_cmd_pktid; // pktid for response to config 582 582 583 /////////////////////////////////////////////////////// 583 584 // Registers controlled by the CONFIG fsm 584 585 /////////////////////////////////////////////////////// 585 586 586 sc_signal<int> r_config_fsm; // FSM state 587 sc_signal<bool> r_config_lock; // lock protecting exclusive access 588 sc_signal<int> r_config_cmd; // config request status 589 sc_signal<addr_t> r_config_address; // target buffer physical address 590 sc_signal<size_t> r_config_srcid; // config request srcid 591 sc_signal<size_t> r_config_trdid; // config request trdid 592 sc_signal<size_t> r_config_pktid; // config request pktid 593 sc_signal<size_t> r_config_nlines; // number of lines covering the buffer 594 sc_signal<size_t> r_config_dir_way; // DIR: selected way 595 sc_signal<size_t> r_config_dir_count; // DIR: number of copies 596 sc_signal<bool> r_config_dir_is_cnt; // DIR: counter mode (broadcast required) 597 sc_signal<size_t> r_config_dir_copy_srcid; // DIR: first copy SRCID 598 sc_signal<bool> r_config_dir_copy_inst; // DIR: first copy L1 type 599 sc_signal<size_t> r_config_dir_next_ptr; // DIR: index of next copy in HEAP 600 sc_signal<size_t> r_config_heap_next; // current pointer to scan HEAP 601 602 sc_signal<size_t> r_config_ivt_index; // IVT index 587 sc_signal<int> r_config_fsm; // FSM state 588 sc_signal<bool> r_config_lock; // lock protecting exclusive access 589 sc_signal<int> r_config_cmd; // config request type 590 sc_signal<addr_t> r_config_address; // target buffer physical address 591 sc_signal<size_t> r_config_srcid; // config request srcid 592 sc_signal<size_t> r_config_trdid; // config request trdid 593 sc_signal<size_t> r_config_pktid; // config request pktid 594 sc_signal<size_t> r_config_cmd_lines; // number of lines to be handled 595 sc_signal<size_t> r_config_rsp_lines; // number of lines not completed 596 sc_signal<size_t> r_config_dir_way; // DIR: selected way 597 sc_signal<bool> r_config_dir_lock; // DIR: locked entry 598 sc_signal<size_t> r_config_dir_count; // DIR: number of copies 599 sc_signal<bool> r_config_dir_is_cnt; // DIR: counter mode (broadcast) 600 sc_signal<size_t> r_config_dir_copy_srcid; // DIR: first copy SRCID 601 sc_signal<bool> r_config_dir_copy_inst; // DIR: first copy L1 type 602 sc_signal<size_t> r_config_dir_ptr; // DIR: index of next copy in HEAP 603 sc_signal<size_t> r_config_heap_next; // current pointer to scan HEAP 604 sc_signal<size_t> r_config_trt_index; // selected entry in TRT 605 sc_signal<size_t> r_config_ivt_index; // selected entry in IVT 606 607 // Buffer between CONFIG fsm and IXR_CMD fsm 608 sc_signal<bool> r_config_to_ixr_cmd_req; // valid request 609 sc_signal<size_t> r_config_to_ixr_cmd_index; // TRT index 610 603 611 604 612 // Buffer between CONFIG fsm and TGT_RSP fsm (send a done response to L1 cache) … … 617 625 GenericFifo<size_t> m_config_to_cc_send_srcid_fifo; // fifo for owners srcid 618 626 619 #if L1_MULTI_CACHE620 GenericFifo<size_t> m_config_to_cc_send_cache_id_fifo; // fifo for cache_id621 #endif622 623 627 /////////////////////////////////////////////////////// 624 628 // Registers controlled by the READ fsm 625 629 /////////////////////////////////////////////////////// 626 630 627 sc_signal<int> r_read_fsm; // FSM state 628 sc_signal<size_t> r_read_copy; // Srcid of the first copy 629 sc_signal<size_t> r_read_copy_cache; // Srcid of the first copy 630 sc_signal<bool> r_read_copy_inst; // Type of the first copy 631 sc_signal<tag_t> r_read_tag; // cache line tag (in directory) 632 sc_signal<bool> r_read_is_cnt; // is_cnt bit (in directory) 633 sc_signal<bool> r_read_lock; // lock bit (in directory) 634 sc_signal<bool> r_read_dirty; // dirty bit (in directory) 635 sc_signal<size_t> r_read_count; // number of copies 636 sc_signal<size_t> r_read_ptr; // pointer to the heap 637 sc_signal<data_t> * r_read_data; // data (one cache line) 638 sc_signal<size_t> r_read_way; // associative way (in cache) 639 sc_signal<size_t> r_read_trt_index; // Transaction Table index 640 sc_signal<size_t> r_read_next_ptr; // Next entry to point to 641 sc_signal<bool> r_read_last_free; // Last free entry 642 sc_signal<addr_t> r_read_ll_key; // LL key from the llsc_global_table 643 644 // Buffer between READ fsm and IXR_CMD fsm (ask a missing cache line to XRAM) 645 sc_signal<bool> r_read_to_ixr_cmd_req; // valid request 646 sc_signal<addr_t> r_read_to_ixr_cmd_nline; // cache line index 647 sc_signal<size_t> r_read_to_ixr_cmd_trdid; // index in Transaction Table 631 sc_signal<int> r_read_fsm; // FSM state 632 sc_signal<size_t> r_read_copy; // Srcid of the first copy 633 sc_signal<size_t> r_read_copy_cache; // Srcid of the first copy 634 sc_signal<bool> r_read_copy_inst; // Type of the first copy 635 sc_signal<tag_t> r_read_tag; // cache line tag (in directory) 636 sc_signal<bool> r_read_is_cnt; // is_cnt bit (in directory) 637 sc_signal<bool> r_read_lock; // lock bit (in directory) 638 sc_signal<bool> r_read_dirty; // dirty bit (in directory) 639 sc_signal<size_t> r_read_count; // number of copies 640 sc_signal<size_t> r_read_ptr; // pointer to the heap 641 sc_signal<data_t> * r_read_data; // data (one cache line) 642 sc_signal<size_t> r_read_way; // associative way (in cache) 643 sc_signal<size_t> r_read_trt_index; // Transaction Table index 644 sc_signal<size_t> r_read_next_ptr; // Next entry to point to 645 sc_signal<bool> r_read_last_free; // Last free entry 646 sc_signal<addr_t> r_read_ll_key; // LL key from llsc_global_table 647 648 // Buffer between READ fsm and IXR_CMD fsm 649 sc_signal<bool> r_read_to_ixr_cmd_req; // valid request 650 sc_signal<size_t> r_read_to_ixr_cmd_index; // TRT index 648 651 649 652 // Buffer between READ fsm and TGT_RSP fsm (send a hit read response to L1 cache) 650 sc_signal<bool> r_read_to_tgt_rsp_req; // valid request651 sc_signal<size_t> r_read_to_tgt_rsp_srcid; // Transaction srcid652 sc_signal<size_t> r_read_to_tgt_rsp_trdid; // Transaction trdid653 sc_signal<size_t> r_read_to_tgt_rsp_pktid; // Transaction pktid654 sc_signal<data_t> * r_read_to_tgt_rsp_data; // data (one cache line)655 sc_signal<size_t> r_read_to_tgt_rsp_word; // first word of the response656 sc_signal<size_t> r_read_to_tgt_rsp_length; // length of the response657 sc_signal<addr_t> r_read_to_tgt_rsp_ll_key; // LL key from thellsc_global_table653 sc_signal<bool> r_read_to_tgt_rsp_req; // valid request 654 sc_signal<size_t> r_read_to_tgt_rsp_srcid; // Transaction srcid 655 sc_signal<size_t> r_read_to_tgt_rsp_trdid; // Transaction trdid 656 sc_signal<size_t> r_read_to_tgt_rsp_pktid; // Transaction pktid 657 sc_signal<data_t> * r_read_to_tgt_rsp_data; // data (one cache line) 658 sc_signal<size_t> r_read_to_tgt_rsp_word; // first word of the response 659 sc_signal<size_t> r_read_to_tgt_rsp_length; // length of the response 660 sc_signal<addr_t> r_read_to_tgt_rsp_ll_key; // LL key from llsc_global_table 658 661 659 662 /////////////////////////////////////////////////////////////// … … 661 664 /////////////////////////////////////////////////////////////// 662 665 663 sc_signal<int> r_write_fsm; // FSM state664 sc_signal<addr_t> r_write_address; // first word address665 sc_signal<size_t> r_write_word_index; // first word index in line666 sc_signal<size_t> r_write_word_count; // number of words in line667 sc_signal<size_t> r_write_srcid; // transaction srcid668 sc_signal<size_t> r_write_trdid; // transaction trdid669 sc_signal<size_t> r_write_pktid; // transaction pktid670 sc_signal<data_t> * r_write_data; // data (one cache line)671 sc_signal<be_t> * r_write_be; // one byte enable per word672 sc_signal<bool> r_write_byte; // (BE != 0X0) and (BE != 0xF)673 sc_signal<bool> r_write_is_cnt; // is_cnt bit (in directory)674 sc_signal<bool> r_write_lock; // lock bit (in directory)675 sc_signal<tag_t> r_write_tag; // cache line tag (in directory)676 sc_signal<size_t> r_write_copy; // first owner of the line677 sc_signal<size_t> r_write_copy_cache; // first owner of the line678 sc_signal<bool> r_write_copy_inst; // is this owner a ICache ?679 sc_signal<size_t> r_write_count; // number of copies680 sc_signal<size_t> r_write_ptr; // pointer to the heap681 sc_signal<size_t> r_write_next_ptr; // next pointer to the heap682 sc_signal<bool> r_write_to_dec; // need to decrement update counter683 sc_signal<size_t> r_write_way; // way of the line684 sc_signal<size_t> r_write_trt_index; // index in Transaction Table685 sc_signal<size_t> r_write_upt_index; // index in Update Table686 sc_signal<bool> r_write_sc_fail; // sc command failed687 sc_signal<bool> r_write_pending_sc; // sc command pending666 sc_signal<int> r_write_fsm; // FSM state 667 sc_signal<addr_t> r_write_address; // first word address 668 sc_signal<size_t> r_write_word_index; // first word index in line 669 sc_signal<size_t> r_write_word_count; // number of words in line 670 sc_signal<size_t> r_write_srcid; // transaction srcid 671 sc_signal<size_t> r_write_trdid; // transaction trdid 672 sc_signal<size_t> r_write_pktid; // transaction pktid 673 sc_signal<data_t> * r_write_data; // data (one cache line) 674 sc_signal<be_t> * r_write_be; // one byte enable per word 675 sc_signal<bool> r_write_byte; // (BE != 0X0) and (BE != 0xF) 676 sc_signal<bool> r_write_is_cnt; // is_cnt bit (in directory) 677 sc_signal<bool> r_write_lock; // lock bit (in directory) 678 sc_signal<tag_t> r_write_tag; // cache line tag (in directory) 679 sc_signal<size_t> r_write_copy; // first owner of the line 680 sc_signal<size_t> r_write_copy_cache; // first owner of the line 681 sc_signal<bool> r_write_copy_inst; // is this owner a ICache ? 682 sc_signal<size_t> r_write_count; // number of copies 683 sc_signal<size_t> r_write_ptr; // pointer to the heap 684 sc_signal<size_t> r_write_next_ptr; // next pointer to the heap 685 sc_signal<bool> r_write_to_dec; // need to decrement update counter 686 sc_signal<size_t> r_write_way; // way of the line 687 sc_signal<size_t> r_write_trt_index; // index in Transaction Table 688 sc_signal<size_t> r_write_upt_index; // index in Update Table 689 sc_signal<bool> r_write_sc_fail; // sc command failed 690 sc_signal<bool> r_write_pending_sc; // sc command pending 688 691 689 692 // Buffer between WRITE fsm and TGT_RSP fsm (acknowledge a write command from L1) … … 694 697 sc_signal<bool> r_write_to_tgt_rsp_sc_fail; // sc command failed 695 698 696 // Buffer between WRITE fsm and IXR_CMD fsm (ask a missing cache line to XRAM) 697 sc_signal<bool> r_write_to_ixr_cmd_req; // valid request 698 sc_signal<bool> r_write_to_ixr_cmd_write; // write request 699 sc_signal<addr_t> r_write_to_ixr_cmd_nline; // cache line index 700 sc_signal<data_t> * r_write_to_ixr_cmd_data; // cache line data 701 sc_signal<size_t> r_write_to_ixr_cmd_trdid; // index in Transaction Table 699 // Buffer between WRITE fsm and IXR_CMD fsm 700 sc_signal<bool> r_write_to_ixr_cmd_req; // valid request 701 sc_signal<bool> r_write_to_ixr_cmd_put; // request type (GET/PUT) 702 sc_signal<size_t> r_write_to_ixr_cmd_index; // TRT index 702 703 703 704 // Buffer between WRITE fsm and CC_SEND fsm (Update/Invalidate L1 caches) … … 713 714 GenericFifo<size_t> m_write_to_cc_send_srcid_fifo; // fifo for srcids 714 715 715 #if L1_MULTI_CACHE716 GenericFifo<size_t> m_write_to_cc_send_cache_id_fifo; // fifo for srcids717 #endif718 719 716 // Buffer between WRITE fsm and MULTI_ACK fsm (Decrement UPT entry) 720 717 sc_signal<bool> r_write_to_multi_ack_req; // valid request … … 732 729 sc_signal<addr_t> r_multi_ack_nline; // pending write nline 733 730 734 // signaling completion of multi-inval to CONFIG fsm735 sc_signal<bool> r_multi_ack_to_config_ack;736 737 731 // Buffer between MULTI_ACK fsm and TGT_RSP fsm (complete write/update transaction) 738 732 sc_signal<bool> r_multi_ack_to_tgt_rsp_req; // valid request … … 751 745 sc_signal<addr_t> r_cleanup_nline; // cache line index 752 746 753 #if L1_MULTI_CACHE754 sc_signal<size_t> r_cleanup_pktid; // transaction pktid755 #endif756 747 757 748 sc_signal<copy_t> r_cleanup_copy; // first copy … … 780 771 sc_signal<size_t> r_cleanup_index; // index of the INVAL line (in the UPT) 781 772 782 // signaling completion of broadcast-inval to CONFIG fsm783 sc_signal<bool> r_cleanup_to_config_ack;784 785 773 // Buffer between CLEANUP fsm and TGT_RSP fsm (acknowledge a write command from L1) 786 774 sc_signal<bool> r_cleanup_to_tgt_rsp_req; // valid request … … 793 781 /////////////////////////////////////////////////////// 794 782 795 sc_signal<int> r_cas_fsm; // FSM state796 sc_signal<data_t> r_cas_wdata; // write data word797 sc_signal<data_t> * r_cas_rdata; // read data word798 sc_signal<uint32_t> r_cas_lfsr; // lfsr for random introducing799 sc_signal<size_t> r_cas_cpt; // size of command800 sc_signal<copy_t> r_cas_copy; // Srcid of the first copy801 sc_signal<copy_t> r_cas_copy_cache; // Srcid of the first copy802 sc_signal<bool> r_cas_copy_inst; // Type of the first copy803 sc_signal<size_t> r_cas_count; // number of copies804 sc_signal<size_t> r_cas_ptr; // pointer to the heap805 sc_signal<size_t> r_cas_next_ptr; // next pointer to the heap806 sc_signal<bool> r_cas_is_cnt; // is_cnt bit (in directory)807 sc_signal<bool> r_cas_dirty; // dirty bit (in directory)808 sc_signal<size_t> r_cas_way; // way in directory809 sc_signal<size_t> r_cas_set; // set in directory810 sc_signal<data_t> r_cas_tag; // cache line tag (in directory)811 sc_signal<size_t> r_cas_trt_index; // Transaction Table index812 sc_signal<size_t> r_cas_upt_index; // Update Table index813 sc_signal<data_t> * r_cas_data; // cache line data814 815 // Buffer between CAS fsm and IXR_CMD fsm (XRAM write)783 sc_signal<int> r_cas_fsm; // FSM state 784 sc_signal<data_t> r_cas_wdata; // write data word 785 sc_signal<data_t> * r_cas_rdata; // read data word 786 sc_signal<uint32_t> r_cas_lfsr; // lfsr for random introducing 787 sc_signal<size_t> r_cas_cpt; // size of command 788 sc_signal<copy_t> r_cas_copy; // Srcid of the first copy 789 sc_signal<copy_t> r_cas_copy_cache; // Srcid of the first copy 790 sc_signal<bool> r_cas_copy_inst; // Type of the first copy 791 sc_signal<size_t> r_cas_count; // number of copies 792 sc_signal<size_t> r_cas_ptr; // pointer to the heap 793 sc_signal<size_t> r_cas_next_ptr; // next pointer to the heap 794 sc_signal<bool> r_cas_is_cnt; // is_cnt bit (in directory) 795 sc_signal<bool> r_cas_dirty; // dirty bit (in directory) 796 sc_signal<size_t> r_cas_way; // way in directory 797 sc_signal<size_t> r_cas_set; // set in directory 798 sc_signal<data_t> r_cas_tag; // cache line tag (in directory) 799 sc_signal<size_t> r_cas_trt_index; // Transaction Table index 800 sc_signal<size_t> r_cas_upt_index; // Update Table index 801 sc_signal<data_t> * r_cas_data; // cache line data 802 803 // Buffer between CAS fsm and IXR_CMD fsm 816 804 sc_signal<bool> r_cas_to_ixr_cmd_req; // valid request 817 sc_signal<addr_t> r_cas_to_ixr_cmd_nline; // cache line index 818 sc_signal<size_t> r_cas_to_ixr_cmd_trdid; // index in Transaction Table 819 sc_signal<bool> r_cas_to_ixr_cmd_write; // write request 820 sc_signal<data_t> * r_cas_to_ixr_cmd_data; // cache line data 821 805 sc_signal<bool> r_cas_to_ixr_cmd_put; // request type (GET/PUT) 806 sc_signal<size_t> r_cas_to_ixr_cmd_index; // TRT index 822 807 823 808 // Buffer between CAS fsm and TGT_RSP fsm … … 840 825 GenericFifo<size_t> m_cas_to_cc_send_srcid_fifo; // fifo for srcids 841 826 842 #if L1_MULTI_CACHE843 GenericFifo<size_t> m_cas_to_cc_send_cache_id_fifo; // fifo for srcids844 #endif845 846 827 //////////////////////////////////////////////////// 847 828 // Registers controlled by the IXR_RSP fsm 848 829 //////////////////////////////////////////////////// 849 830 850 sc_signal<int> r_ixr_rsp_fsm; // FSM state 851 sc_signal<size_t> r_ixr_rsp_trt_index; // TRT entry index 852 sc_signal<size_t> r_ixr_rsp_cpt; // word counter 831 sc_signal<int> r_ixr_rsp_fsm; // FSM state 832 sc_signal<size_t> r_ixr_rsp_trt_index; // TRT entry index 833 sc_signal<size_t> r_ixr_rsp_cpt; // word counter 834 835 // Buffer between IXR_RSP fsm and CONFIG fsm (response from the XRAM) 836 sc_signal<bool> r_ixr_rsp_to_config_ack; // one single bit 853 837 854 838 // Buffer between IXR_RSP fsm and XRAM_RSP fsm (response from the XRAM) 855 sc_signal<bool> * r_ixr_rsp_to_xram_rsp_rok; // A xram response is ready839 sc_signal<bool> * r_ixr_rsp_to_xram_rsp_rok; // one bit per TRT entry 856 840 857 841 //////////////////////////////////////////////////// … … 896 880 GenericFifo<size_t> m_xram_rsp_to_cc_send_srcid_fifo; // fifo for srcids 897 881 898 #if L1_MULTI_CACHE 899 GenericFifo<size_t> m_xram_rsp_to_cc_send_cache_id_fifo; // fifo for srcids 900 #endif 901 902 // Buffer between XRAM_RSP fsm and IXR_CMD fsm (XRAM write) 882 // Buffer between XRAM_RSP fsm and IXR_CMD fsm 903 883 sc_signal<bool> r_xram_rsp_to_ixr_cmd_req; // Valid request 904 sc_signal<addr_t> r_xram_rsp_to_ixr_cmd_nline; // cache line index 905 sc_signal<data_t> * r_xram_rsp_to_ixr_cmd_data; // cache line data 906 sc_signal<size_t> r_xram_rsp_to_ixr_cmd_trdid; // index in transaction table 884 sc_signal<size_t> r_xram_rsp_to_ixr_cmd_index; // TRT index 907 885 908 886 //////////////////////////////////////////////////// … … 911 889 912 890 sc_signal<int> r_ixr_cmd_fsm; 913 sc_signal<size_t> r_ixr_cmd_cpt; 891 sc_signal<size_t> r_ixr_cmd_word; // word index for a put 892 sc_signal<size_t> r_ixr_cmd_trdid; // TRT index value 893 sc_signal<addr_t> r_ixr_cmd_address; // address to XRAM 894 sc_signal<data_t> * r_ixr_cmd_wdata; // cache line buffer 895 sc_signal<bool> r_ixr_cmd_get; // transaction type (PUT/GET) 914 896 915 897 //////////////////////////////////////////////////// -
trunk/modules/vci_mem_cache/caba/source/include/xram_transaction.h
r422 r489 34 34 bool rerror; // error returned by xram 35 35 data_t ll_key; // LL key returned by the llsc_global_table 36 bool config; // transaction required by CONFIG FSM 36 37 37 38 ///////////////////////////////////////////////////////////////////// … … 42 43 valid = false; 43 44 rerror = false; 45 config = false; 44 46 } 45 47 … … 80 82 rerror = source.rerror; 81 83 ll_key = source.ll_key; 84 config = source.config; 82 85 } 83 86 … … 87 90 void print() 88 91 { 92 std::cout << "------- TRT entry -------" << std::endl; 89 93 std::cout << "valid = " << valid << std::endl; 90 94 std::cout << "xram_read = " << xram_read << std::endl; … … 96 100 std::cout << "read_length = " << read_length << std::endl; 97 101 std::cout << "word_index = " << word_index << std::endl; 98 for(size_t i=0; i<wdata_be.size() ; i++){ 99 std::cout << "wdata_be [" << i <<"] = " << wdata_be[i] << std::endl; 100 } 101 for(size_t i=0; i<wdata.size() ; i++){ 102 std::cout << "wdata [" << i <<"] = " << wdata[i] << std::endl; 103 } 102 for(size_t i=0; i<wdata_be.size() ; i++) 103 { 104 std::cout << "wdata_be[" << std::dec << i << "] = " 105 << std::hex << wdata_be[i] << std::endl; 106 } 107 for(size_t i=0; i<wdata.size() ; i++) 108 { 109 std::cout << "wdata[" << std::dec << i << "] = " 110 << std::hex << wdata[i] << std::endl; 111 } 112 std::cout << "rerror = " << rerror << std::endl; 113 std::cout << "ll_key = " << ll_key << std::endl; 114 std::cout << "config = " << config << std::endl; 104 115 std::cout << std::endl; 105 std::cout << "rerror = " << rerror << std::endl;106 116 } 107 117 … … 114 124 wdata_be.clear(); 115 125 wdata.clear(); 116 valid=false; 117 rerror=false; 118 } 119 120 TransactionTabEntry(const TransactionTabEntry &source){ 126 valid = false; 127 rerror = false; 128 config = false; 129 } 130 131 TransactionTabEntry(const TransactionTabEntry &source) 132 { 121 133 valid = source.valid; 122 134 xram_read = source.xram_read; … … 132 144 rerror = source.rerror; 133 145 ll_key = source.ll_key; 146 config = source.config; 134 147 } 135 148 … … 197 210 delete [] tab; 198 211 } 199 200 212 ///////////////////////////////////////////////////////////////////// 201 213 // The size() function returns the size of the tab … … 205 217 return size_tab; 206 218 } 207 208 219 ///////////////////////////////////////////////////////////////////// 209 220 // The init() function initializes the transaction tab entries … … 211 222 void init() 212 223 { 213 for ( size_t i=0; i<size_tab; i++) { 224 for ( size_t i=0; i<size_tab; i++) 225 { 214 226 tab[i].init(); 215 227 } 216 228 } 217 218 229 ///////////////////////////////////////////////////////////////////// 219 230 // The print() function prints a transaction tab entry … … 223 234 void print(const size_t index) 224 235 { 225 assert( (index < size_tab) 226 && "Invalid Transaction Tab Entry"); 236 assert( (index < size_tab) and 237 "MEMC ERROR: The selected entry is out of range in TRT write_data_mask()"); 238 227 239 tab[index].print(); 228 240 return; 229 241 } 230 231 242 ///////////////////////////////////////////////////////////////////// 232 243 // The read() function returns a transaction tab entry. … … 236 247 TransactionTabEntry read(const size_t index) 237 248 { 238 assert( (index < size_tab) 239 && "Invalid Transaction Tab Entry"); 249 assert( (index < size_tab) and 250 "MEMC ERROR: Invalid Transaction Tab Entry"); 251 240 252 return tab[index]; 241 253 } 242 243 254 ///////////////////////////////////////////////////////////////////// 244 255 // The full() function returns the state of the transaction tab … … 249 260 bool full(size_t &index) 250 261 { 251 for(size_t i=0; i<size_tab; i++){ 252 if(!tab[i].valid){ 262 for(size_t i=0; i<size_tab; i++) 263 { 264 if(!tab[i].valid) 265 { 253 266 index=i; 254 267 return false; … … 257 270 return true; 258 271 } 259 260 272 ///////////////////////////////////////////////////////////////////// 261 273 // The hit_read() function checks if an XRAM read transaction exists … … 268 280 bool hit_read(const addr_t nline,size_t &index) 269 281 { 270 for(size_t i=0; i<size_tab; i++){ 271 if((tab[i].valid && (nline==tab[i].nline)) && (tab[i].xram_read)) { 282 for(size_t i=0; i<size_tab; i++) 283 { 284 if((tab[i].valid && (nline==tab[i].nline)) && (tab[i].xram_read)) 285 { 272 286 index=i; 273 287 return true; … … 276 290 return false; 277 291 } 278 279 292 /////////////////////////////////////////////////////////////////////// 280 293 // The hit_write() function looks if an XRAM write transaction exists … … 286 299 bool hit_write(const addr_t nline) 287 300 { 288 for(size_t i=0; i<size_tab; i++){ 289 if(tab[i].valid && (nline==tab[i].nline) && !(tab[i].xram_read)) { 301 for(size_t i=0; i<size_tab; i++) 302 { 303 if(tab[i].valid && (nline==tab[i].nline) && !(tab[i].xram_read)) 304 { 290 305 return true; 291 306 } … … 293 308 return false; 294 309 } 295 296 310 ///////////////////////////////////////////////////////////////////// 297 311 // The write_data_mask() function writes a vector of data (a line). … … 307 321 const std::vector<data_t> &data) 308 322 { 309 assert( (index < size_tab) 310 && "Invalid Transaction Tab Entry"); 311 assert(be.size()==tab[index].wdata_be.size() 312 && "Bad data mask in write_data_mask in TransactionTab"); 313 assert(data.size()==tab[index].wdata.size() 314 && "Bad data in write_data_mask in TransactionTab"); 315 316 for(size_t i=0; i<tab[index].wdata_be.size() ; i++) { 323 assert( (index < size_tab) and 324 "MEMC ERROR: The selected entry is out of range in TRT write_data_mask()"); 325 326 assert( (be.size()==tab[index].wdata_be.size()) and 327 "MEMC ERROR: Bad be size in TRT write_data_mask()"); 328 329 assert( (data.size()==tab[index].wdata.size()) and 330 "MEMC ERROR: Bad data size in TRT write_data_mask()"); 331 332 for(size_t i=0; i<tab[index].wdata_be.size() ; i++) 333 { 317 334 tab[index].wdata_be[i] = tab[index].wdata_be[i] | be[i]; 318 335 data_t mask = be_to_mask(be[i]); … … 320 337 } 321 338 } 322 323 339 ///////////////////////////////////////////////////////////////////// 324 340 // The set() function registers a transaction (read or write) … … 337 353 // - data_be : the mask of the data to write (in case of write) 338 354 // - ll_key : the ll key (if any) returned by the llsc_global_table 355 // - config : transaction required by config FSM 339 356 ///////////////////////////////////////////////////////////////////// 340 357 void set(const size_t index, … … 349 366 const std::vector<be_t> &data_be, 350 367 const std::vector<data_t> &data, 351 const data_t ll_key = 0) 352 { 353 assert( (index < size_tab) 354 && "The selected entry is out of range in set() Transaction Tab"); 355 assert(data_be.size()==tab[index].wdata_be.size() 356 && "Bad data_be argument in set() TransactionTab"); 357 assert(data.size()==tab[index].wdata.size() 358 && "Bad data argument in set() TransactionTab"); 368 const data_t ll_key = 0, 369 const bool config = false) 370 { 371 assert( (index < size_tab) and 372 "MEMC ERROR: The selected entry is out of range in TRT set()"); 373 374 assert( (data_be.size()==tab[index].wdata_be.size()) and 375 "MEMC ERROR: Bad data_be argument in TRT set()"); 376 377 assert( (data.size()==tab[index].wdata.size()) and 378 "MEMC ERROR: Bad data argument in TRT set()"); 359 379 360 380 tab[index].valid = true; … … 368 388 tab[index].word_index = word_index; 369 389 tab[index].ll_key = ll_key; 390 tab[index].config = config; 370 391 for(size_t i=0; i<tab[index].wdata.size(); i++) 371 392 { … … 380 401 // The BE field in TRT is taken into account. 381 402 // Arguments : 382 // - index : the index of the transaction in the transaction tab 383 // - word_index : the index of the data in the line 384 // - data : a 64 bits value 385 // - error : invalid data 403 // - index : index of the entry in TRT 404 // - word : index of the 32 bits word in the line 405 // - data : 64 bits value (first data right) 386 406 ///////////////////////////////////////////////////////////////////// 387 407 void write_rsp(const size_t index, 388 408 const size_t word, 389 const wide_data_t data, 390 const bool rerror) 409 const wide_data_t data) 391 410 { 392 411 data_t value; 393 412 data_t mask; 394 413 395 if ( index >= size_tab ) 396 { 397 std::cout << "VCI_MEM_CACHE ERRROR " << tab_name 398 << " TRT entry out of range in write_rsp()" << std::endl; 399 exit(0); 400 } 401 if ( word > tab[index].wdata_be.size() ) 402 { 403 std::cout << "VCI_MEM_CACHE ERRROR " << tab_name 404 << " Bad word_index in write_rsp() in TRT" << std::endl; 405 exit(0); 406 } 407 if ( not tab[index].valid ) 408 { 409 std::cout << "VCI_MEM_CACHE ERRROR " << tab_name 410 << " TRT Entry invalid in write_rsp()" << std::endl; 411 exit(0); 412 } 413 if ( not tab[index].xram_read ) 414 { 415 std::cout << "VCI_MEM_CACHE ERRROR " << tab_name 416 << " TRT entry is not an XRAM GET in write_rsp()" << std::endl; 417 exit(0); 418 } 414 assert( (index < size_tab) and 415 "MEMC ERROR: The selected entry is out of range in TRT write_rsp()"); 416 417 assert( (word < tab[index].wdata_be.size()) and 418 "MEMC ERROR: Bad word index in TRT write_rsp()"); 419 420 assert( (tab[index].valid) and 421 "MEMC ERROR: TRT entry not valid in TRT write_rsp()"); 422 423 assert( (tab[index].xram_read ) and 424 "MEMC ERROR: TRT entry is not a GET in TRT write_rsp()"); 419 425 420 426 // first 32 bits word … … 427 433 mask = be_to_mask(tab[index].wdata_be[word+1]); 428 434 tab[index].wdata[word+1] = (tab[index].wdata[word+1] & mask) | (value & ~mask); 429 430 // error update 431 tab[index].rerror |= rerror; 432 } 433 435 } 434 436 ///////////////////////////////////////////////////////////////////// 435 437 // The erase() function erases an entry in the transaction tab. … … 439 441 void erase(const size_t index) 440 442 { 441 assert( (index < size_tab) 442 && "The selected entry is out of range in erase() Transaction Tab"); 443 assert( (index < size_tab) and 444 "MEMC ERROR: The selected entry is out of range in TRT erase()"); 445 443 446 tab[index].valid = false; 444 447 tab[index].rerror = false; 448 } 449 ///////////////////////////////////////////////////////////////////// 450 // The is_config() function returns the config flag value. 451 // Arguments : 452 // - index : the index of the entry in the transaction tab 453 ///////////////////////////////////////////////////////////////////// 454 bool is_config(const size_t index) 455 { 456 assert( (index < size_tab) and 457 "MEMC ERROR: The selected entry is out of range in TRT is_config()"); 458 459 return tab[index].config; 445 460 } 446 461 }; // end class TransactionTab
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