Index: trunk/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h
===================================================================
--- trunk/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h	(revision 483)
+++ trunk/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h	(revision 489)
@@ -25,5 +25,6 @@
  * SOCLIB_LGPL_HEADER_END
  *
- * Maintainers: alain eric.guthmuller@polytechnique.edu
+ * Maintainers: alain.greiner@lip6.fr 
+ *              eric.guthmuller@polytechnique.edu
  *              cesar.fuguet-tortolero@lip6.fr
  *              alexandre.joannou@lip6.fr
@@ -150,6 +151,5 @@
         MULTI_ACK_UPT_LOCK,
         MULTI_ACK_UPT_CLEAR,
-        MULTI_ACK_WRITE_RSP,
-        MULTI_ACK_CONFIG_ACK
+        MULTI_ACK_WRITE_RSP
       };
 
@@ -159,15 +159,17 @@
         CONFIG_IDLE,
         CONFIG_LOOP,
+        CONFIG_WAIT,
         CONFIG_RSP,
         CONFIG_DIR_REQ,
         CONFIG_DIR_ACCESS,
-        CONFIG_DIR_IVT_LOCK,
+        CONFIG_IVT_LOCK,
         CONFIG_BC_SEND,
-        CONFIG_BC_WAIT,
-        CONFIG_INV_SEND,
+        CONFIG_INVAL_SEND,
         CONFIG_HEAP_REQ,
         CONFIG_HEAP_SCAN,
         CONFIG_HEAP_LAST,
-        CONFIG_INV_WAIT
+        CONFIG_TRT_LOCK,
+        CONFIG_TRT_SET,
+        CONFIG_PUT_REQ
       };
 
@@ -197,5 +199,4 @@
         WRITE_DIR_REQ,
         WRITE_DIR_LOCK,
-        WRITE_DIR_READ,
         WRITE_DIR_HIT,
         WRITE_UPT_LOCK,
@@ -209,4 +210,5 @@
         WRITE_MISS_TRT_SET,
         WRITE_MISS_XRAM_REQ,
+        WRITE_BC_DIR_READ,
         WRITE_BC_TRT_LOCK,
         WRITE_BC_IVT_LOCK,
@@ -221,5 +223,4 @@
       {
         IXR_RSP_IDLE,
-        IXR_RSP_ACK,
         IXR_RSP_TRT_ERASE,
         IXR_RSP_TRT_READ
@@ -235,5 +236,5 @@
         XRAM_RSP_DIR_UPDT,
         XRAM_RSP_DIR_RSP,
-        XRAM_RSP_INVAL_LOCK,
+        XRAM_RSP_IVT_LOCK,
         XRAM_RSP_INVAL_WAIT,
         XRAM_RSP_INVAL,
@@ -253,8 +254,15 @@
         IXR_CMD_CAS_IDLE,
         IXR_CMD_XRAM_IDLE,
-        IXR_CMD_READ,
-        IXR_CMD_WRITE,
-        IXR_CMD_CAS,
-        IXR_CMD_XRAM
+        IXR_CMD_CONFIG_IDLE,
+        IXR_CMD_READ_TRT,
+        IXR_CMD_WRITE_TRT,
+        IXR_CMD_CAS_TRT,
+        IXR_CMD_XRAM_TRT,
+        IXR_CMD_CONFIG_TRT,
+        IXR_CMD_READ_SEND,
+        IXR_CMD_WRITE_SEND,
+        IXR_CMD_CAS_SEND,
+        IXR_CMD_XRAM_SEND,
+        IXR_CMD_CONFIG_SEND
       };
 
@@ -302,5 +310,4 @@
         CLEANUP_IVT_CLEAR,
         CLEANUP_WRITE_RSP,
-        CLEANUP_CONFIG_ACK,
         CLEANUP_SEND_CLACK
       };
@@ -325,5 +332,7 @@
         ALLOC_TRT_CAS,
         ALLOC_TRT_XRAM_RSP,
-        ALLOC_TRT_IXR_RSP
+        ALLOC_TRT_IXR_RSP,
+        ALLOC_TRT_CONFIG,
+        ALLOC_TRT_IXR_CMD
       };
 
@@ -386,22 +395,11 @@
       };
 
-      /* Configuration commands */
-      enum cmd_config_type_e
-      {
-          CMD_CONFIG_INVAL = 0,
-          CMD_CONFIG_SYNC  = 1
-      };
-
-      // debug variables (for each FSM)
+      // debug variables 
       bool                 m_debug;
       bool                 m_debug_previous_valid;
       size_t               m_debug_previous_count;
       bool                 m_debug_previous_dirty;
-      sc_signal<data_t>*   m_debug_previous_data;
-      sc_signal<data_t>*   m_debug_data;
-
-      bool         m_monitor_ok;
-      addr_t       m_monitor_base;
-      addr_t       m_monitor_length;
+      data_t *             m_debug_previous_data;
+      data_t *             m_debug_data;
 
       // instrumentation counters
@@ -531,10 +529,4 @@
       uint32_t                           m_broadcast_boundaries;
 
-      //////////////////////////////////////////////////
-      // Registers controlled by the TGT_CMD fsm
-      //////////////////////////////////////////////////
-
-      sc_signal<int>         r_tgt_cmd_fsm;
-
       // Fifo between TGT_CMD fsm and READ fsm
       GenericFifo<addr_t>    m_cmd_read_addr_fifo;
@@ -580,25 +572,41 @@
       sc_signal<size_t>   r_tgt_cmd_config_cmd;
 
+      //////////////////////////////////////////////////
+      // Registers controlled by the TGT_CMD fsm
+      //////////////////////////////////////////////////
+
+      sc_signal<int>         r_tgt_cmd_fsm;
+      sc_signal<size_t>      r_tgt_cmd_srcid;           // srcid for response to config
+      sc_signal<size_t>      r_tgt_cmd_trdid;           // trdid for response to config
+      sc_signal<size_t>      r_tgt_cmd_pktid;           // pktid for response to config
+
       ///////////////////////////////////////////////////////
       // Registers controlled by the CONFIG fsm
       ///////////////////////////////////////////////////////
 
-      sc_signal<int>      r_config_fsm;            // FSM state
-      sc_signal<bool>     r_config_lock;           // lock protecting exclusive access
-      sc_signal<int>      r_config_cmd;            // config request status
-      sc_signal<addr_t>   r_config_address;        // target buffer physical address
-      sc_signal<size_t>   r_config_srcid;          // config request srcid
-      sc_signal<size_t>   r_config_trdid;          // config request trdid
-      sc_signal<size_t>   r_config_pktid;          // config request pktid
-      sc_signal<size_t>   r_config_nlines;         // number of lines covering the buffer
-      sc_signal<size_t>   r_config_dir_way;        // DIR: selected way
-      sc_signal<size_t>   r_config_dir_count;      // DIR: number of copies
-      sc_signal<bool>     r_config_dir_is_cnt;     // DIR: counter mode (broadcast required)
-      sc_signal<size_t>   r_config_dir_copy_srcid; // DIR: first copy SRCID
-      sc_signal<bool>     r_config_dir_copy_inst;  // DIR: first copy L1 type
-      sc_signal<size_t>   r_config_dir_next_ptr;   // DIR: index of next copy in HEAP
-      sc_signal<size_t>   r_config_heap_next;      // current pointer to scan HEAP
-
-      sc_signal<size_t>   r_config_ivt_index;      // IVT index
+      sc_signal<int>      r_config_fsm;               // FSM state
+      sc_signal<bool>     r_config_lock;              // lock protecting exclusive access
+      sc_signal<int>      r_config_cmd;               // config request type  
+      sc_signal<addr_t>   r_config_address;           // target buffer physical address
+      sc_signal<size_t>   r_config_srcid;             // config request srcid
+      sc_signal<size_t>   r_config_trdid;             // config request trdid
+      sc_signal<size_t>   r_config_pktid;             // config request pktid
+      sc_signal<size_t>   r_config_cmd_lines;         // number of lines to be handled
+      sc_signal<size_t>   r_config_rsp_lines;         // number of lines not completed
+      sc_signal<size_t>   r_config_dir_way;           // DIR: selected way
+      sc_signal<bool>     r_config_dir_lock;          // DIR: locked entry
+      sc_signal<size_t>   r_config_dir_count;         // DIR: number of copies
+      sc_signal<bool>     r_config_dir_is_cnt;        // DIR: counter mode (broadcast)
+      sc_signal<size_t>   r_config_dir_copy_srcid;    // DIR: first copy SRCID
+      sc_signal<bool>     r_config_dir_copy_inst;     // DIR: first copy L1 type
+      sc_signal<size_t>   r_config_dir_ptr;           // DIR: index of next copy in HEAP
+      sc_signal<size_t>   r_config_heap_next;         // current pointer to scan HEAP
+      sc_signal<size_t>   r_config_trt_index;         // selected entry in TRT
+      sc_signal<size_t>   r_config_ivt_index;         // selected entry in IVT 
+
+      // Buffer between CONFIG fsm and IXR_CMD fsm
+      sc_signal<bool>     r_config_to_ixr_cmd_req;    // valid request
+      sc_signal<size_t>   r_config_to_ixr_cmd_index;  // TRT index
+
 
       // Buffer between CONFIG fsm and TGT_RSP fsm (send a done response to L1 cache)
@@ -617,43 +625,38 @@
       GenericFifo<size_t> m_config_to_cc_send_srcid_fifo;   // fifo for owners srcid
 
-#if L1_MULTI_CACHE
-      GenericFifo<size_t> m_config_to_cc_send_cache_id_fifo; // fifo for cache_id
-#endif
-
       ///////////////////////////////////////////////////////
       // Registers controlled by the READ fsm
       ///////////////////////////////////////////////////////
 
-      sc_signal<int>      r_read_fsm;          // FSM state
-      sc_signal<size_t>   r_read_copy;         // Srcid of the first copy
-      sc_signal<size_t>   r_read_copy_cache;   // Srcid of the first copy
-      sc_signal<bool>     r_read_copy_inst;    // Type of the first copy
-      sc_signal<tag_t>    r_read_tag;          // cache line tag (in directory)
-      sc_signal<bool>     r_read_is_cnt;       // is_cnt bit (in directory)
-      sc_signal<bool>     r_read_lock;         // lock bit (in directory)
-      sc_signal<bool>     r_read_dirty;        // dirty bit (in directory)
-      sc_signal<size_t>   r_read_count;        // number of copies
-      sc_signal<size_t>   r_read_ptr;          // pointer to the heap
-      sc_signal<data_t> * r_read_data;         // data (one cache line)
-      sc_signal<size_t>   r_read_way;          // associative way (in cache)
-      sc_signal<size_t>   r_read_trt_index;    // Transaction Table index
-      sc_signal<size_t>   r_read_next_ptr;     // Next entry to point to
-      sc_signal<bool>     r_read_last_free;    // Last free entry
-      sc_signal<addr_t>   r_read_ll_key;       // LL key from the llsc_global_table
-
-      // Buffer between READ fsm and IXR_CMD fsm (ask a missing cache line to XRAM)
-      sc_signal<bool>     r_read_to_ixr_cmd_req;    // valid request
-      sc_signal<addr_t>   r_read_to_ixr_cmd_nline;  // cache line index
-      sc_signal<size_t>   r_read_to_ixr_cmd_trdid;  // index in Transaction Table
+      sc_signal<int>      r_read_fsm;                 // FSM state
+      sc_signal<size_t>   r_read_copy;                // Srcid of the first copy
+      sc_signal<size_t>   r_read_copy_cache;          // Srcid of the first copy
+      sc_signal<bool>     r_read_copy_inst;           // Type of the first copy
+      sc_signal<tag_t>    r_read_tag;                 // cache line tag (in directory)
+      sc_signal<bool>     r_read_is_cnt;              // is_cnt bit (in directory)
+      sc_signal<bool>     r_read_lock;                // lock bit (in directory)
+      sc_signal<bool>     r_read_dirty;               // dirty bit (in directory)
+      sc_signal<size_t>   r_read_count;               // number of copies
+      sc_signal<size_t>   r_read_ptr;                 // pointer to the heap
+      sc_signal<data_t> * r_read_data;                // data (one cache line)
+      sc_signal<size_t>   r_read_way;                 // associative way (in cache)
+      sc_signal<size_t>   r_read_trt_index;           // Transaction Table index
+      sc_signal<size_t>   r_read_next_ptr;            // Next entry to point to
+      sc_signal<bool>     r_read_last_free;           // Last free entry
+      sc_signal<addr_t>   r_read_ll_key;              // LL key from llsc_global_table
+
+      // Buffer between READ fsm and IXR_CMD fsm 
+      sc_signal<bool>     r_read_to_ixr_cmd_req;      // valid request
+      sc_signal<size_t>   r_read_to_ixr_cmd_index;    // TRT index
 
       // Buffer between READ fsm and TGT_RSP fsm (send a hit read response to L1 cache)
-      sc_signal<bool>     r_read_to_tgt_rsp_req;    // valid request
-      sc_signal<size_t>   r_read_to_tgt_rsp_srcid;  // Transaction srcid
-      sc_signal<size_t>   r_read_to_tgt_rsp_trdid;  // Transaction trdid
-      sc_signal<size_t>   r_read_to_tgt_rsp_pktid;  // Transaction pktid
-      sc_signal<data_t> * r_read_to_tgt_rsp_data;   // data (one cache line)
-      sc_signal<size_t>   r_read_to_tgt_rsp_word;   // first word of the response
-      sc_signal<size_t>   r_read_to_tgt_rsp_length; // length of the response
-      sc_signal<addr_t>   r_read_to_tgt_rsp_ll_key; // LL key from the llsc_global_table
+      sc_signal<bool>     r_read_to_tgt_rsp_req;      // valid request
+      sc_signal<size_t>   r_read_to_tgt_rsp_srcid;    // Transaction srcid
+      sc_signal<size_t>   r_read_to_tgt_rsp_trdid;    // Transaction trdid
+      sc_signal<size_t>   r_read_to_tgt_rsp_pktid;    // Transaction pktid
+      sc_signal<data_t> * r_read_to_tgt_rsp_data;     // data (one cache line)
+      sc_signal<size_t>   r_read_to_tgt_rsp_word;     // first word of the response
+      sc_signal<size_t>   r_read_to_tgt_rsp_length;   // length of the response
+      sc_signal<addr_t>   r_read_to_tgt_rsp_ll_key;   // LL key from llsc_global_table
 
       ///////////////////////////////////////////////////////////////
@@ -661,29 +664,29 @@
       ///////////////////////////////////////////////////////////////
 
-      sc_signal<int>      r_write_fsm;        // FSM state
-      sc_signal<addr_t>   r_write_address;    // first word address
-      sc_signal<size_t>   r_write_word_index; // first word index in line
-      sc_signal<size_t>   r_write_word_count; // number of words in line
-      sc_signal<size_t>   r_write_srcid;      // transaction srcid
-      sc_signal<size_t>   r_write_trdid;      // transaction trdid
-      sc_signal<size_t>   r_write_pktid;      // transaction pktid
-      sc_signal<data_t> * r_write_data;       // data (one cache line)
-      sc_signal<be_t>   * r_write_be;         // one byte enable per word
-      sc_signal<bool>     r_write_byte;       // (BE != 0X0) and (BE != 0xF)
-      sc_signal<bool>     r_write_is_cnt;     // is_cnt bit (in directory)
-      sc_signal<bool>     r_write_lock;       // lock bit (in directory)
-      sc_signal<tag_t>    r_write_tag;        // cache line tag (in directory)
-      sc_signal<size_t>   r_write_copy;       // first owner of the line
-      sc_signal<size_t>   r_write_copy_cache; // first owner of the line
-      sc_signal<bool>     r_write_copy_inst;  // is this owner a ICache ?
-      sc_signal<size_t>   r_write_count;      // number of copies
-      sc_signal<size_t>   r_write_ptr;        // pointer to the heap
-      sc_signal<size_t>   r_write_next_ptr;   // next pointer to the heap
-      sc_signal<bool>     r_write_to_dec;     // need to decrement update counter
-      sc_signal<size_t>   r_write_way;        // way of the line
-      sc_signal<size_t>   r_write_trt_index;  // index in Transaction Table
-      sc_signal<size_t>   r_write_upt_index;  // index in Update Table
-      sc_signal<bool>     r_write_sc_fail;    // sc command failed
-      sc_signal<bool>     r_write_pending_sc; // sc command pending
+      sc_signal<int>      r_write_fsm;                // FSM state
+      sc_signal<addr_t>   r_write_address;            // first word address
+      sc_signal<size_t>   r_write_word_index;         // first word index in line
+      sc_signal<size_t>   r_write_word_count;         // number of words in line
+      sc_signal<size_t>   r_write_srcid;              // transaction srcid
+      sc_signal<size_t>   r_write_trdid;              // transaction trdid
+      sc_signal<size_t>   r_write_pktid;              // transaction pktid
+      sc_signal<data_t> * r_write_data;               // data (one cache line)
+      sc_signal<be_t>   * r_write_be;                 // one byte enable per word
+      sc_signal<bool>     r_write_byte;               // (BE != 0X0) and (BE != 0xF)
+      sc_signal<bool>     r_write_is_cnt;             // is_cnt bit (in directory)
+      sc_signal<bool>     r_write_lock;               // lock bit (in directory)
+      sc_signal<tag_t>    r_write_tag;                // cache line tag (in directory)
+      sc_signal<size_t>   r_write_copy;               // first owner of the line
+      sc_signal<size_t>   r_write_copy_cache;         // first owner of the line
+      sc_signal<bool>     r_write_copy_inst;          // is this owner a ICache ?
+      sc_signal<size_t>   r_write_count;              // number of copies
+      sc_signal<size_t>   r_write_ptr;                // pointer to the heap
+      sc_signal<size_t>   r_write_next_ptr;           // next pointer to the heap
+      sc_signal<bool>     r_write_to_dec;             // need to decrement update counter
+      sc_signal<size_t>   r_write_way;                // way of the line
+      sc_signal<size_t>   r_write_trt_index;          // index in Transaction Table
+      sc_signal<size_t>   r_write_upt_index;          // index in Update Table
+      sc_signal<bool>     r_write_sc_fail;            // sc command failed
+      sc_signal<bool>     r_write_pending_sc;         // sc command pending
 
       // Buffer between WRITE fsm and TGT_RSP fsm (acknowledge a write command from L1)
@@ -694,10 +697,8 @@
       sc_signal<bool>     r_write_to_tgt_rsp_sc_fail; // sc command failed
 
-      // Buffer between WRITE fsm and IXR_CMD fsm (ask a missing cache line to XRAM)
-      sc_signal<bool>     r_write_to_ixr_cmd_req;   // valid request
-      sc_signal<bool>     r_write_to_ixr_cmd_write; // write request
-      sc_signal<addr_t>   r_write_to_ixr_cmd_nline; // cache line index
-      sc_signal<data_t> * r_write_to_ixr_cmd_data;  // cache line data
-      sc_signal<size_t>   r_write_to_ixr_cmd_trdid; // index in Transaction Table
+      // Buffer between WRITE fsm and IXR_CMD fsm 
+      sc_signal<bool>     r_write_to_ixr_cmd_req;     // valid request
+      sc_signal<bool>     r_write_to_ixr_cmd_put;     // request type (GET/PUT)
+      sc_signal<size_t>   r_write_to_ixr_cmd_index;   // TRT index 
 
       // Buffer between WRITE fsm and CC_SEND fsm (Update/Invalidate L1 caches)
@@ -713,8 +714,4 @@
       GenericFifo<size_t> m_write_to_cc_send_srcid_fifo;    // fifo for srcids
 
-#if L1_MULTI_CACHE
-      GenericFifo<size_t> m_write_to_cc_send_cache_id_fifo; // fifo for srcids
-#endif
-
       // Buffer between WRITE fsm and MULTI_ACK fsm (Decrement UPT entry)
       sc_signal<bool>     r_write_to_multi_ack_req;       // valid request
@@ -732,7 +729,4 @@
       sc_signal<addr_t>   r_multi_ack_nline;     // pending write nline
 
-      // signaling completion of multi-inval to CONFIG fsm
-      sc_signal<bool>     r_multi_ack_to_config_ack; 
-
       // Buffer between MULTI_ACK fsm and TGT_RSP fsm (complete write/update transaction)
       sc_signal<bool>     r_multi_ack_to_tgt_rsp_req;   // valid request
@@ -751,7 +745,4 @@
       sc_signal<addr_t>   r_cleanup_nline;         // cache line index
 
-#if L1_MULTI_CACHE
-      sc_signal<size_t>   r_cleanup_pktid;         // transaction pktid
-#endif
 
       sc_signal<copy_t>   r_cleanup_copy;          // first copy
@@ -780,7 +771,4 @@
       sc_signal<size_t>   r_cleanup_index;         // index of the INVAL line (in the UPT)
 
-      // signaling completion of broadcast-inval to CONFIG fsm
-      sc_signal<bool>     r_cleanup_to_config_ack;  
-       
       // Buffer between CLEANUP fsm and TGT_RSP fsm (acknowledge a write command from L1)
       sc_signal<bool>     r_cleanup_to_tgt_rsp_req;   // valid request
@@ -793,31 +781,28 @@
       ///////////////////////////////////////////////////////
 
-      sc_signal<int>      r_cas_fsm;        // FSM state
-      sc_signal<data_t>   r_cas_wdata;      // write data word
-      sc_signal<data_t> * r_cas_rdata;      // read data word
-      sc_signal<uint32_t> r_cas_lfsr;       // lfsr for random introducing
-      sc_signal<size_t>   r_cas_cpt;        // size of command
-      sc_signal<copy_t>   r_cas_copy;       // Srcid of the first copy
-      sc_signal<copy_t>   r_cas_copy_cache; // Srcid of the first copy
-      sc_signal<bool>     r_cas_copy_inst;  // Type of the first copy
-      sc_signal<size_t>   r_cas_count;      // number of copies
-      sc_signal<size_t>   r_cas_ptr;        // pointer to the heap
-      sc_signal<size_t>   r_cas_next_ptr;   // next pointer to the heap
-      sc_signal<bool>     r_cas_is_cnt;     // is_cnt bit (in directory)
-      sc_signal<bool>     r_cas_dirty;      // dirty bit (in directory)
-      sc_signal<size_t>   r_cas_way;        // way in directory
-      sc_signal<size_t>   r_cas_set;        // set in directory
-      sc_signal<data_t>   r_cas_tag;        // cache line tag (in directory)
-      sc_signal<size_t>   r_cas_trt_index;  // Transaction Table index
-      sc_signal<size_t>   r_cas_upt_index;  // Update Table index
-      sc_signal<data_t> * r_cas_data;       // cache line data
-
-      // Buffer between CAS fsm and IXR_CMD fsm (XRAM write)
+      sc_signal<int>      r_cas_fsm;              // FSM state
+      sc_signal<data_t>   r_cas_wdata;            // write data word
+      sc_signal<data_t> * r_cas_rdata;            // read data word
+      sc_signal<uint32_t> r_cas_lfsr;             // lfsr for random introducing
+      sc_signal<size_t>   r_cas_cpt;              // size of command
+      sc_signal<copy_t>   r_cas_copy;             // Srcid of the first copy
+      sc_signal<copy_t>   r_cas_copy_cache;       // Srcid of the first copy
+      sc_signal<bool>     r_cas_copy_inst;        // Type of the first copy
+      sc_signal<size_t>   r_cas_count;            // number of copies
+      sc_signal<size_t>   r_cas_ptr;              // pointer to the heap
+      sc_signal<size_t>   r_cas_next_ptr;         // next pointer to the heap
+      sc_signal<bool>     r_cas_is_cnt;           // is_cnt bit (in directory)
+      sc_signal<bool>     r_cas_dirty;            // dirty bit (in directory)
+      sc_signal<size_t>   r_cas_way;              // way in directory
+      sc_signal<size_t>   r_cas_set;              // set in directory
+      sc_signal<data_t>   r_cas_tag;              // cache line tag (in directory)
+      sc_signal<size_t>   r_cas_trt_index;        // Transaction Table index
+      sc_signal<size_t>   r_cas_upt_index;        // Update Table index
+      sc_signal<data_t> * r_cas_data;             // cache line data
+
+      // Buffer between CAS fsm and IXR_CMD fsm 
       sc_signal<bool>     r_cas_to_ixr_cmd_req;   // valid request
-      sc_signal<addr_t>   r_cas_to_ixr_cmd_nline; // cache line index
-      sc_signal<size_t>   r_cas_to_ixr_cmd_trdid; // index in Transaction Table
-      sc_signal<bool>     r_cas_to_ixr_cmd_write; // write request
-      sc_signal<data_t> * r_cas_to_ixr_cmd_data;  // cache line data
-
+      sc_signal<bool>     r_cas_to_ixr_cmd_put;   // request type (GET/PUT)
+      sc_signal<size_t>   r_cas_to_ixr_cmd_index; // TRT index 
 
       // Buffer between CAS fsm and TGT_RSP fsm
@@ -840,18 +825,17 @@
       GenericFifo<size_t> m_cas_to_cc_send_srcid_fifo;    // fifo for srcids
 
-#if L1_MULTI_CACHE
-      GenericFifo<size_t> m_cas_to_cc_send_cache_id_fifo; // fifo for srcids
-#endif
-
       ////////////////////////////////////////////////////
       // Registers controlled by the IXR_RSP fsm
       ////////////////////////////////////////////////////
 
-      sc_signal<int>      r_ixr_rsp_fsm;       // FSM state
-      sc_signal<size_t>   r_ixr_rsp_trt_index; // TRT entry index
-      sc_signal<size_t>   r_ixr_rsp_cpt;       // word counter
+      sc_signal<int>      r_ixr_rsp_fsm;                // FSM state
+      sc_signal<size_t>   r_ixr_rsp_trt_index;          // TRT entry index
+      sc_signal<size_t>   r_ixr_rsp_cpt;                // word counter
+
+      // Buffer between IXR_RSP fsm and CONFIG fsm  (response from the XRAM)
+      sc_signal<bool>     r_ixr_rsp_to_config_ack;      // one single bit   
 
       // Buffer between IXR_RSP fsm and XRAM_RSP fsm  (response from the XRAM)
-      sc_signal<bool>   * r_ixr_rsp_to_xram_rsp_rok; // A xram response is ready
+      sc_signal<bool>   * r_ixr_rsp_to_xram_rsp_rok;    // one bit per TRT entry
 
       ////////////////////////////////////////////////////
@@ -896,13 +880,7 @@
       GenericFifo<size_t> m_xram_rsp_to_cc_send_srcid_fifo;    // fifo for srcids
 
-#if L1_MULTI_CACHE
-      GenericFifo<size_t> m_xram_rsp_to_cc_send_cache_id_fifo; // fifo for srcids
-#endif
-
-      // Buffer between XRAM_RSP fsm and IXR_CMD fsm (XRAM write)
+      // Buffer between XRAM_RSP fsm and IXR_CMD fsm 
       sc_signal<bool>     r_xram_rsp_to_ixr_cmd_req;   // Valid request
-      sc_signal<addr_t>   r_xram_rsp_to_ixr_cmd_nline; // cache line index
-      sc_signal<data_t> * r_xram_rsp_to_ixr_cmd_data;  // cache line data
-      sc_signal<size_t>   r_xram_rsp_to_ixr_cmd_trdid; // index in transaction table
+      sc_signal<size_t>   r_xram_rsp_to_ixr_cmd_index; // TRT index 
 
       ////////////////////////////////////////////////////
@@ -911,5 +889,9 @@
 
       sc_signal<int>      r_ixr_cmd_fsm;
-      sc_signal<size_t>   r_ixr_cmd_cpt;
+      sc_signal<size_t>   r_ixr_cmd_word;              // word index for a put
+      sc_signal<size_t>   r_ixr_cmd_trdid;             // TRT index value     
+      sc_signal<addr_t>   r_ixr_cmd_address;           // address to XRAM
+      sc_signal<data_t> * r_ixr_cmd_wdata;             // cache line buffer
+      sc_signal<bool>     r_ixr_cmd_get;               // transaction type (PUT/GET)
 
       ////////////////////////////////////////////////////
