Index: trunk/modules/vci_mem_cache/caba/source/include/mem_cache_directory.h =================================================================== --- trunk/modules/vci_mem_cache/caba/source/include/mem_cache_directory.h (revision 488) +++ trunk/modules/vci_mem_cache/caba/source/include/mem_cache_directory.h (revision 489) @@ -6,12 +6,4 @@ #include #include "arithmetics.h" - -// !!! -// The L1_MULTI_CACHE mechanism does no longer work with the new pktid encoding -// of TSAR. Turning the define below to a non null value will cause the memcache -// to behave in an unpredicted way. -// TODO Either remove the mechanism from the mem cache or update its behaviour. - -#define L1_MULTI_CACHE 0 //#define RANDOM_EVICTION @@ -46,38 +38,25 @@ bool inst; // Is the owner an ICache ? size_t srcid; // The SRCID of the owner -#if L1_MULTI_CACHE - size_t cache_id; // In multi_cache configuration -#endif //////////////////////// // Constructors //////////////////////// - Owner(bool i_inst - ,size_t i_srcid -#if L1_MULTI_CACHE - ,size_t i_cache_id -#endif - ){ + Owner(bool i_inst, + size_t i_srcid) + { inst = i_inst; srcid = i_srcid; -#if L1_MULTI_CACHE - cache_id= i_cache_id; -#endif - } - - Owner(const Owner &a){ + } + + Owner(const Owner &a) + { inst = a.inst; srcid = a.srcid; -#if L1_MULTI_CACHE - cache_id= a.cache_id; -#endif - } - - Owner(){ + } + + Owner() + { inst = false; srcid = 0; -#if L1_MULTI_CACHE - cache_id= 0; -#endif } // end constructors @@ -114,7 +93,4 @@ owner.inst = 0; owner.srcid = 0; -#if L1_MULTI_CACHE - owner.cache_id= 0; -#endif ptr = 0; } @@ -171,7 +147,4 @@ << " ; Count = " << count << " ; Owner = " << owner.srcid -#if L1_MULTI_CACHE - << "." << owner.cache_id -#endif << " " << owner.inst << " ; Pointer = " << ptr << std::endl; @@ -322,5 +295,7 @@ // - entry : the entry value ///////////////////////////////////////////////////////////////////// - void write(const size_t &set, const size_t &way, const DirectoryEntry &entry) + void write( const size_t &set, + const size_t &way, + const DirectoryEntry &entry) { assert( (set> 1) ^ ((-(lfsr & 1)) & 0xd0000001); - way = lfsr % m_ways; - return DirectoryEntry(m_dir_tab[set][way]); + lfsr = (lfsr >> 1) ^ ((-(lfsr & 1)) & 0xd0000001); + way = lfsr % m_ways; + return DirectoryEntry(m_dir_tab[set][way]); #endif - for(size_t i=0; i * cache_line) - { - assert((set < m_sets ) && "Cache data error: Trying to read a wrong set" ); - assert((way < m_ways ) && "Cache data error: Trying to read a wrong way" ); - - for (uint32_t word=0; word * cache_line) + { + assert((set < m_sets ) && "Cache data error: Trying to read a wrong set" ); + assert((way < m_ways ) && "Cache data error: Trying to read a wrong way" ); + + for (uint32_t word=0; word* m_debug_previous_data; - sc_signal* m_debug_data; - - bool m_monitor_ok; - addr_t m_monitor_base; - addr_t m_monitor_length; + data_t * m_debug_previous_data; + data_t * m_debug_data; // instrumentation counters @@ -531,10 +529,4 @@ uint32_t m_broadcast_boundaries; - ////////////////////////////////////////////////// - // Registers controlled by the TGT_CMD fsm - ////////////////////////////////////////////////// - - sc_signal r_tgt_cmd_fsm; - // Fifo between TGT_CMD fsm and READ fsm GenericFifo m_cmd_read_addr_fifo; @@ -580,25 +572,41 @@ sc_signal r_tgt_cmd_config_cmd; + ////////////////////////////////////////////////// + // Registers controlled by the TGT_CMD fsm + ////////////////////////////////////////////////// + + sc_signal r_tgt_cmd_fsm; + sc_signal r_tgt_cmd_srcid; // srcid for response to config + sc_signal r_tgt_cmd_trdid; // trdid for response to config + sc_signal r_tgt_cmd_pktid; // pktid for response to config + /////////////////////////////////////////////////////// // Registers controlled by the CONFIG fsm /////////////////////////////////////////////////////// - sc_signal r_config_fsm; // FSM state - sc_signal r_config_lock; // lock protecting exclusive access - sc_signal r_config_cmd; // config request status - sc_signal r_config_address; // target buffer physical address - sc_signal r_config_srcid; // config request srcid - sc_signal r_config_trdid; // config request trdid - sc_signal r_config_pktid; // config request pktid - sc_signal r_config_nlines; // number of lines covering the buffer - sc_signal r_config_dir_way; // DIR: selected way - sc_signal r_config_dir_count; // DIR: number of copies - sc_signal r_config_dir_is_cnt; // DIR: counter mode (broadcast required) - sc_signal r_config_dir_copy_srcid; // DIR: first copy SRCID - sc_signal r_config_dir_copy_inst; // DIR: first copy L1 type - sc_signal r_config_dir_next_ptr; // DIR: index of next copy in HEAP - sc_signal r_config_heap_next; // current pointer to scan HEAP - - sc_signal r_config_ivt_index; // IVT index + sc_signal r_config_fsm; // FSM state + sc_signal r_config_lock; // lock protecting exclusive access + sc_signal r_config_cmd; // config request type + sc_signal r_config_address; // target buffer physical address + sc_signal r_config_srcid; // config request srcid + sc_signal r_config_trdid; // config request trdid + sc_signal r_config_pktid; // config request pktid + sc_signal r_config_cmd_lines; // number of lines to be handled + sc_signal r_config_rsp_lines; // number of lines not completed + sc_signal r_config_dir_way; // DIR: selected way + sc_signal r_config_dir_lock; // DIR: locked entry + sc_signal r_config_dir_count; // DIR: number of copies + sc_signal r_config_dir_is_cnt; // DIR: counter mode (broadcast) + sc_signal r_config_dir_copy_srcid; // DIR: first copy SRCID + sc_signal r_config_dir_copy_inst; // DIR: first copy L1 type + sc_signal r_config_dir_ptr; // DIR: index of next copy in HEAP + sc_signal r_config_heap_next; // current pointer to scan HEAP + sc_signal r_config_trt_index; // selected entry in TRT + sc_signal r_config_ivt_index; // selected entry in IVT + + // Buffer between CONFIG fsm and IXR_CMD fsm + sc_signal r_config_to_ixr_cmd_req; // valid request + sc_signal r_config_to_ixr_cmd_index; // TRT index + // Buffer between CONFIG fsm and TGT_RSP fsm (send a done response to L1 cache) @@ -617,43 +625,38 @@ GenericFifo m_config_to_cc_send_srcid_fifo; // fifo for owners srcid -#if L1_MULTI_CACHE - GenericFifo m_config_to_cc_send_cache_id_fifo; // fifo for cache_id -#endif - /////////////////////////////////////////////////////// // Registers controlled by the READ fsm /////////////////////////////////////////////////////// - sc_signal r_read_fsm; // FSM state - sc_signal r_read_copy; // Srcid of the first copy - sc_signal r_read_copy_cache; // Srcid of the first copy - sc_signal r_read_copy_inst; // Type of the first copy - sc_signal r_read_tag; // cache line tag (in directory) - sc_signal r_read_is_cnt; // is_cnt bit (in directory) - sc_signal r_read_lock; // lock bit (in directory) - sc_signal r_read_dirty; // dirty bit (in directory) - sc_signal r_read_count; // number of copies - sc_signal r_read_ptr; // pointer to the heap - sc_signal * r_read_data; // data (one cache line) - sc_signal r_read_way; // associative way (in cache) - sc_signal r_read_trt_index; // Transaction Table index - sc_signal r_read_next_ptr; // Next entry to point to - sc_signal r_read_last_free; // Last free entry - sc_signal r_read_ll_key; // LL key from the llsc_global_table - - // Buffer between READ fsm and IXR_CMD fsm (ask a missing cache line to XRAM) - sc_signal r_read_to_ixr_cmd_req; // valid request - sc_signal r_read_to_ixr_cmd_nline; // cache line index - sc_signal r_read_to_ixr_cmd_trdid; // index in Transaction Table + sc_signal r_read_fsm; // FSM state + sc_signal r_read_copy; // Srcid of the first copy + sc_signal r_read_copy_cache; // Srcid of the first copy + sc_signal r_read_copy_inst; // Type of the first copy + sc_signal r_read_tag; // cache line tag (in directory) + sc_signal r_read_is_cnt; // is_cnt bit (in directory) + sc_signal r_read_lock; // lock bit (in directory) + sc_signal r_read_dirty; // dirty bit (in directory) + sc_signal r_read_count; // number of copies + sc_signal r_read_ptr; // pointer to the heap + sc_signal * r_read_data; // data (one cache line) + sc_signal r_read_way; // associative way (in cache) + sc_signal r_read_trt_index; // Transaction Table index + sc_signal r_read_next_ptr; // Next entry to point to + sc_signal r_read_last_free; // Last free entry + sc_signal r_read_ll_key; // LL key from llsc_global_table + + // Buffer between READ fsm and IXR_CMD fsm + sc_signal r_read_to_ixr_cmd_req; // valid request + sc_signal r_read_to_ixr_cmd_index; // TRT index // Buffer between READ fsm and TGT_RSP fsm (send a hit read response to L1 cache) - sc_signal r_read_to_tgt_rsp_req; // valid request - sc_signal r_read_to_tgt_rsp_srcid; // Transaction srcid - sc_signal r_read_to_tgt_rsp_trdid; // Transaction trdid - sc_signal r_read_to_tgt_rsp_pktid; // Transaction pktid - sc_signal * r_read_to_tgt_rsp_data; // data (one cache line) - sc_signal r_read_to_tgt_rsp_word; // first word of the response - sc_signal r_read_to_tgt_rsp_length; // length of the response - sc_signal r_read_to_tgt_rsp_ll_key; // LL key from the llsc_global_table + sc_signal r_read_to_tgt_rsp_req; // valid request + sc_signal r_read_to_tgt_rsp_srcid; // Transaction srcid + sc_signal r_read_to_tgt_rsp_trdid; // Transaction trdid + sc_signal r_read_to_tgt_rsp_pktid; // Transaction pktid + sc_signal * r_read_to_tgt_rsp_data; // data (one cache line) + sc_signal r_read_to_tgt_rsp_word; // first word of the response + sc_signal r_read_to_tgt_rsp_length; // length of the response + sc_signal r_read_to_tgt_rsp_ll_key; // LL key from llsc_global_table /////////////////////////////////////////////////////////////// @@ -661,29 +664,29 @@ /////////////////////////////////////////////////////////////// - sc_signal r_write_fsm; // FSM state - sc_signal r_write_address; // first word address - sc_signal r_write_word_index; // first word index in line - sc_signal r_write_word_count; // number of words in line - sc_signal r_write_srcid; // transaction srcid - sc_signal r_write_trdid; // transaction trdid - sc_signal r_write_pktid; // transaction pktid - sc_signal * r_write_data; // data (one cache line) - sc_signal * r_write_be; // one byte enable per word - sc_signal r_write_byte; // (BE != 0X0) and (BE != 0xF) - sc_signal r_write_is_cnt; // is_cnt bit (in directory) - sc_signal r_write_lock; // lock bit (in directory) - sc_signal r_write_tag; // cache line tag (in directory) - sc_signal r_write_copy; // first owner of the line - sc_signal r_write_copy_cache; // first owner of the line - sc_signal r_write_copy_inst; // is this owner a ICache ? - sc_signal r_write_count; // number of copies - sc_signal r_write_ptr; // pointer to the heap - sc_signal r_write_next_ptr; // next pointer to the heap - sc_signal r_write_to_dec; // need to decrement update counter - sc_signal r_write_way; // way of the line - sc_signal r_write_trt_index; // index in Transaction Table - sc_signal r_write_upt_index; // index in Update Table - sc_signal r_write_sc_fail; // sc command failed - sc_signal r_write_pending_sc; // sc command pending + sc_signal r_write_fsm; // FSM state + sc_signal r_write_address; // first word address + sc_signal r_write_word_index; // first word index in line + sc_signal r_write_word_count; // number of words in line + sc_signal r_write_srcid; // transaction srcid + sc_signal r_write_trdid; // transaction trdid + sc_signal r_write_pktid; // transaction pktid + sc_signal * r_write_data; // data (one cache line) + sc_signal * r_write_be; // one byte enable per word + sc_signal r_write_byte; // (BE != 0X0) and (BE != 0xF) + sc_signal r_write_is_cnt; // is_cnt bit (in directory) + sc_signal r_write_lock; // lock bit (in directory) + sc_signal r_write_tag; // cache line tag (in directory) + sc_signal r_write_copy; // first owner of the line + sc_signal r_write_copy_cache; // first owner of the line + sc_signal r_write_copy_inst; // is this owner a ICache ? + sc_signal r_write_count; // number of copies + sc_signal r_write_ptr; // pointer to the heap + sc_signal r_write_next_ptr; // next pointer to the heap + sc_signal r_write_to_dec; // need to decrement update counter + sc_signal r_write_way; // way of the line + sc_signal r_write_trt_index; // index in Transaction Table + sc_signal r_write_upt_index; // index in Update Table + sc_signal r_write_sc_fail; // sc command failed + sc_signal r_write_pending_sc; // sc command pending // Buffer between WRITE fsm and TGT_RSP fsm (acknowledge a write command from L1) @@ -694,10 +697,8 @@ sc_signal r_write_to_tgt_rsp_sc_fail; // sc command failed - // Buffer between WRITE fsm and IXR_CMD fsm (ask a missing cache line to XRAM) - sc_signal r_write_to_ixr_cmd_req; // valid request - sc_signal r_write_to_ixr_cmd_write; // write request - sc_signal r_write_to_ixr_cmd_nline; // cache line index - sc_signal * r_write_to_ixr_cmd_data; // cache line data - sc_signal r_write_to_ixr_cmd_trdid; // index in Transaction Table + // Buffer between WRITE fsm and IXR_CMD fsm + sc_signal r_write_to_ixr_cmd_req; // valid request + sc_signal r_write_to_ixr_cmd_put; // request type (GET/PUT) + sc_signal r_write_to_ixr_cmd_index; // TRT index // Buffer between WRITE fsm and CC_SEND fsm (Update/Invalidate L1 caches) @@ -713,8 +714,4 @@ GenericFifo m_write_to_cc_send_srcid_fifo; // fifo for srcids -#if L1_MULTI_CACHE - GenericFifo m_write_to_cc_send_cache_id_fifo; // fifo for srcids -#endif - // Buffer between WRITE fsm and MULTI_ACK fsm (Decrement UPT entry) sc_signal r_write_to_multi_ack_req; // valid request @@ -732,7 +729,4 @@ sc_signal r_multi_ack_nline; // pending write nline - // signaling completion of multi-inval to CONFIG fsm - sc_signal r_multi_ack_to_config_ack; - // Buffer between MULTI_ACK fsm and TGT_RSP fsm (complete write/update transaction) sc_signal r_multi_ack_to_tgt_rsp_req; // valid request @@ -751,7 +745,4 @@ sc_signal r_cleanup_nline; // cache line index -#if L1_MULTI_CACHE - sc_signal r_cleanup_pktid; // transaction pktid -#endif sc_signal r_cleanup_copy; // first copy @@ -780,7 +771,4 @@ sc_signal r_cleanup_index; // index of the INVAL line (in the UPT) - // signaling completion of broadcast-inval to CONFIG fsm - sc_signal r_cleanup_to_config_ack; - // Buffer between CLEANUP fsm and TGT_RSP fsm (acknowledge a write command from L1) sc_signal r_cleanup_to_tgt_rsp_req; // valid request @@ -793,31 +781,28 @@ /////////////////////////////////////////////////////// - sc_signal r_cas_fsm; // FSM state - sc_signal r_cas_wdata; // write data word - sc_signal * r_cas_rdata; // read data word - sc_signal r_cas_lfsr; // lfsr for random introducing - sc_signal r_cas_cpt; // size of command - sc_signal r_cas_copy; // Srcid of the first copy - sc_signal r_cas_copy_cache; // Srcid of the first copy - sc_signal r_cas_copy_inst; // Type of the first copy - sc_signal r_cas_count; // number of copies - sc_signal r_cas_ptr; // pointer to the heap - sc_signal r_cas_next_ptr; // next pointer to the heap - sc_signal r_cas_is_cnt; // is_cnt bit (in directory) - sc_signal r_cas_dirty; // dirty bit (in directory) - sc_signal r_cas_way; // way in directory - sc_signal r_cas_set; // set in directory - sc_signal r_cas_tag; // cache line tag (in directory) - sc_signal r_cas_trt_index; // Transaction Table index - sc_signal r_cas_upt_index; // Update Table index - sc_signal * r_cas_data; // cache line data - - // Buffer between CAS fsm and IXR_CMD fsm (XRAM write) + sc_signal r_cas_fsm; // FSM state + sc_signal r_cas_wdata; // write data word + sc_signal * r_cas_rdata; // read data word + sc_signal r_cas_lfsr; // lfsr for random introducing + sc_signal r_cas_cpt; // size of command + sc_signal r_cas_copy; // Srcid of the first copy + sc_signal r_cas_copy_cache; // Srcid of the first copy + sc_signal r_cas_copy_inst; // Type of the first copy + sc_signal r_cas_count; // number of copies + sc_signal r_cas_ptr; // pointer to the heap + sc_signal r_cas_next_ptr; // next pointer to the heap + sc_signal r_cas_is_cnt; // is_cnt bit (in directory) + sc_signal r_cas_dirty; // dirty bit (in directory) + sc_signal r_cas_way; // way in directory + sc_signal r_cas_set; // set in directory + sc_signal r_cas_tag; // cache line tag (in directory) + sc_signal r_cas_trt_index; // Transaction Table index + sc_signal r_cas_upt_index; // Update Table index + sc_signal * r_cas_data; // cache line data + + // Buffer between CAS fsm and IXR_CMD fsm sc_signal r_cas_to_ixr_cmd_req; // valid request - sc_signal r_cas_to_ixr_cmd_nline; // cache line index - sc_signal r_cas_to_ixr_cmd_trdid; // index in Transaction Table - sc_signal r_cas_to_ixr_cmd_write; // write request - sc_signal * r_cas_to_ixr_cmd_data; // cache line data - + sc_signal r_cas_to_ixr_cmd_put; // request type (GET/PUT) + sc_signal r_cas_to_ixr_cmd_index; // TRT index // Buffer between CAS fsm and TGT_RSP fsm @@ -840,18 +825,17 @@ GenericFifo m_cas_to_cc_send_srcid_fifo; // fifo for srcids -#if L1_MULTI_CACHE - GenericFifo m_cas_to_cc_send_cache_id_fifo; // fifo for srcids -#endif - //////////////////////////////////////////////////// // Registers controlled by the IXR_RSP fsm //////////////////////////////////////////////////// - sc_signal r_ixr_rsp_fsm; // FSM state - sc_signal r_ixr_rsp_trt_index; // TRT entry index - sc_signal r_ixr_rsp_cpt; // word counter + sc_signal r_ixr_rsp_fsm; // FSM state + sc_signal r_ixr_rsp_trt_index; // TRT entry index + sc_signal r_ixr_rsp_cpt; // word counter + + // Buffer between IXR_RSP fsm and CONFIG fsm (response from the XRAM) + sc_signal r_ixr_rsp_to_config_ack; // one single bit // Buffer between IXR_RSP fsm and XRAM_RSP fsm (response from the XRAM) - sc_signal * r_ixr_rsp_to_xram_rsp_rok; // A xram response is ready + sc_signal * r_ixr_rsp_to_xram_rsp_rok; // one bit per TRT entry //////////////////////////////////////////////////// @@ -896,13 +880,7 @@ GenericFifo m_xram_rsp_to_cc_send_srcid_fifo; // fifo for srcids -#if L1_MULTI_CACHE - GenericFifo m_xram_rsp_to_cc_send_cache_id_fifo; // fifo for srcids -#endif - - // Buffer between XRAM_RSP fsm and IXR_CMD fsm (XRAM write) + // Buffer between XRAM_RSP fsm and IXR_CMD fsm sc_signal r_xram_rsp_to_ixr_cmd_req; // Valid request - sc_signal r_xram_rsp_to_ixr_cmd_nline; // cache line index - sc_signal * r_xram_rsp_to_ixr_cmd_data; // cache line data - sc_signal r_xram_rsp_to_ixr_cmd_trdid; // index in transaction table + sc_signal r_xram_rsp_to_ixr_cmd_index; // TRT index //////////////////////////////////////////////////// @@ -911,5 +889,9 @@ sc_signal r_ixr_cmd_fsm; - sc_signal r_ixr_cmd_cpt; + sc_signal r_ixr_cmd_word; // word index for a put + sc_signal r_ixr_cmd_trdid; // TRT index value + sc_signal r_ixr_cmd_address; // address to XRAM + sc_signal * r_ixr_cmd_wdata; // cache line buffer + sc_signal r_ixr_cmd_get; // transaction type (PUT/GET) //////////////////////////////////////////////////// Index: trunk/modules/vci_mem_cache/caba/source/include/xram_transaction.h =================================================================== --- trunk/modules/vci_mem_cache/caba/source/include/xram_transaction.h (revision 488) +++ trunk/modules/vci_mem_cache/caba/source/include/xram_transaction.h (revision 489) @@ -34,4 +34,5 @@ bool rerror; // error returned by xram data_t ll_key; // LL key returned by the llsc_global_table + bool config; // transaction required by CONFIG FSM ///////////////////////////////////////////////////////////////////// @@ -42,4 +43,5 @@ valid = false; rerror = false; + config = false; } @@ -80,4 +82,5 @@ rerror = source.rerror; ll_key = source.ll_key; + config = source.config; } @@ -87,4 +90,5 @@ void print() { + std::cout << "------- TRT entry -------" << std::endl; std::cout << "valid = " << valid << std::endl; std::cout << "xram_read = " << xram_read << std::endl; @@ -96,12 +100,18 @@ std::cout << "read_length = " << read_length << std::endl; std::cout << "word_index = " << word_index << std::endl; - for(size_t i=0; i &data) { - assert( (index < size_tab) - && "Invalid Transaction Tab Entry"); - assert(be.size()==tab[index].wdata_be.size() - && "Bad data mask in write_data_mask in TransactionTab"); - assert(data.size()==tab[index].wdata.size() - && "Bad data in write_data_mask in TransactionTab"); - - for(size_t i=0; i &data_be, const std::vector &data, - const data_t ll_key = 0) - { - assert( (index < size_tab) - && "The selected entry is out of range in set() Transaction Tab"); - assert(data_be.size()==tab[index].wdata_be.size() - && "Bad data_be argument in set() TransactionTab"); - assert(data.size()==tab[index].wdata.size() - && "Bad data argument in set() TransactionTab"); + const data_t ll_key = 0, + const bool config = false) + { + assert( (index < size_tab) and + "MEMC ERROR: The selected entry is out of range in TRT set()"); + + assert( (data_be.size()==tab[index].wdata_be.size()) and + "MEMC ERROR: Bad data_be argument in TRT set()"); + + assert( (data.size()==tab[index].wdata.size()) and + "MEMC ERROR: Bad data argument in TRT set()"); tab[index].valid = true; @@ -368,4 +388,5 @@ tab[index].word_index = word_index; tab[index].ll_key = ll_key; + tab[index].config = config; for(size_t i=0; i= size_tab ) - { - std::cout << "VCI_MEM_CACHE ERRROR " << tab_name - << " TRT entry out of range in write_rsp()" << std::endl; - exit(0); - } - if ( word > tab[index].wdata_be.size() ) - { - std::cout << "VCI_MEM_CACHE ERRROR " << tab_name - << " Bad word_index in write_rsp() in TRT" << std::endl; - exit(0); - } - if ( not tab[index].valid ) - { - std::cout << "VCI_MEM_CACHE ERRROR " << tab_name - << " TRT Entry invalid in write_rsp()" << std::endl; - exit(0); - } - if ( not tab[index].xram_read ) - { - std::cout << "VCI_MEM_CACHE ERRROR " << tab_name - << " TRT entry is not an XRAM GET in write_rsp()" << std::endl; - exit(0); - } + assert( (index < size_tab) and + "MEMC ERROR: The selected entry is out of range in TRT write_rsp()"); + + assert( (word < tab[index].wdata_be.size()) and + "MEMC ERROR: Bad word index in TRT write_rsp()"); + + assert( (tab[index].valid) and + "MEMC ERROR: TRT entry not valid in TRT write_rsp()"); + + assert( (tab[index].xram_read ) and + "MEMC ERROR: TRT entry is not a GET in TRT write_rsp()"); // first 32 bits word @@ -427,9 +433,5 @@ mask = be_to_mask(tab[index].wdata_be[word+1]); tab[index].wdata[word+1] = (tab[index].wdata[word+1] & mask) | (value & ~mask); - - // error update - tab[index].rerror |= rerror; - } - + } ///////////////////////////////////////////////////////////////////// // The erase() function erases an entry in the transaction tab. @@ -439,8 +441,21 @@ void erase(const size_t index) { - assert( (index < size_tab) - && "The selected entry is out of range in erase() Transaction Tab"); + assert( (index < size_tab) and + "MEMC ERROR: The selected entry is out of range in TRT erase()"); + tab[index].valid = false; tab[index].rerror = false; + } + ///////////////////////////////////////////////////////////////////// + // The is_config() function returns the config flag value. + // Arguments : + // - index : the index of the entry in the transaction tab + ///////////////////////////////////////////////////////////////////// + bool is_config(const size_t index) + { + assert( (index < size_tab) and + "MEMC ERROR: The selected entry is out of range in TRT is_config()"); + + return tab[index].config; } }; // end class TransactionTab Index: trunk/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp =================================================================== --- trunk/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp (revision 488) +++ trunk/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp (revision 489) @@ -45,5 +45,5 @@ #define DEBUG_MEMC_WRITE 1 // detailed trace of WRITE FSM #define DEBUG_MEMC_CAS 1 // detailed trace of CAS FSM -#define DEBUG_MEMC_IXR_CMD 1 // detailed trace of IXR_RSP FSM +#define DEBUG_MEMC_IXR_CMD 1 // detailed trace of IXR_CMD FSM #define DEBUG_MEMC_IXR_RSP 1 // detailed trace of IXR_RSP FSM #define DEBUG_MEMC_XRAM_RSP 1 // detailed trace of XRAM_RSP FSM @@ -124,6 +124,5 @@ "MULTI_ACK_UPT_LOCK", "MULTI_ACK_UPT_CLEAR", - "MULTI_ACK_WRITE_RSP", - "MULTI_ACK_CONFIG_ACK" + "MULTI_ACK_WRITE_RSP" }; const char *config_fsm_str[] = @@ -131,15 +130,17 @@ "CONFIG_IDLE", "CONFIG_LOOP", + "CONFIG_WAIT", "CONFIG_RSP", "CONFIG_DIR_REQ", "CONFIG_DIR_ACCESS", - "CONFIG_DIR_IVT_LOCK", + "CONFIG_IVT_LOCK", "CONFIG_BC_SEND", - "CONFIG_BC_WAIT", - "CONFIG_INV_SEND", + "CONFIG_INVAL_SEND", "CONFIG_HEAP_REQ", "CONFIG_HEAP_SCAN", "CONFIG_HEAP_LAST", - "CONFIG_INV_WAIT" + "CONFIG_TRT_LOCK", + "CONFIG_TRT_SET", + "CONFIG_PUT_REQ" }; const char *read_fsm_str[] = @@ -165,5 +166,4 @@ "WRITE_DIR_REQ", "WRITE_DIR_LOCK", - "WRITE_DIR_READ", "WRITE_DIR_HIT", "WRITE_UPT_LOCK", @@ -177,4 +177,5 @@ "WRITE_MISS_TRT_SET", "WRITE_MISS_XRAM_REQ", + "WRITE_BC_DIR_READ", "WRITE_BC_TRT_LOCK", "WRITE_BC_IVT_LOCK", @@ -187,5 +188,4 @@ { "IXR_RSP_IDLE", - "IXR_RSP_ACK", "IXR_RSP_TRT_ERASE", "IXR_RSP_TRT_READ" @@ -199,5 +199,5 @@ "XRAM_RSP_DIR_UPDT", "XRAM_RSP_DIR_RSP", - "XRAM_RSP_INVAL_LOCK", + "XRAM_RSP_IVT_LOCK", "XRAM_RSP_INVAL_WAIT", "XRAM_RSP_INVAL", @@ -215,8 +215,15 @@ "IXR_CMD_CAS_IDLE", "IXR_CMD_XRAM_IDLE", - "IXR_CMD_READ", - "IXR_CMD_WRITE", - "IXR_CMD_CAS", - "IXR_CMD_XRAM" + "IXR_CMD_CONFIG_IDLE", + "IXR_CMD_READ_TRT", + "IXR_CMD_WRITE_TRT", + "IXR_CMD_CAS_TRT", + "IXR_CMD_XRAM_TRT", + "IXR_CMD_CONFIG_TRT", + "IXR_CMD_READ_SEND", + "IXR_CMD_WRITE_SEND", + "IXR_CMD_CAS_SEND", + "IXR_CMD_XRAM_SEND", + "IXR_CMD_CONFIG_SEND" }; const char *cas_fsm_str[] = @@ -260,5 +267,4 @@ "CLEANUP_IVT_CLEAR", "CLEANUP_WRITE_RSP", - "CLEANUP_CONFIG_ACK", "CLEANUP_SEND_CLACK" }; @@ -279,5 +285,7 @@ "ALLOC_TRT_CAS", "ALLOC_TRT_XRAM_RSP", - "ALLOC_TRT_IXR_RSP" + "ALLOC_TRT_IXR_RSP", + "ALLOC_TRT_CONFIG", + "ALLOC_TRT_IXR_CMD" }; const char *alloc_upt_fsm_str[] = @@ -380,5 +388,4 @@ m_broadcast_boundaries(0x7C1F), - r_tgt_cmd_fsm("r_tgt_cmd_fsm"), // FIFOs @@ -407,4 +414,6 @@ m_cc_receive_to_multi_ack_fifo("m_cc_receive_to_multi_ack_fifo", 4), + r_tgt_cmd_fsm("r_tgt_cmd_fsm"), + r_config_fsm( "r_config_fsm" ), @@ -418,7 +427,4 @@ m_write_to_cc_send_inst_fifo("m_write_to_cc_send_inst_fifo",8), m_write_to_cc_send_srcid_fifo("m_write_to_cc_send_srcid_fifo",8), -#if L1_MULTI_CACHE - m_write_to_cc_send_cache_id_fifo("m_write_to_cc_send_cache_id_fifo",8), -#endif r_multi_ack_fsm("r_multi_ack_fsm"), @@ -430,7 +436,4 @@ m_cas_to_cc_send_inst_fifo("m_cas_to_cc_send_inst_fifo",8), m_cas_to_cc_send_srcid_fifo("m_cas_to_cc_send_srcid_fifo",8), -#if L1_MULTI_CACHE - m_cas_to_cc_send_cache_id_fifo("m_cas_to_cc_send_cache_id_fifo",8), -#endif r_ixr_rsp_fsm("r_ixr_rsp_fsm"), @@ -439,7 +442,4 @@ m_xram_rsp_to_cc_send_inst_fifo("m_xram_rsp_to_cc_send_inst_fifo",8), m_xram_rsp_to_cc_send_srcid_fifo("m_xram_rsp_to_cc_send_srcid_fifo",8), -#if L1_MULTI_CACHE - m_xram_rsp_to_cc_send_cache_id_fifo("m_xram_rsp_to_cc_send_cache_id_fifo",8), -#endif r_ixr_cmd_fsm("r_ixr_cmd_fsm"), @@ -509,5 +509,4 @@ r_xram_rsp_victim_data = new sc_signal[nwords]; r_xram_rsp_to_tgt_rsp_data = new sc_signal[nwords]; - r_xram_rsp_to_ixr_cmd_data = new sc_signal[nwords]; // Allocation for READ FSM @@ -520,14 +519,15 @@ r_write_to_cc_send_data = new sc_signal[nwords]; r_write_to_cc_send_be = new sc_signal[nwords]; - r_write_to_ixr_cmd_data = new sc_signal[nwords]; // Allocation for CAS FSM - r_cas_to_ixr_cmd_data = new sc_signal[nwords]; r_cas_data = new sc_signal[nwords]; r_cas_rdata = new sc_signal[2]; + // Allocation for IXR_CMD FSM + r_ixr_cmd_wdata = new sc_signal[nwords]; + // Allocation for debug - m_debug_previous_data = new sc_signal[nwords]; - m_debug_data = new sc_signal[nwords]; + m_debug_previous_data = new data_t[nwords]; + m_debug_data = new data_t[nwords]; SC_METHOD(transition); @@ -540,36 +540,4 @@ } // end constructor -/////////////////////////////////////////////////////////////////////// -tmpl(void) ::start_monitor(addr_t addr, addr_t length) -/////////////////////////////////////////////////////////////////////// -{ - m_monitor_ok = true; - m_monitor_base = addr; - m_monitor_length = length; -} - -/////////////////////////////////////////////////////////////////////// -tmpl(void) ::stop_monitor() -/////////////////////////////////////////////////////////////////////// -{ - m_monitor_ok = false; -} - -//////////////////////////////////////////////// -tmpl(void) ::check_monitor( addr_t addr, - data_t data, - bool read ) -//////////////////////////////////////////////// -{ - if((addr >= m_monitor_base) and - (addr < m_monitor_base + m_monitor_length)) - { - if ( read ) std::cout << " Monitor MEMC Read "; - else std::cout << " Monitor MEMC Write"; - std::cout << " / Address = " << std::hex << addr - << " / Data = " << data - << " at cycle " << std::dec << m_cpt_cycles << std::endl; - } -} ///////////////////////////////////////////////////// @@ -581,19 +549,20 @@ DirectoryEntry entry = m_cache_directory.read_neutral(addr, &way, &set ); + // read data and compute data_change bool data_change = false; - if ( entry.valid ) { - m_cache_data.read_line( way, set, m_debug_data ); - - for ( size_t i = 0 ; i m_debug_start_cycle) and m_debug_ok; @@ -939,4 +903,6 @@ // - For MEMC_CMD_TYPE, the response is delayed until the operation is completed. //////////////////////////////////////////////////////////////////////////////////// + +//std::cout << std::endl << "tgt_cmd_fsm" << std::endl; switch(r_tgt_cmd_fsm.read()) @@ -1042,5 +1008,5 @@ case TGT_CMD_ERROR: // response error must be sent - // wait if pending TGT_CMD request to TGT_RSP FSM + // wait if pending request if(r_tgt_cmd_to_tgt_rsp_req.read()) break; @@ -1076,4 +1042,5 @@ size_t error; uint32_t rdata = 0; // default value + uint32_t wdata = p_vci_tgt.wdata.read(); if ( (p_vci_tgt.cmd.read() == vci_param_int::CMD_READ) // get lock @@ -1084,7 +1051,14 @@ error = 0; r_config_lock = true; + if ( rdata == 0 ) + { + r_tgt_cmd_srcid = p_vci_tgt.srcid.read(); + r_tgt_cmd_trdid = p_vci_tgt.trdid.read(); + r_tgt_cmd_pktid = p_vci_tgt.pktid.read(); + } } else if ( (p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE) // release lock - and (cell == MEMC_LOCK) ) + and (cell == MEMC_LOCK) + and (p_vci_tgt.srcid.read() == r_tgt_cmd_srcid.read()) ) { need_rsp = true; @@ -1093,6 +1067,10 @@ } else if ( (p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE) // set addr_lo - and (cell == MEMC_ADDR_LO) ) - { + and (cell == MEMC_ADDR_LO) + and (p_vci_tgt.srcid.read() == r_tgt_cmd_srcid.read()) ) + { + assert( ((wdata % (m_words*vci_param_int::B)) == 0) and + "VCI_MEM_CACHE CONFIG ERROR: The buffer must be aligned on a cache line"); + need_rsp = true; error = 0; @@ -1101,5 +1079,7 @@ } else if ( (p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE) // set addr_hi - and (cell == MEMC_ADDR_HI) ) + and (cell == MEMC_ADDR_HI) + and (p_vci_tgt.srcid.read() == r_tgt_cmd_srcid.read()) ) + { need_rsp = true; @@ -1109,18 +1089,23 @@ } else if ( (p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE) // set buf_lines - and (cell == MEMC_BUF_LENGTH) ) + and (cell == MEMC_BUF_LENGTH) + and (p_vci_tgt.srcid.read() == r_tgt_cmd_srcid.read()) ) { need_rsp = true; error = 0; size_t lines = (size_t)(p_vci_tgt.wdata.read()/(m_words<<2)); - if ( r_config_address.read()/(m_words*vci_param_int::B) ) lines++; - r_config_nlines = lines; + if ( r_config_address.read()%(m_words*4) ) lines++; + r_config_cmd_lines = lines; + r_config_rsp_lines = lines; } else if ( (p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE) // set cmd type - and (cell == MEMC_CMD_TYPE) ) + and (cell == MEMC_CMD_TYPE) + and (p_vci_tgt.srcid.read() == r_tgt_cmd_srcid.read()) ) { need_rsp = false; error = 0; r_config_cmd = p_vci_tgt.wdata.read(); + + // prepare delayed response from CONFIG FSM r_config_srcid = p_vci_tgt.srcid.read(); r_config_trdid = p_vci_tgt.trdid.read(); @@ -1153,4 +1138,5 @@ << " address = " << std::hex << p_vci_tgt.address.read() << " / wdata = " << p_vci_tgt.wdata.read() + << " / need_rsp = " << need_rsp << " / error = " << error << std::endl; #endif @@ -1256,7 +1242,6 @@ // MULTI_ACK FSM ///////////////////////////////////////////////////////////////////////// - // This FSM controls the response to the multicast update or multicast - // inval coherence requests sent by the memory cache to the L1 caches and - // update the UPT. + // This FSM controls the response to the multicast update requests sent + // by the memory cache to the L1 caches and update the UPT. // // - The FSM decrements the proper entry in UPT, @@ -1264,10 +1249,10 @@ // - If required, it sends a request to the TGT_RSP FSM to complete // a pending write transaction. - // - If required, it sends an acknowledge to the CONFIG FSM to signal - // completion of a line inval. // // All those multi-ack packets are one flit packet. - // The index in the UPT is defined in the UPDTID field. + // The index in the UPT is defined in the TRDID field. //////////////////////////////////////////////////////////////////////// + +//std::cout << std::endl << "multi_ack_fsm" << std::endl; switch(r_multi_ack_fsm.read()) @@ -1381,5 +1366,4 @@ r_multi_ack_nline = m_upt.nline(r_multi_ack_upt_index.read()); bool need_rsp = m_upt.need_rsp(r_multi_ack_upt_index.read()); - bool need_ack = m_upt.need_ack(r_multi_ack_upt_index.read()); // clear the UPT entry @@ -1387,5 +1371,4 @@ if ( need_rsp ) r_multi_ack_fsm = MULTI_ACK_WRITE_RSP; - else if ( need_ack ) r_multi_ack_fsm = MULTI_ACK_CONFIG_ACK; else r_multi_ack_fsm = MULTI_ACK_IDLE; @@ -1418,20 +1401,4 @@ break; } - ////////////////////////// - case MULTI_ACK_CONFIG_ACK: // Signals multi-inval completion to CONFIG FSM - // Wait if pending request - { - if ( r_multi_ack_to_config_ack.read() ) break; - - r_multi_ack_to_config_ack = true; - r_multi_ack_fsm = MULTI_ACK_IDLE; - -#if DEBUG_MEMC_MULTI_ACK -if(m_debug) -std::cout << " " - << " Signals inval completion to CONFIG FSM" << std::endl; -#endif - break; - } } // end switch r_multi_ack_fsm @@ -1441,29 +1408,42 @@ // The CONFIG FSM handles the VCI configuration requests (INVAL & SYNC). // The target buffer can have any size, and there is one single command for - // all cache lines covered by the target buffer. - // An INVAL or SYNC configuration request is defined by the followinf registers: - // - bool r_config_cmd : INVAL / SYNC / NOP) + // all cache lines covered by the target buffer. + // + // An INVAL or SYNC configuration operation is defined by the following registers: + // - bool r_config_cmd : INVAL / SYNC / NOP // - uint64_t r_config_address : buffer base address - // - uint32_t r_config_nlines : number of lines covering buffer + // - uint32_t r_config_cmd_lines : number of lines to be handled + // - uint32_t r_config_rsp_lines : number of lines not completed // // For both INVAL and SYNC commands, the CONFIG FSM contains the loop handling - // all cache lines covered by the target buffer. - // + // all cache lines covered by the buffer. The various lines of a given buffer + // can be pipelined: the CONFIG FSM does not wait the response for line (n) to send + // the command for line (n+1). It decrements the r_config_cmd_lines counter until + // the last request has been registered in TRT (for a SYNC), or in IVT (for an INVAL). + // // - INVAL request: - // For each line, it access to the DIR array. + // For each line, it access to the DIR. // In case of miss, it does nothing, and a response is requested to TGT_RSP FSM. // In case of hit, with no copies in L1 caches, the line is invalidated and // a response is requested to TGT_RSP FSM. // If there is copies, a multi-inval, or a broadcast-inval coherence transaction - // is launched and registered in UPT. The multi-inval transaction is signaled - // by the r_multi_ack_to config_ack or r_cleanup_to_config_ack flip-flops. - // The config inval response is sent only when the last line has been invalidated. - // + // is launched and registered in UPT. The multi-inval transaction completion + // is signaled by the CLEANUP FSM by decrementing the r_config_rsp_lines counter. + // The CONFIG INVAL response is sent only when the last line has been invalidated. + // TODO : The target buffer address must be aligned on a cache line boundary. + // This constraint can be released, but it requires to make 2 PUT transactions + // for the first and the last line... + // // - SYNC request: - // - // ... Not implemented yet ... + // For each line, it access to the DIR. + // In case of miss, it does nothing, and a response is requested to TGT_RSP FSM. + // In case of hit, a PUT transaction is registered in TRT and a request is sent + // to IXR_CMD FSM. The IXR_RSP FSM decrements the r_config_rsp_lines counter + // when a PUT response is received. + // The CONFIG SYNC response is sent only when the last PUT response is received. // // From the software point of view, a configuration request is a sequence - // of 6 atomic accesses in an uncached segment: + // of 6 atomic accesses in an uncached segment. A dedicated lock is used + // to handle only one configuration command at a given time: // - Read MEMC_LOCK : Get the lock // - Write MEMC_ADDR_LO : Set the buffer address LSB @@ -1474,4 +1454,6 @@ //////////////////////////////////////////////////////////////////////////////////// +//std::cout << std::endl << "config_fsm" << std::endl; + switch( r_config_fsm.read() ) { @@ -1486,6 +1468,6 @@ if(m_debug) std::cout << " Config Request received" - << " address = " << std::hex << r_config_address.read() - << " / nlines = " << std::dec << r_config_nlines.read() + << " / address = " << std::hex << r_config_address.read() + << " / lines = " << std::dec << r_config_cmd_lines.read() << " / type = " << r_config_cmd.read() << std::endl; #endif @@ -1494,10 +1476,10 @@ } ///////////////// - case CONFIG_LOOP: // test last line - { - if ( r_config_nlines.read() == 0 ) + case CONFIG_LOOP: // test if last line to be handled + { + if ( r_config_cmd_lines.read() == 0 ) { r_config_cmd = MEMC_CMD_NOP; - r_config_fsm = CONFIG_RSP; + r_config_fsm = CONFIG_WAIT; } else @@ -1509,9 +1491,48 @@ if(m_debug) std::cout << " " - << " address = " << std::hex << r_config_address.read() - << " / nlines = " << std::dec << r_config_nlines.read() + << " / address = " << std::hex << r_config_address.read() + << " / lines not handled = " << std::dec << r_config_cmd_lines.read() << " / command = " << r_config_cmd.read() << std::endl; #endif break; + } + ///////////////// + case CONFIG_WAIT: // wait completion (last response) + { + if ( r_config_rsp_lines.read() == 0 ) // last response received + { + r_config_fsm = CONFIG_RSP; + } + +#if DEBUG_MEMC_CONFIG +if(m_debug) +std::cout << " " + << " / lines to do = " << std::dec << r_config_rsp_lines.read() << std::endl; +#endif + break; + } + //////////////// + case CONFIG_RSP: // request TGT_RSP FSM to return response + { + if ( not r_config_to_tgt_rsp_req.read() ) + { + r_config_to_tgt_rsp_srcid = r_config_srcid.read(); + r_config_to_tgt_rsp_trdid = r_config_trdid.read(); + r_config_to_tgt_rsp_pktid = r_config_pktid.read(); + r_config_to_tgt_rsp_error = false; + r_config_to_tgt_rsp_req = true; + r_config_fsm = CONFIG_IDLE; + +#if DEBUG_MEMC_CONFIG +if(m_debug) +std::cout << " Request TGT_RSP FSM to return response:" + << " error = " << r_config_to_tgt_rsp_error.read() + << " / rsrcid = " << std::hex << r_config_srcid.read() + << " / rtrdid = " << std::hex << r_config_trdid.read() + << " / rpktid = " << std::hex << r_config_pktid.read() << std::endl; +#endif + } + break; + } //////////////////// @@ -1533,4 +1554,7 @@ case CONFIG_DIR_ACCESS: // Access directory and decode config command { + assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_CONFIG) and + "MEMC ERROR in CONFIG_DIR_ACCESS state: bad DIR allocation"); + size_t way = 0; DirectoryEntry entry = m_cache_directory.read(r_config_address.read(), way); @@ -1543,8 +1567,9 @@ r_config_dir_copy_srcid = entry.owner.srcid; r_config_dir_is_cnt = entry.is_cnt; + r_config_dir_lock = entry.lock; r_config_dir_count = entry.count; - r_config_dir_next_ptr = entry.ptr; - - r_config_fsm = CONFIG_DIR_IVT_LOCK; + r_config_dir_ptr = entry.ptr; + + r_config_fsm = CONFIG_IVT_LOCK; } else if ( entry.valid and // hit & sync command @@ -1552,13 +1577,13 @@ (r_config_cmd.read() == MEMC_CMD_SYNC) ) { - std::cout << "VCI_MEM_CACHE ERROR: " - << "SYNC config request not implemented yet" << std::endl; - exit(0); + r_config_fsm = CONFIG_TRT_LOCK; } - else // return to LOOP + else // miss : return to LOOP { - r_config_nlines = r_config_nlines.read() - 1; - r_config_address = r_config_address.read() + (m_words<<2); - r_config_fsm = CONFIG_LOOP; + r_config_cmd_lines = r_config_cmd_lines.read() - 1; + r_config_rsp_lines = r_config_rsp_lines.read() - 1; + r_config_cmd_lines = r_config_cmd_lines.read() - 1; + r_config_address = r_config_address.read() + (m_words<<2); + r_config_fsm = CONFIG_LOOP; } @@ -1574,11 +1599,131 @@ break; } - ///////////////////////// - case CONFIG_DIR_IVT_LOCK: // enter this state in case of INVAL command - // Try to get both DIR & IVT locks, and return - // to LOOP state if IVT full. - // Register inval in IVT, and invalidate the - // directory if IVT not full. - { + ///////////////////// + case CONFIG_TRT_LOCK: // enter this state in case of SYNC command + // to a dirty cache line + // keep DIR lock, and try to get TRT lock + // return to LOOP state if TRT full + // reset dirty bit in DIR and register a PUT + // trabsaction in TRT if not full. + { + assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_CONFIG) and + "MEMC ERROR in CONFIG_TRT_LOCK state: bad DIR allocation"); + + if ( r_alloc_trt_fsm.read() == ALLOC_TRT_CONFIG ) + { + size_t index = 0; + bool wok = not m_trt.full(index); + + if ( not wok ) + { + r_config_fsm = CONFIG_LOOP; + } + else + { + size_t way = r_config_dir_way.read(); + size_t set = m_y[r_config_address.read()]; + + // reset dirty bit in DIR + DirectoryEntry entry; + entry.valid = true; + entry.dirty = false; + entry.tag = m_z[r_config_address.read()]; + entry.is_cnt = r_config_dir_is_cnt.read(); + entry.lock = r_config_dir_lock.read(); + entry.ptr = r_config_dir_ptr.read(); + entry.count = r_config_dir_count.read(); + entry.owner.inst = r_config_dir_copy_inst.read(); + entry.owner.srcid = r_config_dir_copy_srcid.read(); + m_cache_directory.write( set, + way, + entry ); + + r_config_trt_index = index; + r_config_fsm = CONFIG_TRT_SET; + } + +#if DEBUG_MEMC_CONFIG +if(m_debug) +std::cout << " Access TRT: " + << " wok = " << std::dec << wok + << " index = " << index << std::endl; +#endif + } + break; + } + //////////////////// + case CONFIG_TRT_SET: // read data in cache + // and post a PUT request in TRT + { + assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_CONFIG) and + "MEMC ERROR in CONFIG_TRT_SET state: bad DIR allocation"); + + assert( (r_alloc_trt_fsm.read() == ALLOC_TRT_CONFIG) and + "MEMC ERROR in CONFIG_TRT_SET state: bad TRT allocation"); + + // read data into cache + size_t way = r_config_dir_way.read(); + size_t set = m_y[r_config_address.read()]; + + sc_signal config_data[16]; + m_cache_data.read_line( way, + set, + config_data ); + + // post a PUT request in TRT + std::vector data_vector; + data_vector.clear(); + for(size_t i=0; i(m_words,0xF), + data_vector); + +#if DEBUG_MEMC_CONFIG +if(m_debug) +std::cout << " PUT request in TRT:" + << " address = " << std::hex << r_config_address.read() + << " index = " << std::dec << r_config_trt_index.read() << std::endl; +#endif + break; + } + //////////////////// + case CONFIG_PUT_REQ: // PUT request to IXR_CMD_FSM + { + if ( not r_config_to_ixr_cmd_req.read() ) + { + r_config_to_ixr_cmd_req = true; + r_config_to_ixr_cmd_index = r_config_trt_index.read(); + + // prepare next iteration + r_config_cmd_lines = r_config_cmd_lines.read() - 1; + r_config_address = r_config_address.read() + (m_words<<2); + r_config_fsm = CONFIG_LOOP; + +#if DEBUG_MEMC_CONFIG +if(m_debug) +std::cout << " PUT request to IXR_CMD_FSM" + << " / address = " << std::hex << r_config_address.read() << std::endl; +#endif + } + break; + } + ///////////////////// + case CONFIG_IVT_LOCK: // enter this state in case of INVAL command + // Keep DIR lock and Try to get IVT lock. + // Return to LOOP state if IVT full. + // Register inval in IVT, and invalidate the + // directory if IVT not full. + { + assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_CONFIG) and + "MEMC ERROR in CONFIG_IVT_LOCK state: bad DIR allocation"); + if ( r_alloc_ivt_fsm.read() == ALLOC_IVT_CONFIG ) { @@ -1589,11 +1734,12 @@ { m_cache_directory.inval( way, set ); - r_config_nlines = r_config_nlines.read() - 1; - r_config_address = r_config_address.read() + (m_words<<2); - r_config_fsm = CONFIG_LOOP; + r_config_cmd_lines = r_config_cmd_lines.read() - 1; + r_config_rsp_lines = r_config_rsp_lines.read() - 1; + r_config_address = r_config_address.read() + (m_words<<2); + r_config_fsm = CONFIG_LOOP; #if DEBUG_MEMC_CONFIG if(m_debug) -std::cout << " " +std::cout << " " << " No copies in L1 : inval DIR entry" << std::endl; #endif @@ -1626,11 +1772,11 @@ r_config_ivt_index = index; if ( broadcast ) r_config_fsm = CONFIG_BC_SEND; - else r_config_fsm = CONFIG_INV_SEND; + else r_config_fsm = CONFIG_INVAL_SEND; #if DEBUG_MEMC_CONFIG if(m_debug) -std::cout << " " +std::cout << " " << " Inval DIR entry and register inval in IVT" - << " : index = " << std::dec << index + << " / index = " << std::dec << index << " / broadcast = " << broadcast << std::endl; #endif @@ -1642,5 +1788,5 @@ #if DEBUG_MEMC_CONFIG if(m_debug) -std::cout << " " +std::cout << " " << " IVT full : release DIR & IVT locks and retry" << std::endl; #endif @@ -1656,10 +1802,14 @@ not r_config_to_cc_send_brdcast_req.read() ) { + // post bc inval request r_config_to_cc_send_multi_req = false; r_config_to_cc_send_brdcast_req = true; r_config_to_cc_send_trdid = r_config_ivt_index.read(); r_config_to_cc_send_nline = m_nline[(addr_t)(r_config_address.read())]; - r_cleanup_to_config_ack = false; - r_config_fsm = CONFIG_BC_WAIT; + + // prepare next iteration + r_config_cmd_lines = r_config_cmd_lines.read() - 1; + r_config_address = r_config_address.read() + (m_words<<2); + r_config_fsm = CONFIG_LOOP; #if DEBUG_MEMC_CONFIG @@ -1672,44 +1822,36 @@ break; } - //////////////////// - case CONFIG_BC_WAIT: // wait broadcast completion to return to LOOP - { - if ( r_cleanup_to_config_ack.read() ) - { - r_config_fsm = CONFIG_LOOP; - r_config_nlines = r_config_nlines.read() - 1; - r_config_address = r_config_address.read() + (m_words<<2); - } - -#if DEBUG_MEMC_CONFIG -if(m_debug) -std::cout << " Waiting BC completion " - << " done = " << r_cleanup_to_config_ack.read() - << std::endl; -#endif - break; - } - ///////////////////// - case CONFIG_INV_SEND: // Post a multi inval request to CC_SEND FSM + /////////////////////// + case CONFIG_INVAL_SEND: // Post a multi inval request to CC_SEND FSM { if( not r_config_to_cc_send_multi_req.read() and not r_config_to_cc_send_brdcast_req.read() ) { + // post multi inval request r_config_to_cc_send_multi_req = true; r_config_to_cc_send_brdcast_req = false; r_config_to_cc_send_trdid = r_config_ivt_index.read(); r_config_to_cc_send_nline = m_nline[(addr_t)(r_config_address.read())]; - r_multi_ack_to_config_ack = false; - + + // post data into FIFO config_to_cc_send_fifo_srcid = r_config_dir_copy_srcid.read(); config_to_cc_send_fifo_inst = r_config_dir_copy_inst.read(); config_to_cc_send_fifo_put = true; - if ( r_config_dir_count.read() == 1 ) r_config_fsm = CONFIG_INV_WAIT; - else r_config_fsm = CONFIG_HEAP_REQ; + if ( r_config_dir_count.read() == 1 ) // one copy + { + // prepare next iteration + r_config_cmd_lines = r_config_cmd_lines.read() - 1; + r_config_address = r_config_address.read() + (m_words<<2); + r_config_fsm = CONFIG_LOOP; + } + else // several copies + { + r_config_fsm = CONFIG_HEAP_REQ; + } #if DEBUG_MEMC_CONFIG if(m_debug) -std::cout << " " +std::cout << " " << " Post multi inval request to CC_SEND FSM" << " / address = " << std::hex << r_config_address.read() @@ -1726,5 +1868,5 @@ { r_config_fsm = CONFIG_HEAP_SCAN; - r_config_heap_next = r_config_dir_next_ptr.read(); + r_config_heap_next = r_config_dir_ptr.read(); } @@ -1773,5 +1915,5 @@ if ( m_heap.is_full() ) { - last_entry.next = r_config_dir_next_ptr.read(); + last_entry.next = r_config_dir_ptr.read(); m_heap.unset_full(); } @@ -1781,7 +1923,11 @@ } - m_heap.write_free_ptr( r_config_dir_next_ptr.read() ); + m_heap.write_free_ptr( r_config_dir_ptr.read() ); m_heap.write( r_config_heap_next.read(), last_entry ); - r_config_fsm = CONFIG_INV_WAIT; + + // prepare next iteration + r_config_cmd_lines = r_config_cmd_lines.read() - 1; + r_config_address = r_config_address.read() + (m_words<<2); + r_config_fsm = CONFIG_LOOP; #if DEBUG_MEMC_CONFIG @@ -1791,45 +1937,4 @@ #endif break; - } - ///////////////////// - case CONFIG_INV_WAIT: // wait inval completion to return to LOOP - { - if ( r_multi_ack_to_config_ack.read() ) - { - r_config_fsm = CONFIG_LOOP; - r_config_nlines = r_config_nlines.read() - 1; - r_config_address = r_config_address.read() + (m_words<<2); - } - -#if DEBUG_MEMC_CONFIG -if(m_debug) -std::cout << " Waiting inval completion " - << " done = " << r_multi_ack_to_config_ack.read() - << std::endl; -#endif - break; - } - - //////////////// - case CONFIG_RSP: // request TGT_RSP FSM to return response - { - if ( not r_config_to_tgt_rsp_req.read() ) - { - r_config_to_tgt_rsp_srcid = r_config_srcid.read(); - r_config_to_tgt_rsp_trdid = r_config_trdid.read(); - r_config_to_tgt_rsp_pktid = r_config_pktid.read(); - r_config_to_tgt_rsp_error = false; - r_config_to_tgt_rsp_req = true; - r_config_fsm = CONFIG_IDLE; - -#if DEBUG_MEMC_CONFIG -if(m_debug) -std::cout << " Request TGT_RSP FSM to return response:" - << " error = " << r_config_to_tgt_rsp_error.read() - << " / rsrcid = " << std::hex << r_config_srcid.read() << std::endl; -#endif - } - break; - } } // end switch r_config_fsm @@ -1858,4 +1963,6 @@ //////////////////////////////////////////////////////////////////////////////////// +//std::cout << std::endl << "read_fsm" << std::endl; + switch(r_read_fsm.read()) { @@ -1863,28 +1970,27 @@ case READ_IDLE: // waiting a read request { - if(m_cmd_read_addr_fifo.rok()) - { + if(m_cmd_read_addr_fifo.rok()) + { #if DEBUG_MEMC_READ - if(m_debug) - std::cout << " Read request" - << " : address = " << std::hex << m_cmd_read_addr_fifo.read() - << " / srcid = " << m_cmd_read_srcid_fifo.read() - << " / trdid = " << m_cmd_read_trdid_fifo.read() - << " / pktid = " << m_cmd_read_pktid_fifo.read() - << " / nwords = " << std::dec << m_cmd_read_length_fifo.read() << std::endl; -#endif - r_read_fsm = READ_DIR_REQ; - } - break; - } - +if(m_debug) +std::cout << " Read request" + << " : address = " << std::hex << m_cmd_read_addr_fifo.read() + << " / srcid = " << m_cmd_read_srcid_fifo.read() + << " / trdid = " << m_cmd_read_trdid_fifo.read() + << " / pktid = " << m_cmd_read_pktid_fifo.read() + << " / nwords = " << std::dec << m_cmd_read_length_fifo.read() << std::endl; +#endif + r_read_fsm = READ_DIR_REQ; + } + break; + } ////////////////// case READ_DIR_REQ: // Get the lock to the directory { - if(r_alloc_dir_fsm.read() == ALLOC_DIR_READ) - { - r_read_fsm = READ_DIR_LOCK; - } + if(r_alloc_dir_fsm.read() == ALLOC_DIR_READ) + { + r_read_fsm = READ_DIR_LOCK; + } #if DEBUG_MEMC_READ @@ -1892,5 +1998,5 @@ std::cout << " Requesting DIR lock " << std::endl; #endif - break; + break; } @@ -1898,13 +2004,14 @@ case READ_DIR_LOCK: // check directory for hit / miss { - if(r_alloc_dir_fsm.read() == ALLOC_DIR_READ) - { + assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_READ) and + "MEMC ERROR in READ_DIR_LOCK state: Bad DIR allocation"); + size_t way = 0; - DirectoryEntry entry = - m_cache_directory.read(m_cmd_read_addr_fifo.read(), way); + DirectoryEntry entry = m_cache_directory.read(m_cmd_read_addr_fifo.read(), way); + // access the global table ONLY when we have an LL cmd if((m_cmd_read_pktid_fifo.read() & 0x7) == TYPE_LL) { - r_read_ll_key = m_llsc_table.ll(m_cmd_read_addr_fifo.read()); + r_read_ll_key = m_llsc_table.ll(m_cmd_read_addr_fifo.read()); } r_read_is_cnt = entry.is_cnt; @@ -1915,8 +2022,4 @@ r_read_count = entry.count; r_read_copy = entry.owner.srcid; - -#if L1_MULTI_CACHE - r_read_copy_cache = entry.owner.cache_id; -#endif r_read_copy_inst = entry.owner.inst; r_read_ptr = entry.ptr; // pointer to the heap @@ -1928,17 +2031,17 @@ if(entry.valid) // hit { - // test if we need to register a new copy in the heap - if(entry.is_cnt or (entry.count == 0) or !cached_read) - { - r_read_fsm = READ_DIR_HIT; - } - else - { - r_read_fsm = READ_HEAP_REQ; - } + // test if we need to register a new copy in the heap + if(entry.is_cnt or (entry.count == 0) or !cached_read) + { + r_read_fsm = READ_DIR_HIT; + } + else + { + r_read_fsm = READ_HEAP_REQ; + } } else // miss { - r_read_fsm = READ_TRT_LOCK; + r_read_fsm = READ_TRT_LOCK; } @@ -1955,14 +2058,6 @@ } #endif - } - else - { - std::cout << "VCI_MEM_CACHE ERROR " << name() << " READ_DIR_LOCK state" - << "Bad DIR allocation" << std::endl; - exit(0); - } - break; - } - + break; + } ////////////////// case READ_DIR_HIT: // read data in cache & update the directory @@ -1973,6 +2068,7 @@ { - if(r_alloc_dir_fsm.read() == ALLOC_DIR_READ) - { + assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_READ) and + "MEMC ERROR in READ_DIR_HIT state: Bad DIR allocation"); + // check if this is an instruction read, this means pktid is either // TYPE_READ_INS_UNC 0bX010 with TSAR encoding @@ -1991,6 +2087,4 @@ m_cache_data.read_line(way, set, r_read_data); - if(m_monitor_ok) check_monitor( m_cmd_read_addr_fifo.read(), r_read_data[0], true); - // update the cache directory DirectoryEntry entry; @@ -2004,49 +2098,38 @@ if(cached_read) // Cached read => we must update the copies { - if(!is_cnt) // Not counter mode - { - entry.owner.srcid = m_cmd_read_srcid_fifo.read(); -#if L1_MULTI_CACHE - entry.owner.cache_id = m_cmd_read_pktid_fifo.read(); -#endif - entry.owner.inst = inst_read; - entry.count = r_read_count.read() + 1; - } - else // Counter mode - { - entry.owner.srcid = 0; -#if L1_MULTI_CACHE - entry.owner.cache_id = 0; -#endif - entry.owner.inst = false; - entry.count = r_read_count.read() + 1; - } + if(!is_cnt) // Not counter mode + { + entry.owner.srcid = m_cmd_read_srcid_fifo.read(); + entry.owner.inst = inst_read; + entry.count = r_read_count.read() + 1; + } + else // Counter mode + { + entry.owner.srcid = 0; + entry.owner.inst = false; + entry.count = r_read_count.read() + 1; + } } else // Uncached read { - entry.owner.srcid = r_read_copy.read(); -#if L1_MULTI_CACHE - entry.owner.cache_id = r_read_copy_cache.read(); -#endif - entry.owner.inst = r_read_copy_inst.read(); - entry.count = r_read_count.read(); + entry.owner.srcid = r_read_copy.read(); + entry.owner.inst = r_read_copy_inst.read(); + entry.count = r_read_count.read(); } #if DEBUG_MEMC_READ - if(m_debug) - std::cout << " Update directory entry:" - << " addr = " << std::hex << m_cmd_read_addr_fifo.read() - << " / set = " << std::dec << set - << " / way = " << way - << " / owner_id = " << std::hex << entry.owner.srcid - << " / owner_ins = " << std::dec << entry.owner.inst - << " / count = " << entry.count - << " / is_cnt = " << entry.is_cnt << std::endl; -#endif - +if(m_debug) +std::cout << " Update directory entry:" + << " addr = " << std::hex << m_cmd_read_addr_fifo.read() + << " / set = " << std::dec << set + << " / way = " << way + << " / owner_id = " << std::hex << entry.owner.srcid + << " / owner_ins = " << std::dec << entry.owner.inst + << " / count = " << entry.count + << " / is_cnt = " << entry.is_cnt << std::endl; +#endif m_cache_directory.write(set, way, entry); r_read_fsm = READ_RSP; - } - break; + break; } /////////////////// @@ -2080,6 +2163,4 @@ m_cache_data.read_line(way, set, r_read_data); - - if(m_monitor_ok) check_monitor( m_cmd_read_addr_fifo.read(), r_read_data[0], true); // update the cache directory @@ -2095,7 +2176,4 @@ { entry.owner.srcid = r_read_copy.read(); -#if L1_MULTI_CACHE - entry.owner.cache_id = r_read_copy_cache.read(); -#endif entry.owner.inst = r_read_copy_inst.read(); entry.ptr = m_heap.next_free_ptr(); // set pointer on the heap @@ -2104,7 +2182,4 @@ { entry.owner.srcid = 0; -#if L1_MULTI_CACHE - entry.owner.cache_id = 0; -#endif entry.owner.inst = false; entry.ptr = 0; @@ -2172,7 +2247,4 @@ HeapEntry heap_entry; heap_entry.owner.srcid = m_cmd_read_srcid_fifo.read(); -#if L1_MULTI_CACHE - heap_entry.owner.cache_id = m_cmd_read_pktid_fifo.read(); -#endif heap_entry.owner.inst = ((m_cmd_read_pktid_fifo.read() & 0x2) != 0); @@ -2238,7 +2310,4 @@ HeapEntry last_entry; last_entry.owner.srcid = 0; -#if L1_MULTI_CACHE - last_entry.owner.cache_id = 0; -#endif last_entry.owner.inst = false; @@ -2266,16 +2335,16 @@ case READ_RSP: // request the TGT_RSP FSM to return data { - if(!r_read_to_tgt_rsp_req) - { - for(size_t i=0 ; i Write in Transaction Table:" +std::cout << " Set a GET in TRT:" << " address = " << std::hex << m_cmd_read_addr_fifo.read() << " / srcid = " << std::hex << m_cmd_read_srcid_fifo.read() << std::endl; #endif - r_read_fsm = READ_TRT_REQ; - } - break; + r_read_fsm = READ_TRT_REQ; + } + break; } @@ -2355,11 +2423,10 @@ case READ_TRT_REQ: // consume the read request in FIFO and send it to IXR_CMD_FSM { - if(not r_read_to_ixr_cmd_req) - { - cmd_read_fifo_get = true; - r_read_to_ixr_cmd_req = true; - r_read_to_ixr_cmd_nline = m_nline[(addr_t)(m_cmd_read_addr_fifo.read())]; - r_read_to_ixr_cmd_trdid = r_read_trt_index.read(); - r_read_fsm = READ_IDLE; + if(not r_read_to_ixr_cmd_req) + { + cmd_read_fifo_get = true; + r_read_to_ixr_cmd_req = true; + r_read_to_ixr_cmd_index = r_read_trt_index.read(); + r_read_fsm = READ_IDLE; #if DEBUG_MEMC_READ @@ -2368,6 +2435,6 @@ << std::hex << m_cmd_read_addr_fifo.read() << std::endl; #endif - } - break; + } + break; } } // end switch read_fsm @@ -2387,7 +2454,6 @@ // If the data is cached by other processors, a coherence transaction must // be launched (sc requests always require a coherence transaction): - // It is a multicast update if the line is not in counter mode, and the processor + // It is a multicast update if the line is not in counter mode: the processor // takes the lock protecting the Update Table (UPT) to register this transaction. - // It is a broadcast invalidate if the line is in counter mode. // If the UPT is full, it releases the lock(s) and retry. Then, it sends // a multi-update request to all owners of the line (but the writer), @@ -2395,12 +2461,17 @@ // does not respond to the writing processor, as this response will be sent by // the MULTI_ACK FSM when all update responses have been received. + // It is a broadcast invalidate if the line is in counter mode: The line + // should be erased in memory cache, and written in XRAM with a PUT transaction, + // after registration in TRT. // // - In case of MISS, the WRITE FSM takes the lock protecting the transaction // table (TRT). If a read transaction to the XRAM for this line already exists, // it writes in the TRT (write buffer). Otherwise, if a TRT entry is free, - // the WRITE FSM register a new transaction in TRT, and sends a read line request + // the WRITE FSM register a new transaction in TRT, and sends a GET request // to the XRAM. If the TRT is full, it releases the lock, and waits. // Finally, the WRITE FSM returns an aknowledge response to the writing processor. ///////////////////////////////////////////////////////////////////////////////////// + +//std::cout << std::endl << "write_fsm" << std::endl; switch(r_write_fsm.read()) @@ -2409,42 +2480,44 @@ case WRITE_IDLE: // copy first word of a write burst in local buffer { - if(m_cmd_write_addr_fifo.rok()) - { - if((m_cmd_write_pktid_fifo.read() & 0x7) == TYPE_SC) - m_cpt_sc++; - else - { - m_cpt_write++; - m_cpt_write_cells++; - } - - // consume a word in the FIFO & write it in the local buffer - cmd_write_fifo_get = true; - size_t index = m_x[(addr_t)(m_cmd_write_addr_fifo.read())]; - - r_write_address = (addr_t)(m_cmd_write_addr_fifo.read()); - r_write_word_index = index; - r_write_word_count = 1; - r_write_data[index] = m_cmd_write_data_fifo.read(); - r_write_srcid = m_cmd_write_srcid_fifo.read(); - r_write_trdid = m_cmd_write_trdid_fifo.read(); - r_write_pktid = m_cmd_write_pktid_fifo.read(); - r_write_pending_sc = false; - - // initialize the be field for all words - for(size_t word=0 ; word" - << " Read the cache to complete local buffer" << std::endl; -#endif - break; - } - + break; + } /////////////////// - case WRITE_DIR_HIT: - { - // update the cache directory - // update directory with Dirty bit - DirectoryEntry entry; - entry.valid = true; - entry.dirty = true; - entry.tag = r_write_tag.read(); - entry.is_cnt = r_write_is_cnt.read(); - entry.lock = r_write_lock.read(); - entry.owner.srcid = r_write_copy.read(); -#if L1_MULTI_CACHE - entry.owner.cache_id = r_write_copy_cache.read(); -#endif - entry.owner.inst = r_write_copy_inst.read(); - entry.count = r_write_count.read(); - entry.ptr = r_write_ptr.read(); - - size_t set = m_y[(addr_t)(r_write_address.read())]; - size_t way = r_write_way.read(); - - // update directory - m_cache_directory.write(set, way, entry); - - // owner is true when the the first registered copy is the writer itself - bool owner = (((r_write_copy.read() == r_write_srcid.read()) -#if L1_MULTI_CACHE - and(r_write_copy_cache.read() ==r_write_pktid.read()) -#endif - ) and not r_write_copy_inst.read()); - - // no_update is true when there is no need for coherence transaction - // (tests for sc requests) - bool no_update = ( (r_write_count.read() == 0) or + case WRITE_DIR_HIT: // update the cache directory with Dirty bit + // and update data cache + { + assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE) and + "MEMC ERROR in ALLOC_DIR_HIT state: Bad DIR allocation"); + + DirectoryEntry entry; + entry.valid = true; + entry.dirty = true; + entry.tag = r_write_tag.read(); + entry.is_cnt = r_write_is_cnt.read(); + entry.lock = r_write_lock.read(); + entry.owner.srcid = r_write_copy.read(); + entry.owner.inst = r_write_copy_inst.read(); + entry.count = r_write_count.read(); + entry.ptr = r_write_ptr.read(); + + size_t set = m_y[(addr_t)(r_write_address.read())]; + size_t way = r_write_way.read(); + + // update directory + m_cache_directory.write(set, way, entry); + + // owner is true when the the first registered copy is the writer itself + bool owner = ( (r_write_copy.read() == r_write_srcid.read()) + and not r_write_copy_inst.read() ); + + // no_update is true when there is no need for coherence transaction + bool no_update = ( (r_write_count.read() == 0) or (owner and (r_write_count.read() ==1) and (r_write_pktid.read() != TYPE_SC))); - // write data in the cache if no coherence transaction - if(no_update) - { - for(size_t word=0 ; word Write into cache / No coherence transaction" - << std::endl; - } - else - { - std::cout << " Coherence update required:" - << " is_cnt = " << r_write_is_cnt.read() - << " nb_copies = " << std::dec << r_write_count.read() << std::endl; - if(owner) std::cout << " ... but the first copy is the writer" << std::endl; - } +if(no_update) +{ +std::cout << " Write into cache / No coherence transaction" << std::endl; } -#endif - break; +else +{ +std::cout << " Coherence update required:" + << " is_cnt = " << r_write_is_cnt.read() + << " nb_copies = " << std::dec << r_write_count.read() << std::endl; +if(owner) std::cout << " ... but the first copy is the writer" << std::endl; +} +} +#endif + break; } //////////////////// case WRITE_UPT_LOCK: // Try to register the update request in UPT { - if(r_alloc_upt_fsm.read() == ALLOC_UPT_WRITE) - { - bool wok = false; - size_t index = 0; - size_t srcid = r_write_srcid.read(); - size_t trdid = r_write_trdid.read(); - size_t pktid = r_write_pktid.read(); - addr_t nline = m_nline[(addr_t)(r_write_address.read())]; - size_t nb_copies = r_write_count.read(); - size_t set = m_y[(addr_t)(r_write_address.read())]; - size_t way = r_write_way.read(); - - wok = m_upt.set(true, // it's an update transaction - false, // it's not a broadcast - true, // response required - false, // no acknowledge required - srcid, - trdid, - pktid, - nline, - nb_copies, - index); - if(wok) // write data in cache - { - for(size_t word=0 ; word Register the multicast update in UPT / " - << " nb_copies = " << r_write_count.read() << std::endl; - } +std::cout << " Register the multicast update in UPT / " + << " nb_copies = " << r_write_count.read() << std::endl; } #endif - r_write_upt_index = index; - // releases the lock protecting UPT and the DIR if no entry... - if(wok) r_write_fsm = WRITE_UPT_HEAP_LOCK; - else r_write_fsm = WRITE_WAIT; - } - break; + r_write_upt_index = index; + // releases the lock protecting UPT and the DIR if no entry... + if(wok) r_write_fsm = WRITE_UPT_HEAP_LOCK; + else r_write_fsm = WRITE_WAIT; + } + break; } @@ -2847,9 +2835,6 @@ for(size_t i=min ; i" + << " Read the cache to complete local buffer" << std::endl; +#endif + break; + } + /////////////////////// + case WRITE_BC_TRT_LOCK: // get TRT lock to check TRT not full + { + assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE) and + "MEMC ERROR in WRITE_BC_TRT_LOCK state: Bad DIR allocation"); + + if(r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE) + { + size_t wok_index = 0; + bool wok = not m_trt.full(wok_index); + if( wok ) + { + r_write_trt_index = wok_index; + r_write_fsm = WRITE_BC_IVT_LOCK; + } + else // wait an empty slot in TRT + { + r_write_fsm = WRITE_WAIT; + } #if DEBUG_MEMC_WRITE @@ -3224,32 +3232,36 @@ << " : wok = " << wok << " / index = " << wok_index << std::endl; #endif - } - break; - } - + } + break; + } ////////////////////// - case WRITE_BC_IVT_LOCK: // register BC transaction in IVT - { - if(r_alloc_ivt_fsm.read() == ALLOC_IVT_WRITE) - { - bool wok = false; - size_t index = 0; - size_t srcid = r_write_srcid.read(); - size_t trdid = r_write_trdid.read(); - size_t pktid = r_write_pktid.read(); - addr_t nline = m_nline[(addr_t)(r_write_address.read())]; - size_t nb_copies = r_write_count.read(); - - wok = m_ivt.set(false, // it's an inval transaction - true, // it's a broadcast - true, // response required - false, // no acknowledge required - srcid, - trdid, - pktid, - nline, - nb_copies, - index); - + case WRITE_BC_IVT_LOCK: // get IVT lock and register BC transaction in IVT + { + assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE) and + "MEMC ERROR in WRITE_BC_IVT_LOCK state: Bad DIR allocation"); + + assert( (r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE) and + "MEMC ERROR in WRITE_BC_IVT_LOCK state: Bad TRT allocation"); + + if(r_alloc_ivt_fsm.read() == ALLOC_IVT_WRITE) + { + bool wok = false; + size_t index = 0; + size_t srcid = r_write_srcid.read(); + size_t trdid = r_write_trdid.read(); + size_t pktid = r_write_pktid.read(); + addr_t nline = m_nline[(addr_t)(r_write_address.read())]; + size_t nb_copies = r_write_count.read(); + + wok = m_ivt.set(false, // it's an inval transaction + true, // it's a broadcast + true, // response required + false, // no acknowledge required + srcid, + trdid, + pktid, + nline, + nb_copies, + index); #if DEBUG_MEMC_WRITE if( m_debug and wok ) @@ -3257,65 +3269,63 @@ << " / nb_copies = " << r_write_count.read() << std::endl; #endif - r_write_upt_index = index; - - if(wok) r_write_fsm = WRITE_BC_DIR_INVAL; - else r_write_fsm = WRITE_WAIT; - } - break; - } - + r_write_upt_index = index; + + if( wok ) r_write_fsm = WRITE_BC_DIR_INVAL; + else r_write_fsm = WRITE_WAIT; + } + break; + } //////////////////////// - case WRITE_BC_DIR_INVAL: - { - // Register a put transaction to XRAM in TRT - // and invalidate the line in directory - if((r_alloc_trt_fsm.read() != ALLOC_TRT_WRITE) or - (r_alloc_ivt_fsm.read() != ALLOC_IVT_WRITE) or - (r_alloc_dir_fsm.read() != ALLOC_DIR_WRITE)) - { - std::cout << "VCI_MEM_CACHE ERROR " << name() << " WRITE_BC_DIR_INVAL state" << std::endl; - std::cout << "bad TRT, DIR, or IVT allocation" << std::endl; - exit(0); - } - - // register a write request to XRAM in TRT - m_trt.set(r_write_trt_index.read(), - false, // write request to XRAM - m_nline[(addr_t)(r_write_address.read())], - 0, - 0, - 0, - false, // not a processor read - 0, // not a single word - 0, // word index - std::vector (m_words,0), - std::vector (m_words,0)); - - // invalidate directory entry - DirectoryEntry entry; - entry.valid = false; - entry.dirty = false; - entry.tag = 0; - entry.is_cnt = false; - entry.lock = false; - entry.owner.srcid = 0; -#if L1_MULTI_CACHE - entry.owner.cache_id= 0; -#endif - entry.owner.inst = false; - entry.ptr = 0; - entry.count = 0; - size_t set = m_y[(addr_t)(r_write_address.read())]; - size_t way = r_write_way.read(); - - m_cache_directory.write(set, way, entry); + case WRITE_BC_DIR_INVAL: // Register a put transaction in TRT + // and invalidate the line in directory + { + assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE) and + "MEMC ERROR in WRITE_BC_DIR_INVAL state: Bad DIR allocation"); + + assert( (r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE) and + "MEMC ERROR in WRITE_BC_DIR_INVAL state: Bad TRT allocation"); + + assert( (r_alloc_ivt_fsm.read() == ALLOC_IVT_WRITE) and + "MEMC ERROR in WRITE_BC_DIR_INVAL state: Bad IVT allocation"); + + // register PUT request in TRT + std::vector data_vector; + data_vector.clear(); + for(size_t i=0; i (m_words,0), + data_vector ); + + // invalidate directory entry + DirectoryEntry entry; + entry.valid = false; + entry.dirty = false; + entry.tag = 0; + entry.is_cnt = false; + entry.lock = false; + entry.owner.srcid = 0; + entry.owner.inst = false; + entry.ptr = 0; + entry.count = 0; + size_t set = m_y[(addr_t)(r_write_address.read())]; + size_t way = r_write_way.read(); + + m_cache_directory.write(set, way, entry); #if DEBUG_MEMC_WRITE if(m_debug) -std::cout << " Invalidate the directory entry: @ = " - << r_write_address.read() << " / register the put transaction in TRT:" << std::endl; -#endif - r_write_fsm = WRITE_BC_CC_SEND; - break; +std::cout << " Inval DIR and register in TRT:" + << " address = " << r_write_address.read() << std::endl; +#endif + r_write_fsm = WRITE_BC_CC_SEND; + break; } @@ -3323,19 +3333,19 @@ case WRITE_BC_CC_SEND: // Post a coherence broadcast request to CC_SEND FSM { - if(!r_write_to_cc_send_multi_req.read() and !r_write_to_cc_send_brdcast_req.read()) - { - r_write_to_cc_send_multi_req = false; - r_write_to_cc_send_brdcast_req = true; - r_write_to_cc_send_trdid = r_write_upt_index.read(); - r_write_to_cc_send_nline = m_nline[(addr_t)(r_write_address.read())]; - r_write_to_cc_send_index = 0; - r_write_to_cc_send_count = 0; - - for(size_t i=0; i Post a broadcast request to CC_SEND FSM" << std::endl; #endif - } - break; + } + break; } /////////////////////// - case WRITE_BC_XRAM_REQ: // Post a put request to IXR_CMD FSM - { - if(!r_write_to_ixr_cmd_req) - { - r_write_to_ixr_cmd_req = true; - r_write_to_ixr_cmd_write = true; - r_write_to_ixr_cmd_nline = m_nline[(addr_t)(r_write_address.read())]; - r_write_to_ixr_cmd_trdid = r_write_trt_index.read(); - - for(size_t i=0; i Post a put request to IXR_CMD FSM" << std::endl; #endif - } - break; + } + break; } } // end switch r_write_fsm @@ -3376,27 +3382,33 @@ /////////////////////////////////////////////////////////////////////// // The IXR_CMD fsm controls the command packets to the XRAM : - // It handles requests from the READ, WRITE, CAS, XRAM_RSP FSMs - // with a round-robin priority. + // It handles requests from 5 FSMs with a round-robin priority: + // READ > WRITE > CAS > XRAM_RSP > CONFIG // - // - It sends a single flit VCI read request to the XRAM in case of MISS - // posted by the READ, WRITE or CAS FSMs : the TRDID field contains - // the Transaction Tab index. - // The VCI response is a multi-flit packet : the N cells contain - // the N data words. + // - It sends a single flit VCI read to the XRAM in case of + // GET request posted by the READ, WRITE or CAS FSMs. + // - It sends a multi-flit VCI write in case of PUT request posted by + // the XRAM_RSP, WRITE, CAS, or CONFIG FSMs. // - // - It sends a multi-flit VCI write when the XRAM_RSP FSM, WRITE FSM - // or CAS FSM request to save a dirty line to the XRAM. - // The VCI response is a single flit packet. + // For each client, there is three steps: + // - IXR_CMD_*_IDLE : round-robin allocation to a client + // - IXR_CMD_*_TRT : access to TRT for address and data + // - IXR_CMD_*_SEND : send the PUT or GET VCI command + // + // The address and data to be written (for a PUT) are stored in TRT. + // The trdid field contains always the TRT entry index. //////////////////////////////////////////////////////////////////////// + +//std::cout << std::endl << "ixr_cmd_fsm" << std::endl; switch(r_ixr_cmd_fsm.read()) { - //////////////////////// + /////////////////////// case IXR_CMD_READ_IDLE: { - if (r_write_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_WRITE; - else if(r_cas_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_CAS; - else if(r_xram_rsp_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_XRAM; - else if(r_read_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_READ; + if (r_write_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_WRITE_TRT; + else if(r_cas_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_CAS_TRT; + else if(r_xram_rsp_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_XRAM_TRT; + else if(r_config_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_CONFIG_TRT; + else if(r_read_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_READ_TRT; break; } @@ -3404,154 +3416,289 @@ case IXR_CMD_WRITE_IDLE: { - if (r_cas_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_CAS; - else if(r_xram_rsp_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_XRAM; - else if(r_read_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_READ; - else if(r_write_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_WRITE; + if (r_cas_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_CAS_TRT; + else if(r_xram_rsp_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_XRAM_TRT; + else if(r_config_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_CONFIG_TRT; + else if(r_read_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_READ_TRT; + else if(r_write_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_WRITE_TRT; break; } + ////////////////////// + case IXR_CMD_CAS_IDLE: + { + if (r_xram_rsp_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_XRAM_TRT; + else if(r_config_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_CONFIG_TRT; + else if(r_read_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_READ_TRT; + else if(r_write_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_WRITE_TRT; + else if(r_cas_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_CAS_TRT; + break; + } + /////////////////////// + case IXR_CMD_XRAM_IDLE: + { + if (r_config_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_CONFIG_TRT; + else if(r_read_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_READ_TRT; + else if(r_write_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_WRITE_TRT; + else if(r_cas_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_CAS_TRT; + else if(r_xram_rsp_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_XRAM_TRT; + break; + } + ///////////////////////// + case IXR_CMD_CONFIG_IDLE: + { + if (r_read_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_READ_TRT; + else if(r_write_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_WRITE_TRT; + else if(r_cas_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_CAS_TRT; + else if(r_xram_rsp_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_XRAM_TRT; + else if(r_config_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_CONFIG_TRT; + break; + } + + ////////////////////// + case IXR_CMD_READ_TRT: // access TRT for a GET + { + if ( r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_CMD ) + { + TransactionTabEntry entry = m_trt.read( r_read_to_ixr_cmd_index.read() ); + r_ixr_cmd_address = entry.nline * (m_words<<2); + r_ixr_cmd_trdid = r_read_to_ixr_cmd_index.read(); + r_ixr_cmd_get = true; + r_ixr_cmd_word = 0; + r_ixr_cmd_fsm = IXR_CMD_READ_SEND; + for( size_t i=0 ; i TRT access" + << " index = " << std::dec << r_read_to_ixr_cmd_index.read() + << " / address = " << std::hex << (entry.nline*(m_words<<2)) << std::endl; +#endif + } + break; + } + /////////////////////// + case IXR_CMD_WRITE_TRT: // access TRT for a PUT or a GET + { + if ( r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_CMD ) + { + TransactionTabEntry entry = m_trt.read( r_write_to_ixr_cmd_index.read() ); + r_ixr_cmd_address = entry.nline * (m_words<<2); + r_ixr_cmd_trdid = r_write_to_ixr_cmd_index.read(); + r_ixr_cmd_get = entry.xram_read; + r_ixr_cmd_word = 0; + r_ixr_cmd_fsm = IXR_CMD_WRITE_SEND; + for( size_t i=0 ; i TRT access" + << " index = " << std::dec << r_write_to_ixr_cmd_index.read() + << " / address = " << std::hex << (entry.nline*(m_words<<2)) << std::endl; +#endif + } + break; + } + ///////////////////// + case IXR_CMD_CAS_TRT: // access TRT for a PUT or a GET + { + if ( r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_CMD ) + { + TransactionTabEntry entry = m_trt.read( r_cas_to_ixr_cmd_index.read() ); + r_ixr_cmd_address = entry.nline * (m_words<<2); + r_ixr_cmd_trdid = r_cas_to_ixr_cmd_index.read(); + r_ixr_cmd_get = entry.xram_read; + r_ixr_cmd_word = 0; + r_ixr_cmd_fsm = IXR_CMD_CAS_SEND; + for( size_t i=0 ; i TRT access" + << " index = " << std::dec << r_cas_to_ixr_cmd_index.read() + << " / address = " << std::hex << (entry.nline*(m_words<<2)) << std::endl; +#endif + } + break; + } + ////////////////////// + case IXR_CMD_XRAM_TRT: // access TRT for a PUT + { + if ( r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_CMD ) + { + TransactionTabEntry entry = m_trt.read( r_xram_rsp_to_ixr_cmd_index.read() ); + r_ixr_cmd_address = entry.nline * (m_words<<2); + r_ixr_cmd_trdid = r_xram_rsp_to_ixr_cmd_index.read(); + r_ixr_cmd_get = false; + r_ixr_cmd_word = 0; + r_ixr_cmd_fsm = IXR_CMD_XRAM_SEND; + for( size_t i=0 ; i TRT access" + << " index = " << std::dec << r_xram_rsp_to_ixr_cmd_index.read() + << " / address = " << std::hex << (entry.nline*(m_words<<2)) << std::endl; +#endif + } + break; + } //////////////////////// - case IXR_CMD_CAS_IDLE: - { - if (r_xram_rsp_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_XRAM; - else if(r_read_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_READ; - else if(r_write_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_WRITE; - else if(r_cas_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_CAS; - break; + case IXR_CMD_CONFIG_TRT: // access TRT for a PUT + { + if ( r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_CMD ) + { + TransactionTabEntry entry = m_trt.read( r_config_to_ixr_cmd_index.read() ); + r_ixr_cmd_address = entry.nline * (m_words<<2); + r_ixr_cmd_trdid = r_config_to_ixr_cmd_index.read(); + r_ixr_cmd_get = false; + r_ixr_cmd_word = 0; + r_ixr_cmd_fsm = IXR_CMD_CONFIG_SEND; + for( size_t i=0 ; i TRT access" + << " index = " << std::dec << r_config_to_ixr_cmd_index.read() + << " / address = " << std::hex << (entry.nline*(m_words<<2)) << std::endl; +#endif + } + break; + } + + /////////////////////// + case IXR_CMD_READ_SEND: // send a get from READ FSM + { + if(p_vci_ixr.cmdack) + { + r_ixr_cmd_fsm = IXR_CMD_READ_IDLE; + r_read_to_ixr_cmd_req = false; + +#if DEBUG_MEMC_IXR_CMD +if(m_debug) +std::cout << " GET request:" << std::hex + << " address = " << r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2) << std::endl; +#endif + } + break; } //////////////////////// - case IXR_CMD_XRAM_IDLE: - { - if (r_read_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_READ; - else if(r_write_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_WRITE; - else if(r_cas_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_CAS; - else if(r_xram_rsp_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_XRAM; - break; - } - ////////////////// // send a get from READ FSM - case IXR_CMD_READ: - { - if(p_vci_ixr.cmdack) - { - r_ixr_cmd_fsm = IXR_CMD_READ_IDLE; - r_read_to_ixr_cmd_req = false; + case IXR_CMD_WRITE_SEND: // send a put or get from WRITE FSM + { + if(p_vci_ixr.cmdack) + { + if(r_write_to_ixr_cmd_put.read()) // PUT + { + if(r_ixr_cmd_word.read() == (m_words - 2)) + { + r_ixr_cmd_fsm = IXR_CMD_WRITE_IDLE; + r_write_to_ixr_cmd_req = false; + } + else + { + r_ixr_cmd_word = r_ixr_cmd_word.read() + 2; + } #if DEBUG_MEMC_IXR_CMD if(m_debug) -std::cout << " " - << " Send a get request to xram / address = " << std::hex - << (addr_t)(r_read_to_ixr_cmd_nline.read()*m_words*4) << std::endl; -#endif - } - break; - } - /////////////////// - case IXR_CMD_WRITE: // send a put or get from WRITE FSM - { - if(p_vci_ixr.cmdack) - { - if(r_write_to_ixr_cmd_write.read()) // PUT - { - if(r_ixr_cmd_cpt.read() == (m_words - 2)) - { - r_ixr_cmd_cpt = 0; - r_ixr_cmd_fsm = IXR_CMD_WRITE_IDLE; - r_write_to_ixr_cmd_req = false; - } - else - { - r_ixr_cmd_cpt = r_ixr_cmd_cpt + 2; - } +std::cout << " PUT request:" << std::hex + << " address = " << r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2) << std::endl; +#endif + } + else // GET + { + r_ixr_cmd_fsm = IXR_CMD_WRITE_IDLE; + r_write_to_ixr_cmd_req = false; #if DEBUG_MEMC_IXR_CMD if(m_debug) -std::cout << " " - << " Send a put request to xram / address = " << std::hex - << (addr_t)((r_write_to_ixr_cmd_nline.read() * m_words + - r_ixr_cmd_cpt.read()) * 4 ) << std::endl; -#endif - } - else // GET - { - r_ixr_cmd_fsm = IXR_CMD_WRITE_IDLE; - r_write_to_ixr_cmd_req = false; +std::cout << " GET request:" << std::hex + << " address = " << r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2) << std::endl; +#endif + } + } + break; + } + ////////////////////// + case IXR_CMD_CAS_SEND: // send a put or get command from CAS FSM + { + if(p_vci_ixr.cmdack) + { + if(r_cas_to_ixr_cmd_put.read()) // PUT + { + if(r_ixr_cmd_word.read() == (m_words - 2)) + { + r_ixr_cmd_fsm = IXR_CMD_CAS_IDLE; + r_cas_to_ixr_cmd_req = false; + } + else + { + r_ixr_cmd_word = r_ixr_cmd_word.read() + 2; + } #if DEBUG_MEMC_IXR_CMD if(m_debug) -std::cout << " " - << " Send a get request to xram / address = " << std::hex - << (addr_t)(r_write_to_ixr_cmd_nline.read()*m_words*4) << std::endl; -#endif - } - } - break; - } - ///////////////// - case IXR_CMD_CAS: // send a put or get command from CAS FSM - { - if(p_vci_ixr.cmdack) - { - if(r_cas_to_ixr_cmd_write.read()) // PUT - { - if(r_ixr_cmd_cpt.read() == (m_words - 2)) - { - r_ixr_cmd_cpt = 0; - r_ixr_cmd_fsm = IXR_CMD_CAS_IDLE; - r_cas_to_ixr_cmd_req = false; - } - else - { - r_ixr_cmd_cpt = r_ixr_cmd_cpt + 2; - } +std::cout << " PUT request:" << std::hex + << " address = " << r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2) << std::endl; +#endif + } + else // GET + { + r_ixr_cmd_fsm = IXR_CMD_CAS_IDLE; + r_cas_to_ixr_cmd_req = false; #if DEBUG_MEMC_IXR_CMD if(m_debug) -std::cout << " " - << " Send a put request to xram / address = " << std::hex - << (addr_t)( (r_cas_to_ixr_cmd_nline.read() * m_words + - r_ixr_cmd_cpt.read()) * 4 ) << std::endl; -#endif - } - else // GET - { - r_ixr_cmd_fsm = IXR_CMD_CAS_IDLE; - r_cas_to_ixr_cmd_req = false; +std::cout << " GET request:" << std::hex + << " address = " << r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2) << std::endl; +#endif + } + } + break; + } + /////////////////////// + case IXR_CMD_XRAM_SEND: // send a put from XRAM_RSP FSM + { + if(p_vci_ixr.cmdack) + { + if(r_ixr_cmd_word.read() == (m_words - 2)) + { + r_ixr_cmd_fsm = IXR_CMD_XRAM_IDLE; + r_xram_rsp_to_ixr_cmd_req = false; + } + else + { + r_ixr_cmd_word = r_ixr_cmd_word.read() + 2; + } #if DEBUG_MEMC_IXR_CMD if(m_debug) -std::cout << " " - << " Send a get request to xram / address = " << std::hex - << (addr_t)(r_cas_to_ixr_cmd_nline.read()*m_words*4) << std::endl; -#endif - } - } - break; - } - ////////////////// - case IXR_CMD_XRAM: // send a put from XRAM_RSP FSM - { - if(p_vci_ixr.cmdack) - { - if(r_ixr_cmd_cpt.read() == (m_words - 2)) - { - r_ixr_cmd_cpt = 0; - r_ixr_cmd_fsm = IXR_CMD_XRAM_IDLE; - r_xram_rsp_to_ixr_cmd_req = false; - } - else - { - r_ixr_cmd_cpt = r_ixr_cmd_cpt + 2; - } +std::cout << " PUT request:" << std::hex + << " address = " << r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2) << std::endl; +#endif + } + break; + } + ///////////////////////// + case IXR_CMD_CONFIG_SEND: // send a put from CONFIG FSM + { + if(p_vci_ixr.cmdack) + { + if(r_ixr_cmd_word.read() == (m_words - 2)) + { + r_ixr_cmd_fsm = IXR_CMD_CONFIG_IDLE; + r_config_to_ixr_cmd_req = false; + } + else + { + r_ixr_cmd_word = r_ixr_cmd_word.read() + 2; + } #if DEBUG_MEMC_IXR_CMD if(m_debug) -std::cout << " " - << " Send a put request to xram / address = " << std::hex - << (addr_t)( (r_xram_rsp_to_ixr_cmd_nline.read() * m_words + - r_ixr_cmd_cpt.read()) * 4 ) << std::endl; -#endif - } - break; - } - +std::cout << " PUT request:" << std::hex + << " address = " << r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2) << std::endl; +#endif + } + break; + } } // end switch r_ixr_cmd_fsm @@ -3560,31 +3707,39 @@ //////////////////////////////////////////////////////////////////////////// // The IXR_RSP FSM receives the response packets from the XRAM, - // for both put transaction, and get transaction. + // for both PUT transaction, and GET transaction. // - // - A response to a put request is a single-cell VCI packet. - // The Transaction Tab index is contained in the RTRDID field. + // - A response to a PUT request is a single-cell VCI packet. + // The TRT index is contained in the RTRDID field. // The FSM takes the lock protecting the TRT, and the corresponding - // entry is erased. + // entry is erased. If an acknowledge was required (in case of software SYNC) + // the r_config_rsp_lines counter is decremented. // - // - A response to a get request is a multi-cell VCI packet. - // The Transaction Tab index is contained in the RTRDID field. + // - A response to a GET request is a multi-cell VCI packet. + // The TRT index is contained in the RTRDID field. // The N cells contain the N words of the cache line in the RDATA field. // The FSM takes the lock protecting the TRT to store the line in the TRT // (taking into account the write requests already stored in the TRT). - // When the line is completely written, the corresponding rok signal is set. + // When the line is completely written, the r_ixr_rsp_to_xram_rsp_rok[index] + // signal is set to inform the XRAM_RSP FSM. /////////////////////////////////////////////////////////////////////////////// + +//std::cout << std::endl << "ixr_rsp_fsm" << std::endl; switch(r_ixr_rsp_fsm.read()) { - ////////////////// - case IXR_RSP_IDLE: // test transaction type: PUT/GET - { - if(p_vci_ixr.rspval.read()) - { - r_ixr_rsp_cpt = 0; - r_ixr_rsp_trt_index = p_vci_ixr.rtrdid.read(); - if(p_vci_ixr.reop.read() and !(p_vci_ixr.rerror.read() &0x1)) // PUT transaction - { - r_ixr_rsp_fsm = IXR_RSP_ACK; + ////////////////// + case IXR_RSP_IDLE: // test transaction type: PUT/GET + { + if(p_vci_ixr.rspval.read()) + { + r_ixr_rsp_cpt = 0; + r_ixr_rsp_trt_index = p_vci_ixr.rtrdid.read(); + + assert( ((p_vci_ixr.rerror.read() & 0x1) == 0) and + "MEMC ERROR in IXR_RSP state: XRAM response error !"); + + if(p_vci_ixr.reop.read()) // PUT + { + r_ixr_rsp_fsm = IXR_RSP_TRT_ERASE; #if DEBUG_MEMC_IXR_RSP @@ -3593,8 +3748,8 @@ << " IXR_RSP_IDLE> Response from XRAM to a put transaction" << std::endl; #endif - } - else // GET transaction - { - r_ixr_rsp_fsm = IXR_RSP_TRT_READ; + } + else // GET + { + r_ixr_rsp_fsm = IXR_RSP_TRT_READ; #if DEBUG_MEMC_IXR_RSP @@ -3603,26 +3758,18 @@ << " IXR_RSP_IDLE> Response from XRAM to a get transaction" << std::endl; #endif - } - } - break; - } - ///////////////// - case IXR_RSP_ACK: // Aknowledge the VCI response for a PUT - { - if(p_vci_ixr.rspval.read()) r_ixr_rsp_fsm = IXR_RSP_TRT_ERASE; - -#if DEBUG_MEMC_IXR_RSP -if(m_debug) -std::cout << " " << std::endl; -#endif - break; - } - //////////////////////// - case IXR_RSP_TRT_ERASE: // erase the entry in the TRT - { - if(r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP) - { - m_trt.erase(r_ixr_rsp_trt_index.read()); - r_ixr_rsp_fsm = IXR_RSP_IDLE; + } + } + break; + } + //////////////////////// + case IXR_RSP_TRT_ERASE: // erase the entry in the TRT + // decrease the line counter if config request + { + if(r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP) + { + size_t index = r_ixr_rsp_trt_index.read(); + if (m_trt.is_config(index) ) r_config_rsp_lines = r_config_rsp_lines.read() - 1; + m_trt.erase(index); + r_ixr_rsp_fsm = IXR_RSP_IDLE; #if DEBUG_MEMC_IXR_RSP @@ -3631,43 +3778,43 @@ << r_ixr_rsp_trt_index.read() << std::endl; #endif - } - break; - } - ////////////////////// - case IXR_RSP_TRT_READ: // write a 64 bits data in the TRT - { - if((r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP) and p_vci_ixr.rspval) - { - size_t index = r_ixr_rsp_trt_index.read(); - bool eop = p_vci_ixr.reop.read(); - wide_data_t data = p_vci_ixr.rdata.read(); - bool error = ((p_vci_ixr.rerror.read() & 0x1) == 1); - - assert(((eop == (r_ixr_rsp_cpt.read() == (m_words-2))) or p_vci_ixr.rerror.read()) - and "Error in VCI_MEM_CACHE : invalid length for a response from XRAM"); - - m_trt.write_rsp( index, - r_ixr_rsp_cpt.read(), - data, - error); - - r_ixr_rsp_cpt = r_ixr_rsp_cpt.read() + 2; - - if(eop) - { - r_ixr_rsp_to_xram_rsp_rok[r_ixr_rsp_trt_index.read()]=true; - r_ixr_rsp_fsm = IXR_RSP_IDLE; - } + } + break; + } + ////////////////////// + case IXR_RSP_TRT_READ: // write a 64 bits data word in TRT + { + if((r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP) and p_vci_ixr.rspval) + { + size_t index = r_ixr_rsp_trt_index.read(); + size_t word = r_ixr_rsp_cpt.read(); + bool eop = p_vci_ixr.reop.read(); + wide_data_t data = p_vci_ixr.rdata.read(); + bool error = ((p_vci_ixr.rerror.read() & 0x1) == 1); + + assert(((eop == (word == (m_words-2))) or error) and + "MEMC ERROR in IXR_RSP_TRT_READ state : invalid response from XRAM"); + + m_trt.write_rsp( index, + word, + data ); + + r_ixr_rsp_cpt = word + 2; + + if( eop ) + { + r_ixr_rsp_to_xram_rsp_rok[r_ixr_rsp_trt_index.read()] = true; + r_ixr_rsp_fsm = IXR_RSP_IDLE; + } #if DEBUG_MEMC_IXR_RSP if(m_debug) -std::cout << " Writing a word in TRT : " +std::cout << " Writing 2 words in TRT : " << " index = " << std::dec << index - << " / word = " << r_ixr_rsp_cpt.read() + << " / word = " << word << " / data = " << std::hex << data << std::endl; #endif - } - break; - } + } + break; + } } // end swich r_ixr_rsp_fsm @@ -3675,15 +3822,15 @@ // XRAM_RSP FSM //////////////////////////////////////////////////////////////////////////// - // The XRAM_RSP FSM handles the incoming cache lines from the XRAM. + // The XRAM_RSP FSM handles the incoming cache lines after an XRAM GET. // The cache line has been written in the TRT by the IXR_CMD_FSM. // As the IXR_RSP FSM and the XRAM_RSP FSM are running in parallel, - // there is as many flip-flops r_ixr_rsp_to_xram_rsp_rok[i] - // as the number of entries in the TRT, that are handled with - // a round-robin priority... + // there is as many flip-flops r_ixr_rsp_to_xram_rsp_rok[i] as the number + // of entries in the TRT, that are handled with a round-robin priority... // - // When a response is available, the corresponding TRT entry - // is copied in a local buffer to be written in the cache. - // The FSM takes the lock protecting the TRT, and the lock protecting the DIR. - // It selects a cache slot and writes the line in the cache. + // The FSM takes the lock protecting TRT, and the lock protecting DIR. + // The selected TRT entry is copied in the local buffer r_xram_rsp_trt_buf. + // It selects a cache slot and save the victim line in another local buffer + // r_xram_rsp_victim_***. + // It writes the line extracted from TRT in the cache. // If it was a read MISS, the XRAM_RSP FSM send a request to the TGT_RSP // FSM to return the cache line to the registered processor. @@ -3695,4 +3842,6 @@ /////////////////////////////////////////////////////////////////////////////// +//std::cout << std::endl << "xram_rsp_fsm" << std::endl; + switch(r_xram_rsp_fsm.read()) { @@ -3700,14 +3849,14 @@ case XRAM_RSP_IDLE: // scan the XRAM responses / select a TRT index (round robin) { - size_t ptr = r_xram_rsp_trt_index.read(); - size_t lines = m_trt_lines; - for(size_t i=0 ; i" - << " Select a slot: " + << " Select a victim slot: " << " way = " << std::dec << way << " / set = " << set << " / inval_required = " << inval << std::endl; #endif - } - else - { - std::cout << "VCI_MEM_CACHE ERROR " << name() << " XRAM_RSP_TRT_COPY" - << " bad TRT or DIR allocation" << std::endl; - exit(0); - } - break; - } - ///////////////////////// - case XRAM_RSP_INVAL_LOCK: // Take the IVT lock to check a possible pending inval - { - if(r_alloc_ivt_fsm == ALLOC_IVT_XRAM_RSP) - { - size_t index = 0; - if(m_ivt.search_inval(r_xram_rsp_trt_buf.nline, index)) // pending inval - { - r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT; + break; + } + /////////////////////// + case XRAM_RSP_IVT_LOCK: // Keep DIR and TRT locks and take the IVT lock + // to check a possible pending inval + { + assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP) and + "MEMC ERROR in XRAM_RSP_IVT_LOCK state: Bad DIR allocation"); + + assert( (r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP) and + "MEMC ERROR in XRAM_RSP_IVT_LOCK state: Bad TRT allocation"); + + if(r_alloc_ivt_fsm == ALLOC_IVT_XRAM_RSP) + { + size_t index = 0; + if(m_ivt.search_inval(r_xram_rsp_trt_buf.nline, index)) // pending inval + { + r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT; #if DEBUG_MEMC_XRAM_RSP if(m_debug) -std::cout << " " +std::cout << " " << " Get acces to IVT, but line invalidation registered" - << " / nline = " << std::hex << r_xram_rsp_trt_buf.nline + << " / address = " << std::hex << r_xram_rsp_trt_buf.nline*m_words*4 << " / index = " << std::dec << index << std::endl; #endif - } - else if(m_ivt.is_full() and r_xram_rsp_victim_inval.read()) // IVT full - { - r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT; + } + else if(m_ivt.is_full() and r_xram_rsp_victim_inval.read()) // IVT full + { + r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT; #if DEBUG_MEMC_XRAM_RSP if(m_debug) -std::cout << " " +std::cout << " " << " Get acces to IVT, but inval required and IVT full" << std::endl; #endif - } - else - { - r_xram_rsp_fsm = XRAM_RSP_DIR_UPDT; + } + else + { + r_xram_rsp_fsm = XRAM_RSP_DIR_UPDT; #if DEBUG_MEMC_XRAM_RSP if(m_debug) -std::cout << " " - << " Get acces to IVT" << std::endl; -#endif - } - } - break; +std::cout << " " + << " Get acces to IVT / no pending inval request" << std::endl; +#endif + } + } + break; } ///////////////////////// @@ -3853,94 +3994,88 @@ << " Release all locks and retry" << std::endl; #endif - r_xram_rsp_fsm = XRAM_RSP_DIR_LOCK; - break; + r_xram_rsp_fsm = XRAM_RSP_DIR_LOCK; + break; } /////////////////////// - case XRAM_RSP_DIR_UPDT: // updates the cache (both data & directory) - // and possibly set an inval request in IVT - { - // check if this is an instruction read, this means pktid is either - // TYPE_READ_INS_UNC 0bX010 with TSAR encoding - // TYPE_READ_INS_MISS 0bX011 with TSAR encoding - bool inst_read = (r_xram_rsp_trt_buf.pktid & 0x2) and r_xram_rsp_trt_buf.proc_read; - - // check if this is a cached read, this means pktid is either - // TYPE_READ_DATA_MISS 0bX001 with TSAR encoding - // TYPE_READ_INS_MISS 0bX011 with TSAR encoding - bool cached_read = (r_xram_rsp_trt_buf.pktid & 0x1) and r_xram_rsp_trt_buf.proc_read; - - bool dirty = false; - - // update cache data - size_t set = r_xram_rsp_victim_set.read(); - size_t way = r_xram_rsp_victim_way.read(); - for(size_t word=0; word" << " Set TRT entry for the put transaction" - << " / dirty victim line = " << r_xram_rsp_victim_nline.read() << std::endl; -#endif - if(r_xram_rsp_trt_buf.proc_read) r_xram_rsp_fsm = XRAM_RSP_DIR_RSP; - else if(r_xram_rsp_victim_inval.read()) r_xram_rsp_fsm = XRAM_RSP_INVAL; - else r_xram_rsp_fsm = XRAM_RSP_WRITE_DIRTY; - } - break; + << " / address = " << (r_xram_rsp_victim_nline.read()*m_words*4) << std::endl; +#endif + if(r_xram_rsp_trt_buf.proc_read) r_xram_rsp_fsm = XRAM_RSP_DIR_RSP; + else if(r_xram_rsp_victim_inval.read()) r_xram_rsp_fsm = XRAM_RSP_INVAL; + else r_xram_rsp_fsm = XRAM_RSP_WRITE_DIRTY; + } + break; } ////////////////////// case XRAM_RSP_DIR_RSP: // Request a response to TGT_RSP FSM { - if(!r_xram_rsp_to_tgt_rsp_req.read()) - { - r_xram_rsp_to_tgt_rsp_srcid = r_xram_rsp_trt_buf.srcid; - r_xram_rsp_to_tgt_rsp_trdid = r_xram_rsp_trt_buf.trdid; - r_xram_rsp_to_tgt_rsp_pktid = r_xram_rsp_trt_buf.pktid; - for(size_t i=0; i < m_words; i++) - { - r_xram_rsp_to_tgt_rsp_data[i] = r_xram_rsp_trt_buf.wdata[i]; - } - r_xram_rsp_to_tgt_rsp_word = r_xram_rsp_trt_buf.word_index; - r_xram_rsp_to_tgt_rsp_length = r_xram_rsp_trt_buf.read_length; - r_xram_rsp_to_tgt_rsp_ll_key = r_xram_rsp_trt_buf.ll_key; - r_xram_rsp_to_tgt_rsp_rerror = false; - r_xram_rsp_to_tgt_rsp_req = true; - - if(r_xram_rsp_victim_inval) r_xram_rsp_fsm = XRAM_RSP_INVAL; - else if(r_xram_rsp_victim_dirty) r_xram_rsp_fsm = XRAM_RSP_WRITE_DIRTY; - else r_xram_rsp_fsm = XRAM_RSP_IDLE; + if ( not r_xram_rsp_to_tgt_rsp_req.read() ) + { + r_xram_rsp_to_tgt_rsp_srcid = r_xram_rsp_trt_buf.srcid; + r_xram_rsp_to_tgt_rsp_trdid = r_xram_rsp_trt_buf.trdid; + r_xram_rsp_to_tgt_rsp_pktid = r_xram_rsp_trt_buf.pktid; + for(size_t i=0; i < m_words; i++) + { + r_xram_rsp_to_tgt_rsp_data[i] = r_xram_rsp_trt_buf.wdata[i]; + } + r_xram_rsp_to_tgt_rsp_word = r_xram_rsp_trt_buf.word_index; + r_xram_rsp_to_tgt_rsp_length = r_xram_rsp_trt_buf.read_length; + r_xram_rsp_to_tgt_rsp_ll_key = r_xram_rsp_trt_buf.ll_key; + r_xram_rsp_to_tgt_rsp_rerror = false; + r_xram_rsp_to_tgt_rsp_req = true; + + if(r_xram_rsp_victim_inval.read()) r_xram_rsp_fsm = XRAM_RSP_INVAL; + else if(r_xram_rsp_victim_dirty.read()) r_xram_rsp_fsm = XRAM_RSP_WRITE_DIRTY; + else r_xram_rsp_fsm = XRAM_RSP_IDLE; #if DEBUG_MEMC_XRAM_RSP @@ -4032,6 +4176,6 @@ << " / nwords = " << std::dec << r_xram_rsp_trt_buf.read_length << std::endl; #endif - } - break; + } + break; } //////////////////// @@ -4051,9 +4195,6 @@ xram_rsp_to_cc_send_fifo_srcid = r_xram_rsp_victim_copy.read(); xram_rsp_to_cc_send_fifo_inst = r_xram_rsp_victim_copy_inst.read(); -#if L1_MULTI_CACHE - xram_rsp_to_cc_send_fifo_cache_id = r_xram_rsp_victim_copy_cache.read(); -#endif xram_rsp_to_cc_send_fifo_put = multi_req; - r_xram_rsp_next_ptr = r_xram_rsp_victim_ptr.read(); + r_xram_rsp_next_ptr = r_xram_rsp_victim_ptr.read(); if(r_xram_rsp_victim_dirty) r_xram_rsp_fsm = XRAM_RSP_WRITE_DIRTY; @@ -4065,5 +4206,5 @@ std::cout << " " << " Send an inval request to CC_SEND FSM" - << " / victim line = " << r_xram_rsp_victim_nline.read() << std::endl; + << " / address = " << r_xram_rsp_victim_nline.read()*m_words*4 << std::endl; #endif } @@ -4073,20 +4214,17 @@ case XRAM_RSP_WRITE_DIRTY: // send a write request to IXR_CMD FSM { - if(!r_xram_rsp_to_ixr_cmd_req.read()) - { - r_xram_rsp_to_ixr_cmd_req = true; - r_xram_rsp_to_ixr_cmd_nline = r_xram_rsp_victim_nline.read(); - r_xram_rsp_to_ixr_cmd_trdid = r_xram_rsp_trt_index.read(); - for(size_t i=0; i" << " Send the put request to IXR_CMD FSM" - << " / victim line = " << r_xram_rsp_victim_nline.read() << std::endl; -#endif - } - break; + << " / address = " << r_xram_rsp_victim_nline.read()*m_words*4 << std::endl; +#endif + } + break; } ///////////////////////// case XRAM_RSP_HEAP_REQ: // Get the lock to the HEAP { - if(r_alloc_heap_fsm.read() == ALLOC_HEAP_XRAM_RSP) - { - r_xram_rsp_fsm = XRAM_RSP_HEAP_ERASE; - } + if(r_alloc_heap_fsm.read() == ALLOC_HEAP_XRAM_RSP) + { + r_xram_rsp_fsm = XRAM_RSP_HEAP_ERASE; + } #if DEBUG_MEMC_XRAM_RSP @@ -4112,5 +4250,5 @@ << " Requesting HEAP lock" << std::endl; #endif - break; + break; } ///////////////////////// @@ -4122,7 +4260,4 @@ xram_rsp_to_cc_send_fifo_srcid = entry.owner.srcid; -#if L1_MULTI_CACHE - xram_rsp_to_cc_send_fifo_cache_id = entry.owner.cache_id; -#endif xram_rsp_to_cc_send_fifo_inst = entry.owner.inst; xram_rsp_to_cc_send_fifo_put = true; @@ -4168,7 +4303,4 @@ HeapEntry last_entry; last_entry.owner.srcid = 0; -#if L1_MULTI_CACHE - last_entry.owner.cache_id = 0; -#endif last_entry.owner.inst = false; if(m_heap.is_full()) @@ -4194,5 +4326,5 @@ break; } - // /////////////////////// + ////////////////////////// case XRAM_RSP_ERROR_ERASE: // erase TRT entry in case of error { @@ -4247,49 +4379,36 @@ //////////////////////////////////////////////////////////////////////////////////// +//std::cout << std::endl << "cleanup_fsm" << std::endl; + switch(r_cleanup_fsm.read()) { - ////////////////// - case CLEANUP_IDLE: // Get first DSPIN flit of the CLEANUP command - { - if(not m_cc_receive_to_cleanup_fifo.rok()) break; - - uint64_t flit = m_cc_receive_to_cleanup_fifo.read(); - - uint32_t srcid = - DspinDhccpParam::dspin_get( - flit, - DspinDhccpParam::CLEANUP_SRCID); - - uint8_t type = - DspinDhccpParam::dspin_get( - flit, - DspinDhccpParam::P2M_TYPE); - - r_cleanup_way_index = - DspinDhccpParam::dspin_get( - flit, - DspinDhccpParam::CLEANUP_WAY_INDEX); - - r_cleanup_nline = - DspinDhccpParam::dspin_get( - flit, - DspinDhccpParam::CLEANUP_NLINE_MSB) << 32; - - r_cleanup_inst = (type == DspinDhccpParam::TYPE_CLEANUP_INST); - r_cleanup_srcid = srcid; - - if(srcid >= m_initiators) - { - std::cout - << "VCI_MEM_CACHE ERROR " << name() - << " CLEANUP_IDLE state" << std::endl - << "illegal srcid for cleanup request" << std::endl; - - exit(0); - } - - m_cpt_cleanup++; - cc_receive_to_cleanup_fifo_get = true; - r_cleanup_fsm = CLEANUP_GET_NLINE; + ////////////////// + case CLEANUP_IDLE: // Get first DSPIN flit of the CLEANUP command + { + if(not m_cc_receive_to_cleanup_fifo.rok()) break; + + uint64_t flit = m_cc_receive_to_cleanup_fifo.read(); + + uint32_t srcid = DspinDhccpParam::dspin_get( flit, + DspinDhccpParam::CLEANUP_SRCID); + + uint8_t type = DspinDhccpParam::dspin_get( flit, + DspinDhccpParam::P2M_TYPE); + + r_cleanup_way_index = DspinDhccpParam::dspin_get( flit, + DspinDhccpParam::CLEANUP_WAY_INDEX); + + r_cleanup_nline = DspinDhccpParam::dspin_get( flit, + DspinDhccpParam::CLEANUP_NLINE_MSB) << 32; + + r_cleanup_inst = (type == DspinDhccpParam::TYPE_CLEANUP_INST); + r_cleanup_srcid = srcid; + + assert( (srcid < m_initiators) and + "MEMC ERROR in CLEANUP_IDLE state : illegal SRCID value"); + + m_cpt_cleanup++; + cc_receive_to_cleanup_fifo_get = true; + r_cleanup_fsm = CLEANUP_GET_NLINE; #if DEBUG_MEMC_CLEANUP @@ -4297,23 +4416,22 @@ std::cout << " Cleanup request:" << std::hex - << " / owner_id = " << srcid + << " owner_id = " << srcid << " / owner_ins = " << (type == DspinDhccpParam::TYPE_CLEANUP_INST) << std::endl; #endif - break; - } - - /////////////////////// - case CLEANUP_GET_NLINE: // GET second DSPIN flit of the cleanup command - { - if(not m_cc_receive_to_cleanup_fifo.rok()) break; - - uint64_t flit = m_cc_receive_to_cleanup_fifo.read(); - - addr_t nline = r_cleanup_nline.read() | - DspinDhccpParam::dspin_get(flit, DspinDhccpParam::CLEANUP_NLINE_LSB); - - cc_receive_to_cleanup_fifo_get = true; - r_cleanup_nline = nline; - r_cleanup_fsm = CLEANUP_DIR_REQ; + break; + } + /////////////////////// + case CLEANUP_GET_NLINE: // GET second DSPIN flit of the cleanup command + { + if(not m_cc_receive_to_cleanup_fifo.rok()) break; + + uint64_t flit = m_cc_receive_to_cleanup_fifo.read(); + + addr_t nline = r_cleanup_nline.read() | + DspinDhccpParam::dspin_get(flit, DspinDhccpParam::CLEANUP_NLINE_LSB); + + cc_receive_to_cleanup_fifo_get = true; + r_cleanup_nline = nline; + r_cleanup_fsm = CLEANUP_DIR_REQ; #if DEBUG_MEMC_CLEANUP @@ -4321,15 +4439,14 @@ std::cout << " Cleanup request:" - << " / address = " << std::hex << nline * m_words * 4 << std::endl; -#endif - break; - } - - ///////////////////// - case CLEANUP_DIR_REQ: // Get the lock to the directory - { - if(r_alloc_dir_fsm.read() != ALLOC_DIR_CLEANUP) break; - - r_cleanup_fsm = CLEANUP_DIR_LOCK; + << " address = " << std::hex << nline * m_words * 4 << std::endl; +#endif + break; + } + ///////////////////// + case CLEANUP_DIR_REQ: // Get the lock to the directory + { + if(r_alloc_dir_fsm.read() != ALLOC_DIR_CLEANUP) break; + + r_cleanup_fsm = CLEANUP_DIR_LOCK; #if DEBUG_MEMC_CLEANUP @@ -4337,401 +4454,248 @@ std::cout << " Requesting DIR lock" << std::endl; #endif - break; - } - - ////////////////////// - case CLEANUP_DIR_LOCK: - { - // test directory status - if(r_alloc_dir_fsm.read() != ALLOC_DIR_CLEANUP) - { - std::cout - << "VCI_MEM_CACHE ERROR " << name() - << " CLEANUP_DIR_LOCK state" - << " bad DIR allocation" << std::endl; - - exit(0); - } - - // Read the directory - size_t way = 0; - addr_t cleanup_address = r_cleanup_nline.read() * m_words * 4; - - DirectoryEntry entry = m_cache_directory.read(cleanup_address , way); - r_cleanup_is_cnt = entry.is_cnt; - r_cleanup_dirty = entry.dirty; - r_cleanup_tag = entry.tag; - r_cleanup_lock = entry.lock; - r_cleanup_way = way; - r_cleanup_count = entry.count; - r_cleanup_ptr = entry.ptr; - r_cleanup_copy = entry.owner.srcid; - r_cleanup_copy_inst = entry.owner.inst; -#if L1_MULTI_CACHE - r_cleanup_copy_cache = entry.owner.cache_id; -#endif - - if(entry.valid) // hit : the copy must be cleared - { - assert( - (entry.count > 0) and - "VCI MEM CACHE ERROR: " - "In CLEANUP_DIR_LOCK, CLEANUP command on a valid entry " - "with no copies"); - - // no access to the heap - if((entry.count == 1) or (entry.is_cnt)) - { - r_cleanup_fsm = CLEANUP_DIR_WRITE; - } - // access to the heap - else - { - r_cleanup_fsm = CLEANUP_HEAP_REQ; - } - } - else // miss : check UPT for a pending invalidation transaction - { - r_cleanup_fsm = CLEANUP_IVT_LOCK; - } + break; + } + ////////////////////// + case CLEANUP_DIR_LOCK: // test directory status + { + assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_CLEANUP) and + "MEMC ERROR in CLEANUP_DIR_LOCK: bad DIR allocation"); + + // Read the directory + size_t way = 0; + addr_t cleanup_address = r_cleanup_nline.read() * m_words * 4; + DirectoryEntry entry = m_cache_directory.read(cleanup_address , way); + r_cleanup_is_cnt = entry.is_cnt; + r_cleanup_dirty = entry.dirty; + r_cleanup_tag = entry.tag; + r_cleanup_lock = entry.lock; + r_cleanup_way = way; + r_cleanup_count = entry.count; + r_cleanup_ptr = entry.ptr; + r_cleanup_copy = entry.owner.srcid; + r_cleanup_copy_inst = entry.owner.inst; + + if(entry.valid) // hit : the copy must be cleared + { + assert( (entry.count > 0) and + "MEMC ERROR in CLEANUP_DIR_LOCK state, CLEANUP on valid entry with no copies"); + + if((entry.count == 1) or (entry.is_cnt)) // no access to the heap + { + r_cleanup_fsm = CLEANUP_DIR_WRITE; + } + else // access to the heap + { + r_cleanup_fsm = CLEANUP_HEAP_REQ; + } + } + else // miss : check IVT for a pending inval + { + r_cleanup_fsm = CLEANUP_IVT_LOCK; + } #if DEBUG_MEMC_CLEANUP - if(m_debug) - { - std::cout - << " Test directory status: " - << std::hex - << " line = " << cleanup_address - << " / hit = " << entry.valid - << " / dir_id = " << entry.owner.srcid - << " / dir_ins = " << entry.owner.inst - << " / search_id = " << r_cleanup_srcid.read() - << " / search_ins = " << r_cleanup_inst.read() - << " / count = " << entry.count - << " / is_cnt = " << entry.is_cnt - << std::endl; - } -#endif - break; - } - - /////////////////////// - case CLEANUP_DIR_WRITE: - { - // Update the directory entry without heap access - if(r_alloc_dir_fsm.read() != ALLOC_DIR_CLEANUP) - { - std::cout - << "VCI_MEM_CACHE ERROR " << name() - << " CLEANUP_DIR_WRITE state" - << " bad DIR allocation" << std::endl; - - exit(0); - } - - size_t way = r_cleanup_way.read(); - size_t set = m_y[(addr_t)(r_cleanup_nline.read()*m_words*4)]; - bool match_srcid = (r_cleanup_copy.read() == r_cleanup_srcid.read()); - -#if L1_MULTI_CACHE - match_srcid &= (r_cleanup_copy_cache.read() == r_cleanup_pktid.read()); -#endif - - bool match_inst = (r_cleanup_copy_inst.read() == r_cleanup_inst.read()); - bool match = match_srcid and match_inst; - - if(not r_cleanup_is_cnt.read() and not match) - { - std::cout - << "VCI_MEM_CACHE ERROR : Cleanup request on a valid" - << "entry using linked list mode with no corresponding" - << "directory or heap entry" - << std::endl; - - exit(1); - } - - // update the cache directory (for the copies) - DirectoryEntry entry; - entry.valid = true; - entry.is_cnt = r_cleanup_is_cnt.read(); - entry.dirty = r_cleanup_dirty.read(); - entry.tag = r_cleanup_tag.read(); - entry.lock = r_cleanup_lock.read(); - entry.ptr = r_cleanup_ptr.read(); - entry.count = r_cleanup_count.read() - 1; - entry.owner.srcid = 0; - entry.owner.inst = 0; - -#if L1_MULTI_CACHE - entry.owner.cache_id = 0; -#endif - - m_cache_directory.write(set, way, entry); - - r_cleanup_fsm = CLEANUP_SEND_CLACK; +if(m_debug) +std::cout << " Test directory status: " + << std::hex << " address = " << cleanup_address + << " / hit = " << entry.valid + << " / dir_id = " << entry.owner.srcid + << " / dir_ins = " << entry.owner.inst + << " / search_id = " << r_cleanup_srcid.read() + << " / search_ins = " << r_cleanup_inst.read() + << " / count = " << entry.count + << " / is_cnt = " << entry.is_cnt << std::endl; +#endif + break; + } + /////////////////////// + case CLEANUP_DIR_WRITE: // Update the directory entry without heap access + { + assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_CLEANUP) and + "MEMC ERROR in CLEANUP_DIR_LOCK: bad DIR allocation"); + + size_t way = r_cleanup_way.read(); + size_t set = m_y[(addr_t)(r_cleanup_nline.read()*m_words*4)]; + bool match_srcid = (r_cleanup_copy.read() == r_cleanup_srcid.read()); + bool match_inst = (r_cleanup_copy_inst.read() == r_cleanup_inst.read()); + bool match = match_srcid and match_inst; + + assert( (r_cleanup_is_cnt.read() or match) and + "MEMC ERROR in CLEANUP_DIR_LOCK: illegal CLEANUP on valid entry"); + + // update the cache directory (for the copies) + DirectoryEntry entry; + entry.valid = true; + entry.is_cnt = r_cleanup_is_cnt.read(); + entry.dirty = r_cleanup_dirty.read(); + entry.tag = r_cleanup_tag.read(); + entry.lock = r_cleanup_lock.read(); + entry.ptr = r_cleanup_ptr.read(); + entry.count = r_cleanup_count.read() - 1; + entry.owner.srcid = 0; + entry.owner.inst = 0; + + m_cache_directory.write(set, way, entry); + + r_cleanup_fsm = CLEANUP_SEND_CLACK; #if DEBUG_MEMC_CLEANUP - if(m_debug) - { - std::cout - << " Update directory:" - << std::hex - << " address = " << r_cleanup_nline.read() * m_words * 4 - << " / dir_id = " << entry.owner.srcid - << " / dir_ins = " << entry.owner.inst - << " / count = " << entry.count - << " / is_cnt = " << entry.is_cnt - << std::endl; - } -#endif - - break; - } - - ////////////////////// - case CLEANUP_HEAP_REQ: - { - // get the lock to the HEAP directory - if(r_alloc_heap_fsm.read() != ALLOC_HEAP_CLEANUP) break; - - r_cleanup_fsm = CLEANUP_HEAP_LOCK; +if(m_debug) +std::cout << " Update directory:" + << std::hex << " address = " << r_cleanup_nline.read() * m_words * 4 + << " / dir_id = " << entry.owner.srcid + << " / dir_ins = " << entry.owner.inst + << " / count = " << entry.count + << " / is_cnt = " << entry.is_cnt << std::endl; +#endif + + break; + } + ////////////////////// + case CLEANUP_HEAP_REQ: // get the lock to the HEAP directory + { + if(r_alloc_heap_fsm.read() != ALLOC_HEAP_CLEANUP) break; + + r_cleanup_fsm = CLEANUP_HEAP_LOCK; #if DEBUG_MEMC_CLEANUP - if(m_debug) - { - std::cout - << " HEAP lock acquired " - << std::endl; - } -#endif - break; - } - - ////////////////////// - case CLEANUP_HEAP_LOCK: - { - // two cases are handled in this state : - // 1. the matching copy is directly in the directory - // 2. the matching copy is the first copy in the heap - if(r_alloc_heap_fsm.read() != ALLOC_HEAP_CLEANUP) - { - std::cout - << "VCI_MEM_CACHE ERROR " << name() - << " CLEANUP_HEAP_LOCK state" - << " bad HEAP allocation" << std::endl; - - exit(0); - } - - size_t way = r_cleanup_way.read(); - size_t set = m_y[(addr_t)(r_cleanup_nline.read() *m_words*4)]; - - HeapEntry heap_entry = m_heap.read(r_cleanup_ptr.read()); - bool last = (heap_entry.next == r_cleanup_ptr.read()); - - // match_dir computation - bool match_dir_srcid = (r_cleanup_copy.read() == r_cleanup_srcid.read()); - bool match_dir_inst = (r_cleanup_copy_inst.read() == r_cleanup_inst.read()); - bool match_dir = match_dir_srcid and match_dir_inst; - - // match_heap computation - bool match_heap_srcid = (heap_entry.owner.srcid == r_cleanup_srcid.read()); - bool match_heap_inst = (heap_entry.owner.inst == r_cleanup_inst.read()); - bool match_heap = match_heap_srcid and match_heap_inst; - - r_cleanup_prev_ptr = r_cleanup_ptr.read(); - r_cleanup_prev_srcid = heap_entry.owner.srcid; - r_cleanup_prev_inst = heap_entry.owner.inst; - -#if L1_MULTI_CACHE - match_dir = match_dir and(r_cleanup_copy_cache.read() == r_cleanup_pktid.read()); - match_heap = match_heap and(heap_entry.owner.cache_id == r_cleanup_pktid.read()); - r_cleanup_prev_cache_id = heap_entry.owner.cache_id; -#endif - - if(not match_dir and not match_heap and last) - { - std::cout - << "VCI_MEM_CACHE ERROR " << name() - << " CLEANUP_HEAP_LOCK state" - << " hit but copy not found" - << std::endl; -/**/ - std::cout - << "r_cleanup_srcid = " << r_cleanup_srcid.read() - << " / r_cleanup_inst = " << r_cleanup_inst.read() << std::endl - << "r_cleanup_copy = " << r_cleanup_copy.read() - << " / r_cleanup_copy_inst = " << r_cleanup_copy_inst.read() << std::endl - << "heap_entry.owner.srcid = " << heap_entry.owner.srcid - << " / heap_entry.owner.inst = " << heap_entry.owner.inst << std::endl; -/**/ - exit(0); - } - - if(match_dir and match_heap) - { - std::cout - << "VCI_MEM_CACHE ERROR " << name() - << " CLEANUP_HEAP_LOCK state" - << " two copies matching the cleanup owner id" - << std::endl; -/**/ - std::cout - << "r_cleanup_srcid = " << r_cleanup_srcid.read() - << " / r_cleanup_inst = " << r_cleanup_inst.read() << std::endl - << "r_cleanup_copy = " << r_cleanup_copy.read() - << " / r_cleanup_copy_inst = " << r_cleanup_copy_inst.read() << std::endl - << "heap_entry.owner.srcid = " << heap_entry.owner.srcid - << " / heap_entry.owner.inst = " << heap_entry.owner.inst << std::endl; -/**/ - - exit(0); - } - - DirectoryEntry dir_entry; - dir_entry.valid = true; - dir_entry.is_cnt = r_cleanup_is_cnt.read(); - dir_entry.dirty = r_cleanup_dirty.read(); - dir_entry.tag = r_cleanup_tag.read(); - dir_entry.lock = r_cleanup_lock.read(); - dir_entry.count = r_cleanup_count.read()-1; - - // the matching copy is registered in the directory and - // it must be replaced by the first copy registered in - // the heap. The corresponding entry must be freed - if(match_dir) - { - dir_entry.ptr = heap_entry.next; - dir_entry.owner.srcid = heap_entry.owner.srcid; - dir_entry.owner.inst = heap_entry.owner.inst; - -#if L1_MULTI_CACHE - dir_entry.owner.cache_id = heap_entry.owner.cache_id; -#endif - - r_cleanup_next_ptr = r_cleanup_ptr.read(); - r_cleanup_fsm = CLEANUP_HEAP_FREE; - } - - // the matching copy is the first copy in the heap - // It must be freed and the copy registered in directory - // must point to the next copy in heap - else if(match_heap) - { - dir_entry.ptr = heap_entry.next; - dir_entry.owner.srcid = r_cleanup_copy.read(); - dir_entry.owner.inst = r_cleanup_copy_inst.read(); - -#if L1_MULTI_CACHE - dir_entry.owner.cache_id = r_cleanup_copy_cache.read(); -#endif - - r_cleanup_next_ptr = r_cleanup_ptr.read(); - r_cleanup_fsm = CLEANUP_HEAP_FREE; - } - - // The matching copy is in the heap, but is not the first copy - // The directory entry must be modified to decrement count - else - { - dir_entry.ptr = r_cleanup_ptr.read(); - dir_entry.owner.srcid = r_cleanup_copy.read(); - dir_entry.owner.inst = r_cleanup_copy_inst.read(); - -#if L1_MULTI_CACHE - dir_entry.owner.cache_id = r_cleanup_copy_cache.read(); -#endif - - r_cleanup_next_ptr = heap_entry.next; - r_cleanup_fsm = CLEANUP_HEAP_SEARCH; - } - - m_cache_directory.write(set,way,dir_entry); +if(m_debug) +std::cout << " HEAP lock acquired " << std::endl; +#endif + break; + } + ////////////////////// + case CLEANUP_HEAP_LOCK: // two cases are handled in this state : + // 1. the matching copy is directly in the directory + // 2. the matching copy is the first copy in the heap + { + assert( (r_alloc_heap_fsm.read() == ALLOC_HEAP_CLEANUP) and + "MEMC ERROR in CLEANUP_HEAP_LOCK state: bad HEAP allocation"); + + size_t way = r_cleanup_way.read(); + size_t set = m_y[(addr_t)(r_cleanup_nline.read() *m_words*4)]; + + HeapEntry heap_entry = m_heap.read(r_cleanup_ptr.read()); + bool last = (heap_entry.next == r_cleanup_ptr.read()); + + // match_dir computation + bool match_dir_srcid = (r_cleanup_copy.read() == r_cleanup_srcid.read()); + bool match_dir_inst = (r_cleanup_copy_inst.read() == r_cleanup_inst.read()); + bool match_dir = match_dir_srcid and match_dir_inst; + + // match_heap computation + bool match_heap_srcid = (heap_entry.owner.srcid == r_cleanup_srcid.read()); + bool match_heap_inst = (heap_entry.owner.inst == r_cleanup_inst.read()); + bool match_heap = match_heap_srcid and match_heap_inst; + + r_cleanup_prev_ptr = r_cleanup_ptr.read(); + r_cleanup_prev_srcid = heap_entry.owner.srcid; + r_cleanup_prev_inst = heap_entry.owner.inst; + + assert( (not last or match_dir or match_heap) and + "MEMC ERROR in CLEANUP_HEAP_LOCK state: hit but no copy found"); + + assert( (not match_dir or not match_heap) and + "MEMC ERROR in CLEANUP_HEAP_LOCK state: two matching copies found"); + + DirectoryEntry dir_entry; + dir_entry.valid = true; + dir_entry.is_cnt = r_cleanup_is_cnt.read(); + dir_entry.dirty = r_cleanup_dirty.read(); + dir_entry.tag = r_cleanup_tag.read(); + dir_entry.lock = r_cleanup_lock.read(); + dir_entry.count = r_cleanup_count.read()-1; + + // the matching copy is registered in the directory and + // it must be replaced by the first copy registered in + // the heap. The corresponding entry must be freed + if(match_dir) + { + dir_entry.ptr = heap_entry.next; + dir_entry.owner.srcid = heap_entry.owner.srcid; + dir_entry.owner.inst = heap_entry.owner.inst; + r_cleanup_next_ptr = r_cleanup_ptr.read(); + r_cleanup_fsm = CLEANUP_HEAP_FREE; + } + + // the matching copy is the first copy in the heap + // It must be freed and the copy registered in directory + // must point to the next copy in heap + else if(match_heap) + { + dir_entry.ptr = heap_entry.next; + dir_entry.owner.srcid = r_cleanup_copy.read(); + dir_entry.owner.inst = r_cleanup_copy_inst.read(); + r_cleanup_next_ptr = r_cleanup_ptr.read(); + r_cleanup_fsm = CLEANUP_HEAP_FREE; + } + + // The matching copy is in the heap, but is not the first copy + // The directory entry must be modified to decrement count + else + { + dir_entry.ptr = r_cleanup_ptr.read(); + dir_entry.owner.srcid = r_cleanup_copy.read(); + dir_entry.owner.inst = r_cleanup_copy_inst.read(); + r_cleanup_next_ptr = heap_entry.next; + r_cleanup_fsm = CLEANUP_HEAP_SEARCH; + } + + m_cache_directory.write(set,way,dir_entry); #if DEBUG_MEMC_CLEANUP - if(m_debug) - { - std::cout - << " Checks matching:" - << " address = " << r_cleanup_nline.read() * m_words * 4 - << " / dir_id = " << r_cleanup_copy.read() - << " / dir_ins = " << r_cleanup_copy_inst.read() - << " / heap_id = " << heap_entry.owner.srcid - << " / heap_ins = " << heap_entry.owner.inst - << " / search_id = " << r_cleanup_srcid.read() - << " / search_ins = " << r_cleanup_inst.read() - << std::endl; - } -#endif - break; - } - - //////////////////////// - case CLEANUP_HEAP_SEARCH: - { - // This state is handling the case where the copy - // is in the heap, but is not the first in the linked list - if(r_alloc_heap_fsm.read() != ALLOC_HEAP_CLEANUP) - { - std::cout - << "VCI_MEM_CACHE ERROR " << name() - << " CLEANUP_HEAP_SEARCH state" - << " bad HEAP allocation" << std::endl; - - exit(0); - } - - HeapEntry heap_entry = m_heap.read(r_cleanup_next_ptr.read()); - - bool last = (heap_entry.next == r_cleanup_next_ptr.read()); - bool match_heap_srcid = (heap_entry.owner.srcid == r_cleanup_srcid.read()); - bool match_heap_inst = (heap_entry.owner.inst == r_cleanup_inst.read()); - bool match_heap = match_heap_srcid and match_heap_inst; - -#if L1_MULTI_CACHE - match_heap = match_heap and(heap_entry.owner.cache_id == r_cleanup_pktid.read()); -#endif - - if(not match_heap and last) - { - std::cout - << "VCI_MEM_CACHE_ERROR " << name() - << " CLEANUP_HEAP_SEARCH state" - << " cleanup on valid line but copy not found" - << std::endl; - - exit(0); - } - - // the matching copy must be removed - if(match_heap) - { - // re-use ressources - r_cleanup_ptr = heap_entry.next; - r_cleanup_fsm = CLEANUP_HEAP_CLEAN; - } - // test the next in the linked list - else - { - r_cleanup_prev_ptr = r_cleanup_next_ptr.read(); - r_cleanup_prev_srcid = heap_entry.owner.srcid; - r_cleanup_prev_inst = heap_entry.owner.inst; - r_cleanup_next_ptr = heap_entry.next; - - r_cleanup_fsm = CLEANUP_HEAP_SEARCH; - -#if L1_MULTI_CACHE - r_cleanup_prev_cache_id = heap_entry.owner.cache_id; -#endif - } +if(m_debug) +std::cout << " Checks matching:" + << " address = " << r_cleanup_nline.read() * m_words * 4 + << " / dir_id = " << r_cleanup_copy.read() + << " / dir_ins = " << r_cleanup_copy_inst.read() + << " / heap_id = " << heap_entry.owner.srcid + << " / heap_ins = " << heap_entry.owner.inst + << " / search_id = " << r_cleanup_srcid.read() + << " / search_ins = " << r_cleanup_inst.read() << std::endl; +#endif + break; + } + //////////////////////// + case CLEANUP_HEAP_SEARCH: // This state is handling the case where the copy + // is in the heap, but not the first in linked list + { + assert( (r_alloc_heap_fsm.read() == ALLOC_HEAP_CLEANUP) and + "MEMC ERROR in CLEANUP_HEAP_LOCK state: bad HEAP allocation"); + + HeapEntry heap_entry = m_heap.read(r_cleanup_next_ptr.read()); + + bool last = (heap_entry.next == r_cleanup_next_ptr.read()); + bool match_heap_srcid = (heap_entry.owner.srcid == r_cleanup_srcid.read()); + bool match_heap_inst = (heap_entry.owner.inst == r_cleanup_inst.read()); + bool match_heap = match_heap_srcid and match_heap_inst; + + assert( (not last or match_heap) and + "MEMC ERROR in CLEANUP_HEAP_SEARCH state: no copy found"); + + // the matching copy must be removed + if(match_heap) + { + // re-use ressources + r_cleanup_ptr = heap_entry.next; + r_cleanup_fsm = CLEANUP_HEAP_CLEAN; + } + // test the next in the linked list + else + { + r_cleanup_prev_ptr = r_cleanup_next_ptr.read(); + r_cleanup_prev_srcid = heap_entry.owner.srcid; + r_cleanup_prev_inst = heap_entry.owner.inst; + r_cleanup_next_ptr = heap_entry.next; + r_cleanup_fsm = CLEANUP_HEAP_SEARCH; + } #if DEBUG_MEMC_CLEANUP - if(m_debug) - { +if(m_debug) +{ if(not match_heap) { @@ -4748,5 +4712,4 @@ << std::endl; } - std::cout << " address = " << r_cleanup_nline.read() * m_words * 4 @@ -4757,45 +4720,31 @@ << " / last = " << last << std::endl; - } -#endif - break; - } - //////////////////////// - case CLEANUP_HEAP_CLEAN: // remove a copy in the linked list - { - if(r_alloc_heap_fsm.read() != ALLOC_HEAP_CLEANUP) - { - std::cout - << "VCI_MEM_CACHE ERROR " << name() - << " CLEANUP_HEAP_CLEAN state" - << "Bad HEAP allocation" << std::endl; - - exit(0); - } - - HeapEntry heap_entry; - heap_entry.owner.srcid = r_cleanup_prev_srcid.read(); - heap_entry.owner.inst = r_cleanup_prev_inst.read(); - -#if L1_MULTI_CACHE - heap_entry.owner.cache_id = r_cleanup_prev_cache_id.read(); -#endif - - bool last = (r_cleanup_next_ptr.read() == r_cleanup_ptr.read()); - - // this is the last entry of the list of copies - if(last) - { - heap_entry.next = r_cleanup_prev_ptr.read(); - } - // this is not the last entry - else - { - heap_entry.next = r_cleanup_ptr.read(); - } - - m_heap.write(r_cleanup_prev_ptr.read(), heap_entry); - - r_cleanup_fsm = CLEANUP_HEAP_FREE; +} +#endif + break; + } + //////////////////////// + case CLEANUP_HEAP_CLEAN: // remove a copy in the linked list + { + assert( (r_alloc_heap_fsm.read() == ALLOC_HEAP_CLEANUP) and + "MEMC ERROR in CLEANUP_HEAP_LOCK state: bad HEAP allocation"); + + HeapEntry heap_entry; + heap_entry.owner.srcid = r_cleanup_prev_srcid.read(); + heap_entry.owner.inst = r_cleanup_prev_inst.read(); + bool last = (r_cleanup_next_ptr.read() == r_cleanup_ptr.read()); + + if (last) // this is the last entry of the list of copies + { + heap_entry.next = r_cleanup_prev_ptr.read(); + } + else // this is not the last entry + { + heap_entry.next = r_cleanup_ptr.read(); + } + + m_heap.write(r_cleanup_prev_ptr.read(), heap_entry); + + r_cleanup_fsm = CLEANUP_HEAP_FREE; #if DEBUG_MEMC_CLEANUP @@ -4804,42 +4753,31 @@ << " Remove the copy in the linked list" << std::endl; #endif - break; - } - /////////////////////// - case CLEANUP_HEAP_FREE: // The heap entry pointed by r_cleanup_next_ptr is freed - // and becomes the head of the list of free entries - { - if(r_alloc_heap_fsm.read() != ALLOC_HEAP_CLEANUP) - { - std::cout - << "VCI_MEM_CACHE ERROR " << name() - << " CLEANUP_HEAP_CLEAN state" << std::endl - << "Bad HEAP allocation" << std::endl; - - exit(0); - } - - HeapEntry heap_entry; - heap_entry.owner.srcid = 0; - heap_entry.owner.inst = false; - -#if L1_MULTI_CACHE - heap_entry.owner.cache_id = 0; -#endif - - if(m_heap.is_full()) - { - heap_entry.next = r_cleanup_next_ptr.read(); - } - else - { - heap_entry.next = m_heap.next_free_ptr(); - } - - m_heap.write(r_cleanup_next_ptr.read(),heap_entry); - m_heap.write_free_ptr(r_cleanup_next_ptr.read()); - m_heap.unset_full(); - - r_cleanup_fsm = CLEANUP_SEND_CLACK; + break; + } + /////////////////////// + case CLEANUP_HEAP_FREE: // The heap entry pointed by r_cleanup_next_ptr is freed + // and becomes the head of the list of free entries + { + assert( (r_alloc_heap_fsm.read() == ALLOC_HEAP_CLEANUP) and + "MEMC ERROR in CLEANUP_HEAP_LOCK state: bad HEAP allocation"); + + HeapEntry heap_entry; + heap_entry.owner.srcid = 0; + heap_entry.owner.inst = false; + + if(m_heap.is_full()) + { + heap_entry.next = r_cleanup_next_ptr.read(); + } + else + { + heap_entry.next = m_heap.next_free_ptr(); + } + + m_heap.write(r_cleanup_next_ptr.read(),heap_entry); + m_heap.write_free_ptr(r_cleanup_next_ptr.read()); + m_heap.unset_full(); + + r_cleanup_fsm = CLEANUP_SEND_CLACK; #if DEBUG_MEMC_CLEANUP @@ -4848,78 +4786,60 @@ << " Update the list of free entries" << std::endl; #endif + break; + } + ////////////////////// + case CLEANUP_IVT_LOCK: // get the lock protecting the IVT to search a pending + // invalidate transaction matching the cleanup + { + if(r_alloc_ivt_fsm.read() != ALLOC_IVT_CLEANUP) break; + + size_t index = 0; + bool match_inval; + + match_inval = m_ivt.search_inval(r_cleanup_nline.read(), index); + + if ( not match_inval ) // no pending inval in IVT + { + r_cleanup_fsm = CLEANUP_SEND_CLACK; + +#if DEBUG_MEMC_CLEANUP +if(m_debug) +std::cout << " " + << " Unexpected cleanup with no corresponding IVT entry:" + << " address = " << std::hex << (r_cleanup_nline.read()*4*m_words) << std::endl; +#endif + } + else // pending inval in IVT + { + r_cleanup_write_srcid = m_ivt.srcid(index); + r_cleanup_write_trdid = m_ivt.trdid(index); + r_cleanup_write_pktid = m_ivt.pktid(index); + r_cleanup_need_rsp = m_ivt.need_rsp(index); + r_cleanup_need_ack = m_ivt.need_ack(index); + r_cleanup_index = index; + r_cleanup_fsm = CLEANUP_IVT_DECREMENT; + +#if DEBUG_MEMC_CLEANUP +if(m_debug) +std::cout << " " + << " Cleanup matching pending invalidate transaction on IVT:" + << " address = " << std::hex << (r_cleanup_nline.read()*m_words*4) + << " / ivt_entry = " << index << std::endl; +#endif + } break; - } - ////////////////////// - case CLEANUP_IVT_LOCK: // get the lock protecting the IVT to search a pending - // invalidate transaction matching the cleanup - { - if(r_alloc_ivt_fsm.read() != ALLOC_IVT_CLEANUP) break; - - size_t index = 0; - bool match_inval; - - match_inval = m_ivt.search_inval(r_cleanup_nline.read(), index); - - if ( not match_inval ) // no pending inval - { - r_cleanup_fsm = CLEANUP_SEND_CLACK; - -#if DEBUG_MEMC_CLEANUP -if(m_debug) -std::cout << " Unexpected cleanup" - << " with no corresponding IVT entry:" - << " address = " << std::hex - << (r_cleanup_nline.read() *4*m_words) - << std::endl; -#endif - break; - } - - // pending inval - r_cleanup_write_srcid = m_ivt.srcid(index); - r_cleanup_write_trdid = m_ivt.trdid(index); - r_cleanup_write_pktid = m_ivt.pktid(index); - r_cleanup_need_rsp = m_ivt.need_rsp(index); - r_cleanup_need_ack = m_ivt.need_ack(index); - r_cleanup_index = index; - - r_cleanup_fsm = CLEANUP_IVT_DECREMENT; - -#if DEBUG_MEMC_CLEANUP -if(m_debug) -std::cout << " Cleanup matching pending" - << " invalidate transaction on IVT:" - << " address = " << std::hex << r_cleanup_nline.read() * m_words * 4 - << " / ivt_entry = " << index << std::endl; -#endif - break; - } - /////////////////////////// - case CLEANUP_IVT_DECREMENT: // decrement response counter in IVT matching entry - { - if(r_alloc_ivt_fsm.read() != ALLOC_IVT_CLEANUP) - { - std::cout - << "VCI_MEM_CACHE ERROR " << name() - << " CLEANUP_IVT_DECREMENT state" << std::endl - << "Bad IVT allocation" - << std::endl; - - exit(0); - } - - size_t count = 0; - m_ivt.decrement(r_cleanup_index.read(), count); - - if(count == 0) // multi inval transaction completed - { - r_cleanup_fsm = CLEANUP_IVT_CLEAR; - } - else // multi inval transaction not completed - { - r_cleanup_fsm = CLEANUP_SEND_CLACK ; - } + } + /////////////////////////// + case CLEANUP_IVT_DECREMENT: // decrement response counter in IVT matching entry + // and test if last + { + assert( (r_alloc_ivt_fsm.read() == ALLOC_IVT_CLEANUP) and + "MEMC ERROR in CLEANUP_IVT_DECREMENT state: Bad IVT allocation"); + + size_t count = 0; + m_ivt.decrement(r_cleanup_index.read(), count); + + if(count == 0) r_cleanup_fsm = CLEANUP_IVT_CLEAR; + else r_cleanup_fsm = CLEANUP_SEND_CLACK ; #if DEBUG_MEMC_CLEANUP @@ -4927,28 +4847,28 @@ std::cout << " " << " Decrement response counter in IVT:" - << " IVT_index = " << r_cleanup_index.read() - << " / rsp_count = " << count << std::endl; -#endif - break; - } - /////////////////////// - case CLEANUP_IVT_CLEAR: // Clear IVT entry - { - if(r_alloc_ivt_fsm.read() != ALLOC_IVT_CLEANUP) - { - std::cout - << "VCI_MEM_CACHE ERROR " << name() - << " CLEANUP_IVT_CLEAR state" << std::endl - << "Bad IVT allocation" - << std::endl; - - exit(0); - } - - m_ivt.clear(r_cleanup_index.read()); - - if ( r_cleanup_need_rsp.read() ) r_cleanup_fsm = CLEANUP_WRITE_RSP; - else if ( r_cleanup_need_ack.read() ) r_cleanup_fsm = CLEANUP_CONFIG_ACK; - else r_cleanup_fsm = CLEANUP_SEND_CLACK; + << " IVT_index = " << r_cleanup_index.read() + << " / rsp_count = " << count << std::endl; +#endif + break; + } + /////////////////////// + case CLEANUP_IVT_CLEAR: // Clear IVT entry + // Acknowledge CONFIG FSM if required + { + assert( (r_alloc_ivt_fsm.read() == ALLOC_IVT_CLEANUP) and + "MEMC ERROR in CLEANUP_IVT_CLEAR state : bad IVT allocation"); + + m_ivt.clear(r_cleanup_index.read()); + + if ( r_cleanup_need_ack.read() ) + { + assert( (r_config_rsp_lines.read() > 0) and + "MEMC ERROR in CLEANUP_IVT_CLEAR state"); + + r_config_rsp_lines = r_config_rsp_lines.read() - 1; + } + + if ( r_cleanup_need_rsp.read() ) r_cleanup_fsm = CLEANUP_WRITE_RSP; + else r_cleanup_fsm = CLEANUP_SEND_CLACK; #if DEBUG_MEMC_CLEANUP @@ -4958,19 +4878,18 @@ << " IVT_index = " << r_cleanup_index.read() << std::endl; #endif - break; - } - /////////////////////// - case CLEANUP_WRITE_RSP: // response to a previous write on the direct network + break; + } + /////////////////////// + case CLEANUP_WRITE_RSP: // response to a previous write on the direct network // wait if pending request to the TGT_RSP FSM - { - if(r_cleanup_to_tgt_rsp_req.read()) break; - - // no pending request - r_cleanup_to_tgt_rsp_req = true; - r_cleanup_to_tgt_rsp_srcid = r_cleanup_write_srcid.read(); - r_cleanup_to_tgt_rsp_trdid = r_cleanup_write_trdid.read(); - r_cleanup_to_tgt_rsp_pktid = r_cleanup_write_pktid.read(); - - r_cleanup_fsm = CLEANUP_SEND_CLACK; + { + if(r_cleanup_to_tgt_rsp_req.read()) break; + + // no pending request + r_cleanup_to_tgt_rsp_req = true; + r_cleanup_to_tgt_rsp_srcid = r_cleanup_write_srcid.read(); + r_cleanup_to_tgt_rsp_trdid = r_cleanup_write_trdid.read(); + r_cleanup_to_tgt_rsp_pktid = r_cleanup_write_pktid.read(); + r_cleanup_fsm = CLEANUP_SEND_CLACK; #if DEBUG_MEMC_CLEANUP @@ -4982,29 +4901,13 @@ << " / rpktid = " << r_cleanup_write_pktid.read() << std::endl; #endif - break; - } - //////////////////////// - case CLEANUP_CONFIG_ACK: // signals inval completion to CONFIG FSM - // wait if pending request - { - if ( r_cleanup_to_config_ack.read() ) break; - - r_cleanup_to_config_ack = true; - r_cleanup_fsm = CLEANUP_SEND_CLACK; - -#if DEBUG_MEMC_CLEANUP -if(m_debug) -std::cout << " " - << " Acknowledge broacast inval completion" << std::endl; -#endif - break; - } - //////////////////////// - case CLEANUP_SEND_CLACK: // acknowledgement to a cleanup command - // on the coherence CLACK network. - { - if(not p_dspin_clack.read) break; - - r_cleanup_fsm = CLEANUP_IDLE; + break; + } + //////////////////////// + case CLEANUP_SEND_CLACK: // acknowledgement to a cleanup command + // on the coherence CLACK network. + { + if(not p_dspin_clack.read) break; + + r_cleanup_fsm = CLEANUP_IDLE; #if DEBUG_MEMC_CLEANUP @@ -5012,11 +4915,11 @@ std::cout << " Send the response to a cleanup request:" - << " nline = " << std::hex << r_cleanup_nline.read() + << " address = " << std::hex << r_cleanup_nline.read()*m_words*4 << " / way = " << std::dec << r_cleanup_way.read() << " / srcid = " << std::dec << r_cleanup_srcid.read() << std::endl; #endif - break; - } + break; + } } // end switch cleanup fsm @@ -5024,12 +4927,11 @@ // CAS FSM //////////////////////////////////////////////////////////////////////////////////// - // The CAS FSM handles the CAS (Store Conditionnal) atomic commands, - // that are handled as "compare-and-swap instructions. + // The CAS FSM handles the CAS (Compare And Swap) atomic commands. // // This command contains two or four flits: // - In case of 32 bits atomic access, the first flit contains the value read - // by a previous LL instruction, the second flit contains the value to be writen. + // by a previous READ instruction, the second flit contains the value to be writen. // - In case of 64 bits atomic access, the 2 first flits contains the value read - // by a previous LL instruction, the 2 next flits contains the value to be writen. + // by a previous READ instruction, the 2 next flits contains the value to be writen. // // The target address is cachable. If it is replicated in other L1 caches @@ -5038,86 +4940,78 @@ // It access the directory to check hit / miss. // - In case of miss, the CAS FSM must register a GET transaction in TRT. - // If a read transaction to the XRAM for this line already exists, - // or if the transaction table is full, it goes to the WAIT state - // to release the locks and try again. When the GET transaction has been - // launched, it goes to the WAIT state and try again. - // The CAS request is not consumed in the FIFO until a HIT is obtained. + // If a read transaction to the XRAM for this line already exists, + // or if the transaction table is full, it goes to the WAIT state + // to release the locks and try again. When the GET transaction has been + // launched, it goes to the WAIT state and try again. + // The CAS request is not consumed in the FIFO until a HIT is obtained. // - In case of hit... /////////////////////////////////////////////////////////////////////////////////// +//std::cout << std::endl << "cas_fsm" << std::endl; + switch(r_cas_fsm.read()) { - ///////////// + //////////// case CAS_IDLE: // fill the local rdata buffers { - if(m_cmd_cas_addr_fifo.rok()) - { + if (m_cmd_cas_addr_fifo.rok() ) + { #if DEBUG_MEMC_CAS - if(m_debug) - { - std::cout << " CAS command: " << std::hex - << " srcid = " << std::dec << m_cmd_cas_srcid_fifo.read() - << " addr = " << std::hex << m_cmd_cas_addr_fifo.read() - << " wdata = " << m_cmd_cas_wdata_fifo.read() - << " eop = " << std::dec << m_cmd_cas_eop_fifo.read() - << " cpt = " << std::dec << r_cas_cpt.read() << std::endl; - } -#endif - if(m_cmd_cas_eop_fifo.read()) - { - m_cpt_cas++; - r_cas_fsm = CAS_DIR_REQ; - } - else // we keep the last word in the FIFO - { - cmd_cas_fifo_get = true; - } - // We fill the two buffers - if(r_cas_cpt.read() < 2) // 32 bits access - r_cas_rdata[r_cas_cpt.read()] = m_cmd_cas_wdata_fifo.read(); - - if((r_cas_cpt.read() == 1) and m_cmd_cas_eop_fifo.read()) - r_cas_wdata = m_cmd_cas_wdata_fifo.read(); - - if(r_cas_cpt.read() >3) // more than 4 flits... - { - std::cout << "VCI_MEM_CACHE ERROR in CAS_IDLE state : illegal CAS command" - << std::endl; - exit(0); - } - - if(r_cas_cpt.read() ==2) - r_cas_wdata = m_cmd_cas_wdata_fifo.read(); - - r_cas_cpt = r_cas_cpt.read() +1; - } - break; - } - +if(m_debug) +std::cout << " CAS command: " << std::hex + << " srcid = " << std::dec << m_cmd_cas_srcid_fifo.read() + << " addr = " << std::hex << m_cmd_cas_addr_fifo.read() + << " wdata = " << m_cmd_cas_wdata_fifo.read() + << " eop = " << std::dec << m_cmd_cas_eop_fifo.read() + << " cpt = " << std::dec << r_cas_cpt.read() << std::endl; +#endif + if(m_cmd_cas_eop_fifo.read()) + { + m_cpt_cas++; + r_cas_fsm = CAS_DIR_REQ; + } + else // we keep the last word in the FIFO + { + cmd_cas_fifo_get = true; + } + + // We fill the two buffers + if(r_cas_cpt.read() < 2) // 32 bits access + r_cas_rdata[r_cas_cpt.read()] = m_cmd_cas_wdata_fifo.read(); + + if((r_cas_cpt.read() == 1) and m_cmd_cas_eop_fifo.read()) + r_cas_wdata = m_cmd_cas_wdata_fifo.read(); + + assert( (r_cas_cpt.read() <= 3) and // no more than 4 flits... + "MEMC ERROR in CAS_IDLE state: illegal CAS command"); + + if(r_cas_cpt.read() ==2) + r_cas_wdata = m_cmd_cas_wdata_fifo.read(); + + r_cas_cpt = r_cas_cpt.read() +1; + } + break; + } ///////////////// case CAS_DIR_REQ: { - if(r_alloc_dir_fsm.read() == ALLOC_DIR_CAS) - { - r_cas_fsm = CAS_DIR_LOCK; - } + if(r_alloc_dir_fsm.read() == ALLOC_DIR_CAS) + { + r_cas_fsm = CAS_DIR_LOCK; + } #if DEBUG_MEMC_CAS - if(m_debug) - { - std::cout - << " Requesting DIR lock " - << std::endl; - } -#endif - break; - } - +if(m_debug) +std::cout << " Requesting DIR lock " << std::endl; +#endif + break; + } ///////////////// case CAS_DIR_LOCK: // Read the directory { - if(r_alloc_dir_fsm.read() == ALLOC_DIR_CAS) - { + assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_CAS) and + "MEMC ERROR in CAS_DIR_LOCK: Bad DIR allocation"); + size_t way = 0; DirectoryEntry entry(m_cache_directory.read(m_cmd_cas_addr_fifo.read(), way)); @@ -5128,7 +5022,4 @@ r_cas_way = way; r_cas_copy = entry.owner.srcid; -#if L1_MULTI_CACHE - r_cas_copy_cache = entry.owner.cache_id; -#endif r_cas_copy_inst = entry.owner.inst; r_cas_ptr = entry.ptr; @@ -5139,25 +5030,13 @@ #if DEBUG_MEMC_CAS - if(m_debug) - { - std::cout << " Directory acces" - << " / address = " << std::hex << m_cmd_cas_addr_fifo.read() - << " / hit = " << std::dec << entry.valid - << " / count = " << entry.count - << " / is_cnt = " << entry.is_cnt << std::endl; - } -#endif - } - else - { - std::cout - << "VCI_MEM_CACHE ERROR " << name() - << " CAS_DIR_LOCK state" << std::endl - << "Bad DIR allocation" << std::endl; - - exit(0); - } - - break; +if(m_debug) +std::cout << " Directory acces" + << " / address = " << std::hex << m_cmd_cas_addr_fifo.read() + << " / hit = " << std::dec << entry.valid + << " / count = " << entry.count + << " / is_cnt = " << entry.is_cnt << std::endl; +#endif + + break; } ///////////////////// @@ -5165,28 +5044,28 @@ // and check data change in cache { - size_t way = r_cas_way.read(); - size_t set = m_y[(addr_t)(m_cmd_cas_addr_fifo.read())]; - - // update directory (lock & dirty bits) - DirectoryEntry entry; - entry.valid = true; - entry.is_cnt = r_cas_is_cnt.read(); - entry.dirty = true; - entry.lock = true; - entry.tag = r_cas_tag.read(); - entry.owner.srcid = r_cas_copy.read(); -#if L1_MULTI_CACHE - entry.owner.cache_id = r_cas_copy_cache.read(); -#endif - entry.owner.inst = r_cas_copy_inst.read(); - entry.count = r_cas_count.read(); - entry.ptr = r_cas_ptr.read(); - - m_cache_directory.write(set, way, entry); - - // Stored data from cache in buffer to do the comparison in next state - m_cache_data.read_line(way, set, r_cas_data); - - r_cas_fsm = CAS_DIR_HIT_COMPARE; + assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_CAS) and + "MEMC ERROR in CAS_DIR_HIT_READ: Bad DIR allocation"); + + size_t way = r_cas_way.read(); + size_t set = m_y[(addr_t)(m_cmd_cas_addr_fifo.read())]; + + // update directory (lock & dirty bits) + DirectoryEntry entry; + entry.valid = true; + entry.is_cnt = r_cas_is_cnt.read(); + entry.dirty = true; + entry.lock = true; + entry.tag = r_cas_tag.read(); + entry.owner.srcid = r_cas_copy.read(); + entry.owner.inst = r_cas_copy_inst.read(); + entry.count = r_cas_count.read(); + entry.ptr = r_cas_ptr.read(); + + m_cache_directory.write(set, way, entry); + + // Store data from cache in buffer to do the comparison in next state + m_cache_data.read_line(way, set, r_cas_data); + + r_cas_fsm = CAS_DIR_HIT_COMPARE; #if DEBUG_MEMC_CAS @@ -5195,12 +5074,12 @@ << " cache and store it in buffer" << std::endl; #endif - break; - } - + break; + } + //////////////////////// case CAS_DIR_HIT_COMPARE: { - size_t word = m_x[(addr_t)(m_cmd_cas_addr_fifo.read())]; - - // Read data in buffer & check data change + size_t word = m_x[(addr_t)(m_cmd_cas_addr_fifo.read())]; + + // check data change bool ok = (r_cas_rdata[0].read() == r_cas_data[word].read()); @@ -5212,22 +5091,13 @@ r_cas_lfsr = (r_cas_lfsr >> 1) ^ ((- (r_cas_lfsr & 1)) & 0xd0000001); - // cas success - if(ok and not forced_fail) - { - r_cas_fsm = CAS_DIR_HIT_WRITE; - } - // cas failure - else - { - r_cas_fsm = CAS_RSP_FAIL; - } + if(ok and not forced_fail) r_cas_fsm = CAS_DIR_HIT_WRITE; + else r_cas_fsm = CAS_RSP_FAIL; #if DEBUG_MEMC_CAS if(m_debug) -std::cout << " Compare the old" - << " and the new data" - << " / expected value = " << r_cas_rdata[0].read() - << " / actual value = " << r_cas_data[word].read() - << " / forced_fail = " << forced_fail << std::endl; +std::cout << " Compare old and new data" + << " / expected value = " << std::hex << r_cas_rdata[0].read() + << " / actual value = " << std::hex << r_cas_data[word].read() + << " / forced_fail = " << std::dec << forced_fail << std::endl; #endif break; @@ -5235,48 +5105,63 @@ ////////////////////// case CAS_DIR_HIT_WRITE: // test if a CC transaction is required - // write data in cache if no CC request - { - // The CAS is a success => sw access to the llsc_global_table - m_llsc_table.sw(m_nline[(addr_t)m_cmd_cas_addr_fifo.read()],m_x[(addr_t)(m_cmd_cas_addr_fifo.read())],m_x[(addr_t)(m_cmd_cas_addr_fifo.read())]); - - // test coherence request - if(r_cas_count.read()) // replicated line - { - if(r_cas_is_cnt.read()) - { - r_cas_fsm = CAS_BC_TRT_LOCK; // broadcast invalidate required - } - else if(!r_cas_to_cc_send_multi_req.read() and - !r_cas_to_cc_send_brdcast_req.read()) - { - r_cas_fsm = CAS_UPT_LOCK; // multi update required - } - else - { - r_cas_fsm = CAS_WAIT; - } - } - else // no copies - { - size_t way = r_cas_way.read(); - size_t set = m_y[(addr_t)(m_cmd_cas_addr_fifo.read())]; - size_t word = m_x[(addr_t)(m_cmd_cas_addr_fifo.read())]; - - // cache update - m_cache_data.write(way, set, word, r_cas_wdata.read()); - if(r_cas_cpt.read() == 4) - m_cache_data.write(way, set, word+1, m_cmd_cas_wdata_fifo.read()); - - r_cas_fsm = CAS_RSP_SUCCESS; - - // monitor - if(m_monitor_ok) - { - addr_t address = m_cmd_cas_addr_fifo.read(); - check_monitor( address, r_cas_wdata.read(), false); - - if(r_cas_cpt.read() == 4) - check_monitor( address+4, m_cmd_cas_wdata_fifo.read(), false); - } + // write data in cache if no CC request + { + assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_CAS) and + "MEMC ERROR in CAS_DIR_HIT_WRITE: Bad DIR allocation"); + + // The CAS is a success => sw access to the llsc_global_table + m_llsc_table.sw( m_nline[(addr_t)m_cmd_cas_addr_fifo.read()], + m_x[(addr_t)(m_cmd_cas_addr_fifo.read())], + m_x[(addr_t)(m_cmd_cas_addr_fifo.read())] ); + + // test coherence request + if(r_cas_count.read()) // replicated line + { + if(r_cas_is_cnt.read()) + { + r_cas_fsm = CAS_BC_TRT_LOCK; // broadcast invalidate required + +#if DEBUG_MEMC_CAS +if(m_debug) +std::cout << " " + << " Broacast Inval required" + << " / copies = " << r_cas_count.read() << std::endl; +#endif + } + else if( not r_cas_to_cc_send_multi_req.read() and + not r_cas_to_cc_send_brdcast_req.read() ) + { + r_cas_fsm = CAS_UPT_LOCK; // multi update required + +#if DEBUG_MEMC_CAS +if(m_debug) +std::cout << " " + << " Multi Inval required" + << " / copies = " << r_cas_count.read() << std::endl; +#endif + } + else + { + r_cas_fsm = CAS_WAIT; + +#if DEBUG_MEMC_CAS +if(m_debug) +std::cout << " " + << " CC_SEND FSM busy: release all locks and retry" << std::endl; +#endif + } + } + else // no copies + { + size_t way = r_cas_way.read(); + size_t set = m_y[(addr_t)(m_cmd_cas_addr_fifo.read())]; + size_t word = m_x[(addr_t)(m_cmd_cas_addr_fifo.read())]; + + // cache update + m_cache_data.write(way, set, word, r_cas_wdata.read()); + if(r_cas_cpt.read() == 4) + m_cache_data.write(way, set, word+1, m_cmd_cas_wdata_fifo.read()); + + r_cas_fsm = CAS_RSP_SUCCESS; #if DEBUG_MEMC_CAS @@ -5295,55 +5180,45 @@ ///////////////// case CAS_UPT_LOCK: // try to register the transaction in UPT - // and write data in cache if successful registration - // releases locks to retry later if UPT full - { - if(r_alloc_upt_fsm.read() == ALLOC_UPT_CAS) - { - bool wok = false; - size_t index = 0; - size_t srcid = m_cmd_cas_srcid_fifo.read(); - size_t trdid = m_cmd_cas_trdid_fifo.read(); - size_t pktid = m_cmd_cas_pktid_fifo.read(); - addr_t nline = m_nline[(addr_t)(m_cmd_cas_addr_fifo.read())]; - size_t nb_copies = r_cas_count.read(); - - wok = m_upt.set(true, // it's an update transaction - false, // it's not a broadcast - true, // response required - false, // no acknowledge required - srcid, - trdid, - pktid, - nline, - nb_copies, - index); - if(wok) // coherence transaction registered in UPT - { - // cache update - size_t way = r_cas_way.read(); - size_t set = m_y[(addr_t)(m_cmd_cas_addr_fifo.read())]; - size_t word = m_x[(addr_t)(m_cmd_cas_addr_fifo.read())]; - - m_cache_data.write(way, set, word, r_cas_wdata.read()); - if(r_cas_cpt.read() ==4) - m_cache_data.write(way, set, word+1, m_cmd_cas_wdata_fifo.read()); - - r_cas_upt_index = index; - r_cas_fsm = CAS_UPT_HEAP_LOCK; - - // monitor - if(m_monitor_ok) - { - addr_t address = m_cmd_cas_addr_fifo.read(); - check_monitor( address, r_cas_wdata.read(), false); - - if(r_cas_cpt.read() ==4) - check_monitor( address+4, m_cmd_cas_wdata_fifo.read(), false); - } - } - else // releases the locks protecting UPT and DIR UPT full - { - r_cas_fsm = CAS_WAIT; - } + // and write data in cache if successful registration + // releases locks to retry later if UPT full + { + if(r_alloc_upt_fsm.read() == ALLOC_UPT_CAS) + { + bool wok = false; + size_t index = 0; + size_t srcid = m_cmd_cas_srcid_fifo.read(); + size_t trdid = m_cmd_cas_trdid_fifo.read(); + size_t pktid = m_cmd_cas_pktid_fifo.read(); + addr_t nline = m_nline[(addr_t)(m_cmd_cas_addr_fifo.read())]; + size_t nb_copies = r_cas_count.read(); + + wok = m_upt.set( true, // it's an update transaction + false, // it's not a broadcast + true, // response required + false, // no acknowledge required + srcid, + trdid, + pktid, + nline, + nb_copies, + index); + if(wok) // coherence transaction registered in UPT + { + // cache update + size_t way = r_cas_way.read(); + size_t set = m_y[(addr_t)(m_cmd_cas_addr_fifo.read())]; + size_t word = m_x[(addr_t)(m_cmd_cas_addr_fifo.read())]; + + m_cache_data.write(way, set, word, r_cas_wdata.read()); + if(r_cas_cpt.read() ==4) + m_cache_data.write(way, set, word+1, m_cmd_cas_wdata_fifo.read()); + + r_cas_upt_index = index; + r_cas_fsm = CAS_UPT_HEAP_LOCK; + } + else // releases the locks protecting UPT and DIR UPT full + { + r_cas_fsm = CAS_WAIT; + } #if DEBUG_MEMC_CAS @@ -5352,9 +5227,9 @@ << " CAS_UPT_LOCK> Register multi-update transaction in UPT" << " / wok = " << wok - << " / nline = " << std::hex << nline + << " / address = " << std::hex << nline*m_words*4 << " / count = " << nb_copies << std::endl; #endif - } - break; + } + break; } ///////////// @@ -5363,14 +5238,11 @@ #if DEBUG_MEMC_CAS - if(m_debug) - { - std::cout << " Release all locks" << std::endl; - } -#endif - r_cas_fsm = CAS_DIR_REQ; - break; - } - ////////////////// +if(m_debug) +std::cout << " Release all locks" << std::endl; +#endif + r_cas_fsm = CAS_DIR_REQ; + break; + } + ////////////////////// case CAS_UPT_HEAP_LOCK: // lock the heap { @@ -5418,7 +5290,4 @@ cas_to_cc_send_fifo_inst = r_cas_copy_inst.read(); cas_to_cc_send_fifo_srcid = r_cas_copy.read(); -#if L1_MULTI_CACHE - cas_to_cc_send_fifo_cache_id= r_cas_copy_cache.read(); -#endif if(r_cas_count.read() == 1) // one single copy { @@ -5455,7 +5324,4 @@ HeapEntry entry = m_heap.read(r_cas_ptr.read()); cas_to_cc_send_fifo_srcid = entry.owner.srcid; -#if L1_MULTI_CACHE - cas_to_cc_send_fifo_cache_id = entry.owner.cache_id; -#endif cas_to_cc_send_fifo_inst = entry.owner.inst; cas_to_cc_send_fifo_put = true; @@ -5487,130 +5353,109 @@ } ///////////////////// - case CAS_BC_TRT_LOCK: // check the TRT to register a PUT transaction - { - if(r_alloc_trt_fsm.read() == ALLOC_TRT_CAS) - { - if(!r_cas_to_ixr_cmd_req) // we can transfer the request to IXR_CMD FSM - { - // fill the data buffer - size_t word = m_x[(addr_t)(m_cmd_cas_addr_fifo.read())]; - for(size_t i = 0; i Check TRT" + << " : wok = " << wok << " / index = " << wok_index << std::endl; +#endif + } + break; } ///////////////////// - case CAS_BC_IVT_LOCK: // register a broadcast inval transaction in IVT - // write data in cache in case of successful registration - { - if(r_alloc_ivt_fsm.read() == ALLOC_IVT_CAS) - { - bool wok = false; - size_t index = 0; - size_t srcid = m_cmd_cas_srcid_fifo.read(); - size_t trdid = m_cmd_cas_trdid_fifo.read(); - size_t pktid = m_cmd_cas_pktid_fifo.read(); - addr_t nline = m_nline[(addr_t)(m_cmd_cas_addr_fifo.read())]; - size_t nb_copies = r_cas_count.read(); - - // register a broadcast inval transaction in IVT - wok = m_ivt.set(false, // it's an inval transaction - true, // it's a broadcast - true, // response required - false, // no acknowledge required - srcid, - trdid, - pktid, - nline, - nb_copies, - index); - - if(wok) // IVT not full - { - // cache update - size_t way = r_cas_way.read(); - size_t set = m_y[(addr_t)(m_cmd_cas_addr_fifo.read())]; - size_t word = m_x[(addr_t)(m_cmd_cas_addr_fifo.read())]; - - m_cache_data.write(way, set, word, r_cas_wdata.read()); - if(r_cas_cpt.read() ==4) - m_cache_data.write(way, set, word+1, m_cmd_cas_wdata_fifo.read()); - - // monitor - if(m_monitor_ok) - { - addr_t address = m_cmd_cas_addr_fifo.read(); - check_monitor( address, r_cas_wdata.read(), false); - - if(r_cas_cpt.read() ==4) - check_monitor( address+4, m_cmd_cas_wdata_fifo.read(), false); - } - r_cas_upt_index = index; - r_cas_fsm = CAS_BC_DIR_INVAL; - + case CAS_BC_IVT_LOCK: // get IVT lock and register BC transaction in IVT + { + assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_CAS) and + "MEMC ERROR in CAS_BC_IVT_LOCK state: Bas DIR allocation"); + + assert( (r_alloc_trt_fsm.read() == ALLOC_TRT_CAS) and + "MEMC ERROR in CAS_BC_IVT_LOCK state: Bas TRT allocation"); + + if( r_alloc_ivt_fsm.read() == ALLOC_IVT_CAS ) + { + // register broadcast inval transaction in IVT + bool wok = false; + size_t index = 0; + size_t srcid = m_cmd_cas_srcid_fifo.read(); + size_t trdid = m_cmd_cas_trdid_fifo.read(); + size_t pktid = m_cmd_cas_pktid_fifo.read(); + addr_t nline = m_nline[(addr_t)(m_cmd_cas_addr_fifo.read())]; + size_t nb_copies = r_cas_count.read(); + + wok = m_ivt.set( false, // it's an inval transaction + true, // it's a broadcast + true, // response required + false, // no acknowledge required + srcid, + trdid, + pktid, + nline, + nb_copies, + index); #if DEBUG_MEMC_CAS -if(m_debug) -std::cout << " Register a broadcast inval transaction in IVT" - << " / nline = " << std::hex << nline - << " / count = " << std::dec << nb_copies - << " / ivt_index = " << index << std::endl; -#endif - } - else // releases the lock protecting IVT - { - r_cas_fsm = CAS_WAIT; - } - } - break; +if( m_debug and wok ) +std::cout << " Register broadcast inval in IVT" + << " / copies = " << r_cas_count.read() << std::endl; +#endif + r_cas_upt_index = index; + if( wok ) r_cas_fsm = CAS_BC_DIR_INVAL; + else r_cas_fsm = CAS_WAIT; + } + break; } ////////////////////// - case CAS_BC_DIR_INVAL: // Register the PUT transaction in TRT, and inval the DIR entry - { - if((r_alloc_trt_fsm.read() == ALLOC_TRT_CAS) and - (r_alloc_ivt_fsm.read() == ALLOC_IVT_CAS) and - (r_alloc_dir_fsm.read() == ALLOC_DIR_CAS)) - { + case CAS_BC_DIR_INVAL: // Register PUT transaction in TRT, + // and inval the DIR entry + { + assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_CAS) and + "MEMC ERROR in CAS_BC_DIR_INVAL state: Bad DIR allocation"); + + assert( (r_alloc_trt_fsm.read() == ALLOC_TRT_CAS) and + "MEMC ERROR in CAS_BC_DIR_INVAL state: Bad TRT allocation"); + + assert( (r_alloc_ivt_fsm.read() == ALLOC_IVT_CAS) and + "MEMC ERROR in CAS_BC_DIR_INVAL state: Bad IVT allocation"); + // set TRT - m_trt.set(r_cas_trt_index.read(), - false, // PUT request to XRAM - m_nline[(addr_t)(m_cmd_cas_addr_fifo.read())], - 0, - 0, - 0, - false, // not a processor read - 0, - 0, - std::vector (m_words,0), - std::vector (m_words,0)); + std::vector data_vector; + data_vector.clear(); + size_t word = m_x[(addr_t)(m_cmd_cas_addr_fifo.read())]; + for(size_t i=0; i (m_words,0), + data_vector ); // invalidate directory entry @@ -5618,16 +5463,14 @@ entry.valid = false; entry.dirty = false; - entry.tag = 0; + entry.tag = 0; entry.is_cnt = false; entry.lock = false; entry.count = 0; entry.owner.srcid = 0; -#if L1_MULTI_CACHE - entry.owner.cache_id= 0; -#endif entry.owner.inst = false; entry.ptr = 0; size_t set = m_y[(addr_t)(m_cmd_cas_addr_fifo.read())]; size_t way = r_cas_way.read(); + m_cache_directory.write(set, way, entry); @@ -5636,45 +5479,43 @@ #if DEBUG_MEMC_CAS if(m_debug) -std::cout << " Register the PUT in TRT and invalidate DIR entry" - << " / nline = " << std::hex << m_nline[(addr_t)(m_cmd_cas_addr_fifo.read())] - << " / set = " << std::dec << set << " / way = " << way << std::endl; -#endif - } - else - { - assert(false and "LOCK ERROR in CAS_FSM, STATE = CAS_BC_DIR_INVAL"); - } - break; +std::cout << " Inval DIR & register in TRT:" + << " address = " << m_cmd_cas_addr_fifo.read() << std::endl; +#endif + break; } /////////////////// case CAS_BC_CC_SEND: // Request the broadcast inval to CC_SEND FSM { - if(!r_cas_to_cc_send_multi_req.read() and - !r_cas_to_cc_send_brdcast_req.read()) - { - r_cas_to_cc_send_multi_req = false; - r_cas_to_cc_send_brdcast_req = true; - r_cas_to_cc_send_trdid = r_cas_upt_index.read(); - r_cas_to_cc_send_nline = m_nline[(addr_t)(m_cmd_cas_addr_fifo.read())]; - r_cas_to_cc_send_index = 0; - r_cas_to_cc_send_wdata = 0; - - r_cas_fsm = CAS_BC_XRAM_REQ; - } - break; + if( not r_cas_to_cc_send_multi_req.read() and + not r_cas_to_cc_send_brdcast_req.read() ) + { + r_cas_to_cc_send_multi_req = false; + r_cas_to_cc_send_brdcast_req = true; + r_cas_to_cc_send_trdid = r_cas_upt_index.read(); + r_cas_to_cc_send_nline = m_nline[(addr_t)(m_cmd_cas_addr_fifo.read())]; + r_cas_to_cc_send_index = 0; + r_cas_to_cc_send_wdata = 0; + + r_cas_fsm = CAS_BC_XRAM_REQ; + +#if DEBUG_MEMC_CAS +if(m_debug) +std::cout << " Post a broadcast request to CC_SEND FSM" << std::endl; +#endif + } + break; } //////////////////// - case CAS_BC_XRAM_REQ: // request the IXR FSM to start a put transaction - { - if(!r_cas_to_ixr_cmd_req) - { - r_cas_to_ixr_cmd_req = true; - r_cas_to_ixr_cmd_write = true; - r_cas_to_ixr_cmd_nline = m_nline[(addr_t)(m_cmd_cas_addr_fifo.read())]; - r_cas_to_ixr_cmd_trdid = r_cas_trt_index.read(); - r_cas_fsm = CAS_IDLE; - cmd_cas_fifo_get = true; - r_cas_cpt = 0; + case CAS_BC_XRAM_REQ: // request the IXR FSM to start a PUT transaction + { + if( not r_cas_to_ixr_cmd_req.read() ) + { + r_cas_to_ixr_cmd_req = true; + r_cas_to_ixr_cmd_put = true; + r_cas_to_ixr_cmd_index = r_cas_trt_index.read(); + r_cas_fsm = CAS_IDLE; + cmd_cas_fifo_get = true; + r_cas_cpt = 0; #if DEBUG_MEMC_CAS @@ -5682,28 +5523,23 @@ std::cout << " Request a PUT transaction to IXR_CMD FSM" << std::hex - << " / nline = " << m_nline[(addr_t) m_cmd_cas_addr_fifo.read()] + << " / address = " << (addr_t) m_cmd_cas_addr_fifo.read() << " / trt_index = " << r_cas_trt_index.read() << std::endl; #endif - } - else - { - std::cout << "ERROR in MEM_CACHE / CAS_BC_XRAM_REQ state" - << " : request should not have been previously set" << std::endl; - } - break; + } + break; } ///////////////// case CAS_RSP_FAIL: // request TGT_RSP FSM to send a failure response { - if(!r_cas_to_tgt_rsp_req) - { - cmd_cas_fifo_get = true; - r_cas_cpt = 0; - r_cas_to_tgt_rsp_req = true; - r_cas_to_tgt_rsp_data = 1; - r_cas_to_tgt_rsp_srcid = m_cmd_cas_srcid_fifo.read(); - r_cas_to_tgt_rsp_trdid = m_cmd_cas_trdid_fifo.read(); - r_cas_to_tgt_rsp_pktid = m_cmd_cas_pktid_fifo.read(); - r_cas_fsm = CAS_IDLE; + if( not r_cas_to_tgt_rsp_req.read() ) + { + cmd_cas_fifo_get = true; + r_cas_cpt = 0; + r_cas_to_tgt_rsp_req = true; + r_cas_to_tgt_rsp_data = 1; + r_cas_to_tgt_rsp_srcid = m_cmd_cas_srcid_fifo.read(); + r_cas_to_tgt_rsp_trdid = m_cmd_cas_trdid_fifo.read(); + r_cas_to_tgt_rsp_pktid = m_cmd_cas_pktid_fifo.read(); + r_cas_fsm = CAS_IDLE; #if DEBUG_MEMC_CAS @@ -5712,20 +5548,20 @@ << " CAS_RSP_FAIL> Request TGT_RSP to send a failure response" << std::endl; #endif - } - break; + } + break; } //////////////////// case CAS_RSP_SUCCESS: // request TGT_RSP FSM to send a success response { - if(!r_cas_to_tgt_rsp_req) - { - cmd_cas_fifo_get = true; - r_cas_cpt = 0; - r_cas_to_tgt_rsp_req = true; - r_cas_to_tgt_rsp_data = 0; - r_cas_to_tgt_rsp_srcid = m_cmd_cas_srcid_fifo.read(); - r_cas_to_tgt_rsp_trdid = m_cmd_cas_trdid_fifo.read(); - r_cas_to_tgt_rsp_pktid = m_cmd_cas_pktid_fifo.read(); - r_cas_fsm = CAS_IDLE; + if( not r_cas_to_tgt_rsp_req.read() ) + { + cmd_cas_fifo_get = true; + r_cas_cpt = 0; + r_cas_to_tgt_rsp_req = true; + r_cas_to_tgt_rsp_data = 0; + r_cas_to_tgt_rsp_srcid = m_cmd_cas_srcid_fifo.read(); + r_cas_to_tgt_rsp_trdid = m_cmd_cas_trdid_fifo.read(); + r_cas_to_tgt_rsp_pktid = m_cmd_cas_pktid_fifo.read(); + r_cas_fsm = CAS_IDLE; #if DEBUG_MEMC_CAS @@ -5734,47 +5570,46 @@ << " CAS_RSP_SUCCESS> Request TGT_RSP to send a success response" << std::endl; #endif - } - break; - } - ///////////////////// + } + break; + } + /////////////////////// case CAS_MISS_TRT_LOCK: // cache miss : request access to transaction Table { - if(r_alloc_trt_fsm.read() == ALLOC_TRT_CAS) - { - size_t index = 0; - bool hit_read = m_trt.hit_read( - m_nline[(addr_t) m_cmd_cas_addr_fifo.read()],index); - bool hit_write = m_trt.hit_write( - m_nline[(addr_t) m_cmd_cas_addr_fifo.read()]); - bool wok = !m_trt.full(index); + if(r_alloc_trt_fsm.read() == ALLOC_TRT_CAS) + { + size_t index = 0; + bool hit_read = m_trt.hit_read( + m_nline[(addr_t) m_cmd_cas_addr_fifo.read()],index); + bool hit_write = m_trt.hit_write( + m_nline[(addr_t) m_cmd_cas_addr_fifo.read()]); + bool wok = not m_trt.full(index); #if DEBUG_MEMC_CAS - if(m_debug) - { - std::cout << " Check TRT state" - << " / hit_read = " << hit_read - << " / hit_write = " << hit_write - << " / wok = " << wok - << " / index = " << index << std::endl; - } -#endif - - if(hit_read or !wok or hit_write) // missing line already requested or no space in TRT - { - r_cas_fsm = CAS_WAIT; - } - else - { - r_cas_trt_index = index; - r_cas_fsm = CAS_MISS_TRT_SET; - } - } - break; - } - //////////////////// +if(m_debug) +std::cout << " Check TRT state" + << " / hit_read = " << hit_read + << " / hit_write = " << hit_write + << " / wok = " << wok + << " / index = " << index << std::endl; +#endif + + if(hit_read or !wok or hit_write) // missing line already requested or TRT full + { + r_cas_fsm = CAS_WAIT; + } + else + { + r_cas_trt_index = index; + r_cas_fsm = CAS_MISS_TRT_SET; + } + } + break; + } + ////////////////////// case CAS_MISS_TRT_SET: // register the GET transaction in TRT { - if(r_alloc_trt_fsm.read() == ALLOC_TRT_CAS) - { + assert( (r_alloc_trt_fsm.read() == ALLOC_TRT_CAS) and + "MEMC ERROR in CAS_MISS_TRT_SET state: Bad TRT allocation"); + std::vector be_vector; std::vector data_vector; @@ -5787,49 +5622,44 @@ } - m_trt.set(r_cas_trt_index.read(), - true, // read request - m_nline[(addr_t) m_cmd_cas_addr_fifo.read()], - m_cmd_cas_srcid_fifo.read(), - m_cmd_cas_trdid_fifo.read(), - m_cmd_cas_pktid_fifo.read(), - false, // write request from processor - 0, - 0, - be_vector, - data_vector); + m_trt.set( r_cas_trt_index.read(), + true, // GET + m_nline[(addr_t) m_cmd_cas_addr_fifo.read()], + m_cmd_cas_srcid_fifo.read(), + m_cmd_cas_trdid_fifo.read(), + m_cmd_cas_pktid_fifo.read(), + false, // write request from processor + 0, + 0, + std::vector(m_words,0), + std::vector(m_words,0) ); + r_cas_fsm = CAS_MISS_XRAM_REQ; #if DEBUG_MEMC_CAS - if(m_debug) - { - std::cout << " Register a GET transaction in TRT" << std::hex - << " / nline = " << m_nline[(addr_t) m_cmd_cas_addr_fifo.read()] - << " / trt_index = " << r_cas_trt_index.read() << std::endl; - } -#endif - } - break; +if(m_debug) +std::cout << " Register GET transaction in TRT" + << " / address = " << std::hex << (addr_t)m_cmd_cas_addr_fifo.read() + << " / trt_index = " << std::dec << r_cas_trt_index.read() << std::endl; +#endif + break; } ////////////////////// - case CAS_MISS_XRAM_REQ: // request the IXR_CMD FSM to fetch the missing line - { - if(!r_cas_to_ixr_cmd_req) - { - r_cas_to_ixr_cmd_req = true; - r_cas_to_ixr_cmd_write = false; - r_cas_to_ixr_cmd_trdid = r_cas_trt_index.read(); - r_cas_to_ixr_cmd_nline = m_nline[(addr_t) m_cmd_cas_addr_fifo.read()]; - r_cas_fsm = CAS_WAIT; + case CAS_MISS_XRAM_REQ: // request the IXR_CMD FSM a GET request + { + if( not r_cas_to_ixr_cmd_req.read() ) + { + r_cas_to_ixr_cmd_req = true; + r_cas_to_ixr_cmd_put = false; + r_cas_to_ixr_cmd_index = r_cas_trt_index.read(); + r_cas_fsm = CAS_WAIT; #if DEBUG_MEMC_CAS - if(m_debug) - { - std::cout << " Request a GET transaction to IXR_CMD FSM" << std::hex - << " / nline = " << m_nline[(addr_t) m_cmd_cas_addr_fifo.read()] - << " / trt_index = " << r_cas_trt_index.read() << std::endl; - } -#endif - } - break; +if(m_debug) +std::cout << " Request a GET transaction" + << " / address = " << std::hex << (addr_t) m_cmd_cas_addr_fifo.read() + << " / trt_index = " << std::dec << r_cas_trt_index.read() << std::endl; +#endif + } + break; } } // end switch r_cas_fsm @@ -5864,4 +5694,6 @@ /////////////////////////////////////////////////////////////////////////////// +//std::cout << std::endl << "cc_send_fsm" << std::endl; + switch(r_cc_send_fsm.read()) { @@ -6264,11 +6096,11 @@ if(m_debug) std::cout << " Multicast-Update for line " - << r_write_to_cc_send_nline.read() << std::endl; + << " CC_SEND_WRITE_UPDT_NLINE> Multicast-Update for address " + << r_write_to_cc_send_nline.read()*m_words*4 << std::endl; #endif break; } ///////////////////////////// - case CC_SEND_WRITE_UPDT_DATA: // send N data flits for a multi-update (from WRITE FSM) + case CC_SEND_WRITE_UPDT_DATA: // send data flits for multi-update (from WRITE FSM) { if(not p_dspin_m2p.read) break; @@ -6302,6 +6134,6 @@ if(m_debug) std::cout << " Broadcast-Inval for line " - << r_cas_to_cc_send_nline.read() << std::endl; + << " CC_SEND_CAS_BRDCAST_NLINE> Broadcast-Inval for address: " + << r_cas_to_cc_send_nline.read()*m_words*4 << std::endl; #endif break; @@ -6340,6 +6172,6 @@ if(m_debug) std::cout << " Multicast-Update for line " - << r_cas_to_cc_send_nline.read() << std::endl; + << " CC_SEND_CAS_UPDT_NLINE> Multicast-Update for address " + << r_cas_to_cc_send_nline.read()*m_words*4 << std::endl; #endif break; @@ -6361,5 +6193,5 @@ } //////////////////////////////// - case CC_SEND_CAS_UPDT_DATA_HIGH: // send second data for a multi-update (from CAS FSM) + case CC_SEND_CAS_UPDT_DATA_HIGH: // send second data for multi-update (from CAS FSM) { if(not p_dspin_m2p.read) break; @@ -6378,4 +6210,6 @@ ////////////////////////////////////////////////////////////////////////////// +//std::cout << std::endl << "cc_receive_fsm" << std::endl; + switch(r_cc_receive_fsm.read()) { @@ -6462,4 +6296,5 @@ } } + ////////////////////////////////////////////////////////////////////////// // TGT_RSP FSM @@ -6480,4 +6315,6 @@ ////////////////////////////////////////////////////////////////////////// +//std::cout << std::endl << "tgt_rsp_fsm" << std::endl; + switch(r_tgt_rsp_fsm.read()) { @@ -6675,5 +6512,5 @@ } ///////////////////// - case TGT_RSP_TGT_CMD: // send the response for a segmentation violation + case TGT_RSP_TGT_CMD: // send the response for a configuration access { if ( p_vci_tgt.rspack ) @@ -6687,8 +6524,9 @@ std::cout << " Segmentation violation response" + << " TGT_RSP_TGT_CMD> Send response for a configuration access" << " / rsrcid = " << std::hex << r_tgt_cmd_to_tgt_rsp_srcid.read() << " / rtrdid = " << r_tgt_cmd_to_tgt_rsp_trdid.read() << " / rpktid = " << r_tgt_cmd_to_tgt_rsp_pktid.read() + << " / error = " << r_tgt_cmd_to_tgt_rsp_error.read() << std::endl; } @@ -6871,4 +6709,7 @@ // The resource is always allocated. ///////////////////////////////////////////////////////////////////////////////////// + +//std::cout << std::endl << "alloc_upt_fsm" << std::endl; + switch(r_alloc_upt_fsm.read()) { @@ -6926,11 +6767,14 @@ // The resource is always allocated. ///////////////////////////////////////////////////////////////////////////////////// + +//std::cout << std::endl << "alloc_ivt_fsm" << std::endl; + switch(r_alloc_ivt_fsm.read()) { - ////////////////////////// + ///////////////////// case ALLOC_IVT_WRITE: // allocated to WRITE FSM if (r_write_fsm.read() != WRITE_BC_IVT_LOCK) { - if (r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK) + if (r_xram_rsp_fsm.read() == XRAM_RSP_IVT_LOCK) r_alloc_ivt_fsm = ALLOC_IVT_XRAM_RSP; @@ -6941,12 +6785,12 @@ r_alloc_ivt_fsm = ALLOC_IVT_CAS; - else if (r_config_fsm.read() == CONFIG_DIR_IVT_LOCK) + else if (r_config_fsm.read() == CONFIG_IVT_LOCK) r_alloc_ivt_fsm = ALLOC_IVT_CONFIG; } break; - ////////////////////////// + //////////////////////// case ALLOC_IVT_XRAM_RSP: // allocated to XRAM_RSP FSM - if(r_xram_rsp_fsm.read() != XRAM_RSP_INVAL_LOCK) + if(r_xram_rsp_fsm.read() != XRAM_RSP_IVT_LOCK) { if(r_cleanup_fsm.read() == CLEANUP_IVT_LOCK) @@ -6956,5 +6800,5 @@ r_alloc_ivt_fsm = ALLOC_IVT_CAS; - else if (r_config_fsm.read() == CONFIG_DIR_IVT_LOCK) + else if (r_config_fsm.read() == CONFIG_IVT_LOCK) r_alloc_ivt_fsm = ALLOC_IVT_CONFIG; @@ -6964,5 +6808,5 @@ break; - ////////////////////////// + /////////////////////// case ALLOC_IVT_CLEANUP: // allocated to CLEANUP FSM if ((r_cleanup_fsm.read() != CLEANUP_IVT_LOCK ) and @@ -6972,5 +6816,5 @@ r_alloc_ivt_fsm = ALLOC_IVT_CAS; - else if (r_config_fsm.read() == CONFIG_DIR_IVT_LOCK) + else if (r_config_fsm.read() == CONFIG_IVT_LOCK) r_alloc_ivt_fsm = ALLOC_IVT_CONFIG; @@ -6978,5 +6822,5 @@ r_alloc_ivt_fsm = ALLOC_IVT_WRITE; - else if (r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK) + else if (r_xram_rsp_fsm.read() == XRAM_RSP_IVT_LOCK) r_alloc_ivt_fsm = ALLOC_IVT_XRAM_RSP; } @@ -6987,5 +6831,5 @@ if (r_cas_fsm.read() != CAS_BC_IVT_LOCK) { - if (r_config_fsm.read() == CONFIG_DIR_IVT_LOCK) + if (r_config_fsm.read() == CONFIG_IVT_LOCK) r_alloc_ivt_fsm = ALLOC_IVT_CONFIG; @@ -6993,5 +6837,5 @@ r_alloc_ivt_fsm = ALLOC_IVT_WRITE; - else if (r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK) + else if (r_xram_rsp_fsm.read() == XRAM_RSP_IVT_LOCK) r_alloc_ivt_fsm = ALLOC_IVT_XRAM_RSP; @@ -7003,10 +6847,10 @@ ////////////////////////// case ALLOC_IVT_CONFIG: // allocated to CONFIG FSM - if (r_config_fsm.read() != CONFIG_DIR_IVT_LOCK) + if (r_config_fsm.read() != CONFIG_IVT_LOCK) { if (r_write_fsm.read() == WRITE_BC_IVT_LOCK) r_alloc_ivt_fsm = ALLOC_IVT_WRITE; - else if (r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK) + else if (r_xram_rsp_fsm.read() == XRAM_RSP_IVT_LOCK) r_alloc_ivt_fsm = ALLOC_IVT_XRAM_RSP; @@ -7030,4 +6874,6 @@ ///////////////////////////////////////////////////////////////////////////////////// +//std::cout << std::endl << "alloc_dir_fsm" << std::endl; + switch(r_alloc_dir_fsm.read()) { @@ -7049,5 +6895,7 @@ if ( (r_config_fsm.read() != CONFIG_DIR_REQ) and (r_config_fsm.read() != CONFIG_DIR_ACCESS) and - (r_config_fsm.read() != CONFIG_DIR_IVT_LOCK) ) + (r_config_fsm.read() != CONFIG_TRT_LOCK) and + (r_config_fsm.read() != CONFIG_TRT_SET) and + (r_config_fsm.read() != CONFIG_IVT_LOCK) ) { if(r_read_fsm.read() == READ_DIR_REQ) @@ -7099,5 +6947,5 @@ if(((r_write_fsm.read() != WRITE_DIR_REQ) and (r_write_fsm.read() != WRITE_DIR_LOCK) and - (r_write_fsm.read() != WRITE_DIR_READ) and + (r_write_fsm.read() != WRITE_BC_DIR_READ) and (r_write_fsm.read() != WRITE_DIR_HIT) and (r_write_fsm.read() != WRITE_BC_TRT_LOCK) and @@ -7194,5 +7042,5 @@ if( (r_xram_rsp_fsm.read() != XRAM_RSP_DIR_LOCK) and (r_xram_rsp_fsm.read() != XRAM_RSP_TRT_COPY) and - (r_xram_rsp_fsm.read() != XRAM_RSP_INVAL_LOCK)) + (r_xram_rsp_fsm.read() != XRAM_RSP_IVT_LOCK)) { if(r_config_fsm.read() == CONFIG_DIR_REQ) @@ -7219,125 +7067,243 @@ //////////////////////////////////////////////////////////////////////////////////// // The ALLOC_TRT fsm allocates the access to the Transaction Table (write buffer) - // with a round robin priority between 4 user FSMs : - // The cyclic priority is READ > WRITE > CAS > XRAM_RSP + // with a round robin priority between 7 user FSMs : + // The priority is READ > WRITE > CAS > IXR_CMD > XRAM_RSP > IXR_RSP > CONFIG // The ressource is always allocated. /////////////////////////////////////////////////////////////////////////////////// +//std::cout << std::endl << "alloc_trt_fsm" << std::endl; + switch(r_alloc_trt_fsm.read()) { - //////////////////// - case ALLOC_TRT_READ: - if(r_read_fsm.read() != READ_TRT_LOCK) - { - if((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) or - (r_write_fsm.read() == WRITE_BC_TRT_LOCK)) - r_alloc_trt_fsm = ALLOC_TRT_WRITE; - - else if((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) or - (r_cas_fsm.read() == CAS_BC_TRT_LOCK)) - r_alloc_trt_fsm = ALLOC_TRT_CAS; - - else if((r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) and - (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP)) - r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP; - - else if((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) or - (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ)) - r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP; - } - break; - - ///////////////////// - case ALLOC_TRT_WRITE: - if((r_write_fsm.read() != WRITE_MISS_TRT_LOCK) and - (r_write_fsm.read() != WRITE_BC_TRT_LOCK) and - (r_write_fsm.read() != WRITE_BC_IVT_LOCK)) - { - if((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) or - (r_cas_fsm.read() == CAS_BC_TRT_LOCK)) - r_alloc_trt_fsm = ALLOC_TRT_CAS; - - else if((r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) and - (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP)) - r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP; - - else if((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) or - (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ)) - r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP; - - else if(r_read_fsm.read() == READ_TRT_LOCK) - r_alloc_trt_fsm = ALLOC_TRT_READ; - } - break; - - //////////////////// - case ALLOC_TRT_CAS: - if((r_cas_fsm.read() != CAS_MISS_TRT_LOCK) and - (r_cas_fsm.read() != CAS_BC_TRT_LOCK) and - (r_cas_fsm.read() != CAS_BC_IVT_LOCK)) - { - if((r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) and - (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP)) - r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP; - - else if((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) or - (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ)) - r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP; - - else if(r_read_fsm.read() == READ_TRT_LOCK) - r_alloc_trt_fsm = ALLOC_TRT_READ; - - else if((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) or - (r_write_fsm.read() == WRITE_BC_TRT_LOCK)) - r_alloc_trt_fsm = ALLOC_TRT_WRITE; - } - break; - - //////////////////////// - case ALLOC_TRT_XRAM_RSP: - if(((r_xram_rsp_fsm.read() != XRAM_RSP_DIR_LOCK) or - (r_alloc_dir_fsm.read() != ALLOC_DIR_XRAM_RSP)) and - (r_xram_rsp_fsm.read() != XRAM_RSP_TRT_COPY) and - (r_xram_rsp_fsm.read() != XRAM_RSP_DIR_UPDT) and - (r_xram_rsp_fsm.read() != XRAM_RSP_INVAL_LOCK)) - { - if((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) or - (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ)) - r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP; - - else if(r_read_fsm.read() == READ_TRT_LOCK) - r_alloc_trt_fsm = ALLOC_TRT_READ; - - else if((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) or - (r_write_fsm.read() == WRITE_BC_TRT_LOCK)) - r_alloc_trt_fsm = ALLOC_TRT_WRITE; - - else if((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) or - (r_cas_fsm.read() == CAS_BC_TRT_LOCK)) - r_alloc_trt_fsm = ALLOC_TRT_CAS; - } - break; - - //////////////////////// - case ALLOC_TRT_IXR_RSP: - if((r_ixr_rsp_fsm.read() != IXR_RSP_TRT_ERASE) and - (r_ixr_rsp_fsm.read() != IXR_RSP_TRT_READ)) - { - if(r_read_fsm.read() == READ_TRT_LOCK) - r_alloc_trt_fsm = ALLOC_TRT_READ; - - else if((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) or - (r_write_fsm.read() == WRITE_BC_TRT_LOCK)) - r_alloc_trt_fsm = ALLOC_TRT_WRITE; - - else if((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) or - (r_cas_fsm.read() == CAS_BC_TRT_LOCK)) - r_alloc_trt_fsm = ALLOC_TRT_CAS; - - else if((r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) and - (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP)) - r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP; - } - break; + //////////////////// + case ALLOC_TRT_READ: + if(r_read_fsm.read() != READ_TRT_LOCK) + { + if((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) or + (r_write_fsm.read() == WRITE_BC_TRT_LOCK)) + r_alloc_trt_fsm = ALLOC_TRT_WRITE; + + else if((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) or + (r_cas_fsm.read() == CAS_BC_TRT_LOCK)) + r_alloc_trt_fsm = ALLOC_TRT_CAS; + + else if((r_ixr_cmd_fsm.read() == IXR_CMD_READ_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_WRITE_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_CAS_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_XRAM_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_CONFIG_TRT) ) + r_alloc_trt_fsm = ALLOC_TRT_IXR_CMD; + + else if((r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) and + (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP)) + r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP; + + else if((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) or + (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ)) + r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP; + + else if( r_config_fsm.read() == CONFIG_TRT_LOCK ) + r_alloc_trt_fsm = ALLOC_TRT_CONFIG; + } + break; + + ///////////////////// + case ALLOC_TRT_WRITE: + if((r_write_fsm.read() != WRITE_MISS_TRT_LOCK) and + (r_write_fsm.read() != WRITE_BC_TRT_LOCK) and + (r_write_fsm.read() != WRITE_BC_IVT_LOCK)) + { + if((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) or + (r_cas_fsm.read() == CAS_BC_TRT_LOCK)) + r_alloc_trt_fsm = ALLOC_TRT_CAS; + + else if((r_ixr_cmd_fsm.read() == IXR_CMD_READ_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_WRITE_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_CAS_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_XRAM_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_CONFIG_TRT) ) + r_alloc_trt_fsm = ALLOC_TRT_IXR_CMD; + + else if((r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) and + (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP)) + r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP; + + else if((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) or + (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ)) + r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP; + + else if( r_config_fsm.read() == CONFIG_TRT_LOCK ) + r_alloc_trt_fsm = ALLOC_TRT_CONFIG; + + else if(r_read_fsm.read() == READ_TRT_LOCK) + r_alloc_trt_fsm = ALLOC_TRT_READ; + } + break; + + /////////////////// + case ALLOC_TRT_CAS: + if((r_cas_fsm.read() != CAS_MISS_TRT_LOCK) and + (r_cas_fsm.read() != CAS_BC_TRT_LOCK) and + (r_cas_fsm.read() != CAS_BC_IVT_LOCK)) + { + if((r_ixr_cmd_fsm.read() == IXR_CMD_READ_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_WRITE_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_CAS_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_XRAM_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_CONFIG_TRT) ) + r_alloc_trt_fsm = ALLOC_TRT_IXR_CMD; + + if((r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) and + (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP)) + r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP; + + else if((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) or + (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ)) + r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP; + + else if( r_config_fsm.read() == CONFIG_TRT_LOCK ) + r_alloc_trt_fsm = ALLOC_TRT_CONFIG; + + else if(r_read_fsm.read() == READ_TRT_LOCK) + r_alloc_trt_fsm = ALLOC_TRT_READ; + + else if((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) or + (r_write_fsm.read() == WRITE_BC_TRT_LOCK)) + r_alloc_trt_fsm = ALLOC_TRT_WRITE; + } + break; + + /////////////////////// + case ALLOC_TRT_IXR_CMD: + if((r_ixr_cmd_fsm.read() != IXR_CMD_READ_TRT) and + (r_ixr_cmd_fsm.read() != IXR_CMD_WRITE_TRT) and + (r_ixr_cmd_fsm.read() != IXR_CMD_CAS_TRT) and + (r_ixr_cmd_fsm.read() != IXR_CMD_XRAM_TRT) and + (r_ixr_cmd_fsm.read() != IXR_CMD_CONFIG_TRT)) + { + if((r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) and + (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP)) + r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP; + + else if((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) or + (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ)) + r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP; + + else if( r_config_fsm.read() == CONFIG_TRT_LOCK ) + r_alloc_trt_fsm = ALLOC_TRT_CONFIG; + + else if(r_read_fsm.read() == READ_TRT_LOCK) + r_alloc_trt_fsm = ALLOC_TRT_READ; + + else if((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) or + (r_write_fsm.read() == WRITE_BC_TRT_LOCK)) + r_alloc_trt_fsm = ALLOC_TRT_WRITE; + + else if((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) or + (r_cas_fsm.read() == CAS_BC_TRT_LOCK)) + r_alloc_trt_fsm = ALLOC_TRT_CAS; + } + break; + + //////////////////////// + case ALLOC_TRT_XRAM_RSP: + if(((r_xram_rsp_fsm.read() != XRAM_RSP_DIR_LOCK) or + (r_alloc_dir_fsm.read() != ALLOC_DIR_XRAM_RSP)) and + (r_xram_rsp_fsm.read() != XRAM_RSP_TRT_COPY) and + (r_xram_rsp_fsm.read() != XRAM_RSP_DIR_UPDT) and + (r_xram_rsp_fsm.read() != XRAM_RSP_IVT_LOCK)) + { + if((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) or + (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ)) + r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP; + + else if( r_config_fsm.read() == CONFIG_TRT_LOCK ) + r_alloc_trt_fsm = ALLOC_TRT_CONFIG; + + else if(r_read_fsm.read() == READ_TRT_LOCK) + r_alloc_trt_fsm = ALLOC_TRT_READ; + + else if((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) or + (r_write_fsm.read() == WRITE_BC_TRT_LOCK)) + r_alloc_trt_fsm = ALLOC_TRT_WRITE; + + else if((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) or + (r_cas_fsm.read() == CAS_BC_TRT_LOCK)) + r_alloc_trt_fsm = ALLOC_TRT_CAS; + + else if((r_ixr_cmd_fsm.read() == IXR_CMD_READ_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_WRITE_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_CAS_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_XRAM_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_CONFIG_TRT) ) + r_alloc_trt_fsm = ALLOC_TRT_IXR_CMD; + + } + break; + + /////////////////////// + case ALLOC_TRT_IXR_RSP: + if((r_ixr_rsp_fsm.read() != IXR_RSP_TRT_ERASE) and + (r_ixr_rsp_fsm.read() != IXR_RSP_TRT_READ)) + { + if(r_config_fsm.read() == CONFIG_TRT_LOCK) + r_alloc_trt_fsm = ALLOC_TRT_CONFIG; + + else if(r_read_fsm.read() == READ_TRT_LOCK) + r_alloc_trt_fsm = ALLOC_TRT_READ; + + else if((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) or + (r_write_fsm.read() == WRITE_BC_TRT_LOCK)) + r_alloc_trt_fsm = ALLOC_TRT_WRITE; + + else if((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) or + (r_cas_fsm.read() == CAS_BC_TRT_LOCK)) + r_alloc_trt_fsm = ALLOC_TRT_CAS; + + else if((r_ixr_cmd_fsm.read() == IXR_CMD_READ_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_WRITE_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_CAS_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_XRAM_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_CONFIG_TRT) ) + r_alloc_trt_fsm = ALLOC_TRT_IXR_CMD; + + else if((r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) and + (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP)) + r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP; + } + break; + + ////////////////////// + case ALLOC_TRT_CONFIG: + if((r_config_fsm.read() != CONFIG_TRT_LOCK) and + (r_config_fsm.read() != CONFIG_TRT_SET)) + { + if(r_read_fsm.read() == READ_TRT_LOCK) + r_alloc_trt_fsm = ALLOC_TRT_READ; + + else if((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) or + (r_write_fsm.read() == WRITE_BC_TRT_LOCK)) + r_alloc_trt_fsm = ALLOC_TRT_WRITE; + + else if((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) or + (r_cas_fsm.read() == CAS_BC_TRT_LOCK)) + r_alloc_trt_fsm = ALLOC_TRT_CAS; + + else if((r_ixr_cmd_fsm.read() == IXR_CMD_READ_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_WRITE_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_CAS_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_XRAM_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_CONFIG_TRT) ) + r_alloc_trt_fsm = ALLOC_TRT_IXR_CMD; + + else if((r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) and + (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP)) + r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP; + + else if((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) or + (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ)) + r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP; + } + break; } // end switch alloc_trt_fsm @@ -7352,4 +7318,6 @@ ///////////////////////////////////////////////////////////////////////////////////// +//std::cout << std::endl << "alloc_heap_fsm" << std::endl; + switch(r_alloc_heap_fsm.read()) { @@ -7507,4 +7475,6 @@ } // end switch alloc_heap_fsm + +//std::cout << std::endl << "fifo_update" << std::endl; ///////////////////////////////////////////////////////////////////// @@ -7579,12 +7549,10 @@ //////////////////////////////////////////////////////////////////////////////////// - m_write_to_cc_send_inst_fifo.update( write_to_cc_send_fifo_get, write_to_cc_send_fifo_put, + m_write_to_cc_send_inst_fifo.update( write_to_cc_send_fifo_get, + write_to_cc_send_fifo_put, write_to_cc_send_fifo_inst ); - m_write_to_cc_send_srcid_fifo.update( write_to_cc_send_fifo_get, write_to_cc_send_fifo_put, + m_write_to_cc_send_srcid_fifo.update( write_to_cc_send_fifo_get, + write_to_cc_send_fifo_put, write_to_cc_send_fifo_srcid ); -#if L1_MULTI_CACHE - m_write_to_cc_send_cache_id_fifo.update( write_to_cc_send_fifo_get, write_to_cc_send_fifo_put, - write_to_cc_send_fifo_cache_id ); -#endif //////////////////////////////////////////////////////////////////////////////////// @@ -7592,12 +7560,10 @@ //////////////////////////////////////////////////////////////////////////////////// - m_config_to_cc_send_inst_fifo.update( config_to_cc_send_fifo_get, config_to_cc_send_fifo_put, + m_config_to_cc_send_inst_fifo.update( config_to_cc_send_fifo_get, + config_to_cc_send_fifo_put, config_to_cc_send_fifo_inst ); - m_config_to_cc_send_srcid_fifo.update( config_to_cc_send_fifo_get, config_to_cc_send_fifo_put, + m_config_to_cc_send_srcid_fifo.update( config_to_cc_send_fifo_get, + config_to_cc_send_fifo_put, config_to_cc_send_fifo_srcid ); -#if L1_MULTI_CACHE - m_config_to_cc_send_cache_id_fifo.update( config_to_cc_send_fifo_get, config_to_cc_send_fifo_put, - config_to_cc_send_fifo_cache_id ); -#endif //////////////////////////////////////////////////////////////////////////////////// @@ -7605,12 +7571,10 @@ //////////////////////////////////////////////////////////////////////////////////// - m_xram_rsp_to_cc_send_inst_fifo.update( xram_rsp_to_cc_send_fifo_get, xram_rsp_to_cc_send_fifo_put, + m_xram_rsp_to_cc_send_inst_fifo.update( xram_rsp_to_cc_send_fifo_get, + xram_rsp_to_cc_send_fifo_put, xram_rsp_to_cc_send_fifo_inst ); - m_xram_rsp_to_cc_send_srcid_fifo.update( xram_rsp_to_cc_send_fifo_get, xram_rsp_to_cc_send_fifo_put, + m_xram_rsp_to_cc_send_srcid_fifo.update( xram_rsp_to_cc_send_fifo_get, + xram_rsp_to_cc_send_fifo_put, xram_rsp_to_cc_send_fifo_srcid ); -#if L1_MULTI_CACHE - m_xram_rsp_to_cc_send_cache_id_fifo.update( xram_rsp_to_cc_send_fifo_get, xram_rsp_to_cc_send_fifo_put, - xram_rsp_to_cc_send_fifo_cache_id ); -#endif //////////////////////////////////////////////////////////////////////////////////// @@ -7618,13 +7582,10 @@ //////////////////////////////////////////////////////////////////////////////////// - m_cas_to_cc_send_inst_fifo.update( cas_to_cc_send_fifo_get, cas_to_cc_send_fifo_put, + m_cas_to_cc_send_inst_fifo.update( cas_to_cc_send_fifo_get, + cas_to_cc_send_fifo_put, cas_to_cc_send_fifo_inst ); - m_cas_to_cc_send_srcid_fifo.update( cas_to_cc_send_fifo_get, cas_to_cc_send_fifo_put, + m_cas_to_cc_send_srcid_fifo.update( cas_to_cc_send_fifo_get, + cas_to_cc_send_fifo_put, cas_to_cc_send_fifo_srcid ); -#if L1_MULTI_CACHE - m_cas_to_cc_send_cache_id_fifo.update( cas_to_cc_send_fifo_get, cas_to_cc_send_fifo_put, - cas_to_cc_send_fifo_cache_id ); -#endif - m_cpt_cycles++; @@ -7639,88 +7600,45 @@ //////////////////////////////////////////////////////////// - p_vci_ixr.be = 0xFF; // nor transmited to external ram - p_vci_ixr.pktid = 0; + // DATA width is 8 bytes + // The following values are not transmitted to XRAM + // p_vci_ixr.be + // p_vci_ixr.pktid + // p_vci_ixr.cons + // p_vci_ixr.wrap + // p_vci_ixr.contig + // p_vci_ixr.clen + // p_vci_ixr.cfixed + + p_vci_ixr.plen = 64; p_vci_ixr.srcid = m_srcid_x; - p_vci_ixr.cons = false; - p_vci_ixr.wrap = false; - p_vci_ixr.contig = true; - p_vci_ixr.clen = 0; - p_vci_ixr.cfixed = false; - p_vci_ixr.plen = 64; - - if(r_ixr_cmd_fsm.read() == IXR_CMD_READ) + p_vci_ixr.trdid = r_ixr_cmd_trdid.read(); + p_vci_ixr.address = (addr_t)r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2); + + if ( (r_ixr_cmd_fsm.read() == IXR_CMD_READ_SEND) or + (r_ixr_cmd_fsm.read() == IXR_CMD_WRITE_SEND) or + (r_ixr_cmd_fsm.read() == IXR_CMD_CAS_SEND) or + (r_ixr_cmd_fsm.read() == IXR_CMD_XRAM_SEND) or + (r_ixr_cmd_fsm.read() == IXR_CMD_CONFIG_SEND) ) { - p_vci_ixr.cmd = vci_param_ext::CMD_READ; - p_vci_ixr.cmdval = true; - p_vci_ixr.address = (addr_t)(r_read_to_ixr_cmd_nline.read() * m_words * 4); - p_vci_ixr.wdata = 0; - p_vci_ixr.trdid = r_read_to_ixr_cmd_trdid.read(); - p_vci_ixr.eop = true; - } - else if(r_ixr_cmd_fsm.read() == IXR_CMD_CAS) - { - if(r_cas_to_ixr_cmd_write.read()) - { - size_t word = r_ixr_cmd_cpt.read(); - p_vci_ixr.cmd = vci_param_ext::CMD_WRITE; p_vci_ixr.cmdval = true; - p_vci_ixr.address = (addr_t)( (r_cas_to_ixr_cmd_nline.read() * m_words + word) * 4 ); - p_vci_ixr.wdata = ((wide_data_t)(r_cas_to_ixr_cmd_data[word].read())) | - ((wide_data_t)(r_cas_to_ixr_cmd_data[word+1].read()) << 32); - p_vci_ixr.trdid = r_cas_to_ixr_cmd_trdid.read(); - p_vci_ixr.eop = (r_ixr_cmd_cpt == (m_words-2)); - } - else - { - p_vci_ixr.cmd = vci_param_ext::CMD_READ; - p_vci_ixr.cmdval = true; - p_vci_ixr.address = (addr_t)(r_cas_to_ixr_cmd_nline.read() *m_words*4); - p_vci_ixr.wdata = 0; - p_vci_ixr.trdid = r_cas_to_ixr_cmd_trdid.read(); - p_vci_ixr.eop = true; - } - } - else if(r_ixr_cmd_fsm.read() == IXR_CMD_WRITE) - { - if(r_write_to_ixr_cmd_write.read()) - { - p_vci_ixr.cmd = vci_param_ext::CMD_WRITE; - p_vci_ixr.cmdval = true; - p_vci_ixr.address = (addr_t)( (r_write_to_ixr_cmd_nline.read() * m_words + - r_ixr_cmd_cpt.read()) * 4 ); - p_vci_ixr.wdata = ((wide_data_t)(r_write_to_ixr_cmd_data[r_ixr_cmd_cpt.read()].read()) | - ((wide_data_t)(r_write_to_ixr_cmd_data[r_ixr_cmd_cpt.read()+1].read()) << 32)); - p_vci_ixr.trdid = r_write_to_ixr_cmd_trdid.read(); - p_vci_ixr.eop = (r_ixr_cmd_cpt == (m_words-2)); - } - else - { - p_vci_ixr.cmd = vci_param_ext::CMD_READ; - p_vci_ixr.cmdval = true; - p_vci_ixr.address = (addr_t)(r_write_to_ixr_cmd_nline.read() *m_words*4); - p_vci_ixr.wdata = 0; - p_vci_ixr.trdid = r_write_to_ixr_cmd_trdid.read(); - p_vci_ixr.eop = true; - } - } - else if(r_ixr_cmd_fsm.read() == IXR_CMD_XRAM) - { - p_vci_ixr.cmd = vci_param_ext::CMD_WRITE; - p_vci_ixr.cmdval = true; - p_vci_ixr.address = (addr_t)( (r_xram_rsp_to_ixr_cmd_nline.read() * m_words + - r_ixr_cmd_cpt.read()) * 4 ); - p_vci_ixr.wdata = ((wide_data_t)(r_xram_rsp_to_ixr_cmd_data[r_ixr_cmd_cpt.read()].read()) | - ((wide_data_t)(r_xram_rsp_to_ixr_cmd_data[r_ixr_cmd_cpt.read()+1].read()) << 32)); - p_vci_ixr.trdid = r_xram_rsp_to_ixr_cmd_trdid.read(); - p_vci_ixr.eop = (r_ixr_cmd_cpt == (m_words-2)); + + if ( r_ixr_cmd_get.read() ) // GET + { + p_vci_ixr.cmd = vci_param_ext::CMD_READ; + p_vci_ixr.wdata = 0; + p_vci_ixr.eop = true; + } + else // PUT + { + size_t word = r_ixr_cmd_word.read(); + p_vci_ixr.cmd = vci_param_ext::CMD_WRITE; + p_vci_ixr.wdata = ((wide_data_t)(r_ixr_cmd_wdata[word].read())) | + ((wide_data_t)(r_ixr_cmd_wdata[word+1].read()) << 32); + p_vci_ixr.eop = (word == (m_words-2)); + } } else { - p_vci_ixr.cmdval = false; - p_vci_ixr.cmd = vci_param_ext::CMD_READ; - p_vci_ixr.address = 0; - p_vci_ixr.wdata = 0; - p_vci_ixr.trdid = 0; - p_vci_ixr.eop = false; + p_vci_ixr.cmdval = false; } @@ -7729,12 +7647,13 @@ //////////////////////////////////////////////////// - if(((r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP) and - (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ)) or - (r_ixr_rsp_fsm.read() == IXR_RSP_ACK)) - - p_vci_ixr.rspack = true; - - else - p_vci_ixr.rspack = false; + if( (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ) or + (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) ) + { + p_vci_ixr.rspack = (r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP); + } + else // r_ixr_rsp_fsm == IXR_RSP_IDLE + { + p_vci_ixr.rspack = false; + } //////////////////////////////////////////////////// @@ -7802,9 +7721,8 @@ break; } - case TGT_RSP_TGT_CMD: { p_vci_tgt.rspval = true; - p_vci_tgt.rdata = 0; + p_vci_tgt.rdata = r_tgt_cmd_to_tgt_rsp_rdata.read(); p_vci_tgt.rsrcid = r_tgt_cmd_to_tgt_rsp_srcid.read(); p_vci_tgt.rtrdid = r_tgt_cmd_to_tgt_rsp_trdid.read(); @@ -7815,5 +7733,4 @@ break; } - case TGT_RSP_READ: { @@ -8310,69 +8227,49 @@ //////////////////////////////////////////////////////////////////// - switch(r_cleanup_fsm.read()) + if ( r_cleanup_fsm.read() == CLEANUP_SEND_CLACK ) { - case CLEANUP_IDLE: - case CLEANUP_GET_NLINE: - case CLEANUP_DIR_REQ: - case CLEANUP_DIR_LOCK: - case CLEANUP_DIR_WRITE: - case CLEANUP_HEAP_REQ: - case CLEANUP_HEAP_LOCK: - case CLEANUP_HEAP_SEARCH: - case CLEANUP_HEAP_CLEAN: - case CLEANUP_HEAP_FREE: - case CLEANUP_IVT_LOCK: - case CLEANUP_IVT_DECREMENT: - case CLEANUP_IVT_CLEAR: - case CLEANUP_WRITE_RSP: - case CLEANUP_CONFIG_ACK: + uint8_t cleanup_ack_type; + if(r_cleanup_inst.read()) + { + cleanup_ack_type = DspinDhccpParam::TYPE_CLACK_INST; + } + else + { + cleanup_ack_type = DspinDhccpParam::TYPE_CLACK_DATA; + } + + uint64_t flit = 0; + uint64_t dest = r_cleanup_srcid.read() << + (DspinDhccpParam::SRCID_WIDTH - vci_param_int::S); + + DspinDhccpParam::dspin_set( + flit, + dest, + DspinDhccpParam::CLACK_DEST); + + DspinDhccpParam::dspin_set( + flit, + r_cleanup_nline.read() & 0xFFFF, + DspinDhccpParam::CLACK_SET); + + DspinDhccpParam::dspin_set( + flit, + r_cleanup_way_index.read(), + DspinDhccpParam::CLACK_WAY); + + DspinDhccpParam::dspin_set( + flit, + cleanup_ack_type, + DspinDhccpParam::CLACK_TYPE); + + p_dspin_clack.eop = true; + p_dspin_clack.write = true; + p_dspin_clack.data = flit; + } + else + { p_dspin_clack.write = false; p_dspin_clack.eop = false; p_dspin_clack.data = 0; - - break; - - case CLEANUP_SEND_CLACK: - { - uint8_t cleanup_ack_type; - if(r_cleanup_inst.read()) - { - cleanup_ack_type = DspinDhccpParam::TYPE_CLACK_INST; - } - else - { - cleanup_ack_type = DspinDhccpParam::TYPE_CLACK_DATA; - } - - uint64_t flit = 0; - uint64_t dest = - r_cleanup_srcid.read() << - (DspinDhccpParam::SRCID_WIDTH - vci_param_int::S); - - DspinDhccpParam::dspin_set( - flit, - dest, - DspinDhccpParam::CLACK_DEST); - - DspinDhccpParam::dspin_set( - flit, - r_cleanup_nline.read() & 0xFFFF, - DspinDhccpParam::CLACK_SET); - - DspinDhccpParam::dspin_set( - flit, - r_cleanup_way_index.read(), - DspinDhccpParam::CLACK_WAY); - - DspinDhccpParam::dspin_set( - flit, - cleanup_ack_type, - DspinDhccpParam::CLACK_TYPE); - - p_dspin_clack.eop = true; - p_dspin_clack.write = true; - p_dspin_clack.data = flit; - } - break; } Index: trunk/modules/vci_mem_cache/include/soclib/mem_cache.h =================================================================== --- trunk/modules/vci_mem_cache/include/soclib/mem_cache.h (revision 488) +++ trunk/modules/vci_mem_cache/include/soclib/mem_cache.h (revision 489) @@ -31,8 +31,8 @@ { MEMC_LOCK, - MEMC_CMD_TYPE, MEMC_ADDR_LO, MEMC_ADDR_HI, - MEMC_BUF_LENGTH + MEMC_BUF_LENGTH, + MEMC_CMD_TYPE };