Index: branches/ODCCP/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp
===================================================================
--- branches/ODCCP/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp	(revision 479)
+++ branches/ODCCP/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp	(revision 492)
@@ -36,5 +36,5 @@
 #define DEBUG_CLEANUP		  1
 #define INSTRUMENTATION       1
-#define FETCH_ON_WRITE_ENABLE 1
+#define FETCH_ON_WRITE_ENABLE 0
 #define DEBUG_CMD   		  0
 
@@ -1093,5 +1093,5 @@
 
         // coherence interrupt
-        if ( r_cc_receive_icache_req.read())
+        if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read() )
         {
             r_icache_fsm = ICACHE_CC_CHECK;
@@ -1330,5 +1330,5 @@
 
         // coherence interrupt
-        if ( r_cc_receive_icache_req.read() )
+        if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read() )
         {
             r_icache_fsm = ICACHE_CC_CHECK;
@@ -1382,5 +1382,5 @@
 
         // coherence request (from CC_RECEIVE FSM)
-        if ( r_cc_receive_icache_req.read() )
+        if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read() )
         {
             r_icache_fsm = ICACHE_CC_CHECK;
@@ -1589,5 +1589,5 @@
 
         // coherence interrupt
-        if ( r_cc_receive_icache_req.read() )
+        if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read() )
         {
             r_icache_fsm = ICACHE_CC_CHECK;
@@ -1686,5 +1686,5 @@
 
         // coherence interrupt
-        if ( r_cc_receive_icache_req.read() )
+        if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read() )
         {
             r_icache_fsm = ICACHE_CC_CHECK;
@@ -1765,5 +1765,5 @@
 
         // coherence interrupt
-        if ( r_cc_receive_icache_req.read() )
+        if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read() )
         {
             r_icache_fsm = ICACHE_CC_CHECK;
@@ -1844,5 +1844,5 @@
 
         // coherence interrupt
-        if ( r_cc_receive_icache_req.read() )
+        if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read() )
         {
             r_icache_fsm = ICACHE_CC_CHECK;
@@ -1883,4 +1883,44 @@
         paddr_t  mask  = ~((m_icache_words<<2)-1);
 
+        // CLACK handler
+        // We switch the directory slot to EMPTY state
+        // and reset r_icache_miss_clack if the cleanup ack
+        // is matching a pending miss.
+        if ( r_icache_clack_req.read() )
+        {
+
+            if ( m_ireq.valid ) m_cost_ins_miss_frz++;
+
+#ifdef INSTRUMENTATION
+m_cpt_icache_dir_write++;
+#endif
+            r_icache.write_dir( 0,
+                                r_icache_clack_way.read(),
+                                r_icache_clack_set.read(),
+                                CACHE_SLOT_STATE_EMPTY);
+
+            if ( (r_icache_miss_set.read() == r_icache_clack_set.read()) and
+                 (r_icache_miss_way.read() == r_icache_clack_way.read()) )
+            {
+                r_icache_miss_clack = false;
+            }
+
+            r_icache_clack_req = false;
+
+            // return to cc_save state
+            r_icache_fsm = r_icache_fsm_save.read();
+
+#if DEBUG_ICACHE
+if ( m_debug_activated )
+{
+    std::cout << "  <PROC " << name()
+        << " ICACHE_CC_CHECK>  CC_TYPE_CLACK slot returns to empty state"
+        << " set = " << r_icache_clack_set.read()
+        << " / way = " << r_icache_clack_way.read() << std::endl;
+}
+#endif
+
+            break;
+        }
 
         // Match between MISS address and CC address
@@ -1922,50 +1962,6 @@
         }
 
-        // CLACK handler
-        // We switch the directory slot to EMPTY state
-        // and reset r_icache_miss_clack if the cleanup ack
-        // is matching a pending miss.
-        if ( r_icache_clack_req.read() )
-        {
-
-            if ( m_ireq.valid ) m_cost_ins_miss_frz++;
-
-#ifdef INSTRUMENTATION
-m_cpt_icache_dir_write++;
-#endif
-            r_icache.write_dir( 0,
-                                r_icache_clack_way.read(),
-                                r_icache_clack_set.read(),
-                                CACHE_SLOT_STATE_EMPTY);
-
-            if ( (r_icache_miss_set.read() == r_icache_clack_set.read()) and
-                 (r_icache_miss_way.read() == r_icache_clack_way.read()) )
-            {
-                r_icache_miss_clack = false;
-            }
-
-            r_icache_clack_req = false;
-
-            // return to cc_save state if no pending CC request
-            if ( not r_cc_receive_icache_req.read() )
-                r_icache_fsm = r_icache_fsm_save.read();
-
-#if DEBUG_ICACHE
-if ( m_debug_activated )
-{
-    std::cout << "  <PROC " << name()
-        << " ICACHE_CC_CHECK>  CC_TYPE_CLACK slot returns to empty state"
-        << " set = " << r_icache_clack_set.read()
-        << " / way = " << r_icache_clack_way.read() << std::endl;
-}
-#endif
-
-            break;
-        }
-
-        // wait if pending request to CC_SEND. This way if there are pending
-        // CLACK they can be treated in this state and then a deadlock
-        // situation is avoided
-        if ( r_icache_cc_send_req.read() ) break;
+
+        assert ( not r_icache_cc_send_req.read() and "CC_SEND must be available in ICACHE_CC_CHECK");
 
         // CC request handler
@@ -2407,5 +2403,5 @@
         }
         // coherence request (from CC_RECEIVE FSM)
-        else if ( r_cc_receive_dcache_req.read() )
+        else if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
         {
             r_dcache_fsm = DCACHE_CC_CHECK;
@@ -2762,6 +2758,6 @@
                                 r_dcache_fsm          = DCACHE_MISS_SELECT;
                                
-                                /*ODCCP*/ // if tlb's flag cc egal 0 that means line is no coherent 
-                                bool ncc = ((tlb_flags.cc == 0) and (r_mmu_mode.read() & DATA_TLB_MASK));
+                                /*ODCCP*/ // if tlb's flag ncc egal 1 that means line is no coherent 
+                                bool ncc = ((tlb_flags.ncc == 1) and (r_mmu_mode.read() & DATA_TLB_MASK));
 
                                 if(ncc)
@@ -2880,5 +2876,5 @@
 #endif
                             // check if line is ncc or cc.
-                            bool ncc = ((tlb_flags.cc == 0) and (r_mmu_mode.read() & DATA_TLB_MASK));
+                            bool ncc = ((tlb_flags.ncc == 1) and (r_mmu_mode.read() & DATA_TLB_MASK));
 
                             // cleaning llsc buffer if address matching
@@ -3111,5 +3107,5 @@
 
         // coherence request (from CC_RECEIVE FSM)
-        if ( r_cc_receive_dcache_req.read() )
+        if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read() )
         {
             r_dcache_fsm = DCACHE_CC_CHECK;
@@ -3418,5 +3414,5 @@
 
         // coherence request (from CC_RECEIVE FSM)
-        if ( r_cc_receive_dcache_req.read() )
+        if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read() )
         {
             r_dcache_fsm = DCACHE_CC_CHECK;
@@ -3725,5 +3721,5 @@
 
         // coherence request (from CC_RECEIVE FSM)
-        if ( r_cc_receive_dcache_req.read() )
+        if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read() )
         {
             r_dcache_fsm = DCACHE_CC_CHECK;
@@ -3804,5 +3800,5 @@
 
         // coherence request (from CC_RECEIVE FSM)
-        if ( r_cc_receive_dcache_req.read() )
+        if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read() )
         {
             r_dcache_fsm = DCACHE_CC_CHECK;
@@ -3834,5 +3830,5 @@
 
         // coherence request (from CC_RECEIVE FSM)
-        if ( r_cc_receive_dcache_req.read() )
+        if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read() )
         {
             r_dcache_fsm = DCACHE_CC_CHECK;
@@ -3877,5 +3873,5 @@
 
         // coherence request (from CC_RECEIVE FSM)
-        if ( r_cc_receive_dcache_req.read() )
+        if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read() )
         {
             r_dcache_fsm = DCACHE_CC_CHECK;
@@ -4285,5 +4281,5 @@
 
         // coherence request (from CC_RECEIVE FSM)
-        if ( r_cc_receive_dcache_req.read() )
+        if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read() )
         {
             r_dcache_fsm = DCACHE_CC_CHECK;
@@ -4479,5 +4475,5 @@
 
         // coherence request (from CC_RECEIVE FSM)
-        if ( r_cc_receive_dcache_req.read() )
+        if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read() )
         {
             r_dcache_fsm = DCACHE_CC_CHECK;
@@ -4602,5 +4598,5 @@
 
         // coherence request (from CC_RECEIVE FSM)
-        if ( r_cc_receive_dcache_req.read() )
+        if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read() )
         {
             r_dcache_fsm = DCACHE_CC_CHECK;
@@ -4716,5 +4712,5 @@
 
         // coherence request (from CC_RECEIVE FSM)
-        if ( r_cc_receive_dcache_req.read() )
+        if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read() )
         {
             r_dcache_fsm = DCACHE_CC_CHECK;
@@ -4761,5 +4757,5 @@
 
         // coherence request (from CC_RECEIVE FSM)
-        if ( r_cc_receive_dcache_req.read() )
+        if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read() )
         {
             r_dcache_fsm = DCACHE_CC_CHECK;
@@ -4815,5 +4811,5 @@
 
         // coherence request (from CC_RECEIVE FSM)
-        if ( r_cc_receive_dcache_req.read() )
+        if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read() )
         {
             r_dcache_fsm = DCACHE_CC_CHECK;
@@ -4915,5 +4911,5 @@
 
         // coherence request (from CC_RECEIVE FSM)
-        if ( r_cc_receive_dcache_req.read() )
+        if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read() )
         {
             r_dcache_fsm = DCACHE_CC_CHECK;
@@ -4971,4 +4967,46 @@
 }
 #endif
+        // CLACK handler
+        // We switch the directory slot to EMPTY state and reset
+        // r_dcache_miss_clack if the cleanup ack is matching a pending miss.
+        if ( r_dcache_clack_req.read() )
+        {
+            if ( m_dreq.valid ) m_cost_data_miss_frz++;
+
+#ifdef INSTRUMENTATION
+m_cpt_dcache_dir_write++;
+#endif
+            r_dcache.write_dir( 0,
+                                r_dcache_clack_way.read(),
+                                r_dcache_clack_set.read(),
+                                CACHE_SLOT_STATE_EMPTY);
+            /*STATS DIRTY*/
+            for (size_t word = 0; word < m_dcache_words; word++)
+            {
+                dirty_stats[(r_cc_receive_dcache_way * m_dcache_sets + r_cc_receive_dcache_set) * m_dcache_words + word] = false;
+            }
+
+            if ( (r_dcache_miss_set.read() == r_dcache_clack_set.read()) and
+                 (r_dcache_miss_way.read() == r_dcache_clack_way.read()) )
+            {
+                  r_dcache_miss_clack = false;
+            }
+
+            r_dcache_clack_req = false;
+
+            // return to cc_save state
+            r_dcache_fsm = r_dcache_fsm_cc_save.read() ;
+
+#if DEBUG_DCACHE
+if ( m_debug_activated )
+{
+    std::cout << "  <PROC " << name()
+              << " DCACHE_CC_CHECK> CC_TYPE_CLACK Switch slot to EMPTY state"
+              << " set = " << r_dcache_clack_set.read()
+              << " / way = " << r_dcache_clack_way.read() << std::endl;
+}
+#endif
+            break;
+        }
 
         
@@ -5012,54 +5050,6 @@
         }
 
-        // CLACK handler
-        // We switch the directory slot to EMPTY state and reset
-        // r_dcache_miss_clack if the cleanup ack is matching a pending miss.
-        if ( r_dcache_clack_req.read() )
-        {
-            if ( m_dreq.valid ) m_cost_data_miss_frz++;
-
-#ifdef INSTRUMENTATION
-m_cpt_dcache_dir_write++;
-#endif
-            r_dcache.write_dir( 0,
-                                r_dcache_clack_way.read(),
-                                r_dcache_clack_set.read(),
-                                CACHE_SLOT_STATE_EMPTY);
-            /*STATS DIRTY*/
-            for (size_t word = 0; word < m_dcache_words; word++)
-            {
-                dirty_stats[(r_cc_receive_dcache_way * m_dcache_sets + r_cc_receive_dcache_set) * m_dcache_words + word] = false;
-            }
-
-            if ( (r_dcache_miss_set.read() == r_dcache_clack_set.read()) and
-                 (r_dcache_miss_way.read() == r_dcache_clack_way.read()) )
-            {
-                  r_dcache_miss_clack = false;
-            }
-
-            r_dcache_clack_req = false;
-
-            // return to cc_save state if no pending CC request
-            if ( not r_cc_receive_dcache_req.read() )
-            {
-                r_dcache_fsm = r_dcache_fsm_cc_save.read() ;
-            }
-
-#if DEBUG_DCACHE
-if ( m_debug_activated )
-{
-    std::cout << "  <PROC " << name()
-              << " DCACHE_CC_CHECK> CC_TYPE_CLACK Switch slot to EMPTY state"
-              << " set = " << r_dcache_clack_set.read()
-              << " / way = " << r_dcache_clack_way.read() << std::endl;
-}
-#endif
-            break;
-        }
-
-        // wait if pending request to CC_SEND. This way if there are pending
-        // CLACK they can be treated in this state and then a deadlock
-        // situation is avoided
-        if ( r_dcache_cc_send_req.read() ) break;
+
+        assert ( not r_dcache_cc_send_req.read() and "CC_SEND must be available in DCACHE_CC_CHECK");
 
         // CC request handler
