Index: branches/ODCCP/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h
===================================================================
--- branches/ODCCP/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h	(revision 492)
+++ branches/ODCCP/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h	(revision 494)
@@ -179,9 +179,9 @@
         CC_RECEIVE_INS_UPDT_HEADER,
         CC_RECEIVE_INS_UPDT_NLINE,
-        CC_RECEIVE_INS_UPDT_DATA,
         CC_RECEIVE_DATA_INVAL_HEADER,
         CC_RECEIVE_DATA_INVAL_NLINE,
         CC_RECEIVE_DATA_UPDT_HEADER,
         CC_RECEIVE_DATA_UPDT_NLINE,
+        CC_RECEIVE_INS_UPDT_DATA,
         CC_RECEIVE_DATA_UPDT_DATA,
     };
@@ -404,4 +404,8 @@
     sc_signal<bool>         r_icache_tlb_rsp_error;      // tlb miss response error
 
+    // Filp-Flop in ICACHE FSM for saving the cleanup victim request
+    sc_signal<bool>         r_icache_cleanup_victim_req; 
+    sc_signal<paddr_t>      r_icache_cleanup_victim_nline;
+
     // communication between ICACHE FSM and CC_SEND FSM
     sc_signal<bool>         r_icache_cc_send_req;           // ICACHE cc_send request
@@ -497,4 +501,8 @@
     sc_signal<int>          r_dcache_xtn_opcode;        // xtn request type
 
+    // Filp-Flop in DCACHE FSM for saving the cleanup victim request
+    sc_signal<bool>         r_dcache_cleanup_victim_req; 
+    sc_signal<paddr_t>      r_dcache_cleanup_victim_nline;
+
     // communication between DCACHE FSM and CC_SEND FSM
     sc_signal<bool>         r_dcache_cc_send_req;           // DCACHE cc_send request
@@ -507,4 +515,7 @@
     sc_signal<bool>         r_dcache_cc_cleanup_updt_data;          // Register for cleanup with data (wb updt)
     sc_signal<bool>         r_dcache_cleanup_ncc;                   // Register for cleanup no coherent 
+    //sc_signal<bool>         r_miss_cleanup_ncc_pending;                   // Register for cleanup no coherent 
+    sc_signal<bool>         r_dcache_cleanup_will_contains_data;                   // Register for cleanup no coherent 
+    sc_signal<bool>         r_dcache_cleanup_will_ncc;                   // Register for cleanup no coherent 
     sc_signal<bool>         r_dcache_miss_victim_no_coherence;      // Register for victim in no coherence mode
     sc_signal<bool>         r_dcache_line_no_coherence;             // Register for line current in no coherence mode
Index: branches/ODCCP/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp
===================================================================
--- branches/ODCCP/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp	(revision 492)
+++ branches/ODCCP/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp	(revision 494)
@@ -36,5 +36,5 @@
 #define DEBUG_CLEANUP		  1
 #define INSTRUMENTATION       1
-#define FETCH_ON_WRITE_ENABLE 0
+#define FETCH_ON_WRITE_ENABLE 1
 #define DEBUG_CMD   		  0
 
@@ -285,4 +285,7 @@
       r_icache_tlb_rsp_error("r_icache_tlb_rsp_error"),
 
+      r_icache_cleanup_victim_req("r_icache_cleanup_victim_req"),
+      r_icache_cleanup_victim_nline("r_icache_cleanup_victim_nline"),
+
       r_icache_cc_send_req("r_icache_cc_send_req"),
       r_icache_cc_send_type("r_icache_cc_send_type"),
@@ -357,4 +360,7 @@
       r_dcache_xtn_opcode("r_dcache_xtn_opcode"),
 
+      r_dcache_cleanup_victim_req("r_dcache_cleanup_victim_req"),
+      r_dcache_cleanup_victim_nline("r_dcache_cleanup_victim_nline"),
+    
       r_dcache_cc_send_req("r_dcache_cc_send_req"),
       r_dcache_cc_send_type("r_dcache_cc_send_type"),
@@ -363,5 +369,5 @@
       r_dcache_cc_send_updt_tab_idx("r_dcache_cc_send_updt_tab_idx"),
       
-      r_cc_send_data_fifo("r_cc_send_data_fifo", 2),  // ODCCP
+      r_cc_send_data_fifo("r_cc_send_data_fifo", 16),  // ODCCP
 
       r_vci_cmd_fsm("r_vci_cmd_fsm"),
@@ -792,4 +798,5 @@
         // No request from ICACHE_FSM to CC_SEND FSM
         r_icache_cc_send_req       = false;
+        r_icache_cleanup_victim_req = false;
 
         r_icache_clack_req         = false;
@@ -814,5 +821,6 @@
         // No request from DCACHE FSM to CC_SEND FSM
         r_dcache_cc_send_req       = false;
-
+        r_dcache_cleanup_victim_req = false;
+    
         r_dcache_clack_req         = false;
 
@@ -852,4 +860,5 @@
         r_dcache_miss_data_cpt               = 0;
         r_dcache_miss_data_addr              = 0;
+        //r_miss_cleanup_ncc_pending           = false;
 
         // activity counters
@@ -1093,5 +1102,5 @@
 
         // coherence interrupt
-        if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read() )
+        if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read())
         {
             r_icache_fsm = ICACHE_CC_CHECK;
@@ -1330,5 +1339,5 @@
 
         // coherence interrupt
-        if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read() )
+        if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read())
         {
             r_icache_fsm = ICACHE_CC_CHECK;
@@ -1382,5 +1391,5 @@
 
         // coherence request (from CC_RECEIVE FSM)
-        if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read() )
+        if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read())
         {
             r_icache_fsm = ICACHE_CC_CHECK;
@@ -1572,8 +1581,11 @@
     ////////////////////////
     case ICACHE_MISS_SELECT:       // Try to select a slot in associative set,
-                                   // if previous cleanup has been sent.
                                    // Waiting in this state if no slot available.
-                                   // Set the r_icache_cleanup_req flip-flop
-                                   // and the r_icache_miss_clack flip-flop,
+                                   // If a victim slot has been choosen and the r_icache_cc_send_req is false, 
+                                   // we send the cleanup request in this state. 
+                                   // If not, a r_icache_cleanup_victim_req flip-flop is
+                                   // utilized for saving this cleanup request, and it will be sent later
+                                   // in state ICACHE_MISS_WAIT or ICACHE_MISS_UPDT_DIR. 
+                                   // The r_icache_miss_clack flip-flop is set
                                    // when a cleanup is required
     {
@@ -1589,5 +1601,5 @@
 
         // coherence interrupt
-        if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read() )
+        if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read())
         {
             r_icache_fsm = ICACHE_CC_CHECK;
@@ -1596,40 +1608,51 @@
         }
 
-        if ( not r_icache_cc_send_req.read() ) // wait for previous cc_send request to be sent
-        {
-            bool        found;
-            bool        cleanup;
-            size_t  	way;
-            size_t  	set;
-            paddr_t 	victim;
+
+        bool        found;
+        bool        cleanup;
+        size_t  	way;
+        size_t  	set;
+        paddr_t 	victim;
 
 #ifdef INSTRUMENTATION
 m_cpt_icache_dir_read++;
 #endif
-            r_icache.read_select(r_icache_vci_paddr.read(),
-                                 &victim,
-                                 &way,
-                                 &set,
-                                 &found,
-                                 &cleanup );
-            if ( found )
-            {
-                r_icache_miss_way     = way;
-                r_icache_miss_set     = set;
-
-                if ( cleanup )
+        r_icache.read_select(r_icache_vci_paddr.read(),
+                             &victim,
+                             &way,
+                             &set,
+                             &found,
+                             &cleanup );
+        if ( not found )
+        {
+            break;
+        }
+        else
+        {
+            r_icache_miss_way     = way;
+            r_icache_miss_set     = set;
+
+            if ( cleanup )
+            {
+                if ( not r_icache_cc_send_req.read() )
                 {
-                    r_icache_fsm           = ICACHE_MISS_CLEAN;
-                    r_icache_miss_clack    = true;
-                    // request cleanup
-                    r_icache_cc_send_req   = true;
-                    r_icache_cc_send_nline = victim;
-                    r_icache_cc_send_way   = way;
-                    r_icache_cc_send_type  = CC_TYPE_CLEANUP;
+                    r_icache_cc_send_req    = true;
+                    r_icache_cc_send_nline  = victim;
+                    r_icache_cc_send_way    = way;
+                    r_icache_cc_send_type   = CC_TYPE_CLEANUP;    
                 }
                 else
                 {
-                    r_icache_fsm          = ICACHE_MISS_WAIT;
+                    r_icache_cleanup_victim_req   = true;
+                    r_icache_cleanup_victim_nline = victim;
                 }
+
+                r_icache_miss_clack           = true;
+                r_icache_fsm                  = ICACHE_MISS_CLEAN;
+            }
+            else
+            {
+                r_icache_fsm          = ICACHE_MISS_WAIT;
+            }
 
 #if DEBUG_ICACHE
@@ -1644,5 +1667,4 @@
 }
 #endif
-            }
         }
         break;
@@ -1677,4 +1699,14 @@
         if (m_ireq.valid) m_cost_ins_miss_frz++;
 
+        // send cleanup victim request
+        if ( r_icache_cleanup_victim_req.read() and not r_icache_cc_send_req.read() )
+        {
+            r_icache_cc_send_req        = true;
+            r_icache_cc_send_nline      = r_icache_cleanup_victim_nline;
+            r_icache_cc_send_way        = r_icache_miss_way;
+            r_icache_cc_send_type       = CC_TYPE_CLEANUP; 
+            r_icache_cleanup_victim_req = false;
+        }   
+
         // coherence clack interrupt
         if ( r_icache_clack_req.read() )
@@ -1684,7 +1716,7 @@
             break;
         }
-
+        
         // coherence interrupt
-        if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read() )
+        if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read() and not r_icache_cleanup_victim_req.read() )
         {
             r_icache_fsm = ICACHE_CC_CHECK;
@@ -1756,4 +1788,14 @@
         if ( m_ireq.valid ) m_cost_ins_miss_frz++;
 
+        // send cleanup victim request
+        if ( r_icache_cleanup_victim_req.read() and not r_icache_cc_send_req.read() )
+        {
+            r_icache_cc_send_req        = true;
+            r_icache_cc_send_nline      = r_icache_cleanup_victim_nline;
+            r_icache_cc_send_way        = r_icache_miss_way;
+            r_icache_cc_send_type       = CC_TYPE_CLEANUP; 
+            r_icache_cleanup_victim_req = false;
+        }   
+
         // coherence clack interrupt
         if ( r_icache_clack_req.read() )
@@ -1765,5 +1807,5 @@
 
         // coherence interrupt
-        if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read() )
+        if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read() and not r_icache_cleanup_victim_req.read() )
         {
             r_icache_fsm = ICACHE_CC_CHECK;
@@ -1844,5 +1886,5 @@
 
         // coherence interrupt
-        if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read() )
+        if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read())
         {
             r_icache_fsm = ICACHE_CC_CHECK;
@@ -1923,4 +1965,6 @@
             break;
         }
+        
+        assert ( not r_icache_cc_send_req.read() and "CC_SEND must be available in ICACHE_CC_CHECK");
 
         // Match between MISS address and CC address
@@ -1961,7 +2005,4 @@
 #endif
         }
-
-
-        assert ( not r_icache_cc_send_req.read() and "CC_SEND must be available in ICACHE_CC_CHECK");
 
         // CC request handler
@@ -3107,5 +3148,5 @@
 
         // coherence request (from CC_RECEIVE FSM)
-        if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read() )
+        if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
         {
             r_dcache_fsm = DCACHE_CC_CHECK;
@@ -3414,5 +3455,5 @@
 
         // coherence request (from CC_RECEIVE FSM)
-        if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read() )
+        if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
         {
             r_dcache_fsm = DCACHE_CC_CHECK;
@@ -3721,5 +3762,5 @@
 
         // coherence request (from CC_RECEIVE FSM)
-        if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read() )
+        if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
         {
             r_dcache_fsm = DCACHE_CC_CHECK;
@@ -3800,5 +3841,5 @@
 
         // coherence request (from CC_RECEIVE FSM)
-        if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read() )
+        if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
         {
             r_dcache_fsm = DCACHE_CC_CHECK;
@@ -3830,5 +3871,5 @@
 
         // coherence request (from CC_RECEIVE FSM)
-        if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read() )
+        if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
         {
             r_dcache_fsm = DCACHE_CC_CHECK;
@@ -3873,5 +3914,5 @@
 
         // coherence request (from CC_RECEIVE FSM)
-        if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read() )
+        if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
         {
             r_dcache_fsm = DCACHE_CC_CHECK;
@@ -3971,4 +4012,8 @@
                               &set,
                               &word);
+
+        /*if (m_proc_id == 1) { std::cout << "rdata XTN_FLUSH_DATA = " << std::hex << rdata << std::dec << " | at cycle = " << m_cpt_total_cycles << std::endl; }
+        if (m_proc_id == 1) { r_cc_send_data_fifo.print(); }*/
+
         if(r_cc_send_data_fifo.wok())
         {
@@ -4047,4 +4092,6 @@
         {
             paddr = (paddr_t)r_dcache_save_wdata.read();
+            if (vci_param::N > 32) 
+                paddr = paddr | ((paddr_t)(r_dcache_paddr_ext.read()) << 32);
             hit   = true;
         }
@@ -4233,4 +4280,8 @@
                               &set,
                               &word);
+
+        /*if (m_proc_id == 1) { std::cout << "rdata XTN_INVAL_DATA = " << std::hex << rdata << std::dec << " | at cycle = " << m_cpt_total_cycles << std::endl; }
+        if (m_proc_id == 1) { r_cc_send_data_fifo.print(); }*/
+
         if(r_cc_send_data_fifo.wok())
         {
@@ -4263,10 +4314,13 @@
     }
     ////////////////////////
-    case DCACHE_MISS_SELECT:   // Try to select a slot in associative set
-                               // if previous cleanup has been sent.
-                               // Waiting in this state if no slot available
-                               // Set the r_dcache_cleanup_req flip-flop
-                               // and the r_dcache_miss_clack flip-flop
-                               // when a cleanup is required
+    case DCACHE_MISS_SELECT:       // Try to select a slot in associative set,
+                                   // Waiting in this state if no slot available.
+                                   // If a victim slot has been choosen and the r_icache_cc_send_req is false, 
+                                   // we send the cleanup request in this state. 
+                                   // If not, a r_icache_cleanup_victim_req flip-flop is
+                                   // utilized for saving this cleanup request, and it will be sent later
+                                   // in state ICACHE_MISS_WAIT or ICACHE_MISS_UPDT_DIR. 
+                                   // The r_icache_miss_clack flip-flop is set
+                                   // when a cleanup is required
     {
         if ( m_dreq.valid) m_cost_data_miss_frz++;
@@ -4281,5 +4335,5 @@
 
         // coherence request (from CC_RECEIVE FSM)
-        if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read() )
+        if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
         {
             r_dcache_fsm = DCACHE_CC_CHECK;
@@ -4288,11 +4342,11 @@
         }
 
-        if ( not r_dcache_cc_send_req.read() ) // blocked until previous cc_send request is sent
-        {
-            bool     found = false;
-            bool     cleanup = false;
-            size_t   way = 0;
-            size_t   set = 0;
-            paddr_t  victim = 0;
+        bool     found = false;
+        bool     cleanup = false;
+        bool     dirty = false;
+        bool     ncc = false;
+        size_t   way = 0;
+        size_t   set = 0;
+        paddr_t  victim = 0;
             int state;
 
@@ -4300,60 +4354,94 @@
 m_cpt_dcache_dir_read++;
 #endif
-            r_dcache.read_select( r_dcache_save_paddr.read(),
-                                  &victim,
-                                  &way,
-                                  &set,
-                                  &found,
-                                  &cleanup );
+        r_dcache.read_select( r_dcache_save_paddr.read(),
+                              &victim,
+                              &way,
+                              &set,
+                              &found,
+                              &cleanup );
             state = r_dcache.get_cache_state(way,set);
-            if ( found )
-            {
-                r_dcache_miss_way = way;
-                r_dcache_miss_set = set;
-
-                if ( cleanup )
+        if (  not found )
+        {
+            break;
+        }
+        else
+        {
+            r_dcache_miss_way = way;
+            r_dcache_miss_set = set;
+
+            if ( cleanup )
+            {
+
+                r_dcache_miss_clack           = true;
+                r_dcache_fsm                  = DCACHE_MISS_CLEAN;
+
+                
+                if( (state == CACHE_SLOT_STATE_VALID_NCC) )
                 {
-                    r_dcache_miss_clack   = true;
-                    r_dcache_fsm          = DCACHE_MISS_CLEAN;
-                    // request cleanup
-                    r_dcache_cc_send_req   = true;
-                    r_dcache_cc_send_nline = victim;
-                    r_dcache_cc_send_way   = way;
-                    r_dcache_cc_send_type  = CC_TYPE_CLEANUP;
-                    
-                    if( (state == CACHE_SLOT_STATE_VALID_NCC) )
+                    //r_dcache_cleanup_ncc = true;
+                    ncc = true;
+                    r_dcache_cleanup_will_ncc = true;
+
+                    /*ODCCP*/ // if line is dirty we must save the data values
+                    if (r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_DATA_DIRTY)
                     {
-                        r_dcache_cleanup_ncc = true;
-                        
-                        /*ODCCP*/ // if line is dirty we must save the data values
-                        if (r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_DATA_DIRTY)
+                        //r_dcache_cc_cleanup_updt_data = true;
+                        dirty = true;
+                        r_dcache_cleanup_will_contains_data = true;
+                        r_dcache_miss_data_addr = (victim*m_dcache_words)*4;
+                        r_dcache_fsm = DCACHE_MISS_DATA;
+
+                        /*TEST*/
+                        /*if (not r_dcache_cc_send_req.read()) 
+                            r_miss_cleanup_ncc_pending = true;
+                        else
+                            r_miss_cleanup_ncc_pending = false;*/
+
+                        m_cpt_data_cleanup_dirty ++;
+
+                        /*STATS DIRTY*/
+                        for (size_t w = 0; w < m_dcache_words; w++)
                         {
-                            r_dcache_cc_cleanup_updt_data = true;
-                            r_dcache_miss_data_addr = (victim*m_dcache_words)*4;
-                            r_dcache_fsm = DCACHE_MISS_DATA;
-                            m_cpt_data_cleanup_dirty ++;
-
-                            /*STATS DIRTY*/
-                            for (size_t w = 0; w < m_dcache_words; w++)
-                            {
-                                if(dirty_stats[(way * m_dcache_sets + set) * m_dcache_words + w] == true)
-                                    m_cpt_words_dirty++;
-                            }
+                            if(dirty_stats[(way * m_dcache_sets + set) * m_dcache_words + w] == true)
+                                m_cpt_words_dirty++;
                         }
-                        else
-                        {
-                            r_dcache_cc_cleanup_updt_data = false;
-                        }
-                    } 
+                    }
                     else
                     {
-                        r_dcache_cc_cleanup_updt_data = false;
-                        r_dcache_cleanup_ncc = false;
+                        //r_dcache_cc_cleanup_updt_data = false;
+                        r_dcache_cleanup_will_contains_data = false;
                     }
+                } 
+                else
+                {
+                    r_dcache_cleanup_will_contains_data = false;
+                    r_dcache_cleanup_will_ncc = false;
+                    //r_dcache_cc_cleanup_updt_data = false;
+                    //r_dcache_cleanup_ncc = false;
+                }
+
+                if ( not r_dcache_cc_send_req.read() )
+                {
+                    if (dirty) r_dcache_cc_cleanup_updt_data = true;
+                    else       r_dcache_cc_cleanup_updt_data = false;
+
+                    if (ncc)   r_dcache_cleanup_ncc = true;
+                    else       r_dcache_cleanup_ncc = false;
+
+                    r_dcache_cc_send_req    = true;
+                    r_dcache_cc_send_nline  = victim;
+                    r_dcache_cc_send_way    = way;
+                    r_dcache_cc_send_type   = CC_TYPE_CLEANUP;    
                 }
                 else
                 {
-                    r_dcache_fsm          = DCACHE_MISS_WAIT;
+                    r_dcache_cleanup_victim_req   = true;
+                    r_dcache_cleanup_victim_nline = victim;
                 }
+            }
+            else
+            {
+                r_dcache_fsm          = DCACHE_MISS_WAIT;
+            }
 
 #if DEBUG_DCACHE
@@ -4369,6 +4457,5 @@
 }
 #endif
-            } // end found
-        }
+        } // end found
         break;
     }
@@ -4385,4 +4472,7 @@
                               &set,
                               &word);
+
+        /*if (m_proc_id == 1) { std::cout << "rdata MISS_DATA = " << std::hex << rdata << std::dec << " | at cycle = " << m_cpt_total_cycles << std::endl; }
+        if (m_proc_id == 1) { r_cc_send_data_fifo.print(); }*/
 
         if(r_cc_send_data_fifo.wok())
@@ -4466,4 +4556,21 @@
         if ( m_dreq.valid) m_cost_data_miss_frz++;
 
+        // send cleanup victim request
+        if ( r_dcache_cleanup_victim_req.read() and not r_dcache_cc_send_req.read() )
+        {
+            r_dcache_cc_send_req        = true;
+            r_dcache_cc_send_nline      = r_dcache_cleanup_victim_nline;
+            r_dcache_cc_send_way        = r_dcache_miss_way;
+            r_dcache_cc_send_type       = CC_TYPE_CLEANUP; 
+            r_dcache_cleanup_victim_req = false;
+            if (r_dcache_cleanup_will_contains_data.read() == true)
+                r_dcache_cc_cleanup_updt_data = true;
+            else
+                r_dcache_cc_cleanup_updt_data = false;
+                    
+            if (r_dcache_cleanup_will_ncc.read())   r_dcache_cleanup_ncc = true;
+            else                                    r_dcache_cleanup_ncc = false;
+        }   
+
         // coherence clack request (from DSPIN CLACK)
         if ( r_dcache_clack_req.read() )
@@ -4475,5 +4582,5 @@
 
         // coherence request (from CC_RECEIVE FSM)
-        if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read() )
+        if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read() and not r_dcache_cleanup_victim_req.read() /*and not r_miss_cleanup_ncc_pending.read()*/)
         {
             r_dcache_fsm = DCACHE_CC_CHECK;
@@ -4589,4 +4696,19 @@
         if ( m_dreq.valid) m_cost_data_miss_frz++;
 
+        // send cleanup victim request
+        if ( r_dcache_cleanup_victim_req.read() and not r_dcache_cc_send_req.read() )
+        {
+            r_dcache_cc_send_req        = true;
+            r_dcache_cc_send_nline      = r_dcache_cleanup_victim_nline;
+            r_dcache_cc_send_way        = r_dcache_miss_way;
+            r_dcache_cc_send_type       = CC_TYPE_CLEANUP; 
+            r_dcache_cleanup_victim_req = false;
+            if (r_dcache_cleanup_will_contains_data.read()) r_dcache_cc_cleanup_updt_data = true;
+            else                                            r_dcache_cc_cleanup_updt_data = false;
+            
+            if (r_dcache_cleanup_will_ncc.read())           r_dcache_cleanup_ncc = true;
+            else                                            r_dcache_cleanup_ncc = false;
+        }   
+
         // coherence clack request (from DSPIN CLACK)
         if ( r_dcache_clack_req.read() )
@@ -4598,5 +4720,5 @@
 
         // coherence request (from CC_RECEIVE FSM)
-        if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read() )
+        if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read() and not r_dcache_cleanup_victim_req.read() /*and not r_miss_cleanup_ncc_pending.read()*/)
         {
             r_dcache_fsm = DCACHE_CC_CHECK;
@@ -4712,5 +4834,5 @@
 
         // coherence request (from CC_RECEIVE FSM)
-        if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read() )
+        if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
         {
             r_dcache_fsm = DCACHE_CC_CHECK;
@@ -4757,5 +4879,5 @@
 
         // coherence request (from CC_RECEIVE FSM)
-        if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read() )
+        if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
         {
             r_dcache_fsm = DCACHE_CC_CHECK;
@@ -4811,5 +4933,5 @@
 
         // coherence request (from CC_RECEIVE FSM)
-        if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read() )
+        if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
         {
             r_dcache_fsm = DCACHE_CC_CHECK;
@@ -4911,5 +5033,5 @@
 
         // coherence request (from CC_RECEIVE FSM)
-        if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read() )
+        if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
         {
             r_dcache_fsm = DCACHE_CC_CHECK;
@@ -5010,8 +5132,7 @@
         }
 
-        
+        assert ( not r_dcache_cc_send_req.read() and "CC_SEND must be available in DCACHE_CC_CHECK" );
+
         // Match between MISS address and CC address
-        // note: In the same cycle we can handle a CLACK and a MISS match
-        // because the CLACK access the directory but the MISS match dont.
         if (r_cc_receive_dcache_req.read() and 
           ((r_dcache_fsm_cc_save == DCACHE_MISS_SELECT  )  or
@@ -5049,7 +5170,4 @@
 #endif
         }
-
-
-        assert ( not r_dcache_cc_send_req.read() and "CC_SEND must be available in DCACHE_CC_CHECK");
 
         // CC request handler
@@ -5236,6 +5354,11 @@
                               &set,
                               &word);
+       
+        /*if (m_proc_id == 1) { std::cout << "rdata CC_INVAL_DATA = " << std::hex << rdata << std::dec << " | at cycle = " << m_cpt_total_cycles << std::endl; }
+        if (m_proc_id == 1) { r_cc_send_data_fifo.print(); }*/
+        
         if(r_cc_send_data_fifo.wok())
         {
+            
             r_dcache_cc_inval_addr = r_dcache_cc_inval_addr.read() + 4;
 
@@ -5258,4 +5381,5 @@
                         << " / WAY = " << way
                         << " / SET = " << set << std::endl;
+                    r_dcache.printTrace();
                 }
 #endif
@@ -6005,4 +6129,5 @@
                         r_dcache_cc_send_req = false;
                         r_dcache_cc_cleanup_updt_data = false;
+                        //r_miss_cleanup_ncc_pending = false;
                         r_cc_send_cpt_word = 0;
                         r_cc_send_fsm = CC_SEND_IDLE;
@@ -6095,5 +6220,5 @@
             // flip_flop to check that ?
             if (not (r_cc_receive_icache_req.read()) and 
-                not (r_cc_receive_dcache_req.read()) and 
+                not (r_cc_receive_dcache_req.read()) and
                 (p_dspin_m2p.write.read()))
             {
@@ -6135,5 +6260,6 @@
             uint64_t receive_data = p_dspin_m2p.data.read();
             // for data INVAL, wait for dcache to take the request
-            if (p_dspin_m2p.write.read() and not r_cc_receive_dcache_req.read())
+            if (p_dspin_m2p.write.read()           and 
+                not r_cc_receive_dcache_req.read() )
             {
                 // request dcache to handle the INVAL
@@ -6153,5 +6279,6 @@
             uint64_t receive_data = p_dspin_m2p.data.read();
             // for ins INVAL, wait for icache to take the request
-            if (p_dspin_m2p.write.read() and not r_cc_receive_icache_req.read())
+            if (p_dspin_m2p.write.read()           and 
+                not r_cc_receive_icache_req.read() )
             {
                 // request icache to handle the INVAL
@@ -6203,5 +6330,5 @@
             // for data INVAL, wait for dcache to take the request and fifo to
             // be empty
-            if ( r_cc_receive_updt_fifo_be.empty() and 
+            if ( r_cc_receive_updt_fifo_be.empty() and
                  p_dspin_m2p.write.read() )
             {
@@ -6223,5 +6350,5 @@
             // for ins INVAL, wait for icache to take the request and fifo to be
             // empty
-            if ( r_cc_receive_updt_fifo_be.empty() and 
+            if ( r_cc_receive_updt_fifo_be.empty() and
                  p_dspin_m2p.write.read() )
             {
