Changeset 494 for branches/ODCCP/modules/vci_mem_cache/caba/source

Timestamp:

Aug 20, 2013, 2:13:08 PM (11 years ago)

Author:

devigne

Message:

Merge with the lastest version of trunk

Location:

branches/ODCCP/modules/vci_mem_cache

Files:

• . (modified) (1 prop)
• caba/source/include/mem_cache_directory.h (modified) (12 diffs)
• caba/source/include/vci_mem_cache.h (modified) (24 diffs)
• caba/source/include/xram_transaction.h (modified) (25 diffs)
• caba/source/src/vci_mem_cache.cpp (modified) (214 diffs)

branches/ODCCP/modules/vci_mem_cache/caba/source/include/mem_cache_directory.h

@@ -6 +6 @@
 #include <cassert>
 #include "arithmetics.h"
-
-// !!!
-// The L1_MULTI_CACHE mechanism does no longer work with the new pktid encoding
-// of TSAR. Turning the define below to a non null value will cause the memcache
-// to behave in an unpredicted way.
-// TODO Either remove the mechanism from the mem cache or update its behaviour.
-
-#define L1_MULTI_CACHE 0
 
 //#define RANDOM_EVICTION
@@ -46 +38 @@
       bool      inst;       // Is the owner an ICache ?
       size_t    srcid;      // The SRCID of the owner
-#if L1_MULTI_CACHE
-      size_t    cache_id;   // In multi_cache configuration
-#endif
 
     ////////////////////////
     // Constructors
     ////////////////////////
-      Owner(bool   i_inst
-            ,size_t i_srcid
-#if L1_MULTI_CACHE
-            ,size_t i_cache_id
-#endif
-            ){
+      Owner(bool   i_inst,
+            size_t i_srcid)
+      {
         inst    = i_inst;
         srcid   = i_srcid;
-#if L1_MULTI_CACHE
-        cache_id= i_cache_id;
-#endif
-      }
-
-      Owner(const Owner &a){
+      }
+
+      Owner(const Owner &a)
+      {
         inst    = a.inst;
         srcid   = a.srcid;
-#if L1_MULTI_CACHE
-        cache_id= a.cache_id;
-#endif
-      }
-
-      Owner(){
+      }
+
+      Owner()
+      {
         inst    = false;
         srcid   = 0;
-#if L1_MULTI_CACHE
-        cache_id= 0;
-#endif
       }
       // end constructors
@@ -116 +95 @@
       owner.inst    = 0;
       owner.srcid   = 0;
-#if L1_MULTI_CACHE
-      owner.cache_id= 0;
-#endif
       ptr           = 0;
     }
@@ -176 +152 @@
                 << " ; Count = " << count 
                 << " ; Owner = " << owner.srcid 
-#if L1_MULTI_CACHE
-                << "." << owner.cache_id 
-#endif
                 << " " << owner.inst 
                 << " ; Pointer = " << ptr << std::endl;
@@ -327 +300 @@
     // - entry : the entry value
     /////////////////////////////////////////////////////////////////////
-    void write(const size_t &set, const size_t &way, const DirectoryEntry &entry)
+    void write( const size_t         &set, 
+                const size_t         &way, 
+                const DirectoryEntry &entry)
     {
       assert( (set<m_sets) 
@@ -373 +348 @@
     DirectoryEntry select(const size_t &set, size_t &way)
     {
-      assert( (set < m_sets) 
+        assert( (set < m_sets) 
           && "Cache Directory : (select) The set index is invalid");
 
-      for(size_t i=0; i<m_ways; i++){
-        if(!m_dir_tab[set][i].valid){
-          way=i;
-          return DirectoryEntry(m_dir_tab[set][way]);
+        // looking for an empty slot
+        for(size_t i=0; i<m_ways; i++)
+        {
+            if( not m_dir_tab[set][i].valid )
+            {
+                way=i;
+                return DirectoryEntry(m_dir_tab[set][way]);
+            }
         }
-      }
 
 #ifdef RANDOM_EVICTION
-      lfsr = (lfsr >> 1) ^ ((-(lfsr & 1)) & 0xd0000001);
-      way = lfsr % m_ways;
-      return DirectoryEntry(m_dir_tab[set][way]);
+        lfsr = (lfsr >> 1) ^ ((-(lfsr & 1)) & 0xd0000001);
+        way = lfsr % m_ways;
+        return DirectoryEntry(m_dir_tab[set][way]);
 #endif
 
-      for(size_t i=0; i<m_ways; i++){
-        if(!(m_lru_tab[set][i].recent) && !(m_dir_tab[set][i].lock)){
-          way=i;
-          return DirectoryEntry(m_dir_tab[set][way]);
+        // looking for a not locked and not recently used entry
+        for(size_t i=0; i<m_ways; i++)
+        {
+            if((not m_lru_tab[set][i].recent) && (not m_dir_tab[set][i].lock) )
+            {
+                way=i;
+                return DirectoryEntry(m_dir_tab[set][way]);
+            }
         }
-      }
-      for(size_t i=0; i<m_ways; i++){
-        if( !(m_lru_tab[set][i].recent) && (m_dir_tab[set][i].lock)){
-          way=i;
-          return DirectoryEntry(m_dir_tab[set][way]);
+
+        // looking for a locked not recently used entry
+        for(size_t i=0; i<m_ways; i++)
+        {
+            if( (not m_lru_tab[set][i].recent) && (m_dir_tab[set][i].lock))
+            {
+                way=i;
+                return DirectoryEntry(m_dir_tab[set][way]);
+            }
         }
-      }
-      for(size_t i=0; i<m_ways; i++){
-        if( (m_lru_tab[set][i].recent) && !(m_dir_tab[set][i].lock)){
-          way=i;
-          return DirectoryEntry(m_dir_tab[set][way]);
+
+        // looking for a recently used entry not locked
+        for(size_t i=0; i<m_ways; i++)
+        {
+            if( (m_lru_tab[set][i].recent) && (not m_dir_tab[set][i].lock))
+            {
+                way=i;
+                return DirectoryEntry(m_dir_tab[set][way]);
+            }
         }
-      }
-      way = 0;
-      return DirectoryEntry(m_dir_tab[set][0]);
+
+        // select way 0 (even if entry is locked and recently used)
+        way = 0;
+        return DirectoryEntry(m_dir_tab[set][0]);
     } // end select()
 
@@ -442 +433 @@
     ////////////////////////
       HeapEntry()
-      :owner(false,0
-#if L1_MULTI_CACHE
-             ,0
-#endif
-             )
+      :owner(false,0)
       {
         next = 0;
@@ -454 +441 @@
     // Constructor
     ////////////////////////
-      HeapEntry(const HeapEntry &entry){
+      HeapEntry(const HeapEntry &entry)
+      {
         owner.inst  = entry.owner.inst;
         owner.srcid = entry.owner.srcid;
-#if L1_MULTI_CACHE
-        owner.cache_id = entry.owner.cache_id;
-#endif        
         next           = entry.next;
       } // end constructor
@@ -466 +451 @@
     // The copy() function copies an existing source entry to a target 
     /////////////////////////////////////////////////////////////////////
-      void copy(const HeapEntry &entry){
+      void copy(const HeapEntry &entry)
+      {
         owner.inst     = entry.owner.inst;
         owner.srcid    = entry.owner.srcid;
-#if L1_MULTI_CACHE
-        owner.cache_id = entry.owner.cache_id;
-#endif
         next           = entry.next;
       } // end copy()
@@ -482 +465 @@
         << " -- owner.inst     : " << std::dec << owner.inst << std::endl
         << " -- owner.srcid    : " << std::dec << owner.srcid << std::endl
-#if L1_MULTI_CACHE
-        << " -- owner.cache_id : " << std::dec << owner.cache_id << std::endl
-#endif
         << " -- next           : " << std::dec << next << std::endl;
 
@@ -645 +625 @@
   //                        Cache Data 
   ////////////////////////////////////////////////////////////////////////
-  class CacheData {
+  class CacheData 
+  {
     private:
       const uint32_t m_sets;
@@ -655 +636 @@
     public:
 
+      ///////////////////////////////////////////////////////
       CacheData(uint32_t ways, uint32_t sets, uint32_t words)
-        : m_sets(sets), m_ways(ways), m_words(words) {
-
+        : m_sets(sets), m_ways(ways), m_words(words) 
+      {
           m_cache_data = new uint32_t ** [ways];
-          for ( size_t i=0 ; i < ways ; i++ ) {
-            m_cache_data[i] = new uint32_t * [sets];
+          for ( size_t i=0 ; i < ways ; i++ ) 
+          {
+              m_cache_data[i] = new uint32_t * [sets];
           }
-          for ( size_t i=0; i<ways; i++ ) {
-            for ( size_t j=0; j<sets; j++ ) {
-              m_cache_data[i][j] = new uint32_t [words];
-            }
+          for ( size_t i=0; i<ways; i++ ) 
+          {
+              for ( size_t j=0; j<sets; j++ ) 
+              {
+                  m_cache_data[i][j] = new uint32_t [words];
+              }
           }
-        }
-
-      ~CacheData() {
-          for(size_t i=0; i<m_ways ; i++){
-              for(size_t j=0; j<m_sets ; j++){
+      }
+      ////////////
+      ~CacheData() 
+      {
+          for(size_t i=0; i<m_ways ; i++)
+          {
+              for(size_t j=0; j<m_sets ; j++)
+              {
                   delete [] m_cache_data[i][j];
               }
           }
-          for(size_t i=0; i<m_ways ; i++){
+          for(size_t i=0; i<m_ways ; i++)
+          {
               delete [] m_cache_data[i];
           }
           delete [] m_cache_data;
       }
-
-      uint32_t read (
-          const uint32_t &way,
-          const uint32_t &set,
-          const uint32_t &word) const {
-
-        assert((set  < m_sets ) && "Cache data error: Trying to read a wrong set" );
-        assert((way  < m_ways ) && "Cache data error: Trying to read a wrong way" );
-        assert((word < m_words) && "Cache data error: Trying to read a wrong word");
-
-        return m_cache_data[way][set][word];
-      }
-
-      void read_line(
-          const uint32_t &way,
-          const uint32_t &set,
-          sc_core::sc_signal<uint32_t> * cache_line)
-      {
-        assert((set < m_sets ) && "Cache data error: Trying to read a wrong set" );
-        assert((way < m_ways ) && "Cache data error: Trying to read a wrong way" );
-
-        for (uint32_t word=0; word<m_words; word++)
-          cache_line[word].write(m_cache_data[way][set][word]);
-      }
-
-      void write (
-          const uint32_t &way,
-          const uint32_t &set,
-          const uint32_t &word,
-          const uint32_t &data,
-          const uint32_t &be = 0xF) {
-
-        assert((set  < m_sets ) && "Cache data error: Trying to write a wrong set" );
-        assert((way  < m_ways ) && "Cache data error: Trying to write a wrong way" );
-        assert((word < m_words) && "Cache data error: Trying to write a wrong word");
-        assert((be  <= 0xF    ) && "Cache data error: Trying to write a wrong word cell");
-
-        if (be == 0x0) return;
-
-        if (be == 0xF) {
-            m_cache_data[way][set][word] = data; 
-            return;
-        }
-
-        uint32_t mask = 0;
-        if  (be & 0x1) mask = mask | 0x000000FF;
-        if  (be & 0x2) mask = mask | 0x0000FF00;
-        if  (be & 0x4) mask = mask | 0x00FF0000;
-        if  (be & 0x8) mask = mask | 0xFF000000;
-
-        m_cache_data[way][set][word] = 
-          (data & mask) | (m_cache_data[way][set][word] & ~mask);
+      //////////////////////////////////////////
+      uint32_t read ( const uint32_t &way,
+                      const uint32_t &set,
+                      const uint32_t &word) const 
+      {
+          assert((set  < m_sets ) && "Cache data error: Trying to read a wrong set" );
+          assert((way  < m_ways ) && "Cache data error: Trying to read a wrong way" );
+          assert((word < m_words) && "Cache data error: Trying to read a wrong word");
+
+          return m_cache_data[way][set][word];
+      }
+      //////////////////////////////////////////
+      void read_line( const uint32_t &way,
+                      const uint32_t &set,
+                      sc_core::sc_signal<uint32_t> * cache_line)
+      {
+          assert((set < m_sets ) && "Cache data error: Trying to read a wrong set" );
+          assert((way < m_ways ) && "Cache data error: Trying to read a wrong way" );
+
+          for (uint32_t word=0; word<m_words; word++)
+              cache_line[word].write(m_cache_data[way][set][word]);
+      }
+      /////////////////////////////////////////
+      void write ( const uint32_t &way,
+                   const uint32_t &set,
+                   const uint32_t &word,
+                   const uint32_t &data,
+                   const uint32_t &be = 0xF) 
+      {
+
+          assert((set  < m_sets ) && "Cache data error: Trying to write a wrong set" );
+          assert((way  < m_ways ) && "Cache data error: Trying to write a wrong way" );
+          assert((word < m_words) && "Cache data error: Trying to write a wrong word");
+          assert((be  <= 0xF    ) && "Cache data error: Trying to write a wrong be");
+
+          if (be == 0x0) return;
+
+          if (be == 0xF) 
+          {
+              m_cache_data[way][set][word] = data; 
+              return;
+          }
+
+          uint32_t mask = 0;
+          if  (be & 0x1) mask = mask | 0x000000FF;
+          if  (be & 0x2) mask = mask | 0x0000FF00;
+          if  (be & 0x4) mask = mask | 0x00FF0000;
+          if  (be & 0x8) mask = mask | 0xFF000000;
+
+          m_cache_data[way][set][word] = 
+              (data & mask) | (m_cache_data[way][set][word] & ~mask);
       }
   }; // end class CacheData

branches/ODCCP/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h

@@ -25 +25 @@
  * SOCLIB_LGPL_HEADER_END
  *
- * Maintainers: alain eric.guthmuller@polytechnique.edu
+ * Maintainers: alain.greiner@lip6.fr 
+ *              eric.guthmuller@polytechnique.edu
  *              cesar.fuguet-tortolero@lip6.fr
  *              alexandre.joannou@lip6.fr
@@ -150 +151 @@
         MULTI_ACK_UPT_LOCK,
         MULTI_ACK_UPT_CLEAR,
-        MULTI_ACK_WRITE_RSP,
-        MULTI_ACK_CONFIG_ACK
+        MULTI_ACK_WRITE_RSP
       };
 
@@ -159 +159 @@
         CONFIG_IDLE,
         CONFIG_LOOP,
+        CONFIG_WAIT,
         CONFIG_RSP,
         CONFIG_DIR_REQ,
         CONFIG_DIR_ACCESS,
-        CONFIG_DIR_IVT_LOCK,
+        CONFIG_IVT_LOCK,
         CONFIG_BC_SEND,
-        CONFIG_BC_WAIT,
-        CONFIG_INV_SEND,
+        CONFIG_INVAL_SEND,
         CONFIG_HEAP_REQ,
         CONFIG_HEAP_SCAN,
         CONFIG_HEAP_LAST,
-        CONFIG_INV_WAIT
+        CONFIG_TRT_LOCK,
+        CONFIG_TRT_SET,
+        CONFIG_PUT_REQ
       };
 
@@ -197 +199 @@
         WRITE_DIR_REQ,
         WRITE_DIR_LOCK,
-        WRITE_DIR_READ,
         WRITE_DIR_HIT,
         WRITE_UPT_LOCK,
@@ -209 +210 @@
         WRITE_MISS_TRT_SET,
         WRITE_MISS_XRAM_REQ,
+        WRITE_BC_DIR_READ,
         WRITE_BC_TRT_LOCK,
         WRITE_BC_IVT_LOCK,
@@ -235 +237 @@
         XRAM_RSP_DIR_UPDT,
         XRAM_RSP_DIR_RSP,
-        XRAM_RSP_INVAL_LOCK,
+        XRAM_RSP_IVT_LOCK,
         XRAM_RSP_INVAL_WAIT,
         XRAM_RSP_INVAL,
@@ -254 +256 @@
         IXR_CMD_XRAM_IDLE,
         IXR_CMD_CLEANUP_IDLE,
-        IXR_CMD_TRT_LOCK,
-        IXR_CMD_READ,
-        IXR_CMD_WRITE,
-        IXR_CMD_CAS,
-        IXR_CMD_XRAM,
-        IXR_CMD_CLEANUP_DATA
+        IXR_CMD_CONFIG_IDLE,
+        IXR_CMD_READ_TRT,
+        IXR_CMD_WRITE_TRT,
+        IXR_CMD_CAS_TRT,
+        IXR_CMD_XRAM_TRT,
+        IXR_CMD_CLEANUP_TRT,
+        IXR_CMD_CONFIG_TRT,
+        IXR_CMD_READ_SEND,
+        IXR_CMD_WRITE_SEND,
+        IXR_CMD_CAS_SEND,
+        IXR_CMD_XRAM_SEND,
+        IXR_CMD_CLEANUP_DATA_SEND,
+        IXR_CMD_CONFIG_SEND
       };
 
@@ -306 +315 @@
         CLEANUP_IVT_CLEAR,
         CLEANUP_WRITE_RSP,
-        CLEANUP_CONFIG_ACK,
         CLEANUP_IXR_REQ,
         CLEANUP_WAIT,
@@ -333 +341 @@
         ALLOC_TRT_IXR_RSP,
         ALLOC_TRT_CLEANUP,
-        ALLOC_TRT_IXR_CMD
+        ALLOC_TRT_IXR_CMD,
+        ALLOC_TRT_CONFIG
       };
 
@@ -394 +403 @@
       };
 
-      /* Configuration commands */
-      enum cmd_config_type_e
-      {
-          CMD_CONFIG_INVAL = 0,
-          CMD_CONFIG_SYNC  = 1
-      };
-
-      // debug variables (for each FSM)
+      // debug variables 
       bool                 m_debug;
       bool                 m_debug_previous_valid;
       size_t               m_debug_previous_count;
       bool                 m_debug_previous_dirty;
-      sc_signal<data_t>*   m_debug_previous_data;
-      sc_signal<data_t>*   m_debug_data;
-
-      bool         m_monitor_ok;
-      addr_t       m_monitor_base;
-      addr_t       m_monitor_length;
+      data_t *             m_debug_previous_data;
+      data_t *             m_debug_data;
 
       // instrumentation counters
@@ -619 +617 @@
       uint32_t                           m_broadcast_boundaries;
 
-      //////////////////////////////////////////////////
-      // Registers controlled by the TGT_CMD fsm
-      //////////////////////////////////////////////////
-
-      sc_signal<int>         r_tgt_cmd_fsm;
-
       // Fifo between TGT_CMD fsm and READ fsm
       GenericFifo<addr_t>    m_cmd_read_addr_fifo;
@@ -668 +660 @@
       sc_signal<size_t>   r_tgt_cmd_config_cmd;
 
+      //////////////////////////////////////////////////
+      // Registers controlled by the TGT_CMD fsm
+      //////////////////////////////////////////////////
+
+      sc_signal<int>         r_tgt_cmd_fsm;
+      sc_signal<size_t>      r_tgt_cmd_srcid;           // srcid for response to config
+      sc_signal<size_t>      r_tgt_cmd_trdid;           // trdid for response to config
+      sc_signal<size_t>      r_tgt_cmd_pktid;           // pktid for response to config
+
       ///////////////////////////////////////////////////////
       // Registers controlled by the CONFIG fsm
       ///////////////////////////////////////////////////////
 
-      sc_signal<int>      r_config_fsm;            // FSM state
-      sc_signal<bool>     r_config_lock;           // lock protecting exclusive access
-      sc_signal<int>      r_config_cmd;            // config request status
-      sc_signal<addr_t>   r_config_address;        // target buffer physical address
-      sc_signal<size_t>   r_config_srcid;          // config request srcid
-      sc_signal<size_t>   r_config_trdid;          // config request trdid
-      sc_signal<size_t>   r_config_pktid;          // config request pktid
-      sc_signal<size_t>   r_config_nlines;         // number of lines covering the buffer
-      sc_signal<size_t>   r_config_dir_way;        // DIR: selected way
-      sc_signal<size_t>   r_config_dir_count;      // DIR: number of copies
-      sc_signal<bool>     r_config_dir_is_cnt;     // DIR: counter mode (broadcast required)
-      sc_signal<size_t>   r_config_dir_copy_srcid; // DIR: first copy SRCID
-      sc_signal<bool>     r_config_dir_copy_inst;  // DIR: first copy L1 type
-      sc_signal<size_t>   r_config_dir_next_ptr;   // DIR: index of next copy in HEAP
-      sc_signal<size_t>   r_config_heap_next;      // current pointer to scan HEAP
-
-      sc_signal<size_t>   r_config_ivt_index;      // IVT index
+      sc_signal<int>      r_config_fsm;               // FSM state
+      sc_signal<bool>     r_config_lock;              // lock protecting exclusive access
+      sc_signal<int>      r_config_cmd;               // config request type  
+      sc_signal<addr_t>   r_config_address;           // target buffer physical address
+      sc_signal<size_t>   r_config_srcid;             // config request srcid
+      sc_signal<size_t>   r_config_trdid;             // config request trdid
+      sc_signal<size_t>   r_config_pktid;             // config request pktid
+      sc_signal<size_t>   r_config_cmd_lines;         // number of lines to be handled
+      sc_signal<size_t>   r_config_rsp_lines;         // number of lines not completed
+      sc_signal<size_t>   r_config_dir_way;           // DIR: selected way
+      sc_signal<bool>     r_config_dir_lock;          // DIR: locked entry
+      sc_signal<size_t>   r_config_dir_count;         // DIR: number of copies
+      sc_signal<bool>     r_config_dir_is_cnt;        // DIR: counter mode (broadcast)
+      sc_signal<size_t>   r_config_dir_copy_srcid;    // DIR: first copy SRCID
+      sc_signal<bool>     r_config_dir_copy_inst;     // DIR: first copy L1 type
+      sc_signal<size_t>   r_config_dir_ptr;           // DIR: index of next copy in HEAP
+      sc_signal<size_t>   r_config_heap_next;         // current pointer to scan HEAP
+      sc_signal<size_t>   r_config_trt_index;         // selected entry in TRT
+      sc_signal<size_t>   r_config_ivt_index;         // selected entry in IVT 
+
+      // Buffer between CONFIG fsm and IXR_CMD fsm
+      sc_signal<bool>     r_config_to_ixr_cmd_req;    // valid request
+      sc_signal<size_t>   r_config_to_ixr_cmd_index;  // TRT index
+
 
       // Buffer between CONFIG fsm and TGT_RSP fsm (send a done response to L1 cache)
@@ -705 +713 @@
       GenericFifo<size_t> m_config_to_cc_send_srcid_fifo;   // fifo for owners srcid
 
-#if L1_MULTI_CACHE
-      GenericFifo<size_t> m_config_to_cc_send_cache_id_fifo; // fifo for cache_id
-#endif
-
       ///////////////////////////////////////////////////////
       // Registers controlled by the READ fsm
       ///////////////////////////////////////////////////////
 
-      sc_signal<int>      r_read_fsm;          // FSM state
-      sc_signal<size_t>   r_read_copy;         // Srcid of the first copy
-      sc_signal<size_t>   r_read_copy_cache;   // Srcid of the first copy
-      sc_signal<bool>     r_read_copy_inst;    // Type of the first copy
-      sc_signal<tag_t>    r_read_tag;          // cache line tag (in directory)
-      sc_signal<bool>     r_read_is_cnt;       // is_cnt bit (in directory)
-      sc_signal<bool>     r_read_lock;         // lock bit (in directory)
-      sc_signal<bool>     r_read_dirty;        // dirty bit (in directory)
-      sc_signal<size_t>   r_read_count;        // number of copies
-      sc_signal<size_t>   r_read_ptr;          // pointer to the heap
-      sc_signal<data_t> * r_read_data;         // data (one cache line)
-      sc_signal<size_t>   r_read_way;          // associative way (in cache)
-      sc_signal<size_t>   r_read_trt_index;    // Transaction Table index
-      sc_signal<size_t>   r_read_next_ptr;     // Next entry to point to
-      sc_signal<bool>     r_read_last_free;    // Last free entry
-      sc_signal<addr_t>   r_read_ll_key;       // LL key from the llsc_global_table
-
-      // Buffer between READ fsm and IXR_CMD fsm (ask a missing cache line to XRAM)
-      sc_signal<bool>     r_read_to_ixr_cmd_req;    // valid request
-      sc_signal<addr_t>   r_read_to_ixr_cmd_nline;  // cache line index
-      sc_signal<size_t>   r_read_to_ixr_cmd_trdid;  // index in Transaction Table
+      sc_signal<int>      r_read_fsm;                 // FSM state
+      sc_signal<size_t>   r_read_copy;                // Srcid of the first copy
+      sc_signal<size_t>   r_read_copy_cache;          // Srcid of the first copy
+      sc_signal<bool>     r_read_copy_inst;           // Type of the first copy
+      sc_signal<tag_t>    r_read_tag;                 // cache line tag (in directory)
+      sc_signal<bool>     r_read_is_cnt;              // is_cnt bit (in directory)
+      sc_signal<bool>     r_read_lock;                // lock bit (in directory)
+      sc_signal<bool>     r_read_dirty;               // dirty bit (in directory)
+      sc_signal<size_t>   r_read_count;               // number of copies
+      sc_signal<size_t>   r_read_ptr;                 // pointer to the heap
+      sc_signal<data_t> * r_read_data;                // data (one cache line)
+      sc_signal<size_t>   r_read_way;                 // associative way (in cache)
+      sc_signal<size_t>   r_read_trt_index;           // Transaction Table index
+      sc_signal<size_t>   r_read_next_ptr;            // Next entry to point to
+      sc_signal<bool>     r_read_last_free;           // Last free entry
+      sc_signal<addr_t>   r_read_ll_key;              // LL key from llsc_global_table
+
+      // Buffer between READ fsm and IXR_CMD fsm 
+      sc_signal<bool>     r_read_to_ixr_cmd_req;      // valid request
+      sc_signal<size_t>   r_read_to_ixr_cmd_index;    // TRT index
 
       // Buffer between READ fsm and TGT_RSP fsm (send a hit read response to L1 cache)
-      sc_signal<bool>     r_read_to_tgt_rsp_req;    // valid request
-      sc_signal<size_t>   r_read_to_tgt_rsp_srcid;  // Transaction srcid
-      sc_signal<size_t>   r_read_to_tgt_rsp_trdid;  // Transaction trdid
-      sc_signal<size_t>   r_read_to_tgt_rsp_pktid;  // Transaction pktid
-      sc_signal<data_t> * r_read_to_tgt_rsp_data;   // data (one cache line)
-      sc_signal<size_t>   r_read_to_tgt_rsp_word;   // first word of the response
-      sc_signal<size_t>   r_read_to_tgt_rsp_length; // length of the response
-      sc_signal<addr_t>   r_read_to_tgt_rsp_ll_key; // LL key from the llsc_global_table
+      sc_signal<bool>     r_read_to_tgt_rsp_req;      // valid request
+      sc_signal<size_t>   r_read_to_tgt_rsp_srcid;    // Transaction srcid
+      sc_signal<size_t>   r_read_to_tgt_rsp_trdid;    // Transaction trdid
+      sc_signal<size_t>   r_read_to_tgt_rsp_pktid;    // Transaction pktid
+      sc_signal<data_t> * r_read_to_tgt_rsp_data;     // data (one cache line)
+      sc_signal<size_t>   r_read_to_tgt_rsp_word;     // first word of the response
+      sc_signal<size_t>   r_read_to_tgt_rsp_length;   // length of the response
+      sc_signal<addr_t>   r_read_to_tgt_rsp_ll_key;   // LL key from llsc_global_table
 
       ///////////////////////////////////////////////////////////////
@@ -749 +752 @@
       ///////////////////////////////////////////////////////////////
 
-      sc_signal<int>      r_write_fsm;        // FSM state
-      sc_signal<addr_t>   r_write_address;    // first word address
-      sc_signal<size_t>   r_write_word_index; // first word index in line
-      sc_signal<size_t>   r_write_word_count; // number of words in line
-      sc_signal<size_t>   r_write_srcid;      // transaction srcid
-      sc_signal<size_t>   r_write_trdid;      // transaction trdid
-      sc_signal<size_t>   r_write_pktid;      // transaction pktid
-      sc_signal<data_t> * r_write_data;       // data (one cache line)
-      sc_signal<be_t>   * r_write_be;         // one byte enable per word
-      sc_signal<bool>     r_write_byte;       // (BE != 0X0) and (BE != 0xF)
-      sc_signal<bool>     r_write_is_cnt;     // is_cnt bit (in directory)
-      sc_signal<bool>     r_write_lock;       // lock bit (in directory)
-      sc_signal<tag_t>    r_write_tag;        // cache line tag (in directory)
-      sc_signal<size_t>   r_write_copy;       // first owner of the line
-      sc_signal<size_t>   r_write_copy_cache; // first owner of the line
-      sc_signal<bool>     r_write_copy_inst;  // is this owner a ICache ?
-      sc_signal<size_t>   r_write_count;      // number of copies
-      sc_signal<size_t>   r_write_ptr;        // pointer to the heap
-      sc_signal<size_t>   r_write_next_ptr;   // next pointer to the heap
-      sc_signal<bool>     r_write_to_dec;     // need to decrement update counter
-      sc_signal<size_t>   r_write_way;        // way of the line
-      sc_signal<size_t>   r_write_trt_index;  // index in Transaction Table
-      sc_signal<size_t>   r_write_upt_index;  // index in Update Table
-      sc_signal<bool>     r_write_sc_fail;    // sc command failed
-      sc_signal<bool>     r_write_pending_sc; // sc command pending
+      sc_signal<int>      r_write_fsm;                // FSM state
+      sc_signal<addr_t>   r_write_address;            // first word address
+      sc_signal<size_t>   r_write_word_index;         // first word index in line
+      sc_signal<size_t>   r_write_word_count;         // number of words in line
+      sc_signal<size_t>   r_write_srcid;              // transaction srcid
+      sc_signal<size_t>   r_write_trdid;              // transaction trdid
+      sc_signal<size_t>   r_write_pktid;              // transaction pktid
+      sc_signal<data_t> * r_write_data;               // data (one cache line)
+      sc_signal<be_t>   * r_write_be;                 // one byte enable per word
+      sc_signal<bool>     r_write_byte;               // (BE != 0X0) and (BE != 0xF)
+      sc_signal<bool>     r_write_is_cnt;             // is_cnt bit (in directory)
+      sc_signal<bool>     r_write_lock;               // lock bit (in directory)
+      sc_signal<tag_t>    r_write_tag;                // cache line tag (in directory)
+      sc_signal<size_t>   r_write_copy;               // first owner of the line
+      sc_signal<size_t>   r_write_copy_cache;         // first owner of the line
+      sc_signal<bool>     r_write_copy_inst;          // is this owner a ICache ?
+      sc_signal<size_t>   r_write_count;              // number of copies
+      sc_signal<size_t>   r_write_ptr;                // pointer to the heap
+      sc_signal<size_t>   r_write_next_ptr;           // next pointer to the heap
+      sc_signal<bool>     r_write_to_dec;             // need to decrement update counter
+      sc_signal<size_t>   r_write_way;                // way of the line
+      sc_signal<size_t>   r_write_trt_index;          // index in Transaction Table
+      sc_signal<size_t>   r_write_upt_index;          // index in Update Table
+      sc_signal<bool>     r_write_sc_fail;            // sc command failed
+      sc_signal<bool>     r_write_pending_sc;         // sc command pending
 
       // Buffer between WRITE fsm and TGT_RSP fsm (acknowledge a write command from L1)
@@ -782 +785 @@
       sc_signal<bool>     r_write_to_tgt_rsp_sc_fail; // sc command failed
 
-      // Buffer between WRITE fsm and IXR_CMD fsm (ask a missing cache line to XRAM)
-      sc_signal<bool>     r_write_to_ixr_cmd_req;   // valid request
-      sc_signal<bool>     r_write_to_ixr_cmd_write; // write request
-      sc_signal<addr_t>   r_write_to_ixr_cmd_nline; // cache line index
-      sc_signal<data_t> * r_write_to_ixr_cmd_data;  // cache line data
-      sc_signal<size_t>   r_write_to_ixr_cmd_trdid; // index in Transaction Table
+      // Buffer between WRITE fsm and IXR_CMD fsm 
+      sc_signal<bool>     r_write_to_ixr_cmd_req;     // valid request
+      sc_signal<bool>     r_write_to_ixr_cmd_put;     // request type (GET/PUT)
+      sc_signal<size_t>   r_write_to_ixr_cmd_index;   // TRT index 
 
       // Buffer between WRITE fsm and CC_SEND fsm (Update/Invalidate L1 caches)
@@ -801 +802 @@
       GenericFifo<size_t> m_write_to_cc_send_srcid_fifo;    // fifo for srcids
 
-#if L1_MULTI_CACHE
-      GenericFifo<size_t> m_write_to_cc_send_cache_id_fifo; // fifo for srcids
-#endif
-
       // Buffer between WRITE fsm and MULTI_ACK fsm (Decrement UPT entry)
       sc_signal<bool>     r_write_to_multi_ack_req;       // valid request
@@ -820 +817 @@
       sc_signal<addr_t>   r_multi_ack_nline;     // pending write nline
 
-      // signaling completion of multi-inval to CONFIG fsm
-      sc_signal<bool>     r_multi_ack_to_config_ack; 
-
       // Buffer between MULTI_ACK fsm and TGT_RSP fsm (complete write/update transaction)
       sc_signal<bool>     r_multi_ack_to_tgt_rsp_req;   // valid request
@@ -839 +833 @@
       sc_signal<addr_t>   r_cleanup_nline;         // cache line index
 
-#if L1_MULTI_CACHE
-      sc_signal<size_t>   r_cleanup_pktid;         // transaction pktid
-#endif
 
       sc_signal<copy_t>   r_cleanup_copy;          // first copy
@@ -868 +859 @@
       sc_signal<size_t>   r_cleanup_index;         // index of the INVAL line (in the UPT)
 
-      // signaling completion of broadcast-inval to CONFIG fsm
-      sc_signal<bool>     r_cleanup_to_config_ack;  
-       
       // Buffer between CLEANUP fsm and TGT_RSP fsm (acknowledge a write command from L1)
       sc_signal<bool>     r_cleanup_to_tgt_rsp_req;   // valid request
@@ -881 +869 @@
       ///////////////////////////////////////////////////////
 
-      sc_signal<int>      r_cas_fsm;        // FSM state
-      sc_signal<data_t>   r_cas_wdata;      // write data word
-      sc_signal<data_t> * r_cas_rdata;      // read data word
-      sc_signal<uint32_t> r_cas_lfsr;       // lfsr for random introducing
-      sc_signal<size_t>   r_cas_cpt;        // size of command
-      sc_signal<copy_t>   r_cas_copy;       // Srcid of the first copy
-      sc_signal<copy_t>   r_cas_copy_cache; // Srcid of the first copy
-      sc_signal<bool>     r_cas_copy_inst;  // Type of the first copy
-      sc_signal<size_t>   r_cas_count;      // number of copies
-      sc_signal<size_t>   r_cas_ptr;        // pointer to the heap
-      sc_signal<size_t>   r_cas_next_ptr;   // next pointer to the heap
-      sc_signal<bool>     r_cas_is_cnt;     // is_cnt bit (in directory)
-      sc_signal<bool>     r_cas_dirty;      // dirty bit (in directory)
-      sc_signal<size_t>   r_cas_way;        // way in directory
-      sc_signal<size_t>   r_cas_set;        // set in directory
-      sc_signal<data_t>   r_cas_tag;        // cache line tag (in directory)
-      sc_signal<size_t>   r_cas_trt_index;  // Transaction Table index
-      sc_signal<size_t>   r_cas_upt_index;  // Update Table index
-      sc_signal<data_t> * r_cas_data;       // cache line data
-
-      // Buffer between CAS fsm and IXR_CMD fsm (XRAM write)
+      sc_signal<int>      r_cas_fsm;              // FSM state
+      sc_signal<data_t>   r_cas_wdata;            // write data word
+      sc_signal<data_t> * r_cas_rdata;            // read data word
+      sc_signal<uint32_t> r_cas_lfsr;             // lfsr for random introducing
+      sc_signal<size_t>   r_cas_cpt;              // size of command
+      sc_signal<copy_t>   r_cas_copy;             // Srcid of the first copy
+      sc_signal<copy_t>   r_cas_copy_cache;       // Srcid of the first copy
+      sc_signal<bool>     r_cas_copy_inst;        // Type of the first copy
+      sc_signal<size_t>   r_cas_count;            // number of copies
+      sc_signal<size_t>   r_cas_ptr;              // pointer to the heap
+      sc_signal<size_t>   r_cas_next_ptr;         // next pointer to the heap
+      sc_signal<bool>     r_cas_is_cnt;           // is_cnt bit (in directory)
+      sc_signal<bool>     r_cas_dirty;            // dirty bit (in directory)
+      sc_signal<size_t>   r_cas_way;              // way in directory
+      sc_signal<size_t>   r_cas_set;              // set in directory
+      sc_signal<data_t>   r_cas_tag;              // cache line tag (in directory)
+      sc_signal<size_t>   r_cas_trt_index;        // Transaction Table index
+      sc_signal<size_t>   r_cas_upt_index;        // Update Table index
+      sc_signal<data_t> * r_cas_data;             // cache line data
+
+      // Buffer between CAS fsm and IXR_CMD fsm 
       sc_signal<bool>     r_cas_to_ixr_cmd_req;   // valid request
-      sc_signal<addr_t>   r_cas_to_ixr_cmd_nline; // cache line index
-      sc_signal<size_t>   r_cas_to_ixr_cmd_trdid; // index in Transaction Table
-      sc_signal<bool>     r_cas_to_ixr_cmd_write; // write request
-      sc_signal<data_t> * r_cas_to_ixr_cmd_data;  // cache line data
-
+      sc_signal<bool>     r_cas_to_ixr_cmd_put;   // request type (GET/PUT)
+      sc_signal<size_t>   r_cas_to_ixr_cmd_index; // TRT index 
 
       // Buffer between CAS fsm and TGT_RSP fsm
@@ -928 +913 @@
       GenericFifo<size_t> m_cas_to_cc_send_srcid_fifo;    // fifo for srcids
 
-#if L1_MULTI_CACHE
-      GenericFifo<size_t> m_cas_to_cc_send_cache_id_fifo; // fifo for srcids
-#endif
-
       ////////////////////////////////////////////////////
       // Registers controlled by the IXR_RSP fsm
       ////////////////////////////////////////////////////
 
-      sc_signal<int>      r_ixr_rsp_fsm;       // FSM state
-      sc_signal<size_t>   r_ixr_rsp_trt_index; // TRT entry index
-      sc_signal<size_t>   r_ixr_rsp_cpt;       // word counter
+      sc_signal<int>      r_ixr_rsp_fsm;                // FSM state
+      sc_signal<size_t>   r_ixr_rsp_trt_index;          // TRT entry index
+      sc_signal<size_t>   r_ixr_rsp_cpt;                // word counter
+
+      // Buffer between IXR_RSP fsm and CONFIG fsm  (response from the XRAM)
+      sc_signal<bool>     r_ixr_rsp_to_config_ack;      // one single bit   
 
       // Buffer between IXR_RSP fsm and XRAM_RSP fsm  (response from the XRAM)
-      sc_signal<bool>   * r_ixr_rsp_to_xram_rsp_rok; // A xram response is ready
+      sc_signal<bool>   * r_ixr_rsp_to_xram_rsp_rok;    // one bit per TRT entry
       sc_signal<bool>   * r_ixr_rsp_to_xram_rsp_no_coherent; // A xram response is ready and no coherent (ODCCP)
 
@@ -986 +970 @@
       GenericFifo<size_t> m_xram_rsp_to_cc_send_srcid_fifo;    // fifo for srcids
 
-#if L1_MULTI_CACHE
-      GenericFifo<size_t> m_xram_rsp_to_cc_send_cache_id_fifo; // fifo for srcids
-#endif
-
-      // Buffer between XRAM_RSP fsm and IXR_CMD fsm (XRAM write)
+      // Buffer between XRAM_RSP fsm and IXR_CMD fsm 
       sc_signal<bool>     r_xram_rsp_to_ixr_cmd_req;   // Valid request
-      sc_signal<addr_t>   r_xram_rsp_to_ixr_cmd_nline; // cache line index
-      sc_signal<data_t> * r_xram_rsp_to_ixr_cmd_data;  // cache line data
-      sc_signal<size_t>   r_xram_rsp_to_ixr_cmd_trdid; // index in transaction table
+      sc_signal<size_t>   r_xram_rsp_to_ixr_cmd_index; // TRT index 
 
       ////////////////////////////////////////////////////
@@ -1001 +979 @@
 
       sc_signal<int>      r_ixr_cmd_fsm;
-      sc_signal<size_t>   r_ixr_cmd_cpt;
+      sc_signal<size_t>   r_ixr_cmd_word;              // word index for a put
+      sc_signal<size_t>   r_ixr_cmd_trdid;             // TRT index value     
+      sc_signal<addr_t>   r_ixr_cmd_address;           // address to XRAM
+      sc_signal<data_t> * r_ixr_cmd_wdata;             // cache line buffer
+      sc_signal<bool>     r_ixr_cmd_get;               // transaction type (PUT/GET)
 
       ////////////////////////////////////////////////////
@@ -1076 +1058 @@
       sc_signal<uint32_t>  r_cleanup_to_ixr_cmd_srcid;
       sc_signal<bool>      r_cleanup_to_ixr_cmd_l1_dirty_ncc; // this cleanup was dirty in L1
-      sc_signal<uint32_t>  r_cleanup_to_ixr_cmd_trdid;
+      sc_signal<uint32_t>  r_cleanup_to_ixr_cmd_index;
       sc_signal<uint32_t>  r_cleanup_to_ixr_cmd_pktid;
       sc_signal<addr_t>    r_cleanup_to_ixr_cmd_nline;

branches/ODCCP/modules/vci_mem_cache/caba/source/include/xram_transaction.h

@@ -34 +34 @@
     bool                rerror;         // error returned by xram
     data_t              ll_key;         // LL key returned by the llsc_global_table
+    bool                config;         // transaction required by CONFIG FSM
 
     /////////////////////////////////////////////////////////////////////
@@ -42 +43 @@
         valid           = false;
         rerror      = false;
+        config      = false;
     }
 
@@ -80 +82 @@
         rerror      = source.rerror;
         ll_key      = source.ll_key;
+        config      = source.config;
     }
 
@@ -87 +90 @@
     void print()
     {
+        std::cout << "------- TRT entry -------" << std::endl;
         std::cout << "valid       = " << valid        << std::endl;
         std::cout << "xram_read   = " << xram_read    << std::endl;
@@ -96 +100 @@
         std::cout << "read_length = " << read_length  << std::endl;
         std::cout << "word_index  = " << word_index   << std::endl; 
-        for(size_t i=0; i<wdata_be.size() ; i++){
-            std::cout << "wdata_be [" << i <<"] = " << wdata_be[i] << std::endl;
-        }
-        for(size_t i=0; i<wdata.size() ; i++){
-            std::cout << "wdata [" << i <<"] = " << wdata[i] << std::endl;
-        }
+        for(size_t i=0; i<wdata_be.size() ; i++)
+        {
+            std::cout << "wdata_be[" << std::dec << i << "] = " 
+                      << std::hex << wdata_be[i] << std::endl;
+        }
+        for(size_t i=0; i<wdata.size() ; i++)
+        {
+            std::cout << "wdata[" << std::dec << i << "] = " 
+                      << std::hex << wdata[i] << std::endl;
+        }
+        std::cout << "rerror      = " << rerror       << std::endl;
+        std::cout << "ll_key      = " << ll_key       << std::endl;
+        std::cout << "config      = " << config       << std::endl;
         std::cout << std::endl;
-        std::cout << "rerror      = " << rerror       << std::endl;
     }
 
@@ -114 +124 @@
         wdata_be.clear();
         wdata.clear();
-        valid=false;
-        rerror=false;
-    }
-
-    TransactionTabEntry(const TransactionTabEntry &source){
+        valid  = false;
+        rerror = false;
+        config = false;
+    }
+
+    TransactionTabEntry(const TransactionTabEntry &source)
+    {
         valid       = source.valid;
         xram_read       = source.xram_read;
@@ -132 +144 @@
         rerror      = source.rerror;
         ll_key      = source.ll_key;
+        config      = source.config;
     }
 
@@ -197 +210 @@
         delete [] tab;
     }
-
     /////////////////////////////////////////////////////////////////////
     // The size() function returns the size of the tab
@@ -205 +217 @@
         return size_tab;
     }
-
     /////////////////////////////////////////////////////////////////////
     // The init() function initializes the transaction tab entries
@@ -211 +222 @@
     void init()
     {
-        for ( size_t i=0; i<size_tab; i++) {
+        for ( size_t i=0; i<size_tab; i++) 
+        {
             tab[i].init();
         }
     }
-
     /////////////////////////////////////////////////////////////////////
     // The print() function prints a transaction tab entry
@@ -223 +234 @@
     void print(const size_t index)
     {
-        assert( (index < size_tab) 
-                && "Invalid Transaction Tab Entry");
+        assert( (index < size_tab) and
+        "MEMC ERROR: The selected entry is out of range in TRT write_data_mask()");
+
         tab[index].print();
         return;
     }
-
     /////////////////////////////////////////////////////////////////////
     // The read() function returns a transaction tab entry.
@@ -236 +247 @@
     TransactionTabEntry read(const size_t index)
     {
-        assert( (index < size_tab) 
-                && "Invalid Transaction Tab Entry");
+        assert( (index < size_tab) and 
+        "MEMC ERROR: Invalid Transaction Tab Entry");
+
         return tab[index];
     }
-
     /////////////////////////////////////////////////////////////////////
     // The full() function returns the state of the transaction tab
@@ -249 +260 @@
     bool full(size_t &index)
     {
-        for(size_t i=0; i<size_tab; i++){
-            if(!tab[i].valid){
+        for(size_t i=0; i<size_tab; i++)
+        {
+            if(!tab[i].valid)
+            {
                 index=i;
                 return false;   
@@ -257 +270 @@
         return true;
     }
-
     /////////////////////////////////////////////////////////////////////
     // The hit_read() function checks if an XRAM read transaction exists 
@@ -268 +280 @@
     bool hit_read(const addr_t nline,size_t &index)
     {
-        for(size_t i=0; i<size_tab; i++){
-            if((tab[i].valid && (nline==tab[i].nline)) && (tab[i].xram_read)) {
+        for(size_t i=0; i<size_tab; i++)
+        {
+            if((tab[i].valid && (nline==tab[i].nline)) && (tab[i].xram_read)) 
+            {
                 index=i;
                 return true;    
@@ -276 +290 @@
         return false;
     }
-
     ///////////////////////////////////////////////////////////////////////
     // The hit_write() function looks if an XRAM write transaction exists 
@@ -286 +299 @@
     bool hit_write(const addr_t nline)
     {
-        for(size_t i=0; i<size_tab; i++){
-            if(tab[i].valid && (nline==tab[i].nline) && !(tab[i].xram_read)) {
+        for(size_t i=0; i<size_tab; i++)
+        {
+            if(tab[i].valid && (nline==tab[i].nline) && !(tab[i].xram_read)) 
+            {
                 return true;    
             }
@@ -325 +340 @@
             const std::vector<data_t> &data) 
     {
-        assert( (index < size_tab) 
-                && "Invalid Transaction Tab Entry");
-        assert(be.size()==tab[index].wdata_be.size() 
-                && "Bad data mask in write_data_mask in TransactionTab");
-        assert(data.size()==tab[index].wdata.size() 
-                && "Bad data in write_data_mask in TransactionTab");
-
-        for(size_t i=0; i<tab[index].wdata_be.size() ; i++) {
+        assert( (index < size_tab) and
+        "MEMC ERROR: The selected entry is out of range in TRT write_data_mask()");
+
+        assert( (be.size()==tab[index].wdata_be.size()) and
+        "MEMC ERROR: Bad be size in TRT write_data_mask()");
+
+        assert( (data.size()==tab[index].wdata.size()) and
+        "MEMC ERROR: Bad data size in TRT write_data_mask()");
+
+        for(size_t i=0; i<tab[index].wdata_be.size() ; i++) 
+        {
             tab[index].wdata_be[i] = tab[index].wdata_be[i] | be[i];
             data_t mask = be_to_mask(be[i]);
@@ -338 +356 @@
         }
     }
-
     /////////////////////////////////////////////////////////////////////
     // The set() function registers a transaction (read or write)
@@ -355 +372 @@
     // - data_be : the mask of the data to write (in case of write)
     // - ll_key  : the ll key (if any) returned by the llsc_global_table
+    // - config  : transaction required by config FSM
     /////////////////////////////////////////////////////////////////////
     void set(const size_t index,
@@ -367 +385 @@
             const std::vector<be_t> &data_be,
             const std::vector<data_t> &data, 
-            const data_t ll_key = 0) 
-    {
-        assert( (index < size_tab) 
-                && "The selected entry is out of range in set() Transaction Tab");
-        assert(data_be.size()==tab[index].wdata_be.size() 
-                && "Bad data_be argument in set() TransactionTab");
-        assert(data.size()==tab[index].wdata.size() 
-                && "Bad data argument in set() TransactionTab");
+            const data_t ll_key = 0,
+            const bool config = false) 
+    {
+        assert( (index < size_tab) and
+        "MEMC ERROR: The selected entry is out of range in TRT set()");
+
+        assert( (data_be.size()==tab[index].wdata_be.size()) and 
+        "MEMC ERROR: Bad data_be argument in TRT set()");
+
+        assert( (data.size()==tab[index].wdata.size()) and 
+        "MEMC ERROR: Bad data argument in TRT set()");
 
         tab[index].valid                = true;
@@ -386 +407 @@
         tab[index].word_index       = word_index;
         tab[index].ll_key           = ll_key;
+        tab[index].config           = config;
         for(size_t i=0; i<tab[index].wdata.size(); i++) 
         {
@@ -398 +420 @@
     // The BE field in TRT is taken into account.
     // Arguments :
-    // - index : the index of the transaction in the transaction tab
-    // - word_index : the index of the data in the line
-    // - data : a 64 bits value
-    // - error : invalid data
+    // - index : index of the entry in TRT
+    // - word  : index of the 32 bits word in the line
+    // - data  : 64 bits value (first data right)
     /////////////////////////////////////////////////////////////////////
     void write_rsp(const size_t      index,
                    const size_t      word,
-                   const wide_data_t data,
-                   const bool        rerror)
+                   const wide_data_t data)
     {
         data_t  value;
         data_t  mask;
 
-        if ( index >= size_tab )
-        { 
-            std::cout << "VCI_MEM_CACHE ERRROR " << tab_name
-                      <<  " TRT entry  out of range in write_rsp()" << std::endl;
-            exit(0);
-        }
-        if ( word > tab[index].wdata_be.size() ) 
-        { 
-            std::cout << "VCI_MEM_CACHE ERRROR " << tab_name
-                      <<  " Bad word_index in write_rsp() in TRT" << std::endl;
-            exit(0);
-        }
-        if ( not tab[index].valid )
-        { 
-            std::cout << "VCI_MEM_CACHE ERRROR " << tab_name
-                      <<  " TRT Entry invalid in write_rsp()" << std::endl;
-            exit(0);
-        }
-        if ( not tab[index].xram_read )
-        { 
-            std::cout << "VCI_MEM_CACHE ERRROR " << tab_name
-                      <<  " TRT entry is not an XRAM GET in write_rsp()" << std::endl;
-            exit(0);
-        }
+        assert( (index < size_tab) and
+        "MEMC ERROR: The selected entry is out of range in TRT write_rsp()");
+
+        assert( (word < tab[index].wdata_be.size()) and 
+        "MEMC ERROR: Bad word index in TRT write_rsp()");
+
+        assert( (tab[index].valid) and
+        "MEMC ERROR: TRT entry not valid in TRT write_rsp()");
+
+        assert( (tab[index].xram_read ) and
+        "MEMC ERROR: TRT entry is not a GET in TRT write_rsp()");
 
         // first 32 bits word
@@ -445 +452 @@
         mask  = be_to_mask(tab[index].wdata_be[word+1]);
         tab[index].wdata[word+1] = (tab[index].wdata[word+1] & mask) | (value & ~mask);
-
-        // error update
-        tab[index].rerror |= rerror;
-    }
-
+    }
     /////////////////////////////////////////////////////////////////////
     // The erase() function erases an entry in the transaction tab.
@@ -457 +460 @@
     void erase(const size_t index)
     {
-        assert( (index < size_tab) 
-                && "The selected entry is out of range in erase() Transaction Tab");
+        assert( (index < size_tab) and 
+        "MEMC ERROR: The selected entry is out of range in TRT erase()");
+
         tab[index].valid        = false;
         tab[index].rerror   = false;
+    }
+    /////////////////////////////////////////////////////////////////////
+    // The is_config() function returns the config flag value.
+    // Arguments :
+    // - index : the index of the entry in the transaction tab
+    /////////////////////////////////////////////////////////////////////
+    bool is_config(const size_t index)
+    {
+        assert( (index < size_tab) and
+        "MEMC ERROR: The selected entry is out of range in TRT is_config()");
+
+        return tab[index].config;
     }
 }; // end class TransactionTab

branches/ODCCP/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp

@@ -45 +45 @@
 #define DEBUG_MEMC_WRITE     1 // detailed trace of WRITE FSM
 #define DEBUG_MEMC_CAS       1 // detailed trace of CAS FSM
-#define DEBUG_MEMC_IXR_CMD   1 // detailed trace of IXR_RSP FSM
+#define DEBUG_MEMC_IXR_CMD   1 // detailed trace of IXR_CMD FSM
 #define DEBUG_MEMC_IXR_RSP   1 // detailed trace of IXR_RSP FSM
 #define DEBUG_MEMC_XRAM_RSP  1 // detailed trace of XRAM_RSP FSM
@@ -127 +127 @@
   "MULTI_ACK_UPT_LOCK",
   "MULTI_ACK_UPT_CLEAR",
-  "MULTI_ACK_WRITE_RSP",
-  "MULTI_ACK_CONFIG_ACK"
+  "MULTI_ACK_WRITE_RSP"
 };
 const char *config_fsm_str[] =
@@ -134 +133 @@
   "CONFIG_IDLE",
   "CONFIG_LOOP",
+  "CONFIG_WAIT",
   "CONFIG_RSP",
   "CONFIG_DIR_REQ",
   "CONFIG_DIR_ACCESS",
-  "CONFIG_DIR_IVT_LOCK",
+  "CONFIG_IVT_LOCK",
   "CONFIG_BC_SEND",
-  "CONFIG_BC_WAIT",
-  "CONFIG_INV_SEND",
+  "CONFIG_INVAL_SEND",
   "CONFIG_HEAP_REQ",
   "CONFIG_HEAP_SCAN",
   "CONFIG_HEAP_LAST",
-  "CONFIG_INV_WAIT"
+  "CONFIG_TRT_LOCK",
+  "CONFIG_TRT_SET",
+  "CONFIG_PUT_REQ"
 };
 const char *read_fsm_str[] =
@@ -168 +169 @@
   "WRITE_DIR_REQ",
   "WRITE_DIR_LOCK",
-  "WRITE_DIR_READ",
   "WRITE_DIR_HIT",
   "WRITE_UPT_LOCK",
@@ -180 +180 @@
   "WRITE_MISS_TRT_SET",
   "WRITE_MISS_XRAM_REQ",
+  "WRITE_BC_DIR_READ",
   "WRITE_BC_TRT_LOCK",
   "WRITE_BC_IVT_LOCK",
@@ -202 +203 @@
   "XRAM_RSP_DIR_UPDT",
   "XRAM_RSP_DIR_RSP",
-  "XRAM_RSP_INVAL_LOCK",
+  "XRAM_RSP_IVT_LOCK",
   "XRAM_RSP_INVAL_WAIT",
   "XRAM_RSP_INVAL",
@@ -219 +220 @@
   "IXR_CMD_XRAM_IDLE",
   "IXR_CMD_CLEANUP_IDLE",
-  "IXR_CMD_TRT_LOCK",
-  "IXR_CMD_READ",
-  "IXR_CMD_WRITE",
-  "IXR_CMD_CAS",
-  "IXR_CMD_XRAM",
-  "IXR_CMD_CLEANUP_DATA"
+  "IXR_CMD_CONFIG_IDLE",
+  "IXR_CMD_READ_TRT",
+  "IXR_CMD_WRITE_TRT",
+  "IXR_CMD_CAS_TRT",
+  "IXR_CMD_XRAM_TRT",
+  "IXR_CMD_CLEANUP_TRT",
+  "IXR_CMD_CONFIG_TRT",
+  "IXR_CMD_READ_SEND",
+  "IXR_CMD_WRITE_SEND",
+  "IXR_CMD_CAS_SEND",
+  "IXR_CMD_XRAM_SEND",
+  "IXR_CMD_CLEANUP_DATA_SEND",
+  "IXR_CMD_CONFIG_SEND"
 };
 const char *cas_fsm_str[] =
@@ -267 +275 @@
   "CLEANUP_IVT_CLEAR",
   "CLEANUP_WRITE_RSP",
-  "CLEANUP_CONFIG_ACK",
   "CLEANUP_IXR_REQ",
   "CLEANUP_WAIT",
@@ -290 +297 @@
   "ALLOC_TRT_IXR_RSP",
   "ALLOC_TRT_CLEANUP",
-  "ALLOC_TRT_IXR_CMD"
+  "ALLOC_TRT_IXR_CMD",
+  "ALLOC_TRT_CONFIG"
 };
 const char *alloc_upt_fsm_str[] =
 {
-  "ALLOC_UPT_CONFIG",
   "ALLOC_UPT_WRITE",
   "ALLOC_UPT_CAS",
@@ -351 +358 @@
   : soclib::caba::BaseModule(name),
 
-    m_monitor_ok(false),
+    //m_monitor_ok(false),
     
     p_clk( "p_clk" ),
@@ -394 +401 @@
     m_broadcast_boundaries(0x7C1F),
 
-    r_tgt_cmd_fsm("r_tgt_cmd_fsm"),
 
     //  FIFOs
@@ -421 +427 @@
     m_cc_receive_to_multi_ack_fifo("m_cc_receive_to_multi_ack_fifo", 4),
 
+    r_tgt_cmd_fsm("r_tgt_cmd_fsm"),
+
     r_config_fsm( "r_config_fsm" ),
 
@@ -432 +440 @@
     m_write_to_cc_send_inst_fifo("m_write_to_cc_send_inst_fifo",8),
     m_write_to_cc_send_srcid_fifo("m_write_to_cc_send_srcid_fifo",8),
-#if L1_MULTI_CACHE
-    m_write_to_cc_send_cache_id_fifo("m_write_to_cc_send_cache_id_fifo",8),
-#endif
 
     r_multi_ack_fsm("r_multi_ack_fsm"),
@@ -444 +449 @@
     m_cas_to_cc_send_inst_fifo("m_cas_to_cc_send_inst_fifo",8),
     m_cas_to_cc_send_srcid_fifo("m_cas_to_cc_send_srcid_fifo",8),
-#if L1_MULTI_CACHE
-    m_cas_to_cc_send_cache_id_fifo("m_cas_to_cc_send_cache_id_fifo",8),
-#endif
 
     r_ixr_rsp_fsm("r_ixr_rsp_fsm"),
@@ -453 +455 @@
     m_xram_rsp_to_cc_send_inst_fifo("m_xram_rsp_to_cc_send_inst_fifo",8),
     m_xram_rsp_to_cc_send_srcid_fifo("m_xram_rsp_to_cc_send_srcid_fifo",8),
-#if L1_MULTI_CACHE
-    m_xram_rsp_to_cc_send_cache_id_fifo("m_xram_rsp_to_cc_send_cache_id_fifo",8),
-#endif
 
     r_ixr_cmd_fsm("r_ixr_cmd_fsm"),
@@ -524 +523 @@
     r_xram_rsp_victim_data     = new sc_signal<data_t>[nwords];
     r_xram_rsp_to_tgt_rsp_data = new sc_signal<data_t>[nwords];
-    r_xram_rsp_to_ixr_cmd_data = new sc_signal<data_t>[nwords];
 
     // Allocation for READ FSM
@@ -535 +533 @@
     r_write_to_cc_send_data    = new sc_signal<data_t>[nwords];
     r_write_to_cc_send_be      = new sc_signal<be_t>[nwords];
-    r_write_to_ixr_cmd_data    = new sc_signal<data_t>[nwords];
 
     // Allocation for CAS FSM
-    r_cas_to_ixr_cmd_data      = new sc_signal<data_t>[nwords];
     r_cas_data                 = new sc_signal<data_t>[nwords];
     r_cas_rdata                = new sc_signal<data_t>[2];
@@ -544 +540 @@
     // Allocation for ODCCP
     r_cleanup_data             = new sc_signal<data_t>[nwords];
-    r_ixr_cmd_data             = new sc_signal<data_t>[nwords];
     r_cleanup_to_ixr_cmd_data  = new sc_signal<data_t>[nwords];
 
+    // Allocation for IXR_CMD FSM
+    r_ixr_cmd_wdata            = new sc_signal<data_t>[nwords];
+
     // Allocation for debug
-    m_debug_previous_data      = new sc_signal<data_t>[nwords];
-    m_debug_data               = new sc_signal<data_t>[nwords];
+    m_debug_previous_data      = new data_t[nwords];
+    m_debug_data               = new data_t[nwords];
 
     SC_METHOD(transition);
@@ -560 +558 @@
 } // end constructor
 
-///////////////////////////////////////////////////////////////////////
-tmpl(void) ::start_monitor(addr_t addr, addr_t length)
-///////////////////////////////////////////////////////////////////////
-{
-  m_monitor_ok        = true;
-  m_monitor_base      = addr;
-  m_monitor_length    = length;
-}
-
-///////////////////////////////////////////////////////////////////////
-tmpl(void) ::stop_monitor()
-///////////////////////////////////////////////////////////////////////
-{
-  m_monitor_ok        = false;
-}
-
-////////////////////////////////////////////////
-tmpl(void) ::check_monitor( addr_t      addr,
-                            data_t      data,
-                            bool        read )
-////////////////////////////////////////////////
-{
-  if((addr >= m_monitor_base) and
-      (addr < m_monitor_base + m_monitor_length))
-  {
-    if ( read ) std::cout << " Monitor MEMC Read ";
-    else        std::cout << " Monitor MEMC Write";
-    std::cout << " / Address = " << std::hex << addr
-              << " / Data = " << data
-              << " at cycle " << std::dec << m_cpt_cycles << std::endl;
-  }
-}
 
 /////////////////////////////////////////////////////
@@ -601 +567 @@
     DirectoryEntry entry = m_cache_directory.read_neutral(addr, &way, &set );
 
+    // read data and compute data_change
     bool data_change = false;
-
     if ( entry.valid )
     {
-        m_cache_data.read_line( way, set, m_debug_data );
-
-        for ( size_t i = 0 ; i<m_words ; i++ )
-        {
-            if ( m_debug_previous_valid and
-                 (m_debug_data[i].read() != m_debug_previous_data[i].read()) )
-                 data_change = true;
-            m_debug_previous_data[i] = m_debug_data[i].read();
+        for ( size_t word = 0 ; word<m_words ; word++ )
+        {
+            m_debug_data[word] = m_cache_data.read(way, set, word);
+            if ( m_debug_previous_valid and 
+                 (m_debug_data[word] != m_debug_previous_data[word]) )
+            {
+                data_change = true;
+            }
         }
     }
     
+    // print values if any change
     if ( (entry.valid != m_debug_previous_valid) or
          (entry.valid and (entry.count != m_debug_previous_count)) or
@@ -623 +590 @@
                   << " at cycle " << std::dec << m_cpt_cycles
                   << " for address " << std::hex << addr
-                  << " / HIT = " << std::dec << entry.valid
+                  << " / VAL = " << std::dec << entry.valid
                   << " / WAY = " << way
                   << " / COUNT = " << entry.count 
                   << " / DIRTY = " << entry.dirty
-                  << " / DATA_CHANGE = " << entry.count 
+                  << " / DATA_CHANGE = " << data_change 
                   << std::endl;
-    }
+        std::cout << std::hex << "     /0:" << m_debug_data[0]
+                  << "/1:" << m_debug_data[1]
+                  << "/2:" << m_debug_data[2]
+                  << "/3:" << m_debug_data[3]
+                  << "/4:" << m_debug_data[4]
+                  << "/5:" << m_debug_data[5]
+                  << "/6:" << m_debug_data[6]
+                  << "/7:" << m_debug_data[7]
+                  << "/8:" << m_debug_data[8]
+                  << "/9:" << m_debug_data[9]
+                  << "/A:" << m_debug_data[10]
+                  << "/B:" << m_debug_data[11]
+                  << "/C:" << m_debug_data[12]
+                  << "/D:" << m_debug_data[13]
+                  << "/E:" << m_debug_data[14]
+                  << "/F:" << m_debug_data[15]
+                  << std::endl;
+    }
+
+    // register values
     m_debug_previous_count = entry.count;
     m_debug_previous_valid = entry.valid;
     m_debug_previous_dirty = entry.dirty;
+    for( size_t word=0 ; word<m_words ; word++ ) 
+        m_debug_previous_data[word] = m_debug_data[word];
 }
 
@@ -807 +795 @@
   delete [] r_xram_rsp_victim_data;
   delete [] r_xram_rsp_to_tgt_rsp_data;
-  delete [] r_xram_rsp_to_ixr_cmd_data;
 
   delete [] r_read_data;
@@ -889 +876 @@
     m_config_to_cc_send_inst_fifo.init();
     m_config_to_cc_send_srcid_fifo.init();
-#if L1_MULTI_CACHE
-    m_config_to_cc_send_cache_id_fifo.init();
-#endif
 
     r_tgt_cmd_to_tgt_rsp_req = false;
@@ -906 +890 @@
     m_write_to_cc_send_inst_fifo.init();
     m_write_to_cc_send_srcid_fifo.init();
-#if L1_MULTI_CACHE
-    m_write_to_cc_send_cache_id_fifo.init();
-#endif
 
     r_cleanup_to_tgt_rsp_req      = false;
@@ -914 +895 @@
     m_cc_receive_to_cleanup_fifo.init();
 
-    r_multi_ack_to_tgt_rsp_req     = false;
+    r_multi_ack_to_tgt_rsp_req    = false;
 
     m_cc_receive_to_multi_ack_fifo.init();
@@ -922 +903 @@
     r_cas_lfsr                    = -1   ;
     r_cas_to_ixr_cmd_req          = false;
-    r_cas_to_cc_send_multi_req   = false;
-    r_cas_to_cc_send_brdcast_req = false;
+    r_cas_to_cc_send_multi_req    = false;
+    r_cas_to_cc_send_brdcast_req  = false;
 
     m_cas_to_cc_send_inst_fifo.init();
     m_cas_to_cc_send_srcid_fifo.init();
-#if L1_MULTI_CACHE
-    m_cas_to_cc_send_cache_id_fifo.init();
-#endif
 
     for(size_t i=0; i<m_trt_lines ; i++)
@@ -945 +923 @@
     m_xram_rsp_to_cc_send_inst_fifo.init();
     m_xram_rsp_to_cc_send_srcid_fifo.init();
-#if L1_MULTI_CACHE
-    m_xram_rsp_to_cc_send_cache_id_fifo.init();
-#endif
-
-    r_ixr_cmd_cpt          = 0;
+
     r_alloc_dir_reset_cpt  = 0;
     r_alloc_heap_reset_cpt = 0;
@@ -964 +938 @@
     //r_xram_rsp_to_ixr_cmd_inval_ncc_pending = false;
     r_cleanup_to_ixr_cmd_srcid = 0;
-    r_cleanup_to_ixr_cmd_trdid = 0;
+    r_cleanup_to_ixr_cmd_index = 0;
     r_cleanup_to_ixr_cmd_pktid = 0;
     r_cleanup_to_ixr_cmd_nline = 0;
@@ -971 +945 @@
       r_cleanup_to_ixr_cmd_data[word] = 0;
       r_cleanup_data[word] = 0;
-      r_ixr_cmd_data[word] = 0;
+      r_ixr_cmd_wdata[word] = 0;
     }
 
@@ -1053 +1027 @@
   size_t  write_to_cc_send_fifo_srcid = 0;
 
-#if L1_MULTI_CACHE
-  size_t  write_to_cc_send_fifo_cache_id = 0;
-#endif
-
   bool    xram_rsp_to_cc_send_fifo_put   = false;
   bool    xram_rsp_to_cc_send_fifo_get   = false;
@@ -1062 +1032 @@
   size_t  xram_rsp_to_cc_send_fifo_srcid = 0;
 
-#if L1_MULTI_CACHE
-  size_t  xram_rsp_to_cc_send_fifo_cache_id = 0;
-#endif
-
   bool    config_to_cc_send_fifo_put   = false;
   bool    config_to_cc_send_fifo_get   = false;
@@ -1075 +1041 @@
   bool    cas_to_cc_send_fifo_inst  = false;
   size_t  cas_to_cc_send_fifo_srcid = 0;
-
-#if L1_MULTI_CACHE
-  size_t  cas_to_cc_send_fifo_cache_id = 0;
-#endif
 
   m_debug = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok;
@@ -1129 +1091 @@
   // - For MEMC_CMD_TYPE, the response is delayed until the operation is completed.
   ////////////////////////////////////////////////////////////////////////////////////
+
+//std::cout << std::endl << "tgt_cmd_fsm" << std::endl;
 
   switch(r_tgt_cmd_fsm.read())
@@ -1232 +1196 @@
     case TGT_CMD_ERROR:  // response error must be sent
 
-    // wait if pending TGT_CMD request to TGT_RSP FSM
+    // wait if pending request
     if(r_tgt_cmd_to_tgt_rsp_req.read()) break;
 
@@ -1266 +1230 @@
         size_t   error;  
         uint32_t rdata = 0;         // default value
+        uint32_t wdata = p_vci_tgt.wdata.read();
 
         if ( (p_vci_tgt.cmd.read() == vci_param_int::CMD_READ)         // get lock
@@ -1274 +1239 @@
             error            = 0;
             r_config_lock    = true;
+            if ( rdata == 0 )
+            {
+                r_tgt_cmd_srcid = p_vci_tgt.srcid.read();
+                r_tgt_cmd_trdid = p_vci_tgt.trdid.read();
+                r_tgt_cmd_pktid = p_vci_tgt.pktid.read();
+            }
         }
         else if ( (p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE)  // release lock
-                   and (cell == MEMC_LOCK) )
+                   and (cell == MEMC_LOCK)
+                   and (p_vci_tgt.srcid.read() == r_tgt_cmd_srcid.read()) )
         {
             need_rsp         = true;
@@ -1283 +1255 @@
         }
         else if ( (p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE)   // set addr_lo
-                   and (cell == MEMC_ADDR_LO) )
-        {
+                   and (cell == MEMC_ADDR_LO)
+                   and (p_vci_tgt.srcid.read() == r_tgt_cmd_srcid.read()) )
+        {
+            assert( ((wdata % (m_words*vci_param_int::B)) == 0) and
+            "VCI_MEM_CACHE CONFIG ERROR: The buffer must be aligned on a cache line");
+
             need_rsp         = true;
             error            = 0;
@@ -1291 +1267 @@
         }
         else if ( (p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE)   // set addr_hi
-                   and (cell == MEMC_ADDR_HI) )
+                   and (cell == MEMC_ADDR_HI)
+                   and (p_vci_tgt.srcid.read() == r_tgt_cmd_srcid.read()) )
+
         {
             need_rsp         = true;
@@ -1299 +1277 @@
         }
         else if ( (p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE)   // set buf_lines
-                   and (cell == MEMC_BUF_LENGTH) )
+                   and (cell == MEMC_BUF_LENGTH)
+                   and (p_vci_tgt.srcid.read() == r_tgt_cmd_srcid.read()) )
         {
             need_rsp         = true;
             error            = 0;
             size_t lines = (size_t)(p_vci_tgt.wdata.read()/(m_words<<2));
-            if ( r_config_address.read()/(m_words*vci_param_int::B) ) lines++;
-            r_config_nlines  = lines;
+            if ( r_config_address.read()%(m_words*4) ) lines++;
+            r_config_cmd_lines  = lines;
+            r_config_rsp_lines  = lines;
         }
         else if ( (p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE)   // set cmd type
-                   and (cell == MEMC_CMD_TYPE) )
+                   and (cell == MEMC_CMD_TYPE)
+                   and (p_vci_tgt.srcid.read() == r_tgt_cmd_srcid.read()) )
         {
             need_rsp         = false;
             error            = 0;
             r_config_cmd     = p_vci_tgt.wdata.read();
+
+            // prepare delayed response from CONFIG FSM
             r_config_srcid   = p_vci_tgt.srcid.read();
             r_config_trdid   = p_vci_tgt.trdid.read();
@@ -1343 +1326 @@
           << " address = " << std::hex << p_vci_tgt.address.read()
           << " / wdata = " << p_vci_tgt.wdata.read()
+          << " / need_rsp = " << need_rsp
           << " / error = " << error << std::endl;
 #endif
@@ -1446 +1430 @@
   //    MULTI_ACK FSM
   /////////////////////////////////////////////////////////////////////////
-  // This FSM controls the response to the multicast update or multicast
-  // inval coherence requests sent by the memory cache to the L1 caches and
-  // update the UPT.
+  // This FSM controls the response to the multicast update requests sent 
+  // by the memory cache to the L1 caches and update the UPT.
   //
   // - The FSM decrements the proper entry in UPT,
@@ -1454 +1437 @@
   // - If required, it sends a request to the TGT_RSP FSM to complete
   //   a pending  write transaction.
-  // - If required, it sends an acknowledge to the CONFIG FSM to signal 
-  //   completion of a line inval.
   //
   // All those multi-ack packets are one flit packet.
-  // The index in the UPT is defined in the UPDTID field.
+  // The index in the UPT is defined in the TRDID field.
   ////////////////////////////////////////////////////////////////////////
+
+//std::cout << std::endl << "multi_ack_fsm" << std::endl;
 
   switch(r_multi_ack_fsm.read())
@@ -1574 +1557 @@
         r_multi_ack_nline = m_upt.nline(r_multi_ack_upt_index.read());
         bool need_rsp     = m_upt.need_rsp(r_multi_ack_upt_index.read());
-        bool need_ack     = m_upt.need_ack(r_multi_ack_upt_index.read());
 
         // clear the UPT entry
@@ -1580 +1562 @@
 
         if      ( need_rsp ) r_multi_ack_fsm = MULTI_ACK_WRITE_RSP;
-        else if ( need_ack ) r_multi_ack_fsm = MULTI_ACK_CONFIG_ACK;
         else                 r_multi_ack_fsm = MULTI_ACK_IDLE;
 
@@ -1611 +1592 @@
         break;
     }
-    //////////////////////////
-    case MULTI_ACK_CONFIG_ACK:    // Signals multi-inval completion to CONFIG FSM
-                                  // Wait if pending request 
-    {
-        if ( r_multi_ack_to_config_ack.read() ) break;
-
-        r_multi_ack_to_config_ack   = true;
-        r_multi_ack_fsm              = MULTI_ACK_IDLE;
-
-#if DEBUG_MEMC_MULTI_ACK
-if(m_debug)
-std::cout << "  <MEMC " << name() << " MULTI_ACK_CONFIG_ACK>"
-          << " Signals inval completion to CONFIG FSM" << std::endl;
-#endif
-        break;
-    }
   } // end switch r_multi_ack_fsm
 
@@ -1634 +1599 @@
   // The CONFIG FSM handles the VCI configuration requests (INVAL & SYNC).
   // The target buffer can have any size, and there is one single command for
-  // all cache lines covered by the target buffer. 
-  // An INVAL or SYNC configuration request is defined by the followinf registers:
-  // - bool      r_config_cmd        : INVAL / SYNC / NOP)
+  // all cache lines covered by the target buffer.
+  //
+  // An INVAL or SYNC configuration operation is defined by the following registers:
+  // - bool      r_config_cmd        : INVAL / SYNC / NOP
   // - uint64_t  r_config_address    : buffer base address
-  // - uint32_t  r_config_nlines     : number of lines covering buffer
+  // - uint32_t  r_config_cmd_lines  : number of lines to be handled
+  // - uint32_t  r_config_rsp_lines  : number of lines not completed
   //
   // For both INVAL and SYNC commands, the CONFIG FSM contains the loop handling 
-  // all cache lines covered by the target buffer.
-  //
+  // all cache lines covered by the buffer. The various lines of a given buffer
+  // can be pipelined: the CONFIG FSM does not wait the response for line (n) to send
+  // the command for line (n+1). It decrements the r_config_cmd_lines counter until 
+  // the last request has been registered in TRT (for a SYNC), or in IVT (for an INVAL).
+  // 
   // - INVAL request:
-  //   For each line, it access to the DIR array. 
+  //   For each line, it access to the DIR. 
   //   In case of miss, it does nothing, and a response is requested to TGT_RSP FSM. 
   //   In case of hit, with no copies in L1 caches, the line is invalidated and
   //   a response is requested to TGT_RSP FSM.
   //   If there is copies, a multi-inval, or a broadcast-inval coherence transaction
-  //   is launched and registered in UPT. The multi-inval transaction is signaled
-  //   by the r_multi_ack_to config_ack or r_cleanup_to_config_ack flip-flops.
-  //   The config inval response is sent only when the last line has been invalidated.
-  //
+  //   is launched and registered in UPT. The multi-inval transaction completion
+  //   is signaled by the CLEANUP FSM by decrementing the r_config_rsp_lines counter.
+  //   The CONFIG INVAL response is sent only when the last line has been invalidated.
+  //   TODO : The target buffer address must be aligned on a cache line boundary.
+  //   This constraint can be released, but it requires to make 2 PUT transactions
+  //   for the first and the last line...
+  // 
   // - SYNC request:
-  //
-  //  ...  Not implemented yet ...
+  //   For each line, it access to the DIR. 
+  //   In case of miss, it does nothing, and a response is requested to TGT_RSP FSM. 
+  //   In case of hit, a PUT transaction is registered in TRT and a request is sent
+  //   to IXR_CMD FSM. The IXR_RSP FSM decrements the r_config_rsp_lines counter
+  //   when a PUT response is received.
+  //   The CONFIG SYNC response is sent only when the last PUT response is received.
   //
   // From the software point of view, a configuration request is a sequence
-  // of 6 atomic accesses in an uncached segment:
+  // of 6 atomic accesses in an uncached segment. A dedicated lock is used 
+  // to handle only one configuration command at a given time:
   // - Read  MEMC_LOCK       : Get the lock
   // - Write MEMC_ADDR_LO    : Set the buffer address LSB
@@ -1667 +1645 @@
   ////////////////////////////////////////////////////////////////////////////////////
 
+//std::cout << std::endl << "config_fsm" << std::endl;
+
   switch( r_config_fsm.read() )
   {
@@ -1679 +1659 @@
 if(m_debug)
 std::cout << "  <MEMC " << name() << " CONFIG_IDLE> Config Request received" 
-          << " address = " << std::hex << r_config_address.read()
-          << " / nlines = " << std::dec << r_config_nlines.read()
+          << " / address = " << std::hex << r_config_address.read()
+          << " / lines = " << std::dec << r_config_cmd_lines.read()
           << " / type = " << r_config_cmd.read() << std::endl;
 #endif
@@ -1687 +1667 @@
       }
       /////////////////
-      case CONFIG_LOOP:   // test last line 
-      {
-          if ( r_config_nlines.read() == 0 )
+      case CONFIG_LOOP:   // test if last line to be handled
+      {
+          if ( r_config_cmd_lines.read() == 0 )
           {
               r_config_cmd = MEMC_CMD_NOP;
-              r_config_fsm = CONFIG_RSP;
+              r_config_fsm = CONFIG_WAIT;
           }
           else
@@ -1702 +1682 @@
 if(m_debug)
 std::cout << "  <MEMC " << name() << " CONFIG_LOOP>" 
-          << " address = " << std::hex << r_config_address.read()    
-          << " / nlines = " << std::dec << r_config_nlines.read() 
+          << " / address = " << std::hex << r_config_address.read()    
+          << " / lines not handled = " << std::dec << r_config_cmd_lines.read() 
           << " / command = " << r_config_cmd.read() << std::endl;
 #endif
           break;
+      }
+      /////////////////
+      case CONFIG_WAIT:   // wait completion (last response) 
+      {
+          if ( r_config_rsp_lines.read() == 0 )  // last response received
+          {
+              r_config_fsm = CONFIG_RSP;
+          }
+
+#if DEBUG_MEMC_CONFIG
+if(m_debug)
+std::cout << "  <MEMC " << name() << " CONFIG_WAIT>" 
+          << " / lines to do = " << std::dec << r_config_rsp_lines.read() << std::endl;
+#endif
+          break;
+      }
+      ////////////////
+      case CONFIG_RSP:  // request TGT_RSP FSM to return response 
+      {
+          if ( not r_config_to_tgt_rsp_req.read() )
+          {
+              r_config_to_tgt_rsp_srcid  = r_config_srcid.read();
+              r_config_to_tgt_rsp_trdid  = r_config_trdid.read();
+              r_config_to_tgt_rsp_pktid  = r_config_pktid.read();
+              r_config_to_tgt_rsp_error  = false;
+              r_config_to_tgt_rsp_req    = true;
+              r_config_fsm               = CONFIG_IDLE;
+
+#if DEBUG_MEMC_CONFIG
+if(m_debug)
+std::cout << "  <MEMC " << name() << " CONFIG_RSP> Request TGT_RSP FSM to return response:"
+          << " error = " << r_config_to_tgt_rsp_error.read()
+          << " / rsrcid = " << std::hex << r_config_srcid.read()
+          << " / rtrdid = " << std::hex << r_config_trdid.read()
+          << " / rpktid = " << std::hex << r_config_pktid.read() << std::endl;
+#endif
+          }
+          break;
+
       }
       ////////////////////
@@ -1726 +1745 @@
       case CONFIG_DIR_ACCESS:   // Access directory and decode config command
       {
+          assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_CONFIG) and
+          "MEMC ERROR in CONFIG_DIR_ACCESS state: bad DIR allocation");
+
           size_t way = 0;
           DirectoryEntry entry = m_cache_directory.read(r_config_address.read(), way);
@@ -1736 +1758 @@
               r_config_dir_copy_srcid = entry.owner.srcid;
               r_config_dir_is_cnt     = entry.is_cnt;
+              r_config_dir_lock       = entry.lock;
               r_config_dir_count      = entry.count;
-              r_config_dir_next_ptr   = entry.ptr;
-
-              r_config_fsm    = CONFIG_DIR_IVT_LOCK;
+              r_config_dir_ptr        = entry.ptr;
+
+              r_config_fsm    = CONFIG_IVT_LOCK;
           }
           else if ( entry.valid and                       // hit & sync command
@@ -1745 +1768 @@
                     (r_config_cmd.read() == MEMC_CMD_SYNC) )
           { 
-              std::cout << "VCI_MEM_CACHE ERROR: "
-                        << "SYNC config request not implemented yet" << std::endl;
-              exit(0);
+              r_config_fsm  = CONFIG_TRT_LOCK;
           }
-          else                                            // return to LOOP 
+          else                                            // miss : return to LOOP 
           {
-              r_config_nlines  = r_config_nlines.read() - 1;
-              r_config_address = r_config_address.read() + (m_words<<2);
-              r_config_fsm     = CONFIG_LOOP;
+              r_config_cmd_lines = r_config_cmd_lines.read() - 1;
+              r_config_rsp_lines = r_config_rsp_lines.read() - 1;
+              r_config_cmd_lines = r_config_cmd_lines.read() - 1;
+              r_config_address   = r_config_address.read() + (m_words<<2);
+              r_config_fsm       = CONFIG_LOOP;
           }
 
@@ -1767 +1790 @@
           break;
       }
-      /////////////////////////
-      case CONFIG_DIR_IVT_LOCK:  // enter this state in case of INVAL command
-                                 // Try to get both DIR & IVT locks, and return
-                                 // to LOOP state if IVT full.
-                                 // Register inval in IVT, and invalidate the
-                                 // directory if IVT not full. 
-      {
+      /////////////////////
+      case CONFIG_TRT_LOCK:      // enter this state in case of SYNC command
+                                 // to a dirty cache line 
+                                 // keep DIR lock, and try to get TRT lock
+                                 // return to LOOP state if TRT full
+                                 // reset dirty bit in DIR and register a PUT
+                                 // trabsaction in TRT if not full.
+      {
+          assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_CONFIG) and
+          "MEMC ERROR in CONFIG_TRT_LOCK state: bad DIR allocation");
+
+          if ( r_alloc_trt_fsm.read() == ALLOC_TRT_CONFIG )
+          {
+              size_t index = 0;
+              bool   wok   = not m_trt.full(index);
+
+              if ( not wok )
+              {
+                  r_config_fsm = CONFIG_LOOP;
+              }
+              else
+              {
+                  size_t          way = r_config_dir_way.read();
+                  size_t          set = m_y[r_config_address.read()];
+
+                  // reset dirty bit in DIR
+                  DirectoryEntry  entry;
+                  entry.valid       = true;
+                  entry.dirty       = false;
+                  entry.tag         = m_z[r_config_address.read()];
+                  entry.is_cnt      = r_config_dir_is_cnt.read();
+                  entry.lock        = r_config_dir_lock.read();
+                  entry.ptr         = r_config_dir_ptr.read();
+                  entry.count       = r_config_dir_count.read();
+                  entry.owner.inst  = r_config_dir_copy_inst.read();
+                  entry.owner.srcid = r_config_dir_copy_srcid.read();
+                  m_cache_directory.write( set, 
+                                           way, 
+                                           entry );
+
+                  r_config_trt_index = index;
+                  r_config_fsm       = CONFIG_TRT_SET;
+              }
+
+#if DEBUG_MEMC_CONFIG
+if(m_debug)
+std::cout << "  <MEMC " << name() << " CONFIG_TRT_LOCK> Access TRT: "
+          << " wok = " << std::dec << wok
+          << " index = " << index << std::endl;
+#endif
+          }
+          break;
+      }
+      ////////////////////
+      case CONFIG_TRT_SET:       // read data in cache
+                                 // and post a PUT request in TRT
+      {
+          assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_CONFIG) and
+          "MEMC ERROR in CONFIG_TRT_SET state: bad DIR allocation");
+
+          assert( (r_alloc_trt_fsm.read() == ALLOC_TRT_CONFIG) and
+          "MEMC ERROR in CONFIG_TRT_SET state: bad TRT allocation");
+
+          // read data into cache
+          size_t          way = r_config_dir_way.read();
+          size_t          set = m_y[r_config_address.read()];
+
+          sc_signal<data_t> config_data[16];
+          m_cache_data.read_line( way, 
+                                  set, 
+                                  config_data );
+            
+          // post a PUT request in TRT
+          std::vector<data_t> data_vector;
+          data_vector.clear();
+          for(size_t i=0; i<m_words; i++) data_vector.push_back(config_data[i].read());
+          m_trt.set( r_config_trt_index.read(),
+                     false,                               // PUT
+                     m_nline[r_config_address.read()],    // nline
+                     0,                                   // srcid:       unused
+                     0,                                   // trdid:       unused
+                     0,                                   // pktid:       unused
+                     false,                               // not proc_read
+                     0,                                   // read_length: unused
+                     0,                                   // word_index:  unused
+                     std::vector<be_t>(m_words,0xF),                         
+                     data_vector);
+
+#if DEBUG_MEMC_CONFIG
+if(m_debug)
+std::cout << "  <MEMC " << name() << " CONFIG_TRT_SET> PUT request in TRT:"
+          << " address = " << std::hex << r_config_address.read()
+          << " index = " << std::dec << r_config_trt_index.read() << std::endl;
+#endif
+          break;
+      }
+      ////////////////////
+      case CONFIG_PUT_REQ:       // PUT request to IXR_CMD_FSM
+      {
+          if ( not r_config_to_ixr_cmd_req.read() )
+          {
+              r_config_to_ixr_cmd_req   = true;
+              r_config_to_ixr_cmd_index = r_config_trt_index.read();
+
+              // prepare next iteration
+              r_config_cmd_lines              = r_config_cmd_lines.read() - 1;
+              r_config_address                = r_config_address.read() + (m_words<<2);
+              r_config_fsm                    = CONFIG_LOOP;
+
+#if DEBUG_MEMC_CONFIG
+if(m_debug)
+std::cout << "  <MEMC " << name() << " CONFIG_PUT_REQ> PUT request to IXR_CMD_FSM"
+          << " / address = " << std::hex << r_config_address.read() << std::endl; 
+#endif
+          }
+          break;
+      }
+      /////////////////////
+      case CONFIG_IVT_LOCK:  // enter this state in case of INVAL command
+                             // Keep DIR lock and Try to get IVT lock.
+                             // Return to LOOP state if IVT full.
+                             // Register inval in IVT, and invalidate the
+                             // directory if IVT not full. 
+      {
+          assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_CONFIG) and
+          "MEMC ERROR in CONFIG_IVT_LOCK state: bad DIR allocation");
+
           if ( r_alloc_ivt_fsm.read() == ALLOC_IVT_CONFIG )
           {
@@ -1782 +1925 @@
               {
                   m_cache_directory.inval( way, set );
-                  r_config_nlines  = r_config_nlines.read() - 1;
-                  r_config_address = r_config_address.read() + (m_words<<2);
-                  r_config_fsm     = CONFIG_LOOP;
+                  r_config_cmd_lines  = r_config_cmd_lines.read() - 1;
+                  r_config_rsp_lines  = r_config_rsp_lines.read() - 1;
+                  r_config_address    = r_config_address.read() + (m_words<<2);
+                  r_config_fsm        = CONFIG_LOOP;
 
 #if DEBUG_MEMC_CONFIG
 if(m_debug)
-std::cout << "  <MEMC " << name() << " CONFIG_DIR_IVT_LOCK>"
+std::cout << "  <MEMC " << name() << " CONFIG_IVT_LOCK>"
           << " No copies in L1 : inval DIR entry"  << std::endl;
 #endif
@@ -1819 +1963 @@
                       r_config_ivt_index = index;
                       if ( broadcast )  r_config_fsm = CONFIG_BC_SEND;
-                      else              r_config_fsm = CONFIG_INV_SEND;
+                      else              r_config_fsm = CONFIG_INVAL_SEND;
 
 #if DEBUG_MEMC_CONFIG
 if(m_debug)
-std::cout << "  <MEMC " << name() << " CONFIG_DIR_IVT_LOCK>"
+std::cout << "  <MEMC " << name() << " CONFIG_IVT_LOCK>"
           << " Inval DIR entry and register inval in IVT"
-          << " : index = " << std::dec << index
+          << " / index = " << std::dec << index
           << " / broadcast = " << broadcast << std::endl;
 #endif
@@ -1835 +1979 @@
 #if DEBUG_MEMC_CONFIG
 if(m_debug)
-std::cout << "  <MEMC " << name() << " CONFIG_DIR_IVT_LOCK>"
+std::cout << "  <MEMC " << name() << " CONFIG_IVT_LOCK>"
           << " IVT full : release DIR & IVT locks and retry" << std::endl;
 #endif
@@ -1849 +1993 @@
               not r_config_to_cc_send_brdcast_req.read() )
           {
+              // post bc inval request
               r_config_to_cc_send_multi_req   = false;
               r_config_to_cc_send_brdcast_req = true;
               r_config_to_cc_send_trdid       = r_config_ivt_index.read();
               r_config_to_cc_send_nline       = m_nline[(addr_t)(r_config_address.read())];
-              r_cleanup_to_config_ack         = false;
-              r_config_fsm                    = CONFIG_BC_WAIT;
+
+              // prepare next iteration
+              r_config_cmd_lines              = r_config_cmd_lines.read() - 1;
+              r_config_address                = r_config_address.read() + (m_words<<2);
+              r_config_fsm                    = CONFIG_LOOP;
 
 #if DEBUG_MEMC_CONFIG
@@ -1865 +2013 @@
           break;
       }
-      ////////////////////
-      case CONFIG_BC_WAIT:      // wait broadcast completion to return to LOOP
-      {
-          if ( r_cleanup_to_config_ack.read() ) 
-          {
-              r_config_fsm     = CONFIG_LOOP;
-              r_config_nlines  = r_config_nlines.read() - 1;
-              r_config_address = r_config_address.read() + (m_words<<2);
-          }
-
-#if DEBUG_MEMC_CONFIG
-if(m_debug)
-std::cout << "  <MEMC " << name() << " CONFIG_BC_WAIT> Waiting BC completion " 
-          << " done = " << r_cleanup_to_config_ack.read() 
-          << std::endl; 
-#endif
-          break;
-      }
-      /////////////////////
-      case CONFIG_INV_SEND:    // Post a multi inval request to CC_SEND FSM
+      ///////////////////////
+      case CONFIG_INVAL_SEND:    // Post a multi inval request to CC_SEND FSM
       {
           if( not r_config_to_cc_send_multi_req.read() and 
               not r_config_to_cc_send_brdcast_req.read() )
           {
+              // post multi inval request
               r_config_to_cc_send_multi_req   = true;
               r_config_to_cc_send_brdcast_req = false;
               r_config_to_cc_send_trdid       = r_config_ivt_index.read();
               r_config_to_cc_send_nline       = m_nline[(addr_t)(r_config_address.read())];
-              r_multi_ack_to_config_ack       = false;
-
+
+              // post data into FIFO
               config_to_cc_send_fifo_srcid    = r_config_dir_copy_srcid.read();
               config_to_cc_send_fifo_inst     = r_config_dir_copy_inst.read();
               config_to_cc_send_fifo_put      = true;
 
-              if ( r_config_dir_count.read() == 1 )  r_config_fsm = CONFIG_INV_WAIT;
-              else                                   r_config_fsm = CONFIG_HEAP_REQ;
+              if ( r_config_dir_count.read() == 1 )  // one copy
+              {
+                  // prepare next iteration
+                  r_config_cmd_lines          = r_config_cmd_lines.read() - 1;
+                  r_config_address            = r_config_address.read() + (m_words<<2);
+                  r_config_fsm                = CONFIG_LOOP;
+              }
+              else                                   // several copies
+              {
+                  r_config_fsm = CONFIG_HEAP_REQ;
+              }
 
 #if DEBUG_MEMC_CONFIG
 if(m_debug)
-std::cout << "  <MEMC " << name() << " CONFIG_INV_SEND>"
+std::cout << "  <MEMC " << name() << " CONFIG_INVAL_SEND>"
           << " Post multi inval request to CC_SEND FSM" 
           << " / address = " << std::hex << r_config_address.read() 
@@ -1919 +2059 @@
           {
               r_config_fsm       = CONFIG_HEAP_SCAN;
-              r_config_heap_next = r_config_dir_next_ptr.read();
+              r_config_heap_next = r_config_dir_ptr.read();
           }
 
@@ -1966 +2106 @@
           if ( m_heap.is_full() )
           {
-              last_entry.next = r_config_dir_next_ptr.read();
+              last_entry.next = r_config_dir_ptr.read();
               m_heap.unset_full();
           }
@@ -1974 +2114 @@
           }
 
-          m_heap.write_free_ptr( r_config_dir_next_ptr.read() );
+          m_heap.write_free_ptr( r_config_dir_ptr.read() );
           m_heap.write( r_config_heap_next.read(), last_entry );
-          r_config_fsm = CONFIG_INV_WAIT;
+
+          // prepare next iteration
+          r_config_cmd_lines          = r_config_cmd_lines.read() - 1;
+          r_config_address            = r_config_address.read() + (m_words<<2);
+          r_config_fsm                = CONFIG_LOOP;
 
 #if DEBUG_MEMC_CONFIG
@@ -1984 +2128 @@
 #endif
           break;
-      }
-      /////////////////////
-      case CONFIG_INV_WAIT:      // wait inval completion to return to LOOP
-      {
-          if ( r_multi_ack_to_config_ack.read() )
-          {
-              r_config_fsm     = CONFIG_LOOP;
-              r_config_nlines  = r_config_nlines.read() - 1;
-              r_config_address = r_config_address.read() + (m_words<<2);
-          }
-
-#if DEBUG_MEMC_CONFIG
-if(m_debug)
-std::cout << "  <MEMC " << name() << " CONFIG_INV_WAIT> Waiting inval completion " 
-          << " done = " << r_multi_ack_to_config_ack.read() 
-          << std::endl; 
-#endif
-          break;
-      }
-
-      ////////////////
-      case CONFIG_RSP:  // request TGT_RSP FSM to return response 
-      {
-          if ( not r_config_to_tgt_rsp_req.read() )
-          {
-              r_config_to_tgt_rsp_srcid  = r_config_srcid.read();
-              r_config_to_tgt_rsp_trdid  = r_config_trdid.read();
-              r_config_to_tgt_rsp_pktid  = r_config_pktid.read();
-              r_config_to_tgt_rsp_error  = false;
-              r_config_to_tgt_rsp_req    = true;
-              r_config_fsm               = CONFIG_IDLE;
-
-#if DEBUG_MEMC_CONFIG
-if(m_debug)
-std::cout << "  <MEMC " << name() << " CONFIG_RSP> Request TGT_RSP FSM to return response:"
-          << " error = " << r_config_to_tgt_rsp_error.read()
-          << " / rsrcid = " << std::hex << r_config_srcid.read() << std::endl;
-#endif
-          }
-          break;
-
       }
   }  // end switch r_config_fsm
@@ -2051 +2154 @@
   ////////////////////////////////////////////////////////////////////////////////////
 
+//std::cout << std::endl << "read_fsm" << std::endl;
+
   switch(r_read_fsm.read())
   {
@@ -2056 +2161 @@
     case READ_IDLE:  // waiting a read request
     {
-      if(m_cmd_read_addr_fifo.rok())
-      {
+        if(m_cmd_read_addr_fifo.rok())
+        {
 
 #if DEBUG_MEMC_READ
-        if(m_debug)
-          std::cout << "  <MEMC " << name() << " READ_IDLE> Read request"
-            << " : address = " << std::hex << m_cmd_read_addr_fifo.read()
-            << " / srcid = " << m_cmd_read_srcid_fifo.read()
-            << " / trdid = " << m_cmd_read_trdid_fifo.read()
-            << " / pktid = " << m_cmd_read_pktid_fifo.read()
-            << " / nwords = " << std::dec << m_cmd_read_length_fifo.read() << std::endl;
-#endif
-        r_read_fsm = READ_DIR_REQ;
-      }
-      break;
-    }
-
+if(m_debug)
+std::cout << "  <MEMC " << name() << " READ_IDLE> Read request"
+          << " : address = " << std::hex << m_cmd_read_addr_fifo.read()
+          << " / srcid = " << m_cmd_read_srcid_fifo.read()
+          << " / trdid = " << m_cmd_read_trdid_fifo.read()
+          << " / pktid = " << m_cmd_read_pktid_fifo.read()
+          << " / nwords = " << std::dec << m_cmd_read_length_fifo.read() << std::endl;
+#endif
+            r_read_fsm = READ_DIR_REQ;
+        }
+        break;
+    }
     //////////////////
     case READ_DIR_REQ:  // Get the lock to the directory
@@ -2095 +2199 @@
     case READ_DIR_LOCK:  // check directory for hit / miss
     {
-      if(r_alloc_dir_fsm.read() == ALLOC_DIR_READ)
-      {
+        assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_READ) and
+        "MEMC ERROR in READ_DIR_LOCK state: Bad DIR allocation");
+
         size_t way = 0;
-        DirectoryEntry entry =
-          m_cache_directory.read(m_cmd_read_addr_fifo.read(), way);
+        DirectoryEntry entry = m_cache_directory.read(m_cmd_read_addr_fifo.read(), way);
+
         // access the global table ONLY when we have an LL cmd
         if((m_cmd_read_pktid_fifo.read() & 0x7) == TYPE_LL)   
         {
-          r_read_ll_key   = m_llsc_table.ll(m_cmd_read_addr_fifo.read());
+            r_read_ll_key   = m_llsc_table.ll(m_cmd_read_addr_fifo.read());
         }
         r_read_is_cnt     = entry.is_cnt;
@@ -2112 +2217 @@
         r_read_count      = entry.count;
         r_read_copy       = entry.owner.srcid;
-
-#if L1_MULTI_CACHE
-        r_read_copy_cache = entry.owner.cache_id;
-#endif
         r_read_copy_inst  = entry.owner.inst;
         r_read_ptr        = entry.ptr; // pointer to the heap
@@ -2125 +2226 @@
         if(entry.valid)    // hit
         {
-          // test if we need to register a new copy in the heap
-          if(entry.is_cnt or (entry.count == 0) or !cached_read)
-          {
-            r_read_fsm = READ_DIR_HIT;
-          }
-          else
-          {
-            r_read_fsm = READ_HEAP_REQ;
-          }
+            // test if we need to register a new copy in the heap
+            if(entry.is_cnt or (entry.count == 0) or !cached_read)
+            {
+                r_read_fsm = READ_DIR_HIT;
+            }
+            else
+            {
+                r_read_fsm = READ_HEAP_REQ;
+            }
         }
         else      // miss
         {
-          r_read_fsm = READ_TRT_LOCK;
+            r_read_fsm = READ_TRT_LOCK;
         }
 
@@ -2152 +2253 @@
 }
 #endif
-      }
-      else
-      {
-        std::cout << "VCI_MEM_CACHE ERROR " << name() << " READ_DIR_LOCK state"
-                  << "Bad DIR allocation"   << std::endl;
-        exit(0);
-      }
-      break;
-    }
-
+        break;
+    }
     //////////////////
     case READ_DIR_HIT:    //  read data in cache & update the directory
@@ -2170 +2263 @@
 
     {
-      if(r_alloc_dir_fsm.read() == ALLOC_DIR_READ)
-      {
+        assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_READ) and
+        "MEMC ERROR in READ_DIR_HIT state: Bad DIR allocation");
+
         // check if this is an instruction read, this means pktid is either
         // TYPE_READ_INS_UNC   0bX010 with TSAR encoding
@@ -2188 +2282 @@
         m_cache_data.read_line(way, set, r_read_data);
 
-        if(m_monitor_ok) check_monitor( m_cmd_read_addr_fifo.read(), r_read_data[0], true);
-
         // update the cache directory
         DirectoryEntry entry;
@@ -2209 +2301 @@
         if(cached_read)   // Cached read => we must update the copies
         {
-          if(!is_cnt)  // Not counter mode
-          {
-            entry.owner.srcid    = m_cmd_read_srcid_fifo.read();
-#if L1_MULTI_CACHE
-            entry.owner.cache_id = m_cmd_read_pktid_fifo.read();
-#endif
-            entry.owner.inst     = inst_read;
-            entry.count          = r_read_count.read() + 1;
-          }
-          else  // Counter mode
-          {
-            entry.owner.srcid    = 0;
-#if L1_MULTI_CACHE
-            entry.owner.cache_id = 0;
-#endif
-            entry.owner.inst     = false;
-            entry.count          = r_read_count.read() + 1;
-          }
+            if(!is_cnt)  // Not counter mode
+            {
+                entry.owner.srcid    = m_cmd_read_srcid_fifo.read();
+                entry.owner.inst     = inst_read;
+                entry.count          = r_read_count.read() + 1;
+            }
+            else  // Counter mode
+            {
+                entry.owner.srcid    = 0;
+                entry.owner.inst     = false;
+                entry.count          = r_read_count.read() + 1;
+            }
         }
         else            // Uncached read
         {
-          entry.owner.srcid     = r_read_copy.read();
-#if L1_MULTI_CACHE
-          entry.owner.cache_id  = r_read_copy_cache.read();
-#endif
-          entry.owner.inst      = r_read_copy_inst.read();
-          entry.count           = r_read_count.read();
+            entry.owner.srcid     = r_read_copy.read();
+            entry.owner.inst      = r_read_copy_inst.read();
+            entry.count           = r_read_count.read();
         }
 
 #if DEBUG_MEMC_READ
-        if(m_debug)
-          std::cout << "  <MEMC " << name() << " READ_DIR_HIT> Update directory entry:"
-            << " addr = " << std::hex << m_cmd_read_addr_fifo.read()
-            << " / set = " << std::dec << set
-            << " / way = " << way
-            << " / owner_id = " << std::hex << entry.owner.srcid
-            << " / owner_ins = " << std::dec << entry.owner.inst
-            << " / count = " << entry.count
-            << " / is_cnt = " << entry.is_cnt << std::endl;
-#endif
-
-          if(m_monitor_ok)
+if(m_debug)
+std::cout << "  <MEMC " << name() << " READ_DIR_HIT> Update directory entry:"
+          << " addr = " << std::hex << m_cmd_read_addr_fifo.read()
+          << " / set = " << std::dec << set
+          << " / way = " << way
+          << " / owner_id = " << std::hex << entry.owner.srcid
+          << " / owner_ins = " << std::dec << entry.owner.inst
+          << " / count = " << entry.count
+          << " / is_cnt = " << entry.is_cnt << std::endl;
+#endif
+          /*if(m_monitor_ok)
           {
             char buf[80];
@@ -2257 +2339 @@
                      (int)((m_cmd_read_pktid_fifo.read()&0x2)!=0));
             check_monitor(m_cmd_read_addr_fifo.read(), r_read_data[0], true);
-          }
+          }*/
         m_cache_directory.write(set, way, entry);
         r_read_fsm    = READ_RSP;
-      }
-      break;
+        break;
     }
     ///////////////////
@@ -2297 +2378 @@
 
         m_cache_data.read_line(way, set, r_read_data);
-
-        if(m_monitor_ok) check_monitor( m_cmd_read_addr_fifo.read(), r_read_data[0], true);
 
         // update the cache directory
@@ -2312 +2391 @@
         {
           entry.owner.srcid    = r_read_copy.read();
-#if L1_MULTI_CACHE
-          entry.owner.cache_id = r_read_copy_cache.read();
-#endif
           entry.owner.inst     = r_read_copy_inst.read();
           entry.ptr            = m_heap.next_free_ptr();   // set pointer on the heap
@@ -2321 +2397 @@
         {
           entry.owner.srcid    = 0;
-#if L1_MULTI_CACHE
-          entry.owner.cache_id = 0;
-#endif
           entry.owner.inst     = false;
           entry.ptr            = 0;
@@ -2389 +2462 @@
         HeapEntry heap_entry;
         heap_entry.owner.srcid    = m_cmd_read_srcid_fifo.read();
-#if L1_MULTI_CACHE
-        heap_entry.owner.cache_id = m_cmd_read_pktid_fifo.read();
-#endif
         heap_entry.owner.inst     = ((m_cmd_read_pktid_fifo.read() & 0x2) != 0);
 
@@ -2455 +2525 @@
         HeapEntry last_entry;
         last_entry.owner.srcid    = 0;
-#if L1_MULTI_CACHE
-        last_entry.owner.cache_id = 0;
-#endif
         last_entry.owner.inst     = false;
 
@@ -2483 +2550 @@
     case READ_RSP:    //  request the TGT_RSP FSM to return data
     {
-      if(!r_read_to_tgt_rsp_req)
-      {
-        for(size_t i=0 ; i<m_words ; i++)  r_read_to_tgt_rsp_data[i] = r_read_data[i];
-        r_read_to_tgt_rsp_word   = m_x[(addr_t) m_cmd_read_addr_fifo.read()];
-        r_read_to_tgt_rsp_length = m_cmd_read_length_fifo.read();
-        r_read_to_tgt_rsp_srcid  = m_cmd_read_srcid_fifo.read();
-        r_read_to_tgt_rsp_trdid  = m_cmd_read_trdid_fifo.read();
-        r_read_to_tgt_rsp_pktid  = m_cmd_read_pktid_fifo.read();
-        r_read_to_tgt_rsp_ll_key = r_read_ll_key.read();
-        cmd_read_fifo_get        = true;
-        r_read_to_tgt_rsp_req    = true;
-        r_read_fsm               = READ_IDLE;
+        if(!r_read_to_tgt_rsp_req)
+        {
+            for(size_t i=0 ; i<m_words ; i++)  r_read_to_tgt_rsp_data[i] = r_read_data[i];
+            r_read_to_tgt_rsp_word   = m_x[(addr_t) m_cmd_read_addr_fifo.read()];
+            r_read_to_tgt_rsp_length = m_cmd_read_length_fifo.read();
+            r_read_to_tgt_rsp_srcid  = m_cmd_read_srcid_fifo.read();
+            r_read_to_tgt_rsp_trdid  = m_cmd_read_trdid_fifo.read();
+            r_read_to_tgt_rsp_pktid  = m_cmd_read_pktid_fifo.read();
+            r_read_to_tgt_rsp_ll_key = r_read_ll_key.read();
+            cmd_read_fifo_get        = true;
+            r_read_to_tgt_rsp_req    = true;
+            r_read_fsm               = READ_IDLE;
 
 #if DEBUG_MEMC_READ
@@ -2503 +2570 @@
           << " / nwords = " << std::dec << m_cmd_read_length_fifo.read() << std::endl;
 #endif
-      }
-      break;
+        }
+        break;
     }
     ///////////////////
@@ -2525 +2592 @@
         if(hit_read or !wok or hit_write)    // missing line already requested or no space
         {
-          if(!wok)      m_cpt_trt_full++;
+          if(!wok)                    m_cpt_trt_full++;
           if(hit_read or hit_write)   m_cpt_trt_rb++;
           r_read_fsm = READ_IDLE;
@@ -2551 +2618 @@
       break;
     }
-
     //////////////////
     case READ_TRT_SET:      // register get transaction in TRT
     {
-      if(r_alloc_trt_fsm.read() == ALLOC_TRT_READ)
-      {
-        m_trt.set(r_read_trt_index.read(),
-                              true,
-                              m_nline[(addr_t)(m_cmd_read_addr_fifo.read())],
-                              m_cmd_read_srcid_fifo.read(),
-                              m_cmd_read_trdid_fifo.read(),
-                              m_cmd_read_pktid_fifo.read(),
-                              true,
-                              m_cmd_read_length_fifo.read(),
-                              m_x[(addr_t)(m_cmd_read_addr_fifo.read())],
-                              std::vector<be_t> (m_words,0),
-                              std::vector<data_t> (m_words,0),
-                              r_read_ll_key.read());
+        if(r_alloc_trt_fsm.read() == ALLOC_TRT_READ)
+        {
+            m_trt.set( r_read_trt_index.read(),
+                       true,      // GET 
+                       m_nline[(addr_t)(m_cmd_read_addr_fifo.read())],
+                       m_cmd_read_srcid_fifo.read(),
+                       m_cmd_read_trdid_fifo.read(),
+                       m_cmd_read_pktid_fifo.read(),
+                       true,      // proc read
+                       m_cmd_read_length_fifo.read(),
+                       m_x[(addr_t)(m_cmd_read_addr_fifo.read())],
+                       std::vector<be_t> (m_words,0),
+                       std::vector<data_t> (m_words,0),
+                       r_read_ll_key.read() );
 #if DEBUG_MEMC_READ
 if(m_debug)
-std::cout << "  <MEMC " << name() << " READ_TRT_SET> Write in Transaction Table:"
+std::cout << "  <MEMC " << name() << " READ_TRT_SET> Set a GET in TRT:"
           << " address = " << std::hex << m_cmd_read_addr_fifo.read()
           << " / srcid = " << std::hex << m_cmd_read_srcid_fifo.read() << std::endl;
 #endif
-        r_read_fsm = READ_TRT_REQ;
-      }
-      break;
+            r_read_fsm = READ_TRT_REQ;
+        }
+        break;
     }
 
@@ -2583 +2649 @@
     case READ_TRT_REQ:   // consume the read request in FIFO and send it to IXR_CMD_FSM
     {
-      if(not r_read_to_ixr_cmd_req)
-      {
-        cmd_read_fifo_get       = true;
-        r_read_to_ixr_cmd_req   = true;
-        r_read_to_ixr_cmd_nline = m_nline[(addr_t)(m_cmd_read_addr_fifo.read())];
-        r_read_to_ixr_cmd_trdid = r_read_trt_index.read();
-        r_read_fsm              = READ_IDLE;
+        if(not r_read_to_ixr_cmd_req)
+        {
+            cmd_read_fifo_get       = true;
+            r_read_to_ixr_cmd_req   = true;
+            r_read_to_ixr_cmd_index = r_read_trt_index.read();
+            r_read_fsm              = READ_IDLE;
 
 #if DEBUG_MEMC_READ
@@ -2596 +2661 @@
           << std::hex << m_cmd_read_addr_fifo.read() << std::endl;
 #endif
-      }
-      break;
+        }
+        break;
     }
   } // end switch read_fsm
@@ -2615 +2680 @@
   //   If the data is cached by other processors, a coherence transaction must
   //   be launched (sc requests always require a coherence transaction):
-  //   It is a multicast update if the line is not in counter mode, and the processor
+  //   It is a multicast update if the line is not in counter mode: the processor
   //   takes the lock protecting the Update Table (UPT) to register this transaction.
-  //   It is a broadcast invalidate if the line is in counter mode.
   //   If the UPT is full, it releases the lock(s) and retry. Then, it sends
   //   a multi-update request to all owners of the line (but the writer),
@@ -2623 +2687 @@
   //   does not respond to the writing processor, as this response will be sent by
   //   the MULTI_ACK FSM when all update responses have been received.
+  //   It is a broadcast invalidate if the line is in counter mode: The line
+  //   should be erased in memory cache, and written in XRAM with a PUT transaction,
+  //   after registration in TRT.
   //
   // - In case of MISS, the WRITE FSM takes the lock protecting the transaction
   //   table (TRT). If a read transaction to the XRAM for this line already exists,
   //   it writes in the TRT (write buffer). Otherwise, if a TRT entry is free,
-  //   the WRITE FSM register a new transaction in TRT, and sends a read line request
+  //   the WRITE FSM register a new transaction in TRT, and sends a GET request
   //   to the XRAM. If the TRT is full, it releases the lock, and waits.
   //   Finally, the WRITE FSM returns an aknowledge response to the writing processor.
   /////////////////////////////////////////////////////////////////////////////////////
+
+//std::cout << std::endl << "write_fsm" << std::endl;
 
   switch(r_write_fsm.read())
@@ -2637 +2706 @@
     case WRITE_IDLE:  // copy first word of a write burst in local buffer
     {
-      if(m_cmd_write_addr_fifo.rok())
-      {
-        if((m_cmd_write_pktid_fifo.read() & 0x7) == TYPE_SC)
-          m_cpt_sc++;
-        else
-        {
-          m_cpt_write++;
-          m_cpt_write_cells++;
-        }
-
-        // consume a word in the FIFO & write it in the local buffer
-        cmd_write_fifo_get  = true;
-        size_t index        = m_x[(addr_t)(m_cmd_write_addr_fifo.read())];
-
-        r_write_address     = (addr_t)(m_cmd_write_addr_fifo.read());
-        r_write_word_index  = index;
-        r_write_word_count  = 1;
-        r_write_data[index] = m_cmd_write_data_fifo.read();
-        r_write_srcid       = m_cmd_write_srcid_fifo.read();
-        r_write_trdid       = m_cmd_write_trdid_fifo.read();
-        r_write_pktid       = m_cmd_write_pktid_fifo.read();
-        r_write_pending_sc  = false;
-
-        // initialize the be field for all words
-        for(size_t word=0 ; word<m_words ; word++)
-        {
-          if(word == index) r_write_be[word] = m_cmd_write_be_fifo.read();
-          else              r_write_be[word] = 0x0;
-        }
-
-        if (m_cmd_write_eop_fifo.read() or ((m_cmd_write_pktid_fifo.read() & 0x7) == TYPE_SC))
-        {
-          r_write_fsm = WRITE_DIR_REQ;
-        }
-        else
-        {
-          r_write_fsm = WRITE_NEXT;
-        }
+        if(m_cmd_write_addr_fifo.rok())
+        {
+            if((m_cmd_write_pktid_fifo.read() & 0x7) == TYPE_SC)
+            {
+                m_cpt_sc++;
+            }
+            else
+            { 
+                m_cpt_write++;
+                m_cpt_write_cells++;
+            }
+
+            // consume a word in the FIFO & write it in the local buffer
+            cmd_write_fifo_get  = true;
+            size_t index        = m_x[(addr_t)(m_cmd_write_addr_fifo.read())];
+
+            r_write_address     = (addr_t)(m_cmd_write_addr_fifo.read());
+            r_write_word_index  = index;
+            r_write_word_count  = 1;
+            r_write_data[index] = m_cmd_write_data_fifo.read();
+            r_write_srcid       = m_cmd_write_srcid_fifo.read();
+            r_write_trdid       = m_cmd_write_trdid_fifo.read();
+            r_write_pktid       = m_cmd_write_pktid_fifo.read();
+            r_write_pending_sc  = false;
+
+            // initialize the be field for all words
+            for(size_t word=0 ; word<m_words ; word++)
+            {
+                if(word == index) r_write_be[word] = m_cmd_write_be_fifo.read();
+                else              r_write_be[word] = 0x0;
+            }
+
+            if (m_cmd_write_eop_fifo.read() or ((m_cmd_write_pktid_fifo.read() & 0x7) == TYPE_SC))
+            {
+                r_write_fsm = WRITE_DIR_REQ;
+            }
+            else
+            {
+                r_write_fsm = WRITE_NEXT;
+            }
 
 #if DEBUG_MEMC_WRITE
@@ -2683 +2754 @@
           << " / data = " << m_cmd_write_data_fifo.read() << std::endl;
 #endif
-      }
-      break;
-    }
-
+        }
+        break;
+    }
     ////////////////
     case WRITE_NEXT:  // copy next word of a write burst in local buffer
     {
-      if(m_cmd_write_addr_fifo.rok())
-      {
+        if(m_cmd_write_addr_fifo.rok())
+        {
 
 #if DEBUG_MEMC_WRITE
@@ -2699 +2769 @@
           << std::endl;
 #endif
-        m_cpt_write_cells++;
-
-        // check that the next word is in the same cache line
-        if((m_nline[(addr_t)(r_write_address.read())]       !=
-            m_nline[(addr_t)(m_cmd_write_addr_fifo.read())]))
-        {
-          std::cout << "VCI_MEM_CACHE ERROR " << name() << " WRITE_NEXT state" << std::endl
-                    << "all words in a write burst must be in same cache line" << std::endl;
-
-          exit(0);
-        }
-
-        // consume a word in the FIFO & write it in the local buffer
-        cmd_write_fifo_get  = true;
-        size_t index        = r_write_word_index.read() + r_write_word_count.read();
-
-        r_write_be[index]   = m_cmd_write_be_fifo.read();
-        r_write_data[index] = m_cmd_write_data_fifo.read();
-        r_write_word_count  = r_write_word_count.read() + 1;
-
-        if(m_cmd_write_eop_fifo.read())
-        {
-          r_write_fsm = WRITE_DIR_REQ;
-        }
-      }
-      break;
-    }
-
-    ////////////////////
-    case WRITE_DIR_REQ:
-    {
-      // Get the lock to the directory
-      // and access the llsc_global_table
-      if(r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE)
-      {
-        ///////////////////////////////////////////////////////////////////////
-        // SC command treatment
-        // We test the r_write_pending_sc register to know if we are returning
-        // from the WAIT state.
-        // In this case, the SC has already succeed and we cannot consume
-        // another time from the FIFO. Also, we don't have to test another
-        // time if the SC has succeed
-        if(((r_write_pktid.read() & 0x7) == TYPE_SC) and not r_write_pending_sc.read())
-        {
-          if(not m_cmd_write_addr_fifo.rok()) break;
-
-          assert(m_cmd_write_eop_fifo.read() and
-                 "Error in VCI_MEM_CACHE : "
-                 "invalid packet format for SC command");
-
-          size_t index    = r_write_word_index.read();
-          bool sc_success = m_llsc_table.sc(r_write_address.read()    ,
+            m_cpt_write_cells++;
+
+            // check that the next word is in the same cache line
+            assert( (m_nline[(addr_t)(r_write_address.read())] == 
+                     m_nline[(addr_t)(m_cmd_write_addr_fifo.read())]) and
+            "MEMC ERROR in WRITE_NEXT state: Illegal write burst");
+
+            // consume a word in the FIFO & write it in the local buffer
+            cmd_write_fifo_get  = true;
+            size_t index        = r_write_word_index.read() + r_write_word_count.read();
+
+            r_write_be[index]   = m_cmd_write_be_fifo.read();
+            r_write_data[index] = m_cmd_write_data_fifo.read();
+            r_write_word_count  = r_write_word_count.read() + 1;
+
+            if(m_cmd_write_eop_fifo.read()) r_write_fsm = WRITE_DIR_REQ;
+        }
+        break;
+    }
+    ///////////////////
+    case WRITE_DIR_REQ:    // Get the lock to the directory
+                           // and access the llsc_global_table
+    {
+        if( r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE )
+        {
+            if(((r_write_pktid.read() & 0x7) == TYPE_SC) and not r_write_pending_sc.read())
+            {
+                // We enter here if it is a new SC command
+                // If r_write_pending_sc is set the SC is not new and has already been tested
+
+                if(not m_cmd_write_addr_fifo.rok()) break;
+
+                assert( m_cmd_write_eop_fifo.read() and
+                "MEMC ERROR in WRITE_DIR_REQ state: invalid packet format for SC command");
+
+                size_t index    = r_write_word_index.read();
+                bool sc_success = m_llsc_table.sc(r_write_address.read()    ,
                                             r_write_data[index].read());
 
-          // consume a word in the FIFO & write it in the local buffer
-          cmd_write_fifo_get  = true;
-          r_write_data[index] = m_cmd_write_data_fifo.read();
-          r_write_sc_fail     = not sc_success;
-          r_write_pending_sc  = true;
-
-          if(not sc_success) r_write_fsm = WRITE_RSP;
-          else               r_write_fsm = WRITE_DIR_LOCK;
-
-          break;
-        }
-
-        ///////////////////////////////////////////////////////////////////////
-        // WRITE command treatment or SC command returning from the WAIT state
-        // In the second case, we must access the LL/SC global table to
-        // erase any possible new reservation when we release the lock on the
-        // directory
-        m_llsc_table.sw(m_nline[(addr_t)r_write_address.read()],r_write_word_index.read(),r_write_word_index.read()+r_write_word_count.read());
-
-        r_write_fsm = WRITE_DIR_LOCK;
-        m_cpt_write_fsm_n_dir_lock++;
+                // consume a word in the FIFO & write it in the local buffer
+                cmd_write_fifo_get  = true;
+                r_write_data[index] = m_cmd_write_data_fifo.read();
+                r_write_sc_fail     = not sc_success;
+                r_write_pending_sc  = true;
+
+                if(not sc_success) r_write_fsm = WRITE_RSP;
+                else               r_write_fsm = WRITE_DIR_LOCK;
+            }
+            else
+            {
+                // We enter here if it is a SW command or an already tested SC command 
+
+                m_llsc_table.sw( m_nline[(addr_t)r_write_address.read()],
+                                 r_write_word_index.read(),
+                                 r_write_word_index.read() + r_write_word_count.read() );
+
+                r_write_fsm = WRITE_DIR_LOCK;
+            }
       }
 
@@ -2781 +2834 @@
           << std::endl;
 #endif
-
-      m_cpt_write_fsm_dir_lock++;
-
       break;
     }
-
     ////////////////////
     case WRITE_DIR_LOCK:     // access directory to check hit/miss
     {
-      if(r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE)
-      {
+        assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE) and
+        "MEMC ERROR in ALLOC_DIR_LOCK state: Bad DIR allocation");
+
         size_t  way = 0;
         DirectoryEntry entry(m_cache_directory.read(r_write_address.read(), way));
@@ -2797 +2847 @@
         if(entry.valid)    // hit
         {
-          // copy directory entry in local buffer in case of hit
-          r_write_is_cnt     = entry.is_cnt;
-          r_write_lock       = entry.lock;
-          r_write_tag        = entry.tag;
-          r_write_copy       = entry.owner.srcid;
-#if L1_MULTI_CACHE
-          r_write_copy_cache = entry.owner.cache_id;
-#endif
-          r_write_copy_inst  = entry.owner.inst;
-          r_write_count      = entry.count;
-          r_write_ptr        = entry.ptr;
-          r_write_way        = way;
-
-          if(entry.is_cnt and entry.count)
-          {
-            r_write_fsm = WRITE_DIR_READ;
-          }
-          else
-          {
-            r_write_fsm = WRITE_DIR_HIT;
-          }
+            // copy directory entry in local buffer in case of hit
+            r_write_is_cnt     = entry.is_cnt;
+            r_write_lock       = entry.lock;
+            r_write_tag        = entry.tag;
+            r_write_copy       = entry.owner.srcid;
+            r_write_copy_inst  = entry.owner.inst;
+            r_write_count      = entry.count;
+            r_write_ptr        = entry.ptr;
+            r_write_way        = way;
+
+            if(entry.is_cnt and entry.count) r_write_fsm = WRITE_BC_DIR_READ;
+            else                             r_write_fsm = WRITE_DIR_HIT;
         }
         else  // miss
         {
-          r_write_fsm = WRITE_MISS_TRT_LOCK;
+            r_write_fsm = WRITE_MISS_TRT_LOCK;
         }
 
@@ -2838 +2879 @@
 }
 #endif
-      }
-      else
-      {
-        std::cout << "VCI_MEM_CACHE ERROR " << name()
-                  << " WRITE_DIR_LOCK state"        << std::endl
-                  << "bad DIR allocation"           << std::endl;
-
-        exit(0);
-      }
-      break;
-    }
-    ////////////////////
-    case WRITE_DIR_READ:  // read the cache and complete the buffer when be!=0xF
-    {
-      // update local buffer
-      size_t set  = m_y[(addr_t)(r_write_address.read())];
-      size_t way  = r_write_way.read();
-      for(size_t word=0 ; word<m_words ; word++)
-      {
-        data_t mask = 0;
-        if(r_write_be[word].read() & 0x1) mask = mask | 0x000000FF;
-        if(r_write_be[word].read() & 0x2) mask = mask | 0x0000FF00;
-        if(r_write_be[word].read() & 0x4) mask = mask | 0x00FF0000;
-        if(r_write_be[word].read() & 0x8) mask = mask | 0xFF000000;
-
-        // complete only if mask is not null (for energy consumption)
-        r_write_data[word]  = (r_write_data[word].read() & mask) |
-                              (m_cache_data.read(way, set, word) & ~mask);
-
-      } // end for
-
-      // test if a coherence broadcast is required
-      r_write_fsm = WRITE_BC_TRT_LOCK;
-
-#if DEBUG_MEMC_WRITE
-if(m_debug)
-std::cout << "  <MEMC " << name() << " WRITE_DIR_READ>"
-          << " Read the cache to complete local buffer" << std::endl;
-#endif
-      break;
-    }
-
+        break;
+    }
     ///////////////////
-    case WRITE_DIR_HIT:
-    {
-      // update the cache directory
-      // update directory with Dirty bit
-      DirectoryEntry entry;
-      entry.valid          = true;
-      entry.dirty          = true;
-      entry.tag            = r_write_tag.read();
-      entry.is_cnt         = r_write_is_cnt.read();
-      entry.lock           = r_write_lock.read();
-      entry.owner.srcid    = r_write_copy.read();
-#if L1_MULTI_CACHE
-      entry.owner.cache_id = r_write_copy_cache.read();
-#endif
-      entry.owner.inst     = r_write_copy_inst.read();
-      entry.count          = r_write_count.read();
-      entry.ptr            = r_write_ptr.read();
-
-      size_t set           = m_y[(addr_t)(r_write_address.read())];
-      size_t way           = r_write_way.read();
-
-      // update directory
-      m_cache_directory.write(set, way, entry);
-
-      // owner is true when the  the first registered copy is the writer itself
-      bool owner = (((r_write_copy.read() == r_write_srcid.read())
-#if L1_MULTI_CACHE
-                     and(r_write_copy_cache.read() ==r_write_pktid.read())
-#endif
-                    ) and not r_write_copy_inst.read());
-
-      // no_update is true when there is no need for coherence transaction
-      // (tests for sc requests)
-      bool no_update = ( (r_write_count.read() == 0) or
+    case WRITE_DIR_HIT:    // update the cache directory with Dirty bit
+                           // and update data cache
+    {
+        assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE) and
+        "MEMC ERROR in ALLOC_DIR_HIT state: Bad DIR allocation");
+
+        DirectoryEntry entry;
+        entry.valid          = true;
+        entry.dirty          = true;
+        entry.tag            = r_write_tag.read();
+        entry.is_cnt         = r_write_is_cnt.read();
+        entry.lock           = r_write_lock.read();
+        entry.owner.srcid    = r_write_copy.read();
+        entry.owner.inst     = r_write_copy_inst.read();
+        entry.count          = r_write_count.read();
+        entry.ptr            = r_write_ptr.read();
+
+        size_t set           = m_y[(addr_t)(r_write_address.read())];
+        size_t way           = r_write_way.read();
+
+        // update directory
+        m_cache_directory.write(set, way, entry);
+
+        // owner is true when the  the first registered copy is the writer itself
+        bool owner = ( (r_write_copy.read() == r_write_srcid.read())
+                     and not r_write_copy_inst.read() );
+
+        // no_update is true when there is no need for coherence transaction
+        bool no_update = ( (r_write_count.read() == 0) or
                          (owner and (r_write_count.read() ==1) and 
                          (r_write_pktid.read() != TYPE_SC)));
 
-      // write data in the cache if no coherence transaction
-      if(no_update)
-      {
-        for(size_t word=0 ; word<m_words ; word++)
-        {
-          m_cache_data.write(way, set, word, r_write_data[word].read(), r_write_be[word].read());
-
-          if(m_monitor_ok)
-          {
-            addr_t address = (r_write_address.read() & ~(addr_t) 0x3F) | word<<2;
-            check_monitor( address, r_write_data[word].read(), false);
-          }
-        }
-      }
-
-      if(owner and not no_update and(r_write_pktid.read() != TYPE_SC))
-      {
-        r_write_count = r_write_count.read() - 1;
-      }
-
-      if(no_update)
-      // Write transaction completed
-      {
-        r_write_fsm = WRITE_RSP;
-      }
-      else
-      // coherence update required
-      {
-        if(!r_write_to_cc_send_multi_req.read() and
-           !r_write_to_cc_send_brdcast_req.read())
-        {
-          r_write_fsm = WRITE_UPT_LOCK;
-        }
-        else
-        {
-          r_write_fsm = WRITE_WAIT;
-        }
-      }
+        // write data in the cache if no coherence transaction
+        if(no_update)
+        {
+            for(size_t word=0 ; word<m_words ; word++)
+            {
+                m_cache_data.write( way, 
+                                    set, 
+                                    word, 
+                                    r_write_data[word].read(), 
+                                    r_write_be[word].read());
+            }
+        }
+
+        if(owner and not no_update and(r_write_pktid.read() != TYPE_SC))
+        {
+            r_write_count = r_write_count.read() - 1;
+        }
+
+        if(no_update)     // Write transaction completed
+        {
+            r_write_fsm = WRITE_RSP;
+        }
+        else              // coherence update required
+        {
+            if(!r_write_to_cc_send_multi_req.read() and
+               !r_write_to_cc_send_brdcast_req.read())
+            {
+                r_write_fsm = WRITE_UPT_LOCK;
+            }
+            else
+            {
+                r_write_fsm = WRITE_WAIT;
+            }
+        }
 
 #if DEBUG_MEMC_WRITE
 if(m_debug)
 {
-    if(no_update)
-    {
-        std::cout << "  <MEMC " << name() 
-                  << " WRITE_DIR_HIT> Write into cache / No coherence transaction"
-                  << std::endl;
-    }
-    else
-    {
-        std::cout << "  <MEMC " << name() << " WRITE_DIR_HIT> Coherence update required:"
-                  << " is_cnt = " << r_write_is_cnt.read()
-                  << " nb_copies = " << std::dec << r_write_count.read() << std::endl;
-        if(owner) std::cout << "       ... but the first copy is the writer" << std::endl;
-    }
+if(no_update)
+{
+std::cout << "  <MEMC " << name() 
+          << " WRITE_DIR_HIT> Write into cache / No coherence transaction" << std::endl;
 }
-#endif
-      break;
+else
+{
+std::cout << "  <MEMC " << name() << " WRITE_DIR_HIT> Coherence update required:"
+          << " is_cnt = " << r_write_is_cnt.read()
+          << " nb_copies = " << std::dec << r_write_count.read() << std::endl;
+if(owner) std::cout << "       ... but the first copy is the writer" << std::endl;
+}
+}
+#endif
+        break;
     }
     ////////////////////
     case WRITE_UPT_LOCK:  // Try to register the update request in UPT
     {
-      if(r_alloc_upt_fsm.read() == ALLOC_UPT_WRITE)
-      {
-        bool        wok        = false;
-        size_t      index      = 0;
-        size_t      srcid      = r_write_srcid.read();
-        size_t      trdid      = r_write_trdid.read();
-        size_t      pktid      = r_write_pktid.read();
-        addr_t      nline      = m_nline[(addr_t)(r_write_address.read())];
-        size_t      nb_copies  = r_write_count.read();
-        size_t      set        = m_y[(addr_t)(r_write_address.read())];
-        size_t      way        = r_write_way.read();
-
-        wok = m_upt.set(true,  // it's an update transaction
-                        false, // it's not a broadcast
-                        true,  // response required
-                        false, // no acknowledge required
-                        srcid,    
-                        trdid,
-                        pktid,
-                        nline,
-                        nb_copies,
-                        index);
-        if(wok)       // write data in cache
-        {
-          for(size_t word=0 ; word<m_words ; word++)
-          {
-            m_cache_data.write(way,
-                               set,
-                               word,
-                               r_write_data[word].read(),
-                               r_write_be[word].read());
-
-            if(m_monitor_ok)
+        if(r_alloc_upt_fsm.read() == ALLOC_UPT_WRITE)
+        {
+            bool        wok        = false;
+            size_t      index      = 0;
+            size_t      srcid      = r_write_srcid.read();
+            size_t      trdid      = r_write_trdid.read();
+            size_t      pktid      = r_write_pktid.read();
+            addr_t      nline      = m_nline[(addr_t)(r_write_address.read())];
+            size_t      nb_copies  = r_write_count.read();
+            size_t      set        = m_y[(addr_t)(r_write_address.read())];
+            size_t      way        = r_write_way.read();
+
+            wok = m_upt.set( true,  // it's an update transaction
+                             false, // it's not a broadcast
+                             true,  // response required
+                             false, // no acknowledge required
+                             srcid,    
+                             trdid,
+                             pktid,
+                             nline,
+                             nb_copies,
+                             index);
+
+            if( wok )       // write data in cache
             {
-              addr_t address = (r_write_address.read() & ~(addr_t) 0x3F) | word<<2;
-              check_monitor( address, r_write_data[word].read(), false);
+                for(size_t word=0 ; word<m_words ; word++)
+                {
+                    m_cache_data.write( way,
+                                        set,
+                                        word,
+                                        r_write_data[word].read(),
+                                        r_write_be[word].read());
+                }
             }
-          }
-        }
 
 #if DEBUG_MEMC_WRITE
-if(m_debug)
+if(m_debug and wok)
 {
-    if(wok)
-    {
-        std::cout << "  <MEMC " << name() 
-                  << " WRITE_UPT_LOCK> Register the multicast update in UPT / "
-                  << " nb_copies = " << r_write_count.read() << std::endl;
-    }
+std::cout << "  <MEMC " << name() 
+          << " WRITE_UPT_LOCK> Register the multicast update in UPT / "
+          << " nb_copies = " << r_write_count.read() << std::endl;
 }
 #endif
-        r_write_upt_index = index;
-        //  releases the lock protecting UPT and the DIR if no entry...
-        if(wok) r_write_fsm = WRITE_UPT_HEAP_LOCK;
-        else    r_write_fsm = WRITE_WAIT;
-        m_cpt_write_fsm_n_upt_lock++;
-      }
-
-      m_cpt_write_fsm_upt_lock++;
-
-      break;
+            r_write_upt_index = index;
+            // releases the lock protecting UPT and the DIR if no entry...
+            if(wok) r_write_fsm = WRITE_UPT_HEAP_LOCK;
+            else    r_write_fsm = WRITE_WAIT;
+        }
+        break;
     }
 
@@ -3086 +3065 @@
       for(size_t i=min ; i<max ; i++) r_write_to_cc_send_data[i] = r_write_data[i];
 
-      if((r_write_copy.read() != r_write_srcid.read()) or(r_write_pktid.read() == TYPE_SC) or
-#if L1_MULTI_CACHE
-          (r_write_copy_cache.read() != r_write_pktid.read()) or
-#endif
-          r_write_copy_inst.read())
+      if( (r_write_copy.read() != r_write_srcid.read()) or
+          (r_write_pktid.read() == TYPE_SC) or r_write_copy_inst.read())
       {
         // put the first srcid in the fifo
@@ -3096 +3072 @@
         write_to_cc_send_fifo_inst    = r_write_copy_inst.read();
         write_to_cc_send_fifo_srcid   = r_write_copy.read();
-#if L1_MULTI_CACHE
-        write_to_cc_send_fifo_cache_id= r_write_copy_cache.read();
-#endif
         if(r_write_count.read() == 1)
         {
@@ -3149 +3122 @@
       bool dec_upt_counter;
 
-      if(((entry.owner.srcid != r_write_srcid.read()) or (r_write_pktid.read() == TYPE_SC)) or
-#if L1_MULTI_CACHE
-          (entry.owner.cache_id != r_write_pktid.read()) or
-#endif
-          entry.owner.inst)             // put the next srcid in the fifo
+      // put the next srcid in the fifo
+      if( (entry.owner.srcid != r_write_srcid.read()) or 
+          (r_write_pktid.read() == TYPE_SC) or entry.owner.inst)   
       {
         dec_upt_counter                = false;
@@ -3159 +3130 @@
         write_to_cc_send_fifo_inst     = entry.owner.inst;
         write_to_cc_send_fifo_srcid    = entry.owner.srcid;
-#if L1_MULTI_CACHE
-        write_to_cc_send_fifo_cache_id = entry.owner.cache_id;
-#endif
 
 #if DEBUG_MEMC_WRITE
@@ -3231 +3199 @@
 
     ///////////////
-    case WRITE_RSP:
-    {
-      // Post a request to TGT_RSP FSM to acknowledge the write
-      // In order to increase the Write requests throughput,
-      // we don't wait to return in the IDLE state to consume
-      // a new request in the write FIFO
-
+    case WRITE_RSP:  // Post a request to TGT_RSP FSM to acknowledge the write
+                     // In order to increase the Write requests throughput,
+                     // we don't wait to return in the IDLE state to consume
+                     // a new request in the write FIFO
+    {
       if(!r_write_to_tgt_rsp_req.read())
       {
@@ -3330 +3296 @@
         bool    hit_write = m_trt.hit_write(m_nline[addr]);
 #endif
-        bool    wok       = !m_trt.full(wok_index);
+        bool    wok       = not m_trt.full(wok_index);
 
         if(hit_read)      // register the modified data in TRT
@@ -3418 +3384 @@
           data_vector.push_back(r_write_data[i]);
         }
-        m_trt.write_data_mask(r_write_trt_index.read(),
-                                          be_vector,
-                                          data_vector);
+        m_trt.write_data_mask( r_write_trt_index.read(),
+                               be_vector,
+                               data_vector );
         r_write_fsm = WRITE_RSP;
 
@@ -3430 +3396 @@
       break;
     }
-
     /////////////////////////
     case WRITE_MISS_XRAM_REQ: // send a GET request to IXR_CMD FSM
     {
-      if(!r_write_to_ixr_cmd_req)
+      if( not r_write_to_ixr_cmd_req.read() )
       {
         r_write_to_ixr_cmd_req   = true;
-        r_write_to_ixr_cmd_write = false;
-        r_write_to_ixr_cmd_nline = m_nline[(addr_t)(r_write_address.read())];
-        r_write_to_ixr_cmd_trdid = r_write_trt_index.read();
+        r_write_to_ixr_cmd_put   = false;
+        r_write_to_ixr_cmd_index = r_write_trt_index.read();
         r_write_fsm              = WRITE_RSP;
 
@@ -3449 +3413 @@
       break;
     }
-
     ///////////////////////
-    case WRITE_BC_TRT_LOCK:     // Check TRT not full
-    {
-      if(r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE)
-      {
-        size_t wok_index = 0;
-        bool wok = !m_trt.full(wok_index);
-        if(wok)       // set a new entry in TRT
-        {
-          r_write_trt_index = wok_index;
-          r_write_fsm       = WRITE_BC_IVT_LOCK;
-        }
-        else  // wait an empty entry in TRT
-        {
-          r_write_fsm       = WRITE_WAIT;
-        }
+    case WRITE_BC_DIR_READ:  // enter this state if a broadcast-inval is required
+                             // the cache line must be erased in mem-cache, and written
+                             // into XRAM. we read the cache and complete the buffer
+    {
+        assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE) and
+        "MEMC ERROR in WRITE_BC_DIR_READ state: Bad DIR allocation");
+ 
+        // update local buffer
+        size_t set  = m_y[(addr_t)(r_write_address.read())];
+        size_t way  = r_write_way.read();
+        for(size_t word=0 ; word<m_words ; word++)
+        {
+            data_t mask = 0;
+            if(r_write_be[word].read() & 0x1) mask = mask | 0x000000FF;
+            if(r_write_be[word].read() & 0x2) mask = mask | 0x0000FF00;
+            if(r_write_be[word].read() & 0x4) mask = mask | 0x00FF0000;
+            if(r_write_be[word].read() & 0x8) mask = mask | 0xFF000000;
+
+            // complete only if mask is not null (for energy consumption)
+            r_write_data[word]  = (r_write_data[word].read() & mask) |
+                                  (m_cache_data.read(way, set, word) & ~mask);
+        } // end for
+
+        r_write_fsm = WRITE_BC_TRT_LOCK;
+
+#if DEBUG_MEMC_WRITE
+if(m_debug)
+std::cout << "  <MEMC " << name() << " WRITE_BC_DIR_READ>"
+          << " Read the cache to complete local buffer" << std::endl;
+#endif
+        break;
+    }
+    ///////////////////////
+    case WRITE_BC_TRT_LOCK:     // get TRT lock to check TRT not full
+    {
+        assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE) and
+        "MEMC ERROR in WRITE_BC_TRT_LOCK state: Bad DIR allocation");
+ 
+        if(r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE)
+        {
+            size_t wok_index = 0;
+            bool wok = not m_trt.full(wok_index);
+            if( wok )       
+            {
+                r_write_trt_index = wok_index;
+                r_write_fsm       = WRITE_BC_IVT_LOCK;
+            }
+            else  // wait an empty slot in TRT
+            {
+                r_write_fsm       = WRITE_WAIT;
+            }
 
 #if DEBUG_MEMC_WRITE
@@ -3479 +3478 @@
       break;
     }
-
     //////////////////////
-    case WRITE_BC_IVT_LOCK:      // register BC transaction in IVT
-    {
-      if(r_alloc_ivt_fsm.read() == ALLOC_IVT_WRITE)
-      {
-        bool        wok       = false;
-        size_t      index     = 0;
-        size_t      srcid     = r_write_srcid.read();
-        size_t      trdid     = r_write_trdid.read();
-        size_t      pktid     = r_write_pktid.read();
-        addr_t      nline     = m_nline[(addr_t)(r_write_address.read())];
-        size_t      nb_copies = r_write_count.read();
-
-        wok = m_ivt.set(false,  // it's an inval transaction
-                        true,   // it's a broadcast
-                        true,   // response required
-                        false,  // no acknowledge required
-                        srcid,
-                        trdid,
-                        pktid,
-                        nline,
-                        nb_copies,
-                        index);
+    case WRITE_BC_IVT_LOCK:      // get IVT lock and register BC transaction in IVT
+    {
+        assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE) and
+        "MEMC ERROR in WRITE_BC_IVT_LOCK state: Bad DIR allocation");
+ 
+        assert( (r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE) and
+        "MEMC ERROR in WRITE_BC_IVT_LOCK state: Bad TRT allocation");
+ 
+        if(r_alloc_ivt_fsm.read() == ALLOC_IVT_WRITE)
+        {
+            bool        wok       = false;
+            size_t      index     = 0;
+            size_t      srcid     = r_write_srcid.read();
+            size_t      trdid     = r_write_trdid.read();
+            size_t      pktid     = r_write_pktid.read();
+            addr_t      nline     = m_nline[(addr_t)(r_write_address.read())];
+            size_t      nb_copies = r_write_count.read();
+
+            wok = m_ivt.set(false,  // it's an inval transaction
+                            true,   // it's a broadcast
+                            true,   // response required
+                            false,  // no acknowledge required
+                            srcid,
+                            trdid,
+                            pktid,
+                            nline,
+                            nb_copies,
+                            index);
 #if DEBUG_MEMC_WRITE
 if( m_debug and wok )
@@ -3508 +3512 @@
           << " / nb_copies = " << r_write_count.read() << std::endl;
 #endif
-        r_write_upt_index = index;
-
-        if(wok) r_write_fsm = WRITE_BC_DIR_INVAL;
-        else    r_write_fsm = WRITE_WAIT;
-        m_cpt_write_fsm_n_upt_lock++;
-      }
-
-      m_cpt_write_fsm_upt_lock++;
-
-      break;
-    }
-
+            r_write_upt_index = index;
+
+            if( wok ) r_write_fsm = WRITE_BC_DIR_INVAL;
+            else      r_write_fsm = WRITE_WAIT;
+        }
+        break;
+    }
     ////////////////////////
-    case WRITE_BC_DIR_INVAL:
-    {
-      // Register a put transaction to XRAM in TRT
-      // and invalidate the line in directory
-      if((r_alloc_trt_fsm.read() != ALLOC_TRT_WRITE) or
-         (r_alloc_ivt_fsm.read() != ALLOC_IVT_WRITE) or
-         (r_alloc_dir_fsm.read() != ALLOC_DIR_WRITE))
-      {
-        std::cout << "VCI_MEM_CACHE ERROR " << name() << " WRITE_BC_DIR_INVAL state" << std::endl;
-        std::cout << "bad TRT, DIR, or IVT allocation" << std::endl;
-        exit(0);
-      }
-
-      // register a write request to XRAM in TRT
-      m_trt.set(r_write_trt_index.read(),
-                            false,    // write request to XRAM
-                            m_nline[(addr_t)(r_write_address.read())],
-                            0,
-                            0,
-                            0,
-                            false,    // not a processor read
-                            0,        // not a single word
-                            0,            // word index
-                            std::vector<be_t> (m_words,0),
-                            std::vector<data_t> (m_words,0));
-
-      // invalidate directory entry
-      DirectoryEntry entry;
-      entry.valid         = false;
-      entry.dirty         = false;
-      entry.tag         = 0;
-      entry.is_cnt        = false;
-      entry.lock          = false;
-      entry.owner.srcid   = 0;
-#if L1_MULTI_CACHE
-      entry.owner.cache_id= 0;
-#endif
-      entry.owner.inst    = false;
-      entry.ptr           = 0;
-      entry.count         = 0;
-      size_t set          = m_y[(addr_t)(r_write_address.read())];
-      size_t way          = r_write_way.read();
-
-      m_cache_directory.write(set, way, entry);
+    case WRITE_BC_DIR_INVAL:    // Register a put transaction in TRT
+                                // and invalidate the line in directory
+    {
+        assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE) and
+        "MEMC ERROR in WRITE_BC_DIR_INVAL state: Bad DIR allocation");
+ 
+        assert( (r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE) and
+        "MEMC ERROR in WRITE_BC_DIR_INVAL state: Bad TRT allocation");
+ 
+        assert( (r_alloc_ivt_fsm.read() == ALLOC_IVT_WRITE) and
+        "MEMC ERROR in WRITE_BC_DIR_INVAL state: Bad IVT allocation");
+ 
+        // register PUT request in TRT
+        std::vector<data_t> data_vector;
+        data_vector.clear();
+        for(size_t i=0; i<m_words; i++) data_vector.push_back(r_write_data[i].read());
+        m_trt.set( r_write_trt_index.read(),
+                   false,             // PUT request
+                   m_nline[(addr_t)(r_write_address.read())],
+                   0,                 // unused
+                   0,                 // unused
+                   0,                 // unused
+                   false,             // not a processor read
+                   0,                 // unused
+                   0,                 // unused
+                   std::vector<be_t> (m_words,0),
+                   data_vector );
+
+        // invalidate directory entry
+        DirectoryEntry entry;
+        entry.valid         = false;
+        entry.dirty         = false;
+        entry.tag           = 0;
+        entry.is_cnt        = false;
+        entry.lock          = false;
+        entry.owner.srcid   = 0;
+        entry.owner.inst    = false;
+        entry.ptr           = 0;
+        entry.count         = 0;
+        size_t set          = m_y[(addr_t)(r_write_address.read())];
+        size_t way          = r_write_way.read();
+
+        m_cache_directory.write(set, way, entry);
 
 #if DEBUG_MEMC_WRITE
 if(m_debug)
-std::cout << "  <MEMC " << name() << " WRITE_BC_DIR_INVAL> Invalidate the directory entry: @ = "
-          << r_write_address.read() << " / register the put transaction in TRT:" << std::endl;
-#endif
-      r_write_fsm = WRITE_BC_CC_SEND;
-      break;
+std::cout << "  <MEMC " << name() << " WRITE_BC_DIR_INVAL> Inval DIR and register in TRT:"
+          << " address = " << r_write_address.read() << std::endl;
+#endif
+        r_write_fsm = WRITE_BC_CC_SEND;
+        break;
     }
 
@@ -3578 +3576 @@
     case WRITE_BC_CC_SEND:    // Post a coherence broadcast request to CC_SEND FSM
     {
-      if(!r_write_to_cc_send_multi_req.read() and !r_write_to_cc_send_brdcast_req.read())
-      {
-        r_write_to_cc_send_multi_req   = false;
-        r_write_to_cc_send_brdcast_req = true;
-        r_write_to_cc_send_trdid       = r_write_upt_index.read();
-        r_write_to_cc_send_nline       = m_nline[(addr_t)(r_write_address.read())];
-        r_write_to_cc_send_index       = 0;
-        r_write_to_cc_send_count       = 0;
-
-        for(size_t i=0; i<m_words ; i++)
-        {
-          r_write_to_cc_send_be[i]=0;
-          r_write_to_cc_send_data[i] = 0;
-        }
-        r_write_fsm = WRITE_BC_XRAM_REQ;
+        if(!r_write_to_cc_send_multi_req.read() and !r_write_to_cc_send_brdcast_req.read())
+        {
+            r_write_to_cc_send_multi_req   = false;
+            r_write_to_cc_send_brdcast_req = true;
+            r_write_to_cc_send_trdid       = r_write_upt_index.read();
+            r_write_to_cc_send_nline       = m_nline[(addr_t)(r_write_address.read())];
+            r_write_to_cc_send_index       = 0;
+            r_write_to_cc_send_count       = 0;
+
+            for(size_t i=0; i<m_words ; i++)  // Ã  quoi sert ce for? (AG)
+            {
+                r_write_to_cc_send_be[i]=0;
+                r_write_to_cc_send_data[i] = 0;
+            }
+            r_write_fsm = WRITE_BC_XRAM_REQ;
 
 #if DEBUG_MEMC_WRITE
@@ -3599 +3597 @@
           << " WRITE_BC_CC_SEND> Post a broadcast request to CC_SEND FSM" << std::endl;
 #endif
-      }
-      break;
+        }
+        break;
     }
 
     ///////////////////////
-    case WRITE_BC_XRAM_REQ:   // Post a put request to IXR_CMD FSM
-    {
-      if(!r_write_to_ixr_cmd_req)
-      {
-        r_write_to_ixr_cmd_req     = true;
-        r_write_to_ixr_cmd_write   = true;
-        r_write_to_ixr_cmd_nline   = m_nline[(addr_t)(r_write_address.read())];
-        r_write_to_ixr_cmd_trdid   = r_write_trt_index.read();
-
-        for(size_t i=0; i<m_words; i++) r_write_to_ixr_cmd_data[i] = r_write_data[i];
-
-        r_write_fsm = WRITE_IDLE;
+    case WRITE_BC_XRAM_REQ:   // Post a PUT request to IXR_CMD FSM
+    {
+        if( not r_write_to_ixr_cmd_req.read() )
+        {
+            r_write_to_ixr_cmd_req     = true;
+            r_write_to_ixr_cmd_put     = true;
+            r_write_to_ixr_cmd_index   = r_write_trt_index.read();
+            r_write_fsm = WRITE_IDLE;
 
 #if DEBUG_MEMC_WRITE
@@ -3622 +3616 @@
           << " WRITE_BC_XRAM_REQ> Post a put request to IXR_CMD FSM" << std::endl;
 #endif
-      }
-      break;
+        }
+        break;
     }
   } // end switch r_write_fsm
@@ -3631 +3625 @@
   ///////////////////////////////////////////////////////////////////////
   // The IXR_CMD fsm controls the command packets to the XRAM :
-  // It handles requests from the READ, WRITE, CAS, XRAM_RSP FSMs
-  // with a round-robin priority.
+  // It handles requests from 5 FSMs with a round-robin priority:
+  //  READ > WRITE > CAS > XRAM_RSP > CONFIG
   //
-  // - It sends a single flit VCI read request to the XRAM in case of MISS
-  // posted by the READ, WRITE or CAS FSMs : the TRDID field contains
-  // the Transaction Tab index.
-  // The VCI response is a multi-flit packet : the N cells contain
-  // the N data words.
+  // - It sends a single flit VCI read to the XRAM in case of
+  //   GET request posted by the READ, WRITE or CAS FSMs. 
+  // - It sends a multi-flit VCI write in case of PUT request posted by
+  //   the XRAM_RSP, WRITE, CAS, or CONFIG FSMs.
   //
-  // - It sends a multi-flit VCI write when the XRAM_RSP FSM, WRITE FSM
-  // or CAS FSM request to save a dirty line to the XRAM.
-  // The VCI response is a single flit packet.
+  // For each client, there is three steps:
+  // - IXR_CMD_*_IDLE : round-robin allocation to a client
+  // - IXR_CMD_*_TRT  : access to TRT for address and data
+  // - IXR_CMD_*_SEND : send the PUT or GET VCI command
+  //
+  // The address and data to be written (for a PUT) are stored in TRT.
+  // The trdid field contains always the TRT entry index.
   ////////////////////////////////////////////////////////////////////////
+
+//std::cout << std::endl << "ixr_cmd_fsm" << std::endl;
 
   switch(r_ixr_cmd_fsm.read())
   {
-    ////////////////////////
+    ///////////////////////
     case IXR_CMD_READ_IDLE:
-      if     (r_write_to_ixr_cmd_req)    r_ixr_cmd_fsm = IXR_CMD_WRITE;
-      else if(r_cas_to_ixr_cmd_req)      r_ixr_cmd_fsm = IXR_CMD_CAS;
-      else if(r_xram_rsp_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_XRAM;
+      if     (r_write_to_ixr_cmd_req.read())      r_ixr_cmd_fsm = IXR_CMD_WRITE_TRT;
+      else if(r_cas_to_ixr_cmd_req.read())        r_ixr_cmd_fsm = IXR_CMD_CAS_TRT;
+      else if(r_xram_rsp_to_ixr_cmd_req.read())   r_ixr_cmd_fsm = IXR_CMD_XRAM_TRT;
 #if ODCCP_NON_INCLUSIVE
-      else if(r_cleanup_to_ixr_cmd_req)     r_ixr_cmd_fsm = IXR_CMD_CLEANUP_DATA;
+      else if(r_cleanup_to_ixr_cmd_req.read()) 
+      {
+        r_ixr_cmd_fsm = IXR_CMD_CLEANUP_DATA_SEND;
+        r_ixr_cmd_word = 0;
+      }
 #else
-      else if(r_cleanup_to_ixr_cmd_req)     r_ixr_cmd_fsm = IXR_CMD_TRT_LOCK;
-#endif
-      else if(r_read_to_ixr_cmd_req)     r_ixr_cmd_fsm = IXR_CMD_READ;
+      else if(r_cleanup_to_ixr_cmd_req.read())     r_ixr_cmd_fsm = IXR_CMD_CLEANUP_TRT;
+#endif
+      else if(r_config_to_ixr_cmd_req.read())     r_ixr_cmd_fsm = IXR_CMD_CONFIG_TRT;
+      else if(r_read_to_ixr_cmd_req.read())       r_ixr_cmd_fsm = IXR_CMD_READ_TRT;
       break;
     ////////////////////////
     case IXR_CMD_WRITE_IDLE:
-      if(r_cas_to_ixr_cmd_req)           r_ixr_cmd_fsm = IXR_CMD_CAS;
-      else if(r_xram_rsp_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_XRAM;
+      if     (r_cas_to_ixr_cmd_req.read())        r_ixr_cmd_fsm = IXR_CMD_CAS_TRT;
+      else if(r_xram_rsp_to_ixr_cmd_req.read())   r_ixr_cmd_fsm = IXR_CMD_XRAM_TRT;
 #if ODCCP_NON_INCLUSIVE
-      else if(r_cleanup_to_ixr_cmd_req)     r_ixr_cmd_fsm = IXR_CMD_CLEANUP_DATA;
+      else if(r_cleanup_to_ixr_cmd_req.read()) 
+      {
+        r_ixr_cmd_fsm = IXR_CMD_CLEANUP_DATA_SEND;
+        r_ixr_cmd_word = 0;
+      }
 #else
-      else if(r_cleanup_to_ixr_cmd_req)     r_ixr_cmd_fsm = IXR_CMD_TRT_LOCK;
-#endif
-      else if(r_read_to_ixr_cmd_req)     r_ixr_cmd_fsm = IXR_CMD_READ;
-      else if(r_write_to_ixr_cmd_req)    r_ixr_cmd_fsm = IXR_CMD_WRITE;
+      else if(r_cleanup_to_ixr_cmd_req)           r_ixr_cmd_fsm = IXR_CMD_CLEANUP_TRT;
+#endif
+      else if(r_config_to_ixr_cmd_req.read())     r_ixr_cmd_fsm = IXR_CMD_CONFIG_TRT;
+      else if(r_read_to_ixr_cmd_req.read())       r_ixr_cmd_fsm = IXR_CMD_READ_TRT;
+      else if(r_write_to_ixr_cmd_req.read())      r_ixr_cmd_fsm = IXR_CMD_WRITE_TRT;
       break;
-    ////////////////////////
+    //////////////////////
     case IXR_CMD_CAS_IDLE:
-      if(r_xram_rsp_to_ixr_cmd_req)      r_ixr_cmd_fsm = IXR_CMD_XRAM;
+      if     (r_xram_rsp_to_ixr_cmd_req.read())   r_ixr_cmd_fsm = IXR_CMD_XRAM_TRT;
 #if ODCCP_NON_INCLUSIVE
-      else if(r_cleanup_to_ixr_cmd_req)     r_ixr_cmd_fsm = IXR_CMD_CLEANUP_DATA;
+      else if(r_cleanup_to_ixr_cmd_req.read()) 
+      {
+        r_ixr_cmd_fsm = IXR_CMD_CLEANUP_DATA_SEND;
+        r_ixr_cmd_word = 0;
+      }
 #else
-      else if(r_cleanup_to_ixr_cmd_req)     r_ixr_cmd_fsm = IXR_CMD_TRT_LOCK;
-#endif
-      else if(r_read_to_ixr_cmd_req)     r_ixr_cmd_fsm = IXR_CMD_READ;
-      else if(r_write_to_ixr_cmd_req)    r_ixr_cmd_fsm = IXR_CMD_WRITE;
-      else if(r_cas_to_ixr_cmd_req)      r_ixr_cmd_fsm = IXR_CMD_CAS;
+      else if(r_cleanup_to_ixr_cmd_req)           r_ixr_cmd_fsm = IXR_CMD_CLEANUP_TRT;
+#endif
+      else if(r_config_to_ixr_cmd_req.read())     r_ixr_cmd_fsm = IXR_CMD_CONFIG_TRT;
+      else if(r_read_to_ixr_cmd_req.read())       r_ixr_cmd_fsm = IXR_CMD_READ_TRT;
+      else if(r_write_to_ixr_cmd_req.read())      r_ixr_cmd_fsm = IXR_CMD_WRITE_TRT;
+      else if(r_cas_to_ixr_cmd_req.read())        r_ixr_cmd_fsm = IXR_CMD_CAS_TRT;
       break;
-    ////////////////////////
+    ///////////////////////
     case IXR_CMD_XRAM_IDLE:
 #if ODCCP_NON_INCLUSIVE
-      if(r_cleanup_to_ixr_cmd_req)     r_ixr_cmd_fsm = IXR_CMD_CLEANUP_DATA;
+      if(r_cleanup_to_ixr_cmd_req.read()) 
+      {
+        r_ixr_cmd_fsm = IXR_CMD_CLEANUP_DATA_SEND;
+        r_ixr_cmd_word = 0;
+      }
 #else
-      if(r_cleanup_to_ixr_cmd_req)     r_ixr_cmd_fsm = IXR_CMD_TRT_LOCK;
-#endif
-      else if(r_read_to_ixr_cmd_req)     r_ixr_cmd_fsm = IXR_CMD_READ;
-      else if(r_write_to_ixr_cmd_req)     r_ixr_cmd_fsm = IXR_CMD_WRITE;
-      else if(r_cas_to_ixr_cmd_req)      r_ixr_cmd_fsm = IXR_CMD_CAS;
-      else if(r_xram_rsp_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_XRAM;
+      if(r_cleanup_to_ixr_cmd_req)                r_ixr_cmd_fsm = IXR_CMD_CLEANUP_TRT;
+#endif
+      else if(r_config_to_ixr_cmd_req.read())     r_ixr_cmd_fsm = IXR_CMD_CONFIG_TRT;
+      else if(r_read_to_ixr_cmd_req.read())       r_ixr_cmd_fsm = IXR_CMD_READ_TRT;
+      else if(r_write_to_ixr_cmd_req.read())      r_ixr_cmd_fsm = IXR_CMD_WRITE_TRT;
+      else if(r_cas_to_ixr_cmd_req.read())        r_ixr_cmd_fsm = IXR_CMD_CAS_TRT;
+      else if(r_xram_rsp_to_ixr_cmd_req.read())   r_ixr_cmd_fsm = IXR_CMD_XRAM_TRT;
       break;
       ////////////////////////
     case IXR_CMD_CLEANUP_IDLE:
-      if(r_read_to_ixr_cmd_req)     r_ixr_cmd_fsm = IXR_CMD_READ;
-      else if(r_write_to_ixr_cmd_req)     r_ixr_cmd_fsm = IXR_CMD_WRITE;
-      else if(r_cas_to_ixr_cmd_req)      r_ixr_cmd_fsm = IXR_CMD_CAS;
-      else if(r_xram_rsp_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_XRAM;
+      if(r_config_to_ixr_cmd_req.read())          r_ixr_cmd_fsm = IXR_CMD_CONFIG_TRT;
+      else if(r_read_to_ixr_cmd_req.read())       r_ixr_cmd_fsm = IXR_CMD_READ_TRT;
+      else if(r_write_to_ixr_cmd_req.read())      r_ixr_cmd_fsm = IXR_CMD_WRITE_TRT;
+      else if(r_cas_to_ixr_cmd_req.read())        r_ixr_cmd_fsm = IXR_CMD_CAS_TRT;
+      else if(r_xram_rsp_to_ixr_cmd_req.read())   r_ixr_cmd_fsm = IXR_CMD_XRAM_TRT;
 #if ODCCP_NON_INCLUSIVE
-      else if(r_cleanup_to_ixr_cmd_req)     r_ixr_cmd_fsm = IXR_CMD_CLEANUP_DATA;
+      else if(r_cleanup_to_ixr_cmd_req.read()) 
+      {
+        r_ixr_cmd_fsm = IXR_CMD_CLEANUP_DATA_SEND;
+        r_ixr_cmd_word = 0;
+      }
 #else
-      else if(r_cleanup_to_ixr_cmd_req)     r_ixr_cmd_fsm = IXR_CMD_TRT_LOCK;
+      else if(r_cleanup_to_ixr_cmd_req.read())    r_ixr_cmd_fsm = IXR_CMD_CLEANUP_TRT;
 #endif
       break;     
-
+    /////////////////////////
+    case IXR_CMD_CONFIG_IDLE:
+      if     (r_read_to_ixr_cmd_req.read())       r_ixr_cmd_fsm = IXR_CMD_READ_TRT;
+      else if(r_write_to_ixr_cmd_req.read())      r_ixr_cmd_fsm = IXR_CMD_WRITE_TRT;
+      else if(r_cas_to_ixr_cmd_req.read())        r_ixr_cmd_fsm = IXR_CMD_CAS_TRT;
+      else if(r_xram_rsp_to_ixr_cmd_req.read())   r_ixr_cmd_fsm = IXR_CMD_XRAM_TRT;
+#if ODCCP_NON_INCLUSIVE
+      else if(r_cleanup_to_ixr_cmd_req.read()) 
+      {
+        r_ixr_cmd_fsm = IXR_CMD_CLEANUP_DATA_SEND;
+        r_ixr_cmd_word = 0;
+      }
+#else
+      else if(r_cleanup_to_ixr_cmd_req.read())    r_ixr_cmd_fsm = IXR_CMD_CLEANUP_TRT;
+#endif
+      else if(r_config_to_ixr_cmd_req.read())     r_ixr_cmd_fsm = IXR_CMD_CONFIG_TRT;
+      break;
+
+
+    //////////////////////
+    case IXR_CMD_READ_TRT:       // access TRT for a GET
+    {
+        if ( r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_CMD )
+        {
+            TransactionTabEntry entry = m_trt.read( r_read_to_ixr_cmd_index.read() );
+            r_ixr_cmd_address = entry.nline * (m_words<<2);
+            r_ixr_cmd_trdid   = r_read_to_ixr_cmd_index.read();
+            r_ixr_cmd_get     = true;
+            r_ixr_cmd_word    = 0;
+            r_ixr_cmd_fsm     = IXR_CMD_READ_SEND;
+            for( size_t i=0 ; i<m_words ; i++ ) r_ixr_cmd_wdata[i] = entry.wdata[i];
+
+#if DEBUG_MEMC_IXR_CMD
+if(m_debug)
+std::cout << "  <MEMC " << name() << " IXR_CMD_READ_TRT> TRT access"
+          << " index = " << std::dec << r_read_to_ixr_cmd_index.read()
+          << " / address = " << std::hex << (entry.nline*(m_words<<2)) << std::endl;
+#endif
+        }
+        break;
+    }
+    ///////////////////////
+    case IXR_CMD_WRITE_TRT:       // access TRT for a PUT or a GET
+    {
+        if ( r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_CMD )
+        {
+            TransactionTabEntry entry = m_trt.read( r_write_to_ixr_cmd_index.read() );
+            r_ixr_cmd_address = entry.nline * (m_words<<2);
+            r_ixr_cmd_trdid   = r_write_to_ixr_cmd_index.read();
+            r_ixr_cmd_get     = entry.xram_read;
+            r_ixr_cmd_word    = 0;
+            r_ixr_cmd_fsm     = IXR_CMD_WRITE_SEND;
+            for( size_t i=0 ; i<m_words ; i++ ) r_ixr_cmd_wdata[i] = entry.wdata[i];
+
+#if DEBUG_MEMC_IXR_CMD
+if(m_debug)
+std::cout << "  <MEMC " << name() << " IXR_CMD_WRITE_TRT> TRT access"
+          << " index = " << std::dec << r_write_to_ixr_cmd_index.read()
+          << " / address = " << std::hex << (entry.nline*(m_words<<2)) << std::endl;
+#endif
+        }
+        break;
+    }
     /////////////////////
-    case IXR_CMD_TRT_LOCK:
-    {
-        TransactionTabEntry entry;
-        
-        if(r_alloc_trt_fsm.read() != ALLOC_TRT_IXR_CMD) break;
-        entry.copy( m_trt.read(r_cleanup_to_ixr_cmd_trdid.read()));
-        for(size_t i=0; i < m_words; i++)
-        {
-          r_ixr_cmd_data[i] = entry.wdata[i];
-        }
-
-        r_ixr_cmd_fsm = IXR_CMD_CLEANUP_DATA;
-        break;
-    }
-
-    //////////////////       // send a get from READ FSM
-    case IXR_CMD_READ:
-    {
-      if(p_vci_ixr.cmdack)
-      {
-        r_ixr_cmd_fsm = IXR_CMD_READ_IDLE;
-        r_read_to_ixr_cmd_req = false;
+    case IXR_CMD_CAS_TRT:       // access TRT for a PUT or a GET 
+    {
+        if ( r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_CMD )
+        {
+            TransactionTabEntry entry = m_trt.read( r_cas_to_ixr_cmd_index.read() );
+            r_ixr_cmd_address = entry.nline * (m_words<<2);
+            r_ixr_cmd_trdid   = r_cas_to_ixr_cmd_index.read();
+            r_ixr_cmd_get     = entry.xram_read;
+            r_ixr_cmd_word    = 0;
+            r_ixr_cmd_fsm     = IXR_CMD_CAS_SEND;
+            for( size_t i=0 ; i<m_words ; i++ ) r_ixr_cmd_wdata[i] = entry.wdata[i];
 
 #if DEBUG_MEMC_IXR_CMD
 if(m_debug)
-std::cout << "  <MEMC " << name() << " IXR_CMD_READ>"
-          << " Send a get request to xram / address = " << std::hex
-          << (addr_t)(r_read_to_ixr_cmd_nline.read()*m_words*4) << std::endl;
-#endif
-      }
-      break;
-    }
-    ///////////////////
-    case IXR_CMD_WRITE:     // send a put or get from WRITE FSM
-    {
-      if(p_vci_ixr.cmdack)
-      {
-        if(r_write_to_ixr_cmd_write.read())   // PUT
-        {
-          if(r_ixr_cmd_cpt.read() == (m_words - 2))
-          {
-            r_ixr_cmd_cpt = 0;
-            r_ixr_cmd_fsm = IXR_CMD_WRITE_IDLE;
-            r_write_to_ixr_cmd_req = false;
-          }
-          else
-          {
-            r_ixr_cmd_cpt = r_ixr_cmd_cpt + 2;
-          }
+std::cout << "  <MEMC " << name() << " IXR_CMD_CAS_TRT> TRT access"
+          << " index = " << std::dec << r_cas_to_ixr_cmd_index.read()
+          << " / address = " << std::hex << (entry.nline*(m_words<<2)) << std::endl;
+#endif
+        }
+        break;
+    }
+    //////////////////////
+    case IXR_CMD_XRAM_TRT:       // access TRT for a PUT 
+    {
+        if ( r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_CMD )
+        {
+            TransactionTabEntry entry = m_trt.read( r_xram_rsp_to_ixr_cmd_index.read() );
+            r_ixr_cmd_address = entry.nline * (m_words<<2);
+            r_ixr_cmd_trdid   = r_xram_rsp_to_ixr_cmd_index.read();
+            r_ixr_cmd_get     = false;
+            r_ixr_cmd_word    = 0;
+            r_ixr_cmd_fsm     = IXR_CMD_XRAM_SEND;
+            for( size_t i=0 ; i<m_words ; i++ ) r_ixr_cmd_wdata[i] = entry.wdata[i];
 
 #if DEBUG_MEMC_IXR_CMD
 if(m_debug)
-std::cout << "  <MEMC " << name() << " IXR_CMD_WRITE>"
-          << " Send a put request to xram / address = " << std::hex
-          << (addr_t)((r_write_to_ixr_cmd_nline.read() * m_words +
-                      r_ixr_cmd_cpt.read()) * 4 ) << std::endl;
-#endif
-        }
-        else                                  // GET
-        {
-          r_ixr_cmd_fsm = IXR_CMD_WRITE_IDLE;
-          r_write_to_ixr_cmd_req = false;
+std::cout << "  <MEMC " << name() << " IXR_CMD_XRAM_TRT> TRT access"
+          << " index = " << std::dec << r_xram_rsp_to_ixr_cmd_index.read()
+          << " / address = " << std::hex << (entry.nline*(m_words<<2)) << std::endl;
+#endif
+        }
+        break;
+    }
+    //////////////////////
+    case IXR_CMD_CLEANUP_TRT:       // access TRT for a PUT 
+    {
+        if ( r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_CMD )
+        {
+          
+            TransactionTabEntry entry = m_trt.read( r_cleanup_to_ixr_cmd_index.read() );
+            r_ixr_cmd_address = entry.nline * (m_words<<2);
+            r_ixr_cmd_trdid   = r_cleanup_to_ixr_cmd_index.read();
+            r_ixr_cmd_get     = false;
+            r_ixr_cmd_word    = 0;
+            r_ixr_cmd_fsm     = IXR_CMD_CLEANUP_DATA_SEND;
+            for( size_t i=0 ; i<m_words ; i++ ) r_ixr_cmd_wdata[i] = entry.wdata[i];
 
 #if DEBUG_MEMC_IXR_CMD
 if(m_debug)
-std::cout << "  <MEMC " << name() << " IXR_CMD_WRITE>"
-          << " Send a get request to xram / address = " << std::hex
-          << (addr_t)(r_write_to_ixr_cmd_nline.read()*m_words*4) << std::endl;
-#endif
-        }
-      }
-      break;
-    }
-    /////////////////
-    case IXR_CMD_CAS:      // send a put or get command from CAS FSM
-    {
-      if(p_vci_ixr.cmdack)
-      {
-        if(r_cas_to_ixr_cmd_write.read()) // PUT
-        {
-          if(r_ixr_cmd_cpt.read() == (m_words - 2))
-          {
-            r_ixr_cmd_cpt = 0;
-            r_ixr_cmd_fsm = IXR_CMD_CAS_IDLE;
-            r_cas_to_ixr_cmd_req = false;
-          }
-          else
-          {
-            r_ixr_cmd_cpt = r_ixr_cmd_cpt + 2;
-          }
+std::cout << "  <MEMC " << name() << " IXR_CMD_CLEANUP_TRT> TRT access"
+          << " index = " << std::dec << r_cleanup_to_ixr_cmd_index.read()
+          << " / address = " << std::hex << (entry.nline*(m_words<<2)) << std::endl;
+#endif
+        }
+        break;
+    }
+    ////////////////////////
+    case IXR_CMD_CONFIG_TRT:       // access TRT for a PUT
+    {
+        if ( r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_CMD )
+        {
+            TransactionTabEntry entry = m_trt.read( r_config_to_ixr_cmd_index.read() );
+            r_ixr_cmd_address = entry.nline * (m_words<<2);
+            r_ixr_cmd_trdid   = r_config_to_ixr_cmd_index.read();
+            r_ixr_cmd_get     = false;
+            r_ixr_cmd_word    = 0;
+            r_ixr_cmd_fsm     = IXR_CMD_CONFIG_SEND;
+            for( size_t i=0 ; i<m_words ; i++ ) r_ixr_cmd_wdata[i] = entry.wdata[i];
 
 #if DEBUG_MEMC_IXR_CMD
 if(m_debug)
-std::cout << "  <MEMC " << name() << " IXR_CMD_CAS>"
-          << " Send a put request to xram / address = " << std::hex
-          << (addr_t)( (r_cas_to_ixr_cmd_nline.read() * m_words +
-                      r_ixr_cmd_cpt.read()) * 4 ) << std::endl;
-#endif
-        }
-        else                            // GET
-        {
-          r_ixr_cmd_fsm = IXR_CMD_CAS_IDLE;
-          r_cas_to_ixr_cmd_req = false;
+std::cout << "  <MEMC " << name() << " IXR_CMD_CONFIG_TRT> TRT access"
+          << " index = " << std::dec << r_config_to_ixr_cmd_index.read()
+          << " / address = " << std::hex << (entry.nline*(m_words<<2)) << std::endl;
+#endif
+        }
+        break;
+    }
+
+    ///////////////////////
+    case IXR_CMD_READ_SEND:      // send a get from READ FSM
+    {
+        if(p_vci_ixr.cmdack)
+        {
+            r_ixr_cmd_fsm         = IXR_CMD_READ_IDLE;
+            r_read_to_ixr_cmd_req = false;
 
 #if DEBUG_MEMC_IXR_CMD
 if(m_debug)
-std::cout << "  <MEMC " << name() << " IXR_CMD_CAS>"
-          << " Send a get request to xram / address = " << std::hex
-          << (addr_t)(r_cas_to_ixr_cmd_nline.read()*m_words*4) << std::endl;
-#endif
-        }
-      }
-      break;
-    }
-    //////////////////
-    case IXR_CMD_XRAM:     // send a put from XRAM_RSP FSM
-    {
-      if(p_vci_ixr.cmdack)
-      {
-        if(r_ixr_cmd_cpt.read() == (m_words - 2))
-        {
-          r_ixr_cmd_cpt = 0;
-          r_ixr_cmd_fsm = IXR_CMD_XRAM_IDLE;
-          r_xram_rsp_to_ixr_cmd_req = false;
-        }
-        else
-        {
-          r_ixr_cmd_cpt = r_ixr_cmd_cpt + 2;
-        }
+std::cout << "  <MEMC " << name() << " IXR_CMD_READ_SEND> GET request:" << std::hex
+          << " address = " << r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2) << std::endl;
+#endif
+        }
+        break;
+    }
+    ////////////////////////
+    case IXR_CMD_WRITE_SEND:     // send a put or get from WRITE FSM
+    {
+        if(p_vci_ixr.cmdack)
+        {
+            if(r_write_to_ixr_cmd_put.read())   // PUT
+            {
+                if(r_ixr_cmd_word.read() == (m_words - 2))
+                {
+                    r_ixr_cmd_fsm          = IXR_CMD_WRITE_IDLE;
+                    r_write_to_ixr_cmd_req = false;
+                }
+                else
+                {
+                    r_ixr_cmd_word = r_ixr_cmd_word.read() + 2;
+                }
 
 #if DEBUG_MEMC_IXR_CMD
 if(m_debug)
-std::cout << "  <MEMC " << name() << " IXR_CMD_XRAM>"
-          << " Send a put request to xram / address = " << std::hex
-          << (addr_t)( (r_xram_rsp_to_ixr_cmd_nline.read() * m_words +
-                       r_ixr_cmd_cpt.read()) * 4 ) << std::endl;
-#endif
-      }
-      break;
+std::cout << "  <MEMC " << name() << " IXR_CMD_WRITE_SEND> PUT request:" << std::hex
+          << " address = " << r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2) << std::endl;
+#endif
+            }
+            else                                  // GET
+            {
+                r_ixr_cmd_fsm          = IXR_CMD_WRITE_IDLE;
+                r_write_to_ixr_cmd_req = false;
+
+#if DEBUG_MEMC_IXR_CMD
+if(m_debug)
+std::cout << "  <MEMC " << name() << " IXR_CMD_WRITE_SEND> GET request:" << std::hex
+          << " address = " << r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2) << std::endl;
+#endif
+            }
+        }
+        break;
+    }
+    //////////////////////
+    case IXR_CMD_CAS_SEND:      // send a put or get command from CAS FSM
+    {
+        if(p_vci_ixr.cmdack)
+        {
+            if(r_cas_to_ixr_cmd_put.read()) // PUT
+            {
+                if(r_ixr_cmd_word.read() == (m_words - 2))
+                {
+                    r_ixr_cmd_fsm        = IXR_CMD_CAS_IDLE;
+                    r_cas_to_ixr_cmd_req = false;
+                }
+                else
+                {
+                    r_ixr_cmd_word = r_ixr_cmd_word.read() + 2;
+                }
+
+#if DEBUG_MEMC_IXR_CMD
+if(m_debug)
+std::cout << "  <MEMC " << name() << " IXR_CMD_CAS_SEND> PUT request:" << std::hex
+          << " address = " << r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2) << std::endl;
+#endif
+            }
+            else                            // GET
+            {
+                r_ixr_cmd_fsm        = IXR_CMD_CAS_IDLE;
+                r_cas_to_ixr_cmd_req = false;
+
+#if DEBUG_MEMC_IXR_CMD
+if(m_debug)
+std::cout << "  <MEMC " << name() << " IXR_CMD_CAS_SEND> GET request:" << std::hex
+          << " address = " << r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2) << std::endl;
+#endif
+            }
+        }
+        break;
+    }
+    ///////////////////////
+    case IXR_CMD_XRAM_SEND:     // send a put from XRAM_RSP FSM
+    {
+        if(p_vci_ixr.cmdack.read())
+        {
+            if(r_ixr_cmd_word.read() == (m_words - 2))
+            {
+                r_ixr_cmd_fsm = IXR_CMD_XRAM_IDLE;
+                r_xram_rsp_to_ixr_cmd_req = false;
+            }
+            else
+            {
+                r_ixr_cmd_word = r_ixr_cmd_word.read() + 2;
+            }
+#if DEBUG_MEMC_IXR_CMD
+if(m_debug)
+std::cout << "  <MEMC " << name() << " IXR_CMD_XRAM_SEND> PUT request:" << std::hex
+          << " address = " << r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2) << std::endl;
+#endif
+        }
+        break;
     }
 
       ////////////////////////
-    case IXR_CMD_CLEANUP_DATA:     // send a put command to XRAM
-      if(p_vci_ixr.cmdack)
-      {
-        if(r_ixr_cmd_cpt.read() == (m_words - 2))
-        {
-          r_ixr_cmd_cpt = 0;
+    case IXR_CMD_CLEANUP_DATA_SEND:     // send a put command to XRAM
+    {
+      if(p_vci_ixr.cmdack.read())
+      {
+        /*ODCCP*/ //std::cout << "IXR_CMD_CLEANUP_DATA_SEND STATE at cycle : " << std::dec << m_cpt_cycles << std::endl;
+        if(r_ixr_cmd_word.read() == (m_words - 2))
+        {
+          /*ODCCP*/ //std::cout << "IXR_CMD_CLEANUP_DATA_SEND GO TO IXR_CMD_CLEANUP_IDLE" << std::endl;
           r_ixr_cmd_fsm = IXR_CMD_CLEANUP_IDLE;
           r_cleanup_to_ixr_cmd_req = false;
+          //r_ixr_cmd_word = 0;
           //r_xram_rsp_to_ixr_cmd_inval_ncc_pending = false;
         }
         else
         {
-          r_ixr_cmd_cpt = r_ixr_cmd_cpt.read() + 2;
+          r_ixr_cmd_word = r_ixr_cmd_word.read() + 2;
         }
 
@@ -3869 +4019 @@
         if(m_debug)
         {
-          std::cout << "  <MEMC " << name() << ".IXR_CMD_CLEANUP_DATA> Send a put request to xram" << std::endl;
+          std::cout << "  <MEMC " << name() << ".IXR_CMD_CLEANUP_DATA_SEND> Send a put request to xram" << std::endl;
         }
 #endif
       }
       break;
-
+    }
+
+    /////////////////////////
+    case IXR_CMD_CONFIG_SEND:     // send a put from CONFIG FSM
+    {
+        if(p_vci_ixr.cmdack.read())
+        {
+            if(r_ixr_cmd_word.read() == (m_words - 2))
+            {
+                r_ixr_cmd_fsm = IXR_CMD_CONFIG_IDLE;
+                r_config_to_ixr_cmd_req = false;
+            }
+            else
+            {
+                r_ixr_cmd_word = r_ixr_cmd_word.read() + 2;
+            }
+
+#if DEBUG_MEMC_IXR_CMD
+if(m_debug)
+std::cout << "  <MEMC " << name() << " IXR_CMD_CONFIG_SEND> PUT request:" << std::hex
+          << " address = " << r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2) << std::endl;
+#endif
+        }
+        break;
+    }
   } // end switch r_ixr_cmd_fsm
 
@@ -3881 +4055 @@
   ////////////////////////////////////////////////////////////////////////////
   // The IXR_RSP FSM receives the response packets from the XRAM,
-  // for both put transaction, and get transaction.
+  // for both PUT transaction, and GET transaction.
   //
-  // - A response to a put request is a single-cell VCI packet.
-  // The Transaction Tab index is contained in the RTRDID field.
+  // - A response to a PUT request is a single-cell VCI packet.
+  // The TRT index is contained in the RTRDID field.
   // The FSM takes the lock protecting the TRT, and the corresponding
-  // entry is erased.
+  // entry is erased. If an acknowledge was required (in case of software SYNC)
+  // the r_config_rsp_lines counter is decremented.  
   //
-  // - A response to a get request is a multi-cell VCI packet.
-  // The Transaction Tab index is contained in the RTRDID field.
+  // - A response to a GET request is a multi-cell VCI packet.
+  // The TRT index is contained in the RTRDID field.
   // The N cells contain the N words of the cache line in the RDATA field.
   // The FSM takes the lock protecting the TRT to store the line in the TRT
   // (taking into account the write requests already stored in the TRT).
-  // When the line is completely written, the corresponding rok signal is set.
+  // When the line is completely written, the r_ixr_rsp_to_xram_rsp_rok[index]  
+  // signal is set to inform the XRAM_RSP FSM.
   ///////////////////////////////////////////////////////////////////////////////
+
+//std::cout << std::endl << "ixr_rsp_fsm" << std::endl;
 
   switch(r_ixr_rsp_fsm.read())
   {
-    //////////////////
-    case IXR_RSP_IDLE:  // test transaction type: PUT/GET
-    {
-      if(p_vci_ixr.rspval.read())
-      {
-        r_ixr_rsp_cpt   = 0;
-        r_ixr_rsp_trt_index = p_vci_ixr.rtrdid.read();
-        if(p_vci_ixr.reop.read() and !(p_vci_ixr.rerror.read() &0x1))   // PUT transaction
-        {
-          r_ixr_rsp_fsm = IXR_RSP_ACK;
+      //////////////////
+      case IXR_RSP_IDLE:  // test transaction type: PUT/GET
+      {
+          if(p_vci_ixr.rspval.read())
+          {
+              r_ixr_rsp_cpt       = 0;
+              r_ixr_rsp_trt_index = p_vci_ixr.rtrdid.read();
+
+              assert( ((p_vci_ixr.rerror.read() & 0x1) == 0) and
+              "MEMC ERROR in IXR_RSP state: XRAM response error !");
+
+              if(p_vci_ixr.reop.read())   // PUT
+              {
+#if ODCCP_NON_INCLUSIVE
+                  if (p_vci_ixr.rtrdid.read() == m_trt_lines)
+                    r_ixr_rsp_fsm = IXR_RSP_ACK;
+                  else
+                    r_ixr_rsp_fsm = IXR_RSP_TRT_ERASE;
+#else
+                  r_ixr_rsp_fsm = IXR_RSP_TRT_ERASE;
+#endif
 
 #if DEBUG_MEMC_IXR_RSP
@@ -3914 +4103 @@
           << " IXR_RSP_IDLE> Response from XRAM to a put transaction" << std::endl;
 #endif
-        }
-        else                                                         // GET transaction
-        {
-          r_ixr_rsp_fsm = IXR_RSP_TRT_READ;
+              }
+              else                       // GET 
+              {
+                  r_ixr_rsp_fsm = IXR_RSP_TRT_READ;
 
 #if DEBUG_MEMC_IXR_RSP
@@ -3924 +4113 @@
           << " IXR_RSP_IDLE> Response from XRAM to a get transaction" << std::endl;
 #endif
-        }
-      }
-      break;
-    }
-    /////////////////
-    case IXR_RSP_ACK:        // Aknowledge the VCI response for a PUT
-    {
-#if ODCCP_NON_INCLUSIVE
-      if(p_vci_ixr.rspval.read())
-      {
-        if (r_ixr_rsp_trt_index.read() == m_trt_lines)
-          r_ixr_rsp_fsm = IXR_RSP_IDLE;
-        else
-          r_ixr_rsp_fsm = IXR_RSP_TRT_ERASE;
-      }
-#else
-      if(p_vci_ixr.rspval.read()) r_ixr_rsp_fsm = IXR_RSP_TRT_ERASE;
-#endif
-
-#if DEBUG_MEMC_IXR_RSP
-if(m_debug)
-std::cout << "  <MEMC " << name() << " IXR_RSP_ACK>" << std::endl;
-#endif
-      break;
-    }
-    ////////////////////////
-    case IXR_RSP_TRT_ERASE:   // erase the entry in the TRT
-    {
-      if(r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP)
-      {
-        m_trt.erase(r_ixr_rsp_trt_index.read());
+              }
+          }
+          break;
+      }
+      ////////////////////////
+      case IXR_RSP_ACK:     // Acknowledge PUT transaction
+      {
         r_ixr_rsp_fsm = IXR_RSP_IDLE;
+        break;
+      }
+      ////////////////////////
+      case IXR_RSP_TRT_ERASE:   // erase the entry in the TRT
+                                // decrease the line counter if config request
+      {
+          if(r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP)
+          {
+              size_t  index = r_ixr_rsp_trt_index.read(); 
+              if (m_trt.is_config(index) ) r_config_rsp_lines = r_config_rsp_lines.read() - 1;
+              m_trt.erase(index);
+              r_ixr_rsp_fsm = IXR_RSP_IDLE;
 
 #if DEBUG_MEMC_IXR_RSP
@@ -3962 +4139 @@
           << r_ixr_rsp_trt_index.read() << std::endl;
 #endif
-      m_cpt_ixr_fsm_n_trt_lock++;
-      }
-
-      m_cpt_ixr_fsm_trt_lock++;
-
-      break;
-    }
-    //////////////////////
-    case IXR_RSP_TRT_READ:    // write a 64 bits data in the TRT
-    {
-      if((r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP) and  p_vci_ixr.rspval)
-      {
-        size_t      index    = r_ixr_rsp_trt_index.read();
-        bool        eop      = p_vci_ixr.reop.read();
-        wide_data_t data     = p_vci_ixr.rdata.read();
-        bool        error    = ((p_vci_ixr.rerror.read() & 0x1) == 1);
-
-        assert(((eop == (r_ixr_rsp_cpt.read() == (m_words-2))) or p_vci_ixr.rerror.read())
-               and "Error in VCI_MEM_CACHE : invalid length for a response from XRAM");
-
-        m_trt.write_rsp( index,
-                         r_ixr_rsp_cpt.read(),
-                         data,
-                         error);
-
-        r_ixr_rsp_cpt = r_ixr_rsp_cpt.read() + 2;
-
-        if(eop)
-        {
-          r_ixr_rsp_to_xram_rsp_rok[r_ixr_rsp_trt_index.read()]=true;
-          /*if(p_vci_ixr.rpktid.read()&0xF == 0x9)
-            r_ixr_rsp_to_xram_rsp_no_coherent[r_ixr_rsp_trt_index.read()] = true;
-          else
-            r_ixr_rsp_to_xram_rsp_no_coherent[r_ixr_rsp_trt_index.read()] = false;*/
-          r_ixr_rsp_fsm = IXR_RSP_IDLE;
-        }
+          }
+          break;
+      }
+      //////////////////////
+      case IXR_RSP_TRT_READ:    // write a 64 bits data word in TRT
+      {
+          if((r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP) and  p_vci_ixr.rspval)
+          {
+              size_t      index    = r_ixr_rsp_trt_index.read();
+              size_t      word     = r_ixr_rsp_cpt.read();
+              bool        eop      = p_vci_ixr.reop.read();
+              wide_data_t data     = p_vci_ixr.rdata.read();
+              bool        error    = ((p_vci_ixr.rerror.read() & 0x1) == 1);
+
+              assert(((eop == (word == (m_words-2))) or error) and
+              "MEMC ERROR in IXR_RSP_TRT_READ state : invalid response from XRAM");
+
+              m_trt.write_rsp( index,
+                               word,
+                               data );
+
+              r_ixr_rsp_cpt = word + 2;
+
+              if(eop)
+              {
+                r_ixr_rsp_to_xram_rsp_rok[r_ixr_rsp_trt_index.read()]=true;
+                /*if(p_vci_ixr.rpktid.read()&0xF == 0x9)
+                  r_ixr_rsp_to_xram_rsp_no_coherent[r_ixr_rsp_trt_index.read()] = true;
+                  else
+                  r_ixr_rsp_to_xram_rsp_no_coherent[r_ixr_rsp_trt_index.read()] = false;*/
+                r_ixr_rsp_fsm = IXR_RSP_IDLE;
+              }
 
 #if DEBUG_MEMC_IXR_RSP
 if(m_debug)
-std::cout << "  <MEMC " << name() << " IXR_RSP_TRT_READ> Writing a word in TRT : "
+std::cout << "  <MEMC " << name() << " IXR_RSP_TRT_READ> Writing 2 words in TRT : "
           << " index = " << std::dec << index
-          << " / word = " << r_ixr_rsp_cpt.read()
+          << " / word = " << word
           << " / data = " << std::hex << data << std::endl;
 #endif
-      m_cpt_ixr_fsm_n_trt_lock++;
-      }
-      m_cpt_ixr_fsm_trt_lock++;
-      break;
-    }
+          }
+          break;
+      }
   } // end swich r_ixr_rsp_fsm
 
@@ -4016 +4187 @@
   //                XRAM_RSP FSM
   ////////////////////////////////////////////////////////////////////////////
-  // The XRAM_RSP FSM handles the incoming cache lines from the XRAM.
+  // The XRAM_RSP FSM handles the incoming cache lines after an XRAM GET.
   // The cache line has been written in the TRT by the IXR_CMD_FSM.
   // As the IXR_RSP FSM and the XRAM_RSP FSM are running in parallel,
-  // there is as many flip-flops r_ixr_rsp_to_xram_rsp_rok[i]
-  // as the number of entries in the TRT, that are handled with
-  // a round-robin priority...
+  // there is as many flip-flops r_ixr_rsp_to_xram_rsp_rok[i] as the number 
+  // of entries in the TRT, that are handled with a round-robin priority...
   //
-  // When a response is available, the corresponding TRT entry
-  // is copied in a local buffer to be written in the cache.
-  // The FSM takes the lock protecting the TRT, and the lock protecting the DIR.
-  // It selects a cache slot and writes the line in the cache.
+  // The FSM takes the lock protecting TRT, and the lock protecting DIR.
+  // The selected TRT entry is copied in the local buffer r_xram_rsp_trt_buf.
+  // It selects a cache slot and save the victim line in another local buffer
+  // r_xram_rsp_victim_***.
+  // It writes the line extracted from TRT in the cache.
   // If it was a read MISS, the XRAM_RSP FSM send a request to the TGT_RSP
   // FSM to return the cache line to the registered processor.
@@ -4036 +4207 @@
   ///////////////////////////////////////////////////////////////////////////////
 
+//std::cout << std::endl << "xram_rsp_fsm" << std::endl;
+
   switch(r_xram_rsp_fsm.read())
   {
@@ -4041 +4214 @@
     case XRAM_RSP_IDLE: // scan the XRAM responses / select a TRT index (round robin)
     {
-      size_t ptr   = r_xram_rsp_trt_index.read();
-      size_t lines = m_trt_lines;
-      
-      for(size_t i=0 ; i<lines ; i++)
-      {
-        size_t index = (i+ptr+1) %lines;
-        if(r_ixr_rsp_to_xram_rsp_rok[index])
-        {
-          r_xram_rsp_trt_index             = index;
-          r_ixr_rsp_to_xram_rsp_rok[index] = false;
-          r_xram_rsp_fsm                   = XRAM_RSP_DIR_LOCK;
+        size_t old   = r_xram_rsp_trt_index.read();
+        size_t lines = m_trt_lines;
+        for(size_t i=0 ; i<lines ; i++)
+        {
+            size_t index = (i+old+1) %lines;
+            if(r_ixr_rsp_to_xram_rsp_rok[index])
+            {
+                r_xram_rsp_trt_index             = index;
+                r_ixr_rsp_to_xram_rsp_rok[index] = false;
+                r_xram_rsp_fsm                   = XRAM_RSP_DIR_LOCK;
 
 #if DEBUG_MEMC_XRAM_RSP
@@ -4059 +4231 @@
           << " index = " << std::dec << index << std::endl;
 #endif
-          break;
-        }
-      }
-      break;
+                break;
+            }
+        }
+        break;
     }
     ///////////////////////
@@ -4068 +4240 @@
                             // Copy the TRT entry in a local buffer
     {
-      if((r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP) and
-          (r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP))
-      {
-        // copy the TRT entry in the r_xram_rsp_trt_buf local buffer
-        size_t  index = r_xram_rsp_trt_index.read();
-        r_xram_rsp_trt_buf.copy( m_trt.read(index) );
-
-        r_xram_rsp_fsm = XRAM_RSP_TRT_COPY;
+        if( (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP) and
+            (r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP) )
+        {
+            // copy the TRT entry in the r_xram_rsp_trt_buf local buffer
+            size_t  index = r_xram_rsp_trt_index.read();
+            r_xram_rsp_trt_buf.copy( m_trt.read(index) );
+            r_xram_rsp_fsm = XRAM_RSP_TRT_COPY;
 
 #if DEBUG_MEMC_XRAM_RSP
@@ -4082 +4253 @@
           << " Get access to DIR and TRT" << std::endl;
 #endif
-        m_cpt_xram_rsp_fsm_n_dir_lock++;
-        m_cpt_xram_rsp_fsm_n_trt_lock++;
-      }
-      m_cpt_xram_rsp_fsm_dir_lock++;
-      m_cpt_xram_rsp_fsm_trt_lock++;
-      break;
+        }
+        break;
     }
     ///////////////////////
@@ -4093 +4260 @@
                             // and copy it in a local buffer
     {
-      if ( (r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP) and
-           (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP) )
-      {
+        assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP) and
+        "MEMC ERROR in XRAM_RSP_TRT_COPY state: Bad DIR allocation");
+
+        assert( (r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP) and
+        "MEMC ERROR in XRAM_RSP_TRT_COPY state: Bad TRT allocation");
+
         // selects & extracts a victim line from cache
         size_t way = 0;
@@ -4108 +4278 @@
 #endif
 
-        // copy the victim line in a local buffer
+        // copy the victim line in a local buffer (both data dir)
         m_cache_data.read_line(way, set, r_xram_rsp_victim_data);
 
         r_xram_rsp_victim_copy      = victim.owner.srcid;
-
-#if L1_MULTI_CACHE
-        r_xram_rsp_victim_copy_cache= victim.owner.cache_id;
-#endif
         
         r_xram_rsp_victim_coherent  = victim.coherent;
@@ -4128 +4294 @@
         r_xram_rsp_victim_dirty     = victim.dirty;
 
-
-        if(!r_xram_rsp_trt_buf.rerror)
-        {
-#if ODCCP_NON_INCLUSIVE
-          r_xram_rsp_fsm = XRAM_RSP_INVAL_LOCK;
-#else
-          /*ODCCP*/ //if victim is no coherent and there is an inval no coherent pending we wait
-          /*if(!victim.coherent and r_xram_rsp_to_ixr_cmd_inval_ncc_pending.read())
-          {
-            r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT;
-          }
-          else
-          {*/
-            r_xram_rsp_fsm = XRAM_RSP_INVAL_LOCK;
-         //}
-#endif
-        }
-        else
-        {
-          r_xram_rsp_fsm = XRAM_RSP_ERROR_ERASE;
-        }
+        if( not r_xram_rsp_trt_buf.rerror ) r_xram_rsp_fsm = XRAM_RSP_IVT_LOCK;
+        else                                r_xram_rsp_fsm = XRAM_RSP_ERROR_ERASE;
 
 #if DEBUG_MEMC_XRAM_RSP
 if(m_debug)
 std::cout << "  <MEMC " << name() << " XRAM_RSP_TRT_COPY>"
-          << " Select a slot: "
+          << " Select a victim slot: "
           << " way = " << std::dec << way
           << " / set = " << set
@@ -4160 +4307 @@
           << " / inval_required = " << inval << std::endl;
 #endif
-      }
-      else
-      {
-        std::cout << "VCI_MEM_CACHE ERROR " << name() << " XRAM_RSP_TRT_COPY"
-                  << " bad TRT or DIR allocation" << std::endl;
-        exit(0);
-      }
-      break;
-    }
-    /////////////////////////
-    case XRAM_RSP_INVAL_LOCK: // Take the IVT lock to check a possible pending inval
-    {
-      if(r_alloc_ivt_fsm == ALLOC_IVT_XRAM_RSP)
-      {
-        size_t index = 0;
-        if(m_ivt.search_inval(r_xram_rsp_trt_buf.nline, index))  // pending inval
-        {
-          r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT;
+        break;
+    }
+    ///////////////////////
+    case XRAM_RSP_IVT_LOCK:   // Keep DIR and TRT locks and take the IVT lock 
+                              // to check a possible pending inval
+    {
+        assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP) and
+        "MEMC ERROR in XRAM_RSP_IVT_LOCK state: Bad DIR allocation");
+
+        assert( (r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP) and
+        "MEMC ERROR in XRAM_RSP_IVT_LOCK state: Bad TRT allocation");
+
+        if(r_alloc_ivt_fsm == ALLOC_IVT_XRAM_RSP)
+        {
+            size_t index = 0;
+            if(m_ivt.search_inval(r_xram_rsp_trt_buf.nline, index))  // pending inval
+            {
+                r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT;
 
 #if DEBUG_MEMC_XRAM_RSP
 if(m_debug)
-std::cout << "  <MEMC " << name() << " XRAM_RSP_INVAL_LOCK>"
+std::cout << "  <MEMC " << name() << " XRAM_RSP_IVT_LOCK>"
           << " Get acces to IVT, but line invalidation registered"
-          << " / nline = " << std::hex << r_xram_rsp_trt_buf.nline
+          << " / address = " << std::hex << r_xram_rsp_trt_buf.nline*m_words*4
           << " / index = " << std::dec << index << std::endl;
 #endif
 
-        }
-        else if(m_ivt.is_full() and r_xram_rsp_victim_inval.read()) // IVT full
-        {
-          r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT;
+            }
+            else if(m_ivt.is_full() and r_xram_rsp_victim_inval.read()) // IVT full
+            {
+                r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT;
 
 #if DEBUG_MEMC_XRAM_RSP
 if(m_debug)
-std::cout << "  <MEMC " << name() << " XRAM_RSP_INVAL_LOCK>"
+std::cout << "  <MEMC " << name() << " XRAM_RSP_IVT_LOCK>"
           << " Get acces to IVT, but inval required and IVT full" << std::endl;
 #endif
-        }
-        else
-        {
-          r_xram_rsp_fsm = XRAM_RSP_DIR_UPDT;
+            }
+            else
+            {
+                r_xram_rsp_fsm = XRAM_RSP_DIR_UPDT;
 
 #if DEBUG_MEMC_XRAM_RSP
 if(m_debug)
-std::cout << "  <MEMC " << name() << " XRAM_RSP_INVAL_LOCK>"
-          << " Get acces to IVT" << std::endl;
-#endif
-        }
-        m_cpt_xram_rsp_fsm_n_upt_lock++;
-      }
-
-      m_cpt_xram_rsp_fsm_upt_lock++;
-
-      break;
+std::cout << "  <MEMC " << name() << " XRAM_RSP_IVT_LOCK>"
+          << " Get acces to IVT / no pending inval request" << std::endl;
+#endif
+            }
+        }
+        break;
     }
     /////////////////////////
@@ -4224 +4367 @@
           << " Release all locks and retry" << std::endl;
 #endif
-      r_xram_rsp_fsm = XRAM_RSP_DIR_LOCK;
-      break;
+        r_xram_rsp_fsm = XRAM_RSP_DIR_LOCK;
+        break;
     }
     ///////////////////////
-    case XRAM_RSP_DIR_UPDT:   // updates the cache (both data & directory)
-                              // and possibly set an inval request in IVT
-    {
-      // check if this is an instruction read, this means pktid is either
-      // TYPE_READ_INS_UNC   0bX010 with TSAR encoding
-      // TYPE_READ_INS_MISS  0bX011 with TSAR encoding
-      bool inst_read = (r_xram_rsp_trt_buf.pktid & 0x2) and r_xram_rsp_trt_buf.proc_read;
-
-      // check if this is a cached read, this means pktid is either
-      // TYPE_READ_DATA_MISS 0bX001 with TSAR encoding
-      // TYPE_READ_INS_MISS  0bX011 with TSAR encoding
-      bool cached_read = (r_xram_rsp_trt_buf.pktid & 0x1) and r_xram_rsp_trt_buf.proc_read;
-
-      bool dirty = false;
-
-      // update cache data
-      size_t set   = r_xram_rsp_victim_set.read();
-      size_t way   = r_xram_rsp_victim_way.read();
-      for(size_t word=0; word<m_words ; word++)
-      {
-        m_cache_data.write(way, set, word, r_xram_rsp_trt_buf.wdata[word]);
-
-        dirty = dirty or (r_xram_rsp_trt_buf.wdata_be[word] != 0);
-
-        if(m_monitor_ok)
-        {
-          addr_t address = r_xram_rsp_trt_buf.nline<<6 | word<<2;
-          check_monitor( address, r_xram_rsp_trt_buf.wdata[word], false);
-        }
-      }
+    case XRAM_RSP_DIR_UPDT:   // updates the cache (both data & directory),
+                              // erases the TRT entry if victim not dirty,
+                              // and set inval request in IVT if required
+    {
+        assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP) and
+        "MEMC ERROR in XRAM_RSP_DIR_UPDT state: Bad DIR allocation");
+
+        assert( (r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP) and
+        "MEMC ERROR in XRAM_RSP_DIR_UPDT state: Bad TRT allocation");
+
+        assert( (r_alloc_ivt_fsm.read() == ALLOC_IVT_XRAM_RSP) and
+        "MEMC ERROR in XRAM_RSP_DIR_UPDT state: Bad IVT allocation");
+
+        // check if this is an instruction read, this means pktid is either
+        // TYPE_READ_INS_UNC   0bX010 with TSAR encoding
+        // TYPE_READ_INS_MISS  0bX011 with TSAR encoding
+        bool inst_read = (r_xram_rsp_trt_buf.pktid & 0x2) and r_xram_rsp_trt_buf.proc_read;
+
+        // check if this is a cached read, this means pktid is either
+        // TYPE_READ_DATA_MISS 0bX001 with TSAR encoding
+        // TYPE_READ_INS_MISS  0bX011 with TSAR encoding
+        bool cached_read = (r_xram_rsp_trt_buf.pktid & 0x1) and r_xram_rsp_trt_buf.proc_read;
+
+        bool dirty = false;
+
+        // update cache data
+        size_t set   = r_xram_rsp_victim_set.read();
+        size_t way   = r_xram_rsp_victim_way.read();
+
+        for(size_t word=0; word<m_words ; word++)
+        {
+            m_cache_data.write(way, set, word, r_xram_rsp_trt_buf.wdata[word]);
+            dirty = dirty or (r_xram_rsp_trt_buf.wdata_be[word] != 0);
+        }
 
       // update cache directory
@@ -4297 +4444 @@
       m_cache_directory.write(set, way, entry);
 
-      // request an invalidation request in IVT for victim line
-      if(r_xram_rsp_victim_inval.read())
-      {
-        bool   broadcast    = r_xram_rsp_victim_is_cnt.read();
-        size_t index        = 0;
-        size_t count_copies = r_xram_rsp_victim_count.read();
+        // register invalid request in IVT for victim line if required
+        if(r_xram_rsp_victim_inval.read())
+        {
+            bool   broadcast    = r_xram_rsp_victim_is_cnt.read();
+            size_t index        = 0;
+            size_t count_copies = r_xram_rsp_victim_count.read();
         
-        bool   wok = m_ivt.set(false,      // it's an inval transaction
-                               broadcast,  // set broadcast bit
-                               false,      // no response required 
-                               false,      // no acknowledge required 
-                               0,          // srcid
-                               0,          // trdid
-                               0,          // pktid
-                               r_xram_rsp_victim_nline.read(),
-                               count_copies,
-                               index);
-
-        r_xram_rsp_ivt_index = index;
-
-        if(!wok)
-        {
-          std::cout << "VCI_MEM_CACHE ERROR " << name() << " XRAM_RSP_DIR_UPDT"
-                    << " invalidate_tab entry free but write unsuccessful" << std::endl;
-          exit(0);
-        }
-      }
+            bool   wok = m_ivt.set(false,      // it's an inval transaction
+                                   broadcast,  // set broadcast bit
+                                   false,      // no response required 
+                                   false,      // no acknowledge required 
+                                   0,          // srcid
+                                   0,          // trdid
+                                   0,          // pktid
+                                   r_xram_rsp_victim_nline.read(),
+                                   count_copies,
+                                   index);
+
+            r_xram_rsp_ivt_index = index;
+
+            assert( wok and
+            "MEMC ERROR in XRAM_RSP_DIR_UPDT state: IVT should not be full"); 
+        }
 
 #if DEBUG_MEMC_XRAM_RSP
@@ -4337 +4480 @@
           << " / is_cnt = " << entry.is_cnt << std::endl;
 if(r_xram_rsp_victim_inval.read())
-std::cout << "                           Invalidation request for victim line "
-          << std::hex << r_xram_rsp_victim_nline.read()
+std::cout << "                           Invalidation request for address "
+          << std::hex << r_xram_rsp_victim_nline.read()*m_words*4
           << " / broadcast = " << r_xram_rsp_victim_is_cnt.read() << std::endl;
 }
@@ -4367 +4510 @@
     case XRAM_RSP_TRT_DIRTY:  // set the TRT entry (PUT to XRAM) if the victim is dirty
     {
-      if(r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP)
-      {
-        std::vector<data_t> data_vector;
-        data_vector.clear();
-        
-        for(size_t i=0; i<m_words; i++)
-        {
-          data_vector.push_back(r_xram_rsp_victim_data[i]);
-        }
-        /*m_trt.set(r_xram_rsp_trt_index.read(),
-                              false,       // write to XRAM
-                              r_xram_rsp_victim_nline.read(),  // line index
-                              0,
-                              0,
-                              0,
-                              false,
-                              0,
-                              0,
-                              std::vector<be_t> (m_words,0),
-                              std::vector<data_t> (m_words,0));*/
-        
-        m_trt.set(r_xram_rsp_trt_index.read(),
-                  false,       // write to XRAM
-                  r_xram_rsp_victim_nline.read(),  // line index
-                  0,
-                  0,
-                  0,
-                  false,
-                  0,
-                  0,
-                  std::vector<be_t> (m_words,0),
-                  data_vector);
+        if(r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP)
+        {
+            std::vector<data_t> data_vector;
+            data_vector.clear();
+            for(size_t i=0; i<m_words; i++)
+            {
+                data_vector.push_back(r_xram_rsp_victim_data[i].read());
+            }
+            m_trt.set( r_xram_rsp_trt_index.read(),
+                       false,                             // PUT
+                       r_xram_rsp_victim_nline.read(),    // line index
+                       0,                                 // unused
+                       0,                                 // unused
+                       0,                                 // unused
+                       false,                             // not proc_read
+                       0,                                 // unused
+                       0,                                 // unused
+                       std::vector<be_t>(m_words,0xF),                         
+                       data_vector);
 
 #if DEBUG_MEMC_XRAM_RSP
@@ -4404 +4534 @@
 std::cout << "  <MEMC " << name() << " XRAM_RSP_TRT_DIRTY>"
           << " Set TRT entry for the put transaction"
-          << " / dirty victim line = " << r_xram_rsp_victim_nline.read() << std::endl;
-#endif
-        if(r_xram_rsp_trt_buf.proc_read)         r_xram_rsp_fsm = XRAM_RSP_DIR_RSP;
-        else if(r_xram_rsp_victim_inval.read())  r_xram_rsp_fsm = XRAM_RSP_INVAL;
-        else                                     r_xram_rsp_fsm = XRAM_RSP_WRITE_DIRTY;
-        m_cpt_xram_rsp_fsm_n_trt_lock++;
-      }
-
-      m_cpt_xram_rsp_fsm_trt_lock++;
-
-      break;
+          << " / address = " << (r_xram_rsp_victim_nline.read()*m_words*4) << std::endl;
+#endif
+            if(r_xram_rsp_trt_buf.proc_read)         r_xram_rsp_fsm = XRAM_RSP_DIR_RSP;
+            else if(r_xram_rsp_victim_inval.read())  r_xram_rsp_fsm = XRAM_RSP_INVAL;
+            else                                     r_xram_rsp_fsm = XRAM_RSP_WRITE_DIRTY;
+        }
+        break;
     }
     //////////////////////
     case XRAM_RSP_DIR_RSP:     // Request a response to TGT_RSP FSM
     {
-      if(!r_xram_rsp_to_tgt_rsp_req.read())
-      {
-        r_xram_rsp_to_tgt_rsp_srcid = r_xram_rsp_trt_buf.srcid;
-        r_xram_rsp_to_tgt_rsp_trdid = r_xram_rsp_trt_buf.trdid;
-        r_xram_rsp_to_tgt_rsp_pktid = r_xram_rsp_trt_buf.pktid;
-        for(size_t i=0; i < m_words; i++)
-        {
-            r_xram_rsp_to_tgt_rsp_data[i] = r_xram_rsp_trt_buf.wdata[i];
-        }
-        r_xram_rsp_to_tgt_rsp_word   = r_xram_rsp_trt_buf.word_index;
-        r_xram_rsp_to_tgt_rsp_length = r_xram_rsp_trt_buf.read_length;
-        r_xram_rsp_to_tgt_rsp_ll_key = r_xram_rsp_trt_buf.ll_key;
-        r_xram_rsp_to_tgt_rsp_rerror = false;
-        r_xram_rsp_to_tgt_rsp_req    = true;
+        if ( not r_xram_rsp_to_tgt_rsp_req.read() )
+        {
+            r_xram_rsp_to_tgt_rsp_srcid = r_xram_rsp_trt_buf.srcid;
+            r_xram_rsp_to_tgt_rsp_trdid = r_xram_rsp_trt_buf.trdid;
+            r_xram_rsp_to_tgt_rsp_pktid = r_xram_rsp_trt_buf.pktid;
+            for(size_t i=0; i < m_words; i++)
+            {
+                r_xram_rsp_to_tgt_rsp_data[i] = r_xram_rsp_trt_buf.wdata[i];
+            }
+            r_xram_rsp_to_tgt_rsp_word   = r_xram_rsp_trt_buf.word_index;
+            r_xram_rsp_to_tgt_rsp_length = r_xram_rsp_trt_buf.read_length;
+            r_xram_rsp_to_tgt_rsp_ll_key = r_xram_rsp_trt_buf.ll_key;
+            r_xram_rsp_to_tgt_rsp_rerror = false;
+            r_xram_rsp_to_tgt_rsp_req    = true;
 
 #if ODCCP_NON_INCLUSIVE
@@ -4454 +4580 @@
           << " / nwords = " << std::dec << r_xram_rsp_trt_buf.read_length << std::endl;
 #endif
-      }
-      break;
+        }
+        break;
     }
     ////////////////////
@@ -4473 +4599 @@
         xram_rsp_to_cc_send_fifo_srcid     = r_xram_rsp_victim_copy.read();
         xram_rsp_to_cc_send_fifo_inst      = r_xram_rsp_victim_copy_inst.read();
-#if L1_MULTI_CACHE
-        xram_rsp_to_cc_send_fifo_cache_id  = r_xram_rsp_victim_copy_cache.read();
-#endif
         xram_rsp_to_cc_send_fifo_put       = multi_req;
-        r_xram_rsp_next_ptr                 = r_xram_rsp_victim_ptr.read();
+        r_xram_rsp_next_ptr                = r_xram_rsp_victim_ptr.read();
 
 #if ODCCP_NON_INCLUSIVE
@@ -4494 +4617 @@
 std::cout << "  <MEMC " << name() << " XRAM_RSP_INVAL>"
           << " Send an inval request to CC_SEND FSM"
-          << " / victim line = " << r_xram_rsp_victim_nline.read() << std::endl;
+          << " / address = " << r_xram_rsp_victim_nline.read()*m_words*4 << std::endl;
 #endif
       }
@@ -4506 +4629 @@
 
         r_xram_rsp_to_ixr_cmd_req = true;
-        r_xram_rsp_to_ixr_cmd_nline = r_xram_rsp_victim_nline.read();
-        r_xram_rsp_to_ixr_cmd_trdid = r_xram_rsp_trt_index.read();
-        for(size_t i=0; i<m_words ; i++)
-        {
-            r_xram_rsp_to_ixr_cmd_data[i] = r_xram_rsp_victim_data[i];
-        }
-        m_cpt_write_dirty++;
-
+        //r_xram_rsp_to_ixr_cmd_nline = r_xram_rsp_victim_nline.read();
+        r_xram_rsp_to_ixr_cmd_index = r_xram_rsp_trt_index.read();
+        /*for(size_t i=0; i<m_words ; i++)
+        {
+          r_xram_rsp_to_ixr_cmd_data[i] = r_xram_rsp_victim_data[i];
+        }*/
 #if (ODCCP_NON_INCLUSIVE == 0)
         // if victim is no coherent, we dont request a ixr command
@@ -4525 +4646 @@
 #endif
 
-        bool multi_req = !r_xram_rsp_victim_is_cnt.read() and r_xram_rsp_victim_inval.read();
+        m_cpt_write_dirty++;
+
+        bool multi_req = not r_xram_rsp_victim_is_cnt.read() and 
+          r_xram_rsp_victim_inval.read();
         bool not_last_multi_req = multi_req and (r_xram_rsp_victim_count.read() != 1);
 
@@ -4535 +4659 @@
 std::cout << "  <MEMC " << name() << " XRAM_RSP_WRITE_DIRTY>"
           << " Send the put request to IXR_CMD FSM"
-          << " / victim line = " << r_xram_rsp_victim_nline.read() << std::endl;
-#endif
-      }
-      break;
+          << " / address = " << r_xram_rsp_victim_nline.read()*m_words*4 << std::endl;
+#endif
+        }
+        break;
     }
     /////////////////////////
     case XRAM_RSP_HEAP_REQ:    // Get the lock to the HEAP
     {
-      if(r_alloc_heap_fsm.read() == ALLOC_HEAP_XRAM_RSP)
-      {
-        r_xram_rsp_fsm = XRAM_RSP_HEAP_ERASE;
-        m_cpt_xram_rsp_fsm_n_heap_lock++;
-      }
+        if(r_alloc_heap_fsm.read() == ALLOC_HEAP_XRAM_RSP)
+        {
+            r_xram_rsp_fsm = XRAM_RSP_HEAP_ERASE;
+        }
 
 #if DEBUG_MEMC_XRAM_RSP
@@ -4554 +4677 @@
           << " Requesting HEAP lock" << std::endl;
 #endif
-
-      m_cpt_xram_rsp_fsm_heap_lock++;
-
-      break;
+        break;
     }
     /////////////////////////
@@ -4567 +4687 @@
 
         xram_rsp_to_cc_send_fifo_srcid    = entry.owner.srcid;
-#if L1_MULTI_CACHE
-        xram_rsp_to_cc_send_fifo_cache_id = entry.owner.cache_id;
-#endif
         xram_rsp_to_cc_send_fifo_inst  = entry.owner.inst;
         xram_rsp_to_cc_send_fifo_put   = true;
@@ -4613 +4730 @@
       HeapEntry last_entry;
       last_entry.owner.srcid    = 0;
-#if L1_MULTI_CACHE
-      last_entry.owner.cache_id = 0;
-#endif
       last_entry.owner.inst     = false;
       if(m_heap.is_full())
@@ -4639 +4753 @@
       break;