Index: branches/RWT/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h
===================================================================
--- branches/RWT/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h	(revision 477)
+++ branches/RWT/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h	(revision 495)
@@ -179,9 +179,9 @@
         CC_RECEIVE_INS_UPDT_HEADER,
         CC_RECEIVE_INS_UPDT_NLINE,
-        CC_RECEIVE_INS_UPDT_DATA,
         CC_RECEIVE_DATA_INVAL_HEADER,
         CC_RECEIVE_DATA_INVAL_NLINE,
         CC_RECEIVE_DATA_UPDT_HEADER,
         CC_RECEIVE_DATA_UPDT_NLINE,
+        CC_RECEIVE_INS_UPDT_DATA,
         CC_RECEIVE_DATA_UPDT_DATA,
     };
@@ -403,4 +403,8 @@
     sc_signal<bool>         r_icache_tlb_rsp_error;      // tlb miss response error
 
+    // Filp-Flop in ICACHE FSM for saving the cleanup victim request
+    sc_signal<bool>         r_icache_cleanup_victim_req; 
+    sc_signal<paddr_t>      r_icache_cleanup_victim_nline;
+
     // communication between ICACHE FSM and CC_SEND FSM
     sc_signal<bool>         r_icache_cc_send_req;           // ICACHE cc_send request
@@ -504,4 +508,10 @@
     sc_signal<bool>         r_dcache_xtn_req;           // xtn request (caused by processor)
     sc_signal<int>          r_dcache_xtn_opcode;        // xtn request type
+
+    // Filp-Flop in DCACHE FSM for saving the cleanup victim request
+    sc_signal<bool>         r_dcache_cleanup_victim_req; 
+    sc_signal<bool>         r_dcache_cleanup_victim_line_ncc; 
+    sc_signal<bool>         r_dcache_cleanup_victim_updt_data; 
+    sc_signal<paddr_t>      r_dcache_cleanup_victim_nline;
 
     // communication between DCACHE FSM and CC_SEND FSM
Index: branches/RWT/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp
===================================================================
--- branches/RWT/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp	(revision 477)
+++ branches/RWT/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp	(revision 495)
@@ -354,5 +354,8 @@
       r_dcache_xtn_req("r_dcache_xtn_req"),
       r_dcache_xtn_opcode("r_dcache_xtn_opcode"),
-
+ 
+      r_dcache_cleanup_victim_req("r_dcache_cleanup_victim_req"),
+      r_dcache_cleanup_victim_nline("r_dcache_cleanup_victim_nline"),
+  
       r_dcache_cc_send_req("r_dcache_cc_send_req"),
       r_dcache_cc_send_type("r_dcache_cc_send_type"),
@@ -374,5 +377,5 @@
       r_vci_rsp_fifo_dcache("r_vci_rsp_fifo_dcache", 2),	// 2 words depth
       r_vci_rsp_fifo_rpktid("r_vci_rsp_fifo_rpktid", 2),    // 2 words depth
-      r_cc_send_data_fifo("r_cc_send_data_fifo", 2),
+      r_cc_send_data_fifo("r_cc_send_data_fifo", 16),
 
       r_cc_send_fsm("r_cc_send_fsm"),
@@ -815,5 +818,4 @@
         // No request from DCACHE FSM to CC_SEND FSM
         r_dcache_cc_send_req       = false;
-
         r_dcache_clack_req         = false;
 
@@ -852,4 +854,8 @@
         r_dcache_miss_data_cpt = 0;
         r_dcache_miss_data_addr = 0;
+
+        r_dcache_cleanup_victim_req = false;
+        r_dcache_cleanup_victim_line_ncc = false;
+        r_dcache_cleanup_victim_updt_data = false;
 
         // activity counters
@@ -1093,5 +1099,5 @@
 
         // coherence interrupt
-        if ( r_cc_receive_icache_req.read() )
+        if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read())
         {
             r_icache_fsm = ICACHE_CC_CHECK;
@@ -1329,5 +1335,5 @@
 
         // coherence interrupt
-        if ( r_cc_receive_icache_req.read() )
+        if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read())
         {
             r_icache_fsm = ICACHE_CC_CHECK;
@@ -1381,5 +1387,5 @@
 
         // coherence request (from CC_RECEIVE FSM)
-        if ( r_cc_receive_icache_req.read() )
+        if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read())
         {
             r_icache_fsm = ICACHE_CC_CHECK;
@@ -1588,5 +1594,5 @@
 
         // coherence interrupt
-        if ( r_cc_receive_icache_req.read() )
+        if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read())
         {
             r_icache_fsm = ICACHE_CC_CHECK;
@@ -1685,5 +1691,5 @@
 
         // coherence interrupt
-        if ( r_cc_receive_icache_req.read() )
+        if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read())
         {
             r_icache_fsm = ICACHE_CC_CHECK;
@@ -1764,5 +1770,5 @@
 
         // coherence interrupt
-        if ( r_cc_receive_icache_req.read() )
+        if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read())
         {
             r_icache_fsm = ICACHE_CC_CHECK;
@@ -1843,5 +1849,5 @@
 
         // coherence interrupt
-        if ( r_cc_receive_icache_req.read() )
+        if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read())
         {
             r_icache_fsm = ICACHE_CC_CHECK;
@@ -1882,4 +1888,44 @@
         paddr_t  mask  = ~((m_icache_words<<2)-1);
 
+        // CLACK handler
+        // We switch the directory slot to EMPTY state
+        // and reset r_icache_miss_clack if the cleanup ack
+        // is matching a pending miss.
+        if ( r_icache_clack_req.read() )
+        {
+
+            if ( m_ireq.valid ) m_cost_ins_miss_frz++;
+
+#ifdef INSTRUMENTATION
+m_cpt_icache_dir_write++;
+#endif
+            r_icache.write_dir( 0,
+                                r_icache_clack_way.read(),
+                                r_icache_clack_set.read(),
+                                CACHE_SLOT_STATE_EMPTY);
+
+            if ( (r_icache_miss_set.read() == r_icache_clack_set.read()) and
+                 (r_icache_miss_way.read() == r_icache_clack_way.read()) )
+            {
+                r_icache_miss_clack = false;
+            }
+
+            r_icache_clack_req = false;
+
+            // return to cc_save state
+            r_icache_fsm = r_icache_fsm_save.read();
+
+#if DEBUG_ICACHE
+if ( m_debug_activated )
+{
+    std::cout << "  <PROC " << name()
+        << " ICACHE_CC_CHECK>  CC_TYPE_CLACK slot returns to empty state"
+        << " set = " << r_icache_clack_set.read()
+        << " / way = " << r_icache_clack_way.read() << std::endl;
+}
+#endif
+
+            break;
+        }
 
         // Match between MISS address and CC address
@@ -1921,50 +1967,5 @@
         }
 
-        // CLACK handler
-        // We switch the directory slot to EMPTY state
-        // and reset r_icache_miss_clack if the cleanup ack
-        // is matching a pending miss.
-        if ( r_icache_clack_req.read() )
-        {
-
-            if ( m_ireq.valid ) m_cost_ins_miss_frz++;
-
-#ifdef INSTRUMENTATION
-m_cpt_icache_dir_write++;
-#endif
-            r_icache.write_dir( 0,
-                                r_icache_clack_way.read(),
-                                r_icache_clack_set.read(),
-                                CACHE_SLOT_STATE_EMPTY);
-
-            if ( (r_icache_miss_set.read() == r_icache_clack_set.read()) and
-                 (r_icache_miss_way.read() == r_icache_clack_way.read()) )
-            {
-                r_icache_miss_clack = false;
-            }
-
-            r_icache_clack_req = false;
-
-            // return to cc_save state if no pending CC request
-            if ( not r_cc_receive_icache_req.read() )
-                r_icache_fsm = r_icache_fsm_save.read();
-
-#if DEBUG_ICACHE
-if ( m_debug_activated )
-{
-    std::cout << "  <PROC " << name()
-        << " ICACHE_CC_CHECK>  CC_TYPE_CLACK slot returns to empty state"
-        << " set = " << r_icache_clack_set.read()
-        << " / way = " << r_icache_clack_way.read() << std::endl;
-}
-#endif
-
-            break;
-        }
-
-        // wait if pending request to CC_SEND. This way if there are pending
-        // CLACK they can be treated in this state and then a deadlock
-        // situation is avoided
-        if ( r_icache_cc_send_req.read() ) break;
+        assert ( not r_icache_cc_send_req.read() and "CC_SEND must be available in ICACHE_CC_CHECK");
 
         // CC request handler
@@ -2418,5 +2419,5 @@
         }
         // coherence request (from CC_RECEIVE FSM)
-        else if ( r_cc_receive_dcache_req.read() )
+        else if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
         {
             r_dcache_fsm = DCACHE_CC_CHECK;
@@ -3057,5 +3058,5 @@
 
         // coherence request (from CC_RECEIVE FSM)
-        if ( r_cc_receive_dcache_req.read() )
+        if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
         {
             r_dcache_fsm = DCACHE_CC_CHECK;
@@ -3369,5 +3370,5 @@
 
         // coherence request (from CC_RECEIVE FSM)
-        if ( r_cc_receive_dcache_req.read() )
+        if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
         {
             r_dcache_fsm = DCACHE_CC_CHECK;
@@ -3737,5 +3738,5 @@
 
         // coherence request (from CC_RECEIVE FSM)
-        if ( r_cc_receive_dcache_req.read() )
+        if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
         {
             r_dcache_fsm = DCACHE_CC_CHECK;
@@ -3816,5 +3817,5 @@
 
         // coherence request (from CC_RECEIVE FSM)
-        if ( r_cc_receive_dcache_req.read() )
+        if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
         {
             r_dcache_fsm = DCACHE_CC_CHECK;
@@ -3846,5 +3847,5 @@
 
         // coherence request (from CC_RECEIVE FSM)
-        if ( r_cc_receive_dcache_req.read() )
+        if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
         {
             r_dcache_fsm = DCACHE_CC_CHECK;
@@ -3889,5 +3890,5 @@
 
         // coherence request (from CC_RECEIVE FSM)
-        if ( r_cc_receive_dcache_req.read() )
+        if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
         {
             r_dcache_fsm = DCACHE_CC_CHECK;
@@ -3980,4 +3981,5 @@
         size_t   set;
         size_t   word;
+
         r_dcache.read_neutral(r_dcache_xtn_flush_addr_data.read(),
                               &rdata,
@@ -3999,4 +4001,10 @@
             }
         }
+//       else if ( r_dcache_clack_req.read() )
+//       {
+//           r_dcache_fsm = DCACHE_CC_CHECK;
+//           r_dcache_fsm_cc_save = r_dcache_fsm.read();
+//           break;
+//       }
         break;
     }
@@ -4311,5 +4319,5 @@
 
         // coherence request (from CC_RECEIVE FSM)
-        if ( r_cc_receive_dcache_req.read() )
+        if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
         {
             r_dcache_fsm = DCACHE_CC_CHECK;
@@ -4318,6 +4326,4 @@
         }
 
-        if ( not r_dcache_cc_send_req.read() ) // blocked until previous cc_send request is sent
-        {
             bool     found = false;
             bool     cleanup = false;
@@ -4326,4 +4332,6 @@
             paddr_t  victim = 0;
             int state;
+            bool     s_cleanup_updt_data = false;
+            bool     s_cleanup_line_ncc = false;
 
 #ifdef INSTRUMENTATION
@@ -4347,18 +4355,13 @@
                     r_dcache_miss_clack   = true;
                     r_dcache_fsm          = DCACHE_MISS_CLEAN;
-                    // request cleanup
-                    r_dcache_cc_send_req   = true;
-                    r_dcache_cc_send_nline = victim;
-                    r_dcache_cc_send_way   = way;
-                    r_dcache_cc_send_type  = CC_TYPE_CLEANUP;
                     if( (state == CACHE_SLOT_STATE_VALID_NCC) )//and (r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_DATA_DIRTY) )
                     {
                         //MODIFIER POUR DIRTY BIT //
-                        r_dcache_cc_cleanup_line_ncc = true;
+                        s_cleanup_line_ncc = true;
                         r_dcache_miss_data_addr = (victim*m_dcache_words)*4;
                         //if ((r_dcache_content_state[way*m_dcache_sets+set] != LINE_CACHE_DATA_NOT_DIRTY))//must send data
                         if (true)//must send data
                         {
-                            r_dcache_cc_cleanup_updt_data = true;
+                            s_cleanup_updt_data = true;
                             for (size_t w = 0; w< m_dcache_words; w++)
                             {
@@ -4369,5 +4372,5 @@
                         else
                         {
-                            r_dcache_cc_cleanup_updt_data = false;
+                            s_cleanup_updt_data = false;
                         }
 
@@ -4378,6 +4381,28 @@
                     else
                     {
-                        r_dcache_cc_cleanup_line_ncc  = false;
-                        r_dcache_cc_cleanup_updt_data = false;
+                        s_cleanup_line_ncc  = false;
+                        s_cleanup_updt_data = false;
+                    }
+
+                    if( not r_dcache_cc_send_req.read() )
+                    {
+                        // request cleanup
+                        r_dcache_cc_send_req   = true;
+                        r_dcache_cc_send_nline = victim;
+                        r_dcache_cc_send_way   = way;
+                        r_dcache_cc_send_type  = CC_TYPE_CLEANUP;
+                        r_dcache_cc_cleanup_updt_data = s_cleanup_updt_data;
+                        r_dcache_cc_cleanup_line_ncc  = s_cleanup_line_ncc;
+                    }
+                    else
+                    {
+                        r_dcache_cleanup_victim_nline = victim;
+                        r_dcache_cleanup_victim_req = true;
+                        r_dcache_cleanup_victim_updt_data = s_cleanup_updt_data;
+                        r_dcache_cleanup_victim_line_ncc = s_cleanup_line_ncc;
+                        std::cout << "  <PROC " << name()
+                                  << "/ CYCLE = "
+                                  << m_cpt_total_cycles
+                                  << std :: endl;
                     }
                 }
@@ -4400,5 +4425,4 @@
 #endif
             } // end found
-        }
         break;
     }
@@ -4410,4 +4434,15 @@
         size_t set;
         size_t word;
+
+        if( r_dcache_cleanup_victim_req.read() and not r_dcache_cc_send_req.read() )
+        {
+            r_dcache_cc_send_req = true;
+            r_dcache_cc_send_type = CC_TYPE_CLEANUP;
+            r_dcache_cc_send_nline = r_dcache_cleanup_victim_nline.read();
+            r_dcache_cleanup_victim_req = false;
+            r_dcache_cc_cleanup_updt_data = r_dcache_cleanup_victim_updt_data.read();
+            r_dcache_cc_cleanup_line_ncc = r_dcache_cleanup_victim_line_ncc.read();
+            r_dcache_cc_send_way = r_dcache_miss_way;
+        }
 
         r_dcache.read_neutral(r_dcache_miss_data_addr,
@@ -4430,4 +4465,11 @@
             }
         }
+//       else if ( r_dcache_clack_req.read() )
+//       {
+//           r_dcache_fsm = DCACHE_CC_CHECK;
+//           r_dcache_fsm_cc_save = r_dcache_fsm.read();
+//           break;
+//       }
+
         break;
     }
@@ -4495,4 +4537,16 @@
     {
         if ( m_dreq.valid) m_cost_data_miss_frz++;
+
+        if( r_dcache_cleanup_victim_req.read() and not r_dcache_cc_send_req.read() )
+        {
+            r_dcache_cc_send_req = true;
+            r_dcache_cc_send_type = CC_TYPE_CLEANUP;
+            r_dcache_cc_send_nline = r_dcache_cleanup_victim_nline.read();
+            r_dcache_cleanup_victim_req = false;
+            r_dcache_cc_cleanup_updt_data = r_dcache_cleanup_victim_updt_data.read();
+            r_dcache_cc_cleanup_line_ncc = r_dcache_cleanup_victim_line_ncc.read();
+            r_dcache_cc_send_way = r_dcache_miss_way;
+        }
+
         // coherence clack request (from DSPIN CLACK)
         if ( r_dcache_clack_req.read() )
@@ -4504,5 +4558,5 @@
 
         // coherence request (from CC_RECEIVE FSM)
-        if ( r_cc_receive_dcache_req.read() )
+        if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read() and not r_dcache_cleanup_victim_req.read() )
         {
             r_dcache_fsm = DCACHE_CC_CHECK;
@@ -4623,4 +4677,15 @@
         if ( m_dreq.valid) m_cost_data_miss_frz++;
 
+        if( r_dcache_cleanup_victim_req.read() and not r_dcache_cc_send_req.read() )
+        {
+            r_dcache_cc_send_req = true;
+            r_dcache_cc_send_type = CC_TYPE_CLEANUP;
+            r_dcache_cc_send_nline = r_dcache_cleanup_victim_nline.read();
+            r_dcache_cleanup_victim_req = false;
+            r_dcache_cc_cleanup_updt_data = r_dcache_cleanup_victim_updt_data.read();
+            r_dcache_cc_cleanup_line_ncc = r_dcache_cleanup_victim_line_ncc.read();
+            r_dcache_cc_send_way = r_dcache_miss_way;
+        }
+
         // coherence clack request (from DSPIN CLACK)
         if ( r_dcache_clack_req.read() )
@@ -4632,5 +4697,5 @@
 
         // coherence request (from CC_RECEIVE FSM)
-        if ( r_cc_receive_dcache_req.read() )
+        if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read() and not r_dcache_cleanup_victim_req.read() )
         {
             r_dcache_fsm = DCACHE_CC_CHECK;
@@ -4736,5 +4801,5 @@
 
         // coherence request (from CC_RECEIVE FSM)
-        if ( r_cc_receive_dcache_req.read() )
+        if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
         {
             r_dcache_fsm = DCACHE_CC_CHECK;
@@ -4781,5 +4846,5 @@
 
         // coherence request (from CC_RECEIVE FSM)
-        if ( r_cc_receive_dcache_req.read() )
+        if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
         {
             r_dcache_fsm = DCACHE_CC_CHECK;
@@ -4835,5 +4900,5 @@
 
         // coherence request (from CC_RECEIVE FSM)
-        if ( r_cc_receive_dcache_req.read() )
+        if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
         {
             r_dcache_fsm = DCACHE_CC_CHECK;
@@ -4954,5 +5019,5 @@
 
         // coherence request (from CC_RECEIVE FSM)
-        if ( r_cc_receive_dcache_req.read() )
+        if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
         {
             r_dcache_fsm = DCACHE_CC_CHECK;
@@ -5045,4 +5110,41 @@
 }
 #endif
+        // CLACK handler
+        // We switch the directory slot to EMPTY state and reset
+        // r_dcache_miss_clack if the cleanup ack is matching a pending miss.
+        if ( r_dcache_clack_req.read() )
+        {
+            if ( m_dreq.valid ) m_cost_data_miss_frz++;
+
+#ifdef INSTRUMENTATION
+m_cpt_dcache_dir_write++;
+#endif
+            r_dcache.write_dir( 0,
+                                r_dcache_clack_way.read(),
+                                r_dcache_clack_set.read(),
+                                CACHE_SLOT_STATE_EMPTY);
+
+            if ( (r_dcache_miss_set.read() == r_dcache_clack_set.read()) and
+                 (r_dcache_miss_way.read() == r_dcache_clack_way.read()) )
+            {
+                  r_dcache_miss_clack = false;
+            }
+
+            r_dcache_clack_req = false;
+
+            // return to cc_save state
+            r_dcache_fsm = r_dcache_fsm_cc_save.read() ;
+
+#if DEBUG_DCACHE
+if ( m_debug_activated )
+{
+    std::cout << "  <PROC " << name()
+              << " DCACHE_CC_CHECK> CC_TYPE_CLACK Switch slot to EMPTY state"
+              << " set = " << r_dcache_clack_set.read()
+              << " / way = " << r_dcache_clack_way.read() << std::endl;
+}
+#endif
+            break;
+        }
 
         
@@ -5086,49 +5188,6 @@
         }
 
-        // CLACK handler
-        // We switch the directory slot to EMPTY state and reset
-        // r_dcache_miss_clack if the cleanup ack is matching a pending miss.
-        if ( r_dcache_clack_req.read() )
-        {
-            if ( m_dreq.valid ) m_cost_data_miss_frz++;
-
-#ifdef INSTRUMENTATION
-m_cpt_dcache_dir_write++;
-#endif
-            r_dcache.write_dir( 0,
-                                r_dcache_clack_way.read(),
-                                r_dcache_clack_set.read(),
-                                CACHE_SLOT_STATE_EMPTY);
-
-            if ( (r_dcache_miss_set.read() == r_dcache_clack_set.read()) and
-                 (r_dcache_miss_way.read() == r_dcache_clack_way.read()) )
-            {
-                  r_dcache_miss_clack = false;
-            }
-
-            r_dcache_clack_req = false;
-
-            // return to cc_save state if no pending CC request
-            if ( not r_cc_receive_dcache_req.read() )
-            {
-                r_dcache_fsm = r_dcache_fsm_cc_save.read() ;
-            }
-
-#if DEBUG_DCACHE
-if ( m_debug_activated )
-{
-    std::cout << "  <PROC " << name()
-              << " DCACHE_CC_CHECK> CC_TYPE_CLACK Switch slot to EMPTY state"
-              << " set = " << r_dcache_clack_set.read()
-              << " / way = " << r_dcache_clack_way.read() << std::endl;
-}
-#endif
-            break;
-        }
-
-        // wait if pending request to CC_SEND. This way if there are pending
-        // CLACK they can be treated in this state and then a deadlock
-        // situation is avoided
-        if ( r_dcache_cc_send_req.read() ) break;
+
+        assert ( not r_dcache_cc_send_req.read() and "CC_SEND must be available in DCACHE_CC_CHECK" );
 
         // CC request handler
@@ -5943,4 +6002,11 @@
             if (p_vci.rspval.read())
             {
+                /**/
+                if( p_vci.reop.read() ==0)
+                {
+                    std::cout << "PROC " << m_srcid 
+                              << "/ CYCLE " << m_cpt_total_cycles
+                              <<std::endl; 
+                }
                 assert( p_vci.reop.read() and
                 "a VCI response packet must contain one flit for a write transaction");
@@ -6153,5 +6219,5 @@
             // flip_flop to check that ?
             if (not (r_cc_receive_icache_req.read()) and 
-                not (r_cc_receive_dcache_req.read()) and 
+                not (r_cc_receive_dcache_req.read()) and
                 (p_dspin_m2p.write.read()))
             {
@@ -6193,5 +6259,6 @@
             uint64_t receive_data = p_dspin_m2p.data.read();
             // for data INVAL, wait for dcache to take the request
-            if (p_dspin_m2p.write.read() and not r_cc_receive_dcache_req.read())
+            if (p_dspin_m2p.write.read()           and 
+                not r_cc_receive_dcache_req.read() )
             {
                 // request dcache to handle the INVAL
@@ -6211,5 +6278,6 @@
             uint64_t receive_data = p_dspin_m2p.data.read();
             // for ins INVAL, wait for icache to take the request
-            if (p_dspin_m2p.write.read() and not r_cc_receive_icache_req.read())
+            if (p_dspin_m2p.write.read()           and 
+                not r_cc_receive_icache_req.read() )
             {
                 // request icache to handle the INVAL
@@ -6261,5 +6329,5 @@
             // for data INVAL, wait for dcache to take the request and fifo to
             // be empty
-            if ( r_cc_receive_updt_fifo_be.empty() and 
+            if ( r_cc_receive_updt_fifo_be.empty() and
                  p_dspin_m2p.write.read() )
             {
@@ -6281,5 +6349,5 @@
             // for ins INVAL, wait for icache to take the request and fifo to be
             // empty
-            if ( r_cc_receive_updt_fifo_be.empty() and 
+            if ( r_cc_receive_updt_fifo_be.empty() and
                  p_dspin_m2p.write.read() )
             {
