Index: branches/RWT/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h =================================================================== --- branches/RWT/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h (revision 477) +++ branches/RWT/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h (revision 495) @@ -179,9 +179,9 @@ CC_RECEIVE_INS_UPDT_HEADER, CC_RECEIVE_INS_UPDT_NLINE, - CC_RECEIVE_INS_UPDT_DATA, CC_RECEIVE_DATA_INVAL_HEADER, CC_RECEIVE_DATA_INVAL_NLINE, CC_RECEIVE_DATA_UPDT_HEADER, CC_RECEIVE_DATA_UPDT_NLINE, + CC_RECEIVE_INS_UPDT_DATA, CC_RECEIVE_DATA_UPDT_DATA, }; @@ -403,4 +403,8 @@ sc_signal r_icache_tlb_rsp_error; // tlb miss response error + // Filp-Flop in ICACHE FSM for saving the cleanup victim request + sc_signal r_icache_cleanup_victim_req; + sc_signal r_icache_cleanup_victim_nline; + // communication between ICACHE FSM and CC_SEND FSM sc_signal r_icache_cc_send_req; // ICACHE cc_send request @@ -504,4 +508,10 @@ sc_signal r_dcache_xtn_req; // xtn request (caused by processor) sc_signal r_dcache_xtn_opcode; // xtn request type + + // Filp-Flop in DCACHE FSM for saving the cleanup victim request + sc_signal r_dcache_cleanup_victim_req; + sc_signal r_dcache_cleanup_victim_line_ncc; + sc_signal r_dcache_cleanup_victim_updt_data; + sc_signal r_dcache_cleanup_victim_nline; // communication between DCACHE FSM and CC_SEND FSM Index: branches/RWT/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp =================================================================== --- branches/RWT/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp (revision 477) +++ branches/RWT/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp (revision 495) @@ -354,5 +354,8 @@ r_dcache_xtn_req("r_dcache_xtn_req"), r_dcache_xtn_opcode("r_dcache_xtn_opcode"), - + + r_dcache_cleanup_victim_req("r_dcache_cleanup_victim_req"), + r_dcache_cleanup_victim_nline("r_dcache_cleanup_victim_nline"), + r_dcache_cc_send_req("r_dcache_cc_send_req"), r_dcache_cc_send_type("r_dcache_cc_send_type"), @@ -374,5 +377,5 @@ r_vci_rsp_fifo_dcache("r_vci_rsp_fifo_dcache", 2), // 2 words depth r_vci_rsp_fifo_rpktid("r_vci_rsp_fifo_rpktid", 2), // 2 words depth - r_cc_send_data_fifo("r_cc_send_data_fifo", 2), + r_cc_send_data_fifo("r_cc_send_data_fifo", 16), r_cc_send_fsm("r_cc_send_fsm"), @@ -815,5 +818,4 @@ // No request from DCACHE FSM to CC_SEND FSM r_dcache_cc_send_req = false; - r_dcache_clack_req = false; @@ -852,4 +854,8 @@ r_dcache_miss_data_cpt = 0; r_dcache_miss_data_addr = 0; + + r_dcache_cleanup_victim_req = false; + r_dcache_cleanup_victim_line_ncc = false; + r_dcache_cleanup_victim_updt_data = false; // activity counters @@ -1093,5 +1099,5 @@ // coherence interrupt - if ( r_cc_receive_icache_req.read() ) + if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read()) { r_icache_fsm = ICACHE_CC_CHECK; @@ -1329,5 +1335,5 @@ // coherence interrupt - if ( r_cc_receive_icache_req.read() ) + if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read()) { r_icache_fsm = ICACHE_CC_CHECK; @@ -1381,5 +1387,5 @@ // coherence request (from CC_RECEIVE FSM) - if ( r_cc_receive_icache_req.read() ) + if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read()) { r_icache_fsm = ICACHE_CC_CHECK; @@ -1588,5 +1594,5 @@ // coherence interrupt - if ( r_cc_receive_icache_req.read() ) + if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read()) { r_icache_fsm = ICACHE_CC_CHECK; @@ -1685,5 +1691,5 @@ // coherence interrupt - if ( r_cc_receive_icache_req.read() ) + if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read()) { r_icache_fsm = ICACHE_CC_CHECK; @@ -1764,5 +1770,5 @@ // coherence interrupt - if ( r_cc_receive_icache_req.read() ) + if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read()) { r_icache_fsm = ICACHE_CC_CHECK; @@ -1843,5 +1849,5 @@ // coherence interrupt - if ( r_cc_receive_icache_req.read() ) + if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read()) { r_icache_fsm = ICACHE_CC_CHECK; @@ -1882,4 +1888,44 @@ paddr_t mask = ~((m_icache_words<<2)-1); + // CLACK handler + // We switch the directory slot to EMPTY state + // and reset r_icache_miss_clack if the cleanup ack + // is matching a pending miss. + if ( r_icache_clack_req.read() ) + { + + if ( m_ireq.valid ) m_cost_ins_miss_frz++; + +#ifdef INSTRUMENTATION +m_cpt_icache_dir_write++; +#endif + r_icache.write_dir( 0, + r_icache_clack_way.read(), + r_icache_clack_set.read(), + CACHE_SLOT_STATE_EMPTY); + + if ( (r_icache_miss_set.read() == r_icache_clack_set.read()) and + (r_icache_miss_way.read() == r_icache_clack_way.read()) ) + { + r_icache_miss_clack = false; + } + + r_icache_clack_req = false; + + // return to cc_save state + r_icache_fsm = r_icache_fsm_save.read(); + +#if DEBUG_ICACHE +if ( m_debug_activated ) +{ + std::cout << " CC_TYPE_CLACK slot returns to empty state" + << " set = " << r_icache_clack_set.read() + << " / way = " << r_icache_clack_way.read() << std::endl; +} +#endif + + break; + } // Match between MISS address and CC address @@ -1921,50 +1967,5 @@ } - // CLACK handler - // We switch the directory slot to EMPTY state - // and reset r_icache_miss_clack if the cleanup ack - // is matching a pending miss. - if ( r_icache_clack_req.read() ) - { - - if ( m_ireq.valid ) m_cost_ins_miss_frz++; - -#ifdef INSTRUMENTATION -m_cpt_icache_dir_write++; -#endif - r_icache.write_dir( 0, - r_icache_clack_way.read(), - r_icache_clack_set.read(), - CACHE_SLOT_STATE_EMPTY); - - if ( (r_icache_miss_set.read() == r_icache_clack_set.read()) and - (r_icache_miss_way.read() == r_icache_clack_way.read()) ) - { - r_icache_miss_clack = false; - } - - r_icache_clack_req = false; - - // return to cc_save state if no pending CC request - if ( not r_cc_receive_icache_req.read() ) - r_icache_fsm = r_icache_fsm_save.read(); - -#if DEBUG_ICACHE -if ( m_debug_activated ) -{ - std::cout << " CC_TYPE_CLACK slot returns to empty state" - << " set = " << r_icache_clack_set.read() - << " / way = " << r_icache_clack_way.read() << std::endl; -} -#endif - - break; - } - - // wait if pending request to CC_SEND. This way if there are pending - // CLACK they can be treated in this state and then a deadlock - // situation is avoided - if ( r_icache_cc_send_req.read() ) break; + assert ( not r_icache_cc_send_req.read() and "CC_SEND must be available in ICACHE_CC_CHECK"); // CC request handler @@ -2418,5 +2419,5 @@ } // coherence request (from CC_RECEIVE FSM) - else if ( r_cc_receive_dcache_req.read() ) + else if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) { r_dcache_fsm = DCACHE_CC_CHECK; @@ -3057,5 +3058,5 @@ // coherence request (from CC_RECEIVE FSM) - if ( r_cc_receive_dcache_req.read() ) + if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) { r_dcache_fsm = DCACHE_CC_CHECK; @@ -3369,5 +3370,5 @@ // coherence request (from CC_RECEIVE FSM) - if ( r_cc_receive_dcache_req.read() ) + if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) { r_dcache_fsm = DCACHE_CC_CHECK; @@ -3737,5 +3738,5 @@ // coherence request (from CC_RECEIVE FSM) - if ( r_cc_receive_dcache_req.read() ) + if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) { r_dcache_fsm = DCACHE_CC_CHECK; @@ -3816,5 +3817,5 @@ // coherence request (from CC_RECEIVE FSM) - if ( r_cc_receive_dcache_req.read() ) + if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) { r_dcache_fsm = DCACHE_CC_CHECK; @@ -3846,5 +3847,5 @@ // coherence request (from CC_RECEIVE FSM) - if ( r_cc_receive_dcache_req.read() ) + if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) { r_dcache_fsm = DCACHE_CC_CHECK; @@ -3889,5 +3890,5 @@ // coherence request (from CC_RECEIVE FSM) - if ( r_cc_receive_dcache_req.read() ) + if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) { r_dcache_fsm = DCACHE_CC_CHECK; @@ -3980,4 +3981,5 @@ size_t set; size_t word; + r_dcache.read_neutral(r_dcache_xtn_flush_addr_data.read(), &rdata, @@ -3999,4 +4001,10 @@ } } +// else if ( r_dcache_clack_req.read() ) +// { +// r_dcache_fsm = DCACHE_CC_CHECK; +// r_dcache_fsm_cc_save = r_dcache_fsm.read(); +// break; +// } break; } @@ -4311,5 +4319,5 @@ // coherence request (from CC_RECEIVE FSM) - if ( r_cc_receive_dcache_req.read() ) + if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) { r_dcache_fsm = DCACHE_CC_CHECK; @@ -4318,6 +4326,4 @@ } - if ( not r_dcache_cc_send_req.read() ) // blocked until previous cc_send request is sent - { bool found = false; bool cleanup = false; @@ -4326,4 +4332,6 @@ paddr_t victim = 0; int state; + bool s_cleanup_updt_data = false; + bool s_cleanup_line_ncc = false; #ifdef INSTRUMENTATION @@ -4347,18 +4355,13 @@ r_dcache_miss_clack = true; r_dcache_fsm = DCACHE_MISS_CLEAN; - // request cleanup - r_dcache_cc_send_req = true; - r_dcache_cc_send_nline = victim; - r_dcache_cc_send_way = way; - r_dcache_cc_send_type = CC_TYPE_CLEANUP; if( (state == CACHE_SLOT_STATE_VALID_NCC) )//and (r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_DATA_DIRTY) ) { //MODIFIER POUR DIRTY BIT // - r_dcache_cc_cleanup_line_ncc = true; + s_cleanup_line_ncc = true; r_dcache_miss_data_addr = (victim*m_dcache_words)*4; //if ((r_dcache_content_state[way*m_dcache_sets+set] != LINE_CACHE_DATA_NOT_DIRTY))//must send data if (true)//must send data { - r_dcache_cc_cleanup_updt_data = true; + s_cleanup_updt_data = true; for (size_t w = 0; w< m_dcache_words; w++) { @@ -4369,5 +4372,5 @@ else { - r_dcache_cc_cleanup_updt_data = false; + s_cleanup_updt_data = false; } @@ -4378,6 +4381,28 @@ else { - r_dcache_cc_cleanup_line_ncc = false; - r_dcache_cc_cleanup_updt_data = false; + s_cleanup_line_ncc = false; + s_cleanup_updt_data = false; + } + + if( not r_dcache_cc_send_req.read() ) + { + // request cleanup + r_dcache_cc_send_req = true; + r_dcache_cc_send_nline = victim; + r_dcache_cc_send_way = way; + r_dcache_cc_send_type = CC_TYPE_CLEANUP; + r_dcache_cc_cleanup_updt_data = s_cleanup_updt_data; + r_dcache_cc_cleanup_line_ncc = s_cleanup_line_ncc; + } + else + { + r_dcache_cleanup_victim_nline = victim; + r_dcache_cleanup_victim_req = true; + r_dcache_cleanup_victim_updt_data = s_cleanup_updt_data; + r_dcache_cleanup_victim_line_ncc = s_cleanup_line_ncc; + std::cout << " CC_TYPE_CLACK Switch slot to EMPTY state" + << " set = " << r_dcache_clack_set.read() + << " / way = " << r_dcache_clack_way.read() << std::endl; +} +#endif + break; + } @@ -5086,49 +5188,6 @@ } - // CLACK handler - // We switch the directory slot to EMPTY state and reset - // r_dcache_miss_clack if the cleanup ack is matching a pending miss. - if ( r_dcache_clack_req.read() ) - { - if ( m_dreq.valid ) m_cost_data_miss_frz++; - -#ifdef INSTRUMENTATION -m_cpt_dcache_dir_write++; -#endif - r_dcache.write_dir( 0, - r_dcache_clack_way.read(), - r_dcache_clack_set.read(), - CACHE_SLOT_STATE_EMPTY); - - if ( (r_dcache_miss_set.read() == r_dcache_clack_set.read()) and - (r_dcache_miss_way.read() == r_dcache_clack_way.read()) ) - { - r_dcache_miss_clack = false; - } - - r_dcache_clack_req = false; - - // return to cc_save state if no pending CC request - if ( not r_cc_receive_dcache_req.read() ) - { - r_dcache_fsm = r_dcache_fsm_cc_save.read() ; - } - -#if DEBUG_DCACHE -if ( m_debug_activated ) -{ - std::cout << " CC_TYPE_CLACK Switch slot to EMPTY state" - << " set = " << r_dcache_clack_set.read() - << " / way = " << r_dcache_clack_way.read() << std::endl; -} -#endif - break; - } - - // wait if pending request to CC_SEND. This way if there are pending - // CLACK they can be treated in this state and then a deadlock - // situation is avoided - if ( r_dcache_cc_send_req.read() ) break; + + assert ( not r_dcache_cc_send_req.read() and "CC_SEND must be available in DCACHE_CC_CHECK" ); // CC request handler @@ -5943,4 +6002,11 @@ if (p_vci.rspval.read()) { + /**/ + if( p_vci.reop.read() ==0) + { + std::cout << "PROC " << m_srcid + << "/ CYCLE " << m_cpt_total_cycles + < #include "arithmetics.h" - -// !!! -// The L1_MULTI_CACHE mechanism does no longer work with the new pktid encoding -// of TSAR. Turning the define below to a non null value will cause the memcache -// to behave in an unpredicted way. -// TODO Either remove the mechanism from the mem cache or update its behaviour. - -#define L1_MULTI_CACHE 0 //#define RANDOM_EVICTION @@ -46,38 +38,25 @@ bool inst; // Is the owner an ICache ? size_t srcid; // The SRCID of the owner -#if L1_MULTI_CACHE - size_t cache_id; // In multi_cache configuration -#endif //////////////////////// // Constructors //////////////////////// - Owner(bool i_inst - ,size_t i_srcid -#if L1_MULTI_CACHE - ,size_t i_cache_id -#endif - ){ + Owner(bool i_inst, + size_t i_srcid) + { inst = i_inst; srcid = i_srcid; -#if L1_MULTI_CACHE - cache_id= i_cache_id; -#endif - } - - Owner(const Owner &a){ + } + + Owner(const Owner &a) + { inst = a.inst; srcid = a.srcid; -#if L1_MULTI_CACHE - cache_id= a.cache_id; -#endif - } - - Owner(){ + } + + Owner() + { inst = false; srcid = 0; -#if L1_MULTI_CACHE - cache_id= 0; -#endif } // end constructors @@ -116,7 +95,4 @@ owner.inst = 0; owner.srcid = 0; -#if L1_MULTI_CACHE - owner.cache_id= 0; -#endif ptr = 0; } @@ -177,7 +153,4 @@ << " ; Count = " << count << " ; Owner = " << owner.srcid -#if L1_MULTI_CACHE - << "." << owner.cache_id -#endif << " " << owner.inst << " ; Pointer = " << ptr << std::endl; @@ -328,5 +301,7 @@ // - entry : the entry value ///////////////////////////////////////////////////////////////////// - void write(const size_t &set, const size_t &way, const DirectoryEntry &entry) + void write( const size_t &set, + const size_t &way, + const DirectoryEntry &entry) { assert( (set> 1) ^ ((-(lfsr & 1)) & 0xd0000001); - way = lfsr % m_ways; - return DirectoryEntry(m_dir_tab[set][way]); + lfsr = (lfsr >> 1) ^ ((-(lfsr & 1)) & 0xd0000001); + way = lfsr % m_ways; + return DirectoryEntry(m_dir_tab[set][way]); #endif - for(size_t i=0; i * cache_line) - { - assert((set < m_sets ) && "Cache data error: Trying to read a wrong set" ); - assert((way < m_ways ) && "Cache data error: Trying to read a wrong way" ); - - for (uint32_t word=0; word * cache_line) + { + assert((set < m_sets ) && "Cache data error: Trying to read a wrong set" ); + assert((way < m_ways ) && "Cache data error: Trying to read a wrong way" ); + + for (uint32_t word=0; word* m_debug_previous_data; - sc_signal* m_debug_data; - - bool m_monitor_ok; - addr_t m_monitor_base; - addr_t m_monitor_length; + data_t * m_debug_previous_data; + data_t * m_debug_data; // instrumentation counters @@ -644,10 +644,4 @@ uint32_t m_broadcast_boundaries; - ////////////////////////////////////////////////// - // Registers controlled by the TGT_CMD fsm - ////////////////////////////////////////////////// - - sc_signal r_tgt_cmd_fsm; - // Fifo between TGT_CMD fsm and READ fsm GenericFifo m_cmd_read_addr_fifo; @@ -693,25 +687,41 @@ sc_signal r_tgt_cmd_config_cmd; + ////////////////////////////////////////////////// + // Registers controlled by the TGT_CMD fsm + ////////////////////////////////////////////////// + + sc_signal r_tgt_cmd_fsm; + sc_signal r_tgt_cmd_srcid; // srcid for response to config + sc_signal r_tgt_cmd_trdid; // trdid for response to config + sc_signal r_tgt_cmd_pktid; // pktid for response to config + /////////////////////////////////////////////////////// // Registers controlled by the CONFIG fsm /////////////////////////////////////////////////////// - sc_signal r_config_fsm; // FSM state - sc_signal r_config_lock; // lock protecting exclusive access - sc_signal r_config_cmd; // config request status - sc_signal r_config_address; // target buffer physical address - sc_signal r_config_srcid; // config request srcid - sc_signal r_config_trdid; // config request trdid - sc_signal r_config_pktid; // config request pktid - sc_signal r_config_nlines; // number of lines covering the buffer - sc_signal r_config_dir_way; // DIR: selected way - sc_signal r_config_dir_count; // DIR: number of copies - sc_signal r_config_dir_is_cnt; // DIR: counter mode (broadcast required) - sc_signal r_config_dir_copy_srcid; // DIR: first copy SRCID - sc_signal r_config_dir_copy_inst; // DIR: first copy L1 type - sc_signal r_config_dir_next_ptr; // DIR: index of next copy in HEAP - sc_signal r_config_heap_next; // current pointer to scan HEAP - - sc_signal r_config_ivt_index; // IVT index + sc_signal r_config_fsm; // FSM state + sc_signal r_config_lock; // lock protecting exclusive access + sc_signal r_config_cmd; // config request type + sc_signal r_config_address; // target buffer physical address + sc_signal r_config_srcid; // config request srcid + sc_signal r_config_trdid; // config request trdid + sc_signal r_config_pktid; // config request pktid + sc_signal r_config_cmd_lines; // number of lines to be handled + sc_signal r_config_rsp_lines; // number of lines not completed + sc_signal r_config_dir_way; // DIR: selected way + sc_signal r_config_dir_lock; // DIR: locked entry + sc_signal r_config_dir_count; // DIR: number of copies + sc_signal r_config_dir_is_cnt; // DIR: counter mode (broadcast) + sc_signal r_config_dir_copy_srcid; // DIR: first copy SRCID + sc_signal r_config_dir_copy_inst; // DIR: first copy L1 type + sc_signal r_config_dir_ptr; // DIR: index of next copy in HEAP + sc_signal r_config_heap_next; // current pointer to scan HEAP + sc_signal r_config_trt_index; // selected entry in TRT + sc_signal r_config_ivt_index; // selected entry in IVT + + // Buffer between CONFIG fsm and IXR_CMD fsm + sc_signal r_config_to_ixr_cmd_req; // valid request + sc_signal r_config_to_ixr_cmd_index; // TRT index + // Buffer between CONFIG fsm and TGT_RSP fsm (send a done response to L1 cache) @@ -730,43 +740,38 @@ GenericFifo m_config_to_cc_send_srcid_fifo; // fifo for owners srcid -#if L1_MULTI_CACHE - GenericFifo m_config_to_cc_send_cache_id_fifo; // fifo for cache_id -#endif - /////////////////////////////////////////////////////// // Registers controlled by the READ fsm /////////////////////////////////////////////////////// - sc_signal r_read_fsm; // FSM state - sc_signal r_read_copy; // Srcid of the first copy - sc_signal r_read_copy_cache; // Srcid of the first copy - sc_signal r_read_copy_inst; // Type of the first copy - sc_signal r_read_tag; // cache line tag (in directory) - sc_signal r_read_is_cnt; // is_cnt bit (in directory) - sc_signal r_read_lock; // lock bit (in directory) - sc_signal r_read_dirty; // dirty bit (in directory) - sc_signal r_read_count; // number of copies - sc_signal r_read_ptr; // pointer to the heap - sc_signal * r_read_data; // data (one cache line) - sc_signal r_read_way; // associative way (in cache) - sc_signal r_read_trt_index; // Transaction Table index - sc_signal r_read_next_ptr; // Next entry to point to - sc_signal r_read_last_free; // Last free entry - sc_signal r_read_ll_key; // LL key from the llsc_global_table - - // Buffer between READ fsm and IXR_CMD fsm (ask a missing cache line to XRAM) - sc_signal r_read_to_ixr_cmd_req; // valid request - sc_signal r_read_to_ixr_cmd_nline; // cache line index - sc_signal r_read_to_ixr_cmd_trdid; // index in Transaction Table + sc_signal r_read_fsm; // FSM state + sc_signal r_read_copy; // Srcid of the first copy + sc_signal r_read_copy_cache; // Srcid of the first copy + sc_signal r_read_copy_inst; // Type of the first copy + sc_signal r_read_tag; // cache line tag (in directory) + sc_signal r_read_is_cnt; // is_cnt bit (in directory) + sc_signal r_read_lock; // lock bit (in directory) + sc_signal r_read_dirty; // dirty bit (in directory) + sc_signal r_read_count; // number of copies + sc_signal r_read_ptr; // pointer to the heap + sc_signal * r_read_data; // data (one cache line) + sc_signal r_read_way; // associative way (in cache) + sc_signal r_read_trt_index; // Transaction Table index + sc_signal r_read_next_ptr; // Next entry to point to + sc_signal r_read_last_free; // Last free entry + sc_signal r_read_ll_key; // LL key from llsc_global_table + + // Buffer between READ fsm and IXR_CMD fsm + sc_signal r_read_to_ixr_cmd_req; // valid request + sc_signal r_read_to_ixr_cmd_index; // TRT index // Buffer between READ fsm and TGT_RSP fsm (send a hit read response to L1 cache) - sc_signal r_read_to_tgt_rsp_req; // valid request - sc_signal r_read_to_tgt_rsp_srcid; // Transaction srcid - sc_signal r_read_to_tgt_rsp_trdid; // Transaction trdid - sc_signal r_read_to_tgt_rsp_pktid; // Transaction pktid - sc_signal * r_read_to_tgt_rsp_data; // data (one cache line) - sc_signal r_read_to_tgt_rsp_word; // first word of the response - sc_signal r_read_to_tgt_rsp_length; // length of the response - sc_signal r_read_to_tgt_rsp_ll_key; // LL key from the llsc_global_table + sc_signal r_read_to_tgt_rsp_req; // valid request + sc_signal r_read_to_tgt_rsp_srcid; // Transaction srcid + sc_signal r_read_to_tgt_rsp_trdid; // Transaction trdid + sc_signal r_read_to_tgt_rsp_pktid; // Transaction pktid + sc_signal * r_read_to_tgt_rsp_data; // data (one cache line) + sc_signal r_read_to_tgt_rsp_word; // first word of the response + sc_signal r_read_to_tgt_rsp_length; // length of the response + sc_signal r_read_to_tgt_rsp_ll_key; // LL key from llsc_global_table //RWT: Buffer between READ fsm and CC_SEND fsm (send inval) @@ -795,29 +800,29 @@ /////////////////////////////////////////////////////////////// - sc_signal r_write_fsm; // FSM state - sc_signal r_write_address; // first word address - sc_signal r_write_word_index; // first word index in line - sc_signal r_write_word_count; // number of words in line - sc_signal r_write_srcid; // transaction srcid - sc_signal r_write_trdid; // transaction trdid - sc_signal r_write_pktid; // transaction pktid - sc_signal * r_write_data; // data (one cache line) - sc_signal * r_write_be; // one byte enable per word - sc_signal r_write_byte; // (BE != 0X0) and (BE != 0xF) - sc_signal r_write_is_cnt; // is_cnt bit (in directory) - sc_signal r_write_lock; // lock bit (in directory) - sc_signal r_write_tag; // cache line tag (in directory) - sc_signal r_write_copy; // first owner of the line - sc_signal r_write_copy_cache; // first owner of the line - sc_signal r_write_copy_inst; // is this owner a ICache ? - sc_signal r_write_count; // number of copies - sc_signal r_write_ptr; // pointer to the heap - sc_signal r_write_next_ptr; // next pointer to the heap - sc_signal r_write_to_dec; // need to decrement update counter - sc_signal r_write_way; // way of the line - sc_signal r_write_trt_index; // index in Transaction Table - sc_signal r_write_upt_index; // index in Update Table - sc_signal r_write_sc_fail; // sc command failed - sc_signal r_write_pending_sc; // sc command pending + sc_signal r_write_fsm; // FSM state + sc_signal r_write_address; // first word address + sc_signal r_write_word_index; // first word index in line + sc_signal r_write_word_count; // number of words in line + sc_signal r_write_srcid; // transaction srcid + sc_signal r_write_trdid; // transaction trdid + sc_signal r_write_pktid; // transaction pktid + sc_signal * r_write_data; // data (one cache line) + sc_signal * r_write_be; // one byte enable per word + sc_signal r_write_byte; // (BE != 0X0) and (BE != 0xF) + sc_signal r_write_is_cnt; // is_cnt bit (in directory) + sc_signal r_write_lock; // lock bit (in directory) + sc_signal r_write_tag; // cache line tag (in directory) + sc_signal r_write_copy; // first owner of the line + sc_signal r_write_copy_cache; // first owner of the line + sc_signal r_write_copy_inst; // is this owner a ICache ? + sc_signal r_write_count; // number of copies + sc_signal r_write_ptr; // pointer to the heap + sc_signal r_write_next_ptr; // next pointer to the heap + sc_signal r_write_to_dec; // need to decrement update counter + sc_signal r_write_way; // way of the line + sc_signal r_write_trt_index; // index in Transaction Table + sc_signal r_write_upt_index; // index in Update Table + sc_signal r_write_sc_fail; // sc command failed + sc_signal r_write_pending_sc; // sc command pending // Buffer between WRITE fsm and TGT_RSP fsm (acknowledge a write command from L1) @@ -828,10 +833,8 @@ sc_signal r_write_to_tgt_rsp_sc_fail; // sc command failed - // Buffer between WRITE fsm and IXR_CMD fsm (ask a missing cache line to XRAM) - sc_signal r_write_to_ixr_cmd_req; // valid request - sc_signal r_write_to_ixr_cmd_write; // write request - sc_signal r_write_to_ixr_cmd_nline; // cache line index - sc_signal * r_write_to_ixr_cmd_data; // cache line data - sc_signal r_write_to_ixr_cmd_trdid; // index in Transaction Table + // Buffer between WRITE fsm and IXR_CMD fsm + sc_signal r_write_to_ixr_cmd_req; // valid request + sc_signal r_write_to_ixr_cmd_put; // request type (GET/PUT) + sc_signal r_write_to_ixr_cmd_index; // TRT index // Buffer between WRITE fsm and CC_SEND fsm (Update/Invalidate L1 caches) @@ -847,8 +850,4 @@ GenericFifo m_write_to_cc_send_srcid_fifo; // fifo for srcids -#if L1_MULTI_CACHE - GenericFifo m_write_to_cc_send_cache_id_fifo; // fifo for srcids -#endif - // Buffer between WRITE fsm and MULTI_ACK fsm (Decrement UPT entry) sc_signal r_write_to_multi_ack_req; // valid request @@ -878,7 +877,4 @@ sc_signal r_multi_ack_nline; // pending write nline - // signaling completion of multi-inval to CONFIG fsm - sc_signal r_multi_ack_to_config_ack; - // Buffer between MULTI_ACK fsm and TGT_RSP fsm (complete write/update transaction) sc_signal r_multi_ack_to_tgt_rsp_req; // valid request @@ -897,7 +893,4 @@ sc_signal r_cleanup_nline; // cache line index -#if L1_MULTI_CACHE - sc_signal r_cleanup_pktid; // transaction pktid -#endif sc_signal r_cleanup_copy; // first copy @@ -926,7 +919,4 @@ sc_signal r_cleanup_index; // index of the INVAL line (in the UPT) - // signaling completion of broadcast-inval to CONFIG fsm - sc_signal r_cleanup_to_config_ack; - // Buffer between CLEANUP fsm and TGT_RSP fsm (acknowledge a write command from L1) sc_signal r_cleanup_to_tgt_rsp_req; // valid request @@ -950,23 +940,23 @@ /////////////////////////////////////////////////////// - sc_signal r_cas_fsm; // FSM state - sc_signal r_cas_wdata; // write data word - sc_signal * r_cas_rdata; // read data word - sc_signal r_cas_lfsr; // lfsr for random introducing - sc_signal r_cas_cpt; // size of command - sc_signal r_cas_copy; // Srcid of the first copy - sc_signal r_cas_copy_cache; // Srcid of the first copy - sc_signal r_cas_copy_inst; // Type of the first copy - sc_signal r_cas_count; // number of copies - sc_signal r_cas_ptr; // pointer to the heap - sc_signal r_cas_next_ptr; // next pointer to the heap - sc_signal r_cas_is_cnt; // is_cnt bit (in directory) - sc_signal r_cas_dirty; // dirty bit (in directory) - sc_signal r_cas_way; // way in directory - sc_signal r_cas_set; // set in directory - sc_signal r_cas_tag; // cache line tag (in directory) - sc_signal r_cas_trt_index; // Transaction Table index - sc_signal r_cas_upt_index; // Update Table index - sc_signal * r_cas_data; // cache line data + sc_signal r_cas_fsm; // FSM state + sc_signal r_cas_wdata; // write data word + sc_signal * r_cas_rdata; // read data word + sc_signal r_cas_lfsr; // lfsr for random introducing + sc_signal r_cas_cpt; // size of command + sc_signal r_cas_copy; // Srcid of the first copy + sc_signal r_cas_copy_cache; // Srcid of the first copy + sc_signal r_cas_copy_inst; // Type of the first copy + sc_signal r_cas_count; // number of copies + sc_signal r_cas_ptr; // pointer to the heap + sc_signal r_cas_next_ptr; // next pointer to the heap + sc_signal r_cas_is_cnt; // is_cnt bit (in directory) + sc_signal r_cas_dirty; // dirty bit (in directory) + sc_signal r_cas_way; // way in directory + sc_signal r_cas_set; // set in directory + sc_signal r_cas_tag; // cache line tag (in directory) + sc_signal r_cas_trt_index; // Transaction Table index + sc_signal r_cas_upt_index; // Update Table index + sc_signal * r_cas_data; // cache line data sc_signal r_cas_coherent; @@ -974,9 +964,6 @@ // Buffer between CAS fsm and IXR_CMD fsm (XRAM write) sc_signal r_cas_to_ixr_cmd_req; // valid request - sc_signal r_cas_to_ixr_cmd_nline; // cache line index - sc_signal r_cas_to_ixr_cmd_trdid; // index in Transaction Table - sc_signal r_cas_to_ixr_cmd_write; // write request - sc_signal * r_cas_to_ixr_cmd_data; // cache line data - + sc_signal r_cas_to_ixr_cmd_put; // request type (GET/PUT) + sc_signal r_cas_to_ixr_cmd_index; // TRT index // Buffer between CAS fsm and TGT_RSP fsm @@ -999,18 +986,17 @@ GenericFifo m_cas_to_cc_send_srcid_fifo; // fifo for srcids -#if L1_MULTI_CACHE - GenericFifo m_cas_to_cc_send_cache_id_fifo; // fifo for srcids -#endif - //////////////////////////////////////////////////// // Registers controlled by the IXR_RSP fsm //////////////////////////////////////////////////// - sc_signal r_ixr_rsp_fsm; // FSM state - sc_signal r_ixr_rsp_trt_index; // TRT entry index - sc_signal r_ixr_rsp_cpt; // word counter + sc_signal r_ixr_rsp_fsm; // FSM state + sc_signal r_ixr_rsp_trt_index; // TRT entry index + sc_signal r_ixr_rsp_cpt; // word counter + + // Buffer between IXR_RSP fsm and CONFIG fsm (response from the XRAM) + sc_signal r_ixr_rsp_to_config_ack; // one single bit // Buffer between IXR_RSP fsm and XRAM_RSP fsm (response from the XRAM) - sc_signal * r_ixr_rsp_to_xram_rsp_rok; // A xram response is ready + sc_signal * r_ixr_rsp_to_xram_rsp_rok; // one bit per TRT entry //////////////////////////////////////////////////// @@ -1055,13 +1041,7 @@ GenericFifo m_xram_rsp_to_cc_send_srcid_fifo; // fifo for srcids -#if L1_MULTI_CACHE - GenericFifo m_xram_rsp_to_cc_send_cache_id_fifo; // fifo for srcids -#endif - - // Buffer between XRAM_RSP fsm and IXR_CMD fsm (XRAM write) + // Buffer between XRAM_RSP fsm and IXR_CMD fsm sc_signal r_xram_rsp_to_ixr_cmd_req; // Valid request - sc_signal r_xram_rsp_to_ixr_cmd_nline; // cache line index - sc_signal * r_xram_rsp_to_ixr_cmd_data; // cache line data - sc_signal r_xram_rsp_to_ixr_cmd_trdid; // index in transaction table + sc_signal r_xram_rsp_to_ixr_cmd_index; // TRT index //RWT @@ -1073,5 +1053,9 @@ sc_signal r_ixr_cmd_fsm; - sc_signal r_ixr_cmd_cpt; + sc_signal r_ixr_cmd_word; // word index for a put + sc_signal r_ixr_cmd_trdid; // TRT index value + sc_signal r_ixr_cmd_address; // address to XRAM + sc_signal * r_ixr_cmd_wdata; // cache line buffer + sc_signal r_ixr_cmd_get; // transaction type (PUT/GET) //////////////////////////////////////////////////// @@ -1149,5 +1133,5 @@ sc_signal *r_cleanup_to_ixr_cmd_data; sc_signal r_cleanup_to_ixr_cmd_srcid; - sc_signal r_cleanup_to_ixr_cmd_trdid; + sc_signal r_cleanup_to_ixr_cmd_index; sc_signal r_cleanup_to_ixr_cmd_pktid; sc_signal r_cleanup_to_ixr_cmd_nline; Index: branches/RWT/modules/vci_mem_cache/caba/source/include/xram_transaction.h =================================================================== --- branches/RWT/modules/vci_mem_cache/caba/source/include/xram_transaction.h (revision 477) +++ branches/RWT/modules/vci_mem_cache/caba/source/include/xram_transaction.h (revision 495) @@ -34,4 +34,5 @@ bool rerror; // error returned by xram data_t ll_key; // LL key returned by the llsc_global_table + bool config; // transaction required by CONFIG FSM ///////////////////////////////////////////////////////////////////// @@ -42,4 +43,5 @@ valid = false; rerror = false; + config = false; } @@ -80,4 +82,5 @@ rerror = source.rerror; ll_key = source.ll_key; + config = source.config; } @@ -87,4 +90,5 @@ void print() { + std::cout << "------- TRT entry -------" << std::endl; std::cout << "valid = " << valid << std::endl; std::cout << "xram_read = " << xram_read << std::endl; @@ -96,12 +100,18 @@ std::cout << "read_length = " << read_length << std::endl; std::cout << "word_index = " << word_index << std::endl; - for(size_t i=0; i &data) { - assert( (index < size_tab) - && "Invalid Transaction Tab Entry"); - assert(be.size()==tab[index].wdata_be.size() - && "Bad data mask in write_data_mask in TransactionTab"); - assert(data.size()==tab[index].wdata.size() - && "Bad data in write_data_mask in TransactionTab"); - - for(size_t i=0; i &data_be, const std::vector &data, - const data_t ll_key = 0) - { - assert( (index < size_tab) - && "The selected entry is out of range in set() Transaction Tab"); - assert(data_be.size()==tab[index].wdata_be.size() - && "Bad data_be argument in set() TransactionTab"); - assert(data.size()==tab[index].wdata.size() - && "Bad data argument in set() TransactionTab"); + const data_t ll_key = 0, + const bool config = false) + { + assert( (index < size_tab) and + "MEMC ERROR: The selected entry is out of range in TRT set()"); + + assert( (data_be.size()==tab[index].wdata_be.size()) and + "MEMC ERROR: Bad data_be argument in TRT set()"); + + assert( (data.size()==tab[index].wdata.size()) and + "MEMC ERROR: Bad data argument in TRT set()"); tab[index].valid = true; @@ -386,4 +407,5 @@ tab[index].word_index = word_index; tab[index].ll_key = ll_key; + tab[index].config = config; for(size_t i=0; i= size_tab ) - { - std::cout << "VCI_MEM_CACHE ERRROR " << tab_name - << " TRT entry out of range in write_rsp()" << std::endl; - exit(0); - } - if ( word > tab[index].wdata_be.size() ) - { - std::cout << "VCI_MEM_CACHE ERRROR " << tab_name - << " Bad word_index in write_rsp() in TRT" << std::endl; - exit(0); - } - if ( not tab[index].valid ) - { - std::cout << "VCI_MEM_CACHE ERRROR " << tab_name - << " TRT Entry invalid in write_rsp()" << std::endl; - exit(0); - } - if ( not tab[index].xram_read ) - { - std::cout << "VCI_MEM_CACHE ERRROR " << tab_name - << " TRT entry is not an XRAM GET in write_rsp()" << std::endl; - exit(0); - } + assert( (index < size_tab) and + "MEMC ERROR: The selected entry is out of range in TRT write_rsp()"); + + assert( (word < tab[index].wdata_be.size()) and + "MEMC ERROR: Bad word index in TRT write_rsp()"); + + assert( (tab[index].valid) and + "MEMC ERROR: TRT entry not valid in TRT write_rsp()"); + + assert( (tab[index].xram_read ) and + "MEMC ERROR: TRT entry is not a GET in TRT write_rsp()"); // first 32 bits word @@ -445,9 +452,5 @@ mask = be_to_mask(tab[index].wdata_be[word+1]); tab[index].wdata[word+1] = (tab[index].wdata[word+1] & mask) | (value & ~mask); - - // error update - tab[index].rerror |= rerror; - } - + } ///////////////////////////////////////////////////////////////////// // The erase() function erases an entry in the transaction tab. @@ -457,8 +460,21 @@ void erase(const size_t index) { - assert( (index < size_tab) - && "The selected entry is out of range in erase() Transaction Tab"); + assert( (index < size_tab) and + "MEMC ERROR: The selected entry is out of range in TRT erase()"); + tab[index].valid = false; tab[index].rerror = false; + } + ///////////////////////////////////////////////////////////////////// + // The is_config() function returns the config flag value. + // Arguments : + // - index : the index of the entry in the transaction tab + ///////////////////////////////////////////////////////////////////// + bool is_config(const size_t index) + { + assert( (index < size_tab) and + "MEMC ERROR: The selected entry is out of range in TRT is_config()"); + + return tab[index].config; } }; // end class TransactionTab Index: branches/RWT/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp =================================================================== --- branches/RWT/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp (revision 477) +++ branches/RWT/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp (revision 495) @@ -45,5 +45,5 @@ #define DEBUG_MEMC_WRITE 1 // detailed trace of WRITE FSM #define DEBUG_MEMC_CAS 1 // detailed trace of CAS FSM -#define DEBUG_MEMC_IXR_CMD 1 // detailed trace of IXR_RSP FSM +#define DEBUG_MEMC_IXR_CMD 1 // detailed trace of IXR_CMD FSM #define DEBUG_MEMC_IXR_RSP 1 // detailed trace of IXR_RSP FSM #define DEBUG_MEMC_XRAM_RSP 1 // detailed trace of XRAM_RSP FSM @@ -129,5 +129,4 @@ "MULTI_ACK_UPT_CLEAR", "MULTI_ACK_WRITE_RSP", - "MULTI_ACK_CONFIG_ACK" }; const char *config_fsm_str[] = @@ -135,15 +134,17 @@ "CONFIG_IDLE", "CONFIG_LOOP", + "CONFIG_WAIT" "CONFIG_RSP", "CONFIG_DIR_REQ", "CONFIG_DIR_ACCESS", - "CONFIG_DIR_IVT_LOCK", + "CONFIG_IVT_LOCK", "CONFIG_BC_SEND", - "CONFIG_BC_WAIT", - "CONFIG_INV_SEND", + "CONFIG_INVAL_SEND" "CONFIG_HEAP_REQ", "CONFIG_HEAP_SCAN", "CONFIG_HEAP_LAST", - "CONFIG_INV_WAIT" + "CONFIG_TRT_LOCK", + "CONFIG_TRT_SET", + "CONFIG_PUT_REQ" }; const char *read_fsm_str[] = @@ -172,5 +173,4 @@ "WRITE_DIR_LOCK", "WRITE_IVT_LOCK_HIT_WB", - "WRITE_DIR_READ", "WRITE_DIR_HIT", "WRITE_UPT_LOCK", @@ -185,4 +185,5 @@ "WRITE_MISS_TRT_SET", "WRITE_MISS_XRAM_REQ", + "WRITE_BC_DIR_READ", "WRITE_BC_TRT_LOCK", "WRITE_BC_IVT_LOCK", @@ -207,5 +208,5 @@ "XRAM_RSP_DIR_UPDT", "XRAM_RSP_DIR_RSP", - "XRAM_RSP_INVAL_LOCK", + "XRAM_RSP_IVT_LOCK", "XRAM_RSP_INVAL_WAIT", "XRAM_RSP_INVAL", @@ -224,9 +225,17 @@ "IXR_CMD_XRAM_IDLE", "IXR_CMD_CLEANUP_IDLE", - "IXR_CMD_READ", - "IXR_CMD_WRITE", - "IXR_CMD_CAS", - "IXR_CMD_XRAM", - "IXR_CMD_CLEANUP_DATA" + "IXR_CMD_CONFIG_IDLE", + "IXR_CMD_READ_TRT", + "IXR_CMD_WRITE_TRT", + "IXR_CMD_CAS_TRT", + "IXR_CMD_XRAM_TRT", + "IXR_CMD_CLEANUP_TRT", + "IXR_CMD_CONFIG_TRT", + "IXR_CMD_READ_SEND", + "IXR_CMD_WRITE_SEND", + "IXR_CMD_CAS_SEND", + "IXR_CMD_XRAM_SEND", + "IXR_CMD_CLEANUP_DATA_SEND", + "IXR_CMD_CONFIG_SEND" }; const char *cas_fsm_str[] = @@ -276,5 +285,4 @@ "CLEANUP_IXR_REQ", "CLEANUP_WAIT", - "CLEANUP_CONFIG_ACK", "CLEANUP_SEND_CLACK" }; @@ -297,4 +305,6 @@ "ALLOC_TRT_IXR_RSP", "ALLOC_TRT_CLEANUP" + "ALLOC_TRT_IXR_CMD", + "ALLOC_TRT_CONFIG" }; const char *alloc_upt_fsm_str[] = @@ -357,5 +367,4 @@ : soclib::caba::BaseModule(name), - m_monitor_ok(false), p_clk( "p_clk" ), p_resetn( "p_resetn" ), @@ -437,7 +446,4 @@ m_write_to_cc_send_inst_fifo("m_write_to_cc_send_inst_fifo",8), m_write_to_cc_send_srcid_fifo("m_write_to_cc_send_srcid_fifo",8), -#if L1_MULTI_CACHE - m_write_to_cc_send_cache_id_fifo("m_write_to_cc_send_cache_id_fifo",8), -#endif r_multi_ack_fsm("r_multi_ack_fsm"), @@ -449,7 +455,4 @@ m_cas_to_cc_send_inst_fifo("m_cas_to_cc_send_inst_fifo",8), m_cas_to_cc_send_srcid_fifo("m_cas_to_cc_send_srcid_fifo",8), -#if L1_MULTI_CACHE - m_cas_to_cc_send_cache_id_fifo("m_cas_to_cc_send_cache_id_fifo",8), -#endif r_ixr_rsp_fsm("r_ixr_rsp_fsm"), @@ -458,7 +461,4 @@ m_xram_rsp_to_cc_send_inst_fifo("m_xram_rsp_to_cc_send_inst_fifo",8), m_xram_rsp_to_cc_send_srcid_fifo("m_xram_rsp_to_cc_send_srcid_fifo",8), -#if L1_MULTI_CACHE - m_xram_rsp_to_cc_send_cache_id_fifo("m_xram_rsp_to_cc_send_cache_id_fifo",8), -#endif r_ixr_cmd_fsm("r_ixr_cmd_fsm"), @@ -528,5 +528,5 @@ r_xram_rsp_victim_data = new sc_signal[nwords]; r_xram_rsp_to_tgt_rsp_data = new sc_signal[nwords]; - r_xram_rsp_to_ixr_cmd_data = new sc_signal[nwords]; + //r_xram_rsp_to_ixr_cmd_data = new sc_signal[nwords]; // Allocation for READ FSM @@ -539,10 +539,13 @@ r_write_to_cc_send_data = new sc_signal[nwords]; r_write_to_cc_send_be = new sc_signal[nwords]; - r_write_to_ixr_cmd_data = new sc_signal[nwords]; + //r_write_to_ixr_cmd_data = new sc_signal[nwords]; // Allocation for CAS FSM - r_cas_to_ixr_cmd_data = new sc_signal[nwords]; + //r_cas_to_ixr_cmd_data = new sc_signal[nwords]; r_cas_data = new sc_signal[nwords]; r_cas_rdata = new sc_signal[2]; + + // Allocation for IXR_CMD FSM + r_ixr_cmd_wdata = new sc_signal[nwords]; // Allocation for ODCCP @@ -553,6 +556,6 @@ // Allocation for debug - m_debug_previous_data = new sc_signal[nwords]; - m_debug_data = new sc_signal[nwords]; + m_debug_previous_data = new data_t[nwords]; + m_debug_data = new data_t[nwords]; SC_METHOD(transition); @@ -564,37 +567,4 @@ sensitive << p_clk.neg(); } // end constructor - -/////////////////////////////////////////////////////////////////////// -tmpl(void) ::start_monitor(addr_t addr, addr_t length) -/////////////////////////////////////////////////////////////////////// -{ - m_monitor_ok = true; - m_monitor_base = addr; - m_monitor_length = length; -} - -/////////////////////////////////////////////////////////////////////// -tmpl(void) ::stop_monitor() -/////////////////////////////////////////////////////////////////////// -{ - m_monitor_ok = false; -} - -//////////////////////////////////////////////// -tmpl(void) ::check_monitor( addr_t addr, - data_t data, - bool read ) -//////////////////////////////////////////////// -{ - if((addr >= m_monitor_base) and - (addr < m_monitor_base + m_monitor_length)) - { - if ( read ) std::cout << " Monitor MEMC Read "; - else std::cout << " Monitor MEMC Write"; - std::cout << " / Address = " << std::hex << addr - << " / Data = " << data - << " at cycle " << std::dec << m_cpt_cycles << std::endl; - } -} ///////////////////////////////////////////////////// @@ -609,33 +579,53 @@ if ( entry.valid ) - { - m_cache_data.read_line( way, set, m_debug_data ); - - for ( size_t i = 0 ; i m_debug_start_cycle) and m_debug_ok; @@ -1275,5 +1241,5 @@ case TGT_CMD_ERROR: // response error must be sent - // wait if pending TGT_CMD request to TGT_RSP FSM + // wait if pending request if(r_tgt_cmd_to_tgt_rsp_req.read()) break; @@ -1309,4 +1275,5 @@ size_t error; uint32_t rdata = 0; // default value + uint32_t wdata = p_vci_tgt.wdata.read(); if ( (p_vci_tgt.cmd.read() == vci_param_int::CMD_READ) // get lock @@ -1317,7 +1284,15 @@ error = 0; r_config_lock = true; + if ( rdata == 0 ) + { + r_tgt_cmd_srcid = p_vci_tgt.srcid.read(); + r_tgt_cmd_trdid = p_vci_tgt.trdid.read(); + r_tgt_cmd_pktid = p_vci_tgt.pktid.read(); + } + } else if ( (p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE) // release lock - and (cell == MEMC_LOCK) ) + and (cell == MEMC_LOCK) + and (p_vci_tgt.srcid.read() == r_tgt_cmd_srcid.read()) ) { need_rsp = true; @@ -1326,6 +1301,10 @@ } else if ( (p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE) // set addr_lo - and (cell == MEMC_ADDR_LO) ) - { + and (cell == MEMC_ADDR_LO) + and (p_vci_tgt.srcid.read() == r_tgt_cmd_srcid.read()) ) + { + assert( ((wdata % (m_words*vci_param_int::B)) == 0) and + "VCI_MEM_CACHE CONFIG ERROR: The buffer must be aligned on a cache line"); + need_rsp = true; error = 0; @@ -1334,5 +1313,6 @@ } else if ( (p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE) // set addr_hi - and (cell == MEMC_ADDR_HI) ) + and (cell == MEMC_ADDR_HI) + and (p_vci_tgt.srcid.read() == r_tgt_cmd_srcid.read()) ) { need_rsp = true; @@ -1342,14 +1322,17 @@ } else if ( (p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE) // set buf_lines - and (cell == MEMC_BUF_LENGTH) ) + and (cell == MEMC_BUF_LENGTH) + and (p_vci_tgt.srcid.read() == r_tgt_cmd_srcid.read()) ) { need_rsp = true; error = 0; size_t lines = (size_t)(p_vci_tgt.wdata.read()/(m_words<<2)); - if ( r_config_address.read()/(m_words*vci_param_int::B) ) lines++; - r_config_nlines = lines; + if ( r_config_address.read()%(m_words*4) ) lines++; + r_config_cmd_lines = lines; + r_config_rsp_lines = lines; } else if ( (p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE) // set cmd type - and (cell == MEMC_CMD_TYPE) ) + and (cell == MEMC_CMD_TYPE) + and (p_vci_tgt.srcid.read() == r_tgt_cmd_srcid.read()) ) { need_rsp = false; @@ -1386,4 +1369,5 @@ << " address = " << std::hex << p_vci_tgt.address.read() << " / wdata = " << p_vci_tgt.wdata.read() + << " / need_rsp = " << need_rsp << " / error = " << error << std::endl; #endif @@ -1489,7 +1473,6 @@ // MULTI_ACK FSM ///////////////////////////////////////////////////////////////////////// - // This FSM controls the response to the multicast update or multicast - // inval coherence requests sent by the memory cache to the L1 caches and - // update the UPT. + // This FSM controls the response to the multicast update requests sent + // by the memory cache to the L1 caches and update the UPT. // // - The FSM decrements the proper entry in UPT, @@ -1497,9 +1480,7 @@ // - If required, it sends a request to the TGT_RSP FSM to complete // a pending write transaction. - // - If required, it sends an acknowledge to the CONFIG FSM to signal - // completion of a line inval. // // All those multi-ack packets are one flit packet. - // The index in the UPT is defined in the UPDTID field. + // The index in the UPT is defined in the TRDID field. //////////////////////////////////////////////////////////////////////// @@ -1618,5 +1599,4 @@ r_multi_ack_nline = m_upt.nline(r_multi_ack_upt_index.read()); bool need_rsp = m_upt.need_rsp(r_multi_ack_upt_index.read()); - bool need_ack = m_upt.need_ack(r_multi_ack_upt_index.read()); // clear the UPT entry @@ -1624,5 +1604,4 @@ if ( need_rsp ) r_multi_ack_fsm = MULTI_ACK_WRITE_RSP; - else if ( need_ack ) r_multi_ack_fsm = MULTI_ACK_CONFIG_ACK; else r_multi_ack_fsm = MULTI_ACK_IDLE; @@ -1655,20 +1634,4 @@ break; } - ////////////////////////// - case MULTI_ACK_CONFIG_ACK: // Signals multi-inval completion to CONFIG FSM - // Wait if pending request - { - if ( r_multi_ack_to_config_ack.read() ) break; - - r_multi_ack_to_config_ack = true; - r_multi_ack_fsm = MULTI_ACK_IDLE; - -#if DEBUG_MEMC_MULTI_ACK -if(m_debug) -std::cout << " " - << " Signals inval completion to CONFIG FSM" << std::endl; -#endif - break; - } } // end switch r_multi_ack_fsm @@ -1678,29 +1641,46 @@ // The CONFIG FSM handles the VCI configuration requests (INVAL & SYNC). // The target buffer can have any size, and there is one single command for - // all cache lines covered by the target buffer. - // An INVAL or SYNC configuration request is defined by the followinf registers: - // - bool r_config_cmd : INVAL / SYNC / NOP) + // all cache lines covered by the target buffer. + // + // An INVAL or SYNC configuration operation is defined by the following registers: + // - bool r_config_cmd : INVAL / SYNC / NOP + // - uint64_t r_config_address : buffer base address - // - uint32_t r_config_nlines : number of lines covering buffer + // - uint32_t r_config_cmd_lines : number of lines to be handled + // - uint32_t r_config_rsp_lines : number of lines not completed + // // For both INVAL and SYNC commands, the CONFIG FSM contains the loop handling - // all cache lines covered by the target buffer. // + // all cache lines covered by the buffer. The various lines of a given buffer + // can be pipelined: the CONFIG FSM does not wait the response for line (n) to send + // the command for line (n+1). It decrements the r_config_cmd_lines counter until + // the last request has been registered in TRT (for a SYNC), or in IVT (for an INVAL). + // // - INVAL request: - // For each line, it access to the DIR array. + // For each line, it access to the DIR. // In case of miss, it does nothing, and a response is requested to TGT_RSP FSM. // In case of hit, with no copies in L1 caches, the line is invalidated and // a response is requested to TGT_RSP FSM. // If there is copies, a multi-inval, or a broadcast-inval coherence transaction - // is launched and registered in UPT. The multi-inval transaction is signaled - // by the r_multi_ack_to config_ack or r_cleanup_to_config_ack flip-flops. - // The config inval response is sent only when the last line has been invalidated. // + // is launched and registered in UPT. The multi-inval transaction completion + // is signaled by the CLEANUP FSM by decrementing the r_config_rsp_lines counter. + // The CONFIG INVAL response is sent only when the last line has been invalidated. + // TODO : The target buffer address must be aligned on a cache line boundary. + // This constraint can be released, but it requires to make 2 PUT transactions + // for the first and the last line... + // // - SYNC request: - // - // ... Not implemented yet ... + // For each line, it access to the DIR. + // In case of miss, it does nothing, and a response is requested to TGT_RSP FSM. + // In case of hit, a PUT transaction is registered in TRT and a request is sent + // to IXR_CMD FSM. The IXR_RSP FSM decrements the r_config_rsp_lines counter + // when a PUT response is received. + // The CONFIG SYNC response is sent only when the last PUT response is received. // // From the software point of view, a configuration request is a sequence - // of 6 atomic accesses in an uncached segment: + // of 6 atomic accesses in an uncached segment. A dedicated lock is used + // to handle only one configuration command at a given time: // - Read MEMC_LOCK : Get the lock // - Write MEMC_ADDR_LO : Set the buffer address LSB @@ -1724,5 +1704,5 @@ std::cout << " Config Request received" << " address = " << std::hex << r_config_address.read() - << " / nlines = " << std::dec << r_config_nlines.read() + << " / nlines = " << std::dec << r_config_cmd_lines.read() << " / type = " << r_config_cmd.read() << std::endl; #endif @@ -1731,10 +1711,10 @@ } ///////////////// - case CONFIG_LOOP: // test last line - { - if ( r_config_nlines.read() == 0 ) + case CONFIG_LOOP: // test last line to be handled + { + if ( r_config_cmd_lines.read() == 0 ) { r_config_cmd = MEMC_CMD_NOP; - r_config_fsm = CONFIG_RSP; + r_config_fsm = CONFIG_WAIT; } else @@ -1747,9 +1727,49 @@ std::cout << " " << " address = " << std::hex << r_config_address.read() - << " / nlines = " << std::dec << r_config_nlines.read() + << " / nlines = " << std::dec << r_config_cmd_lines.read() << " / command = " << r_config_cmd.read() << std::endl; #endif break; } + ///////////////// + case CONFIG_WAIT: // wait completion (last response) + { + if ( r_config_rsp_lines.read() == 0 ) // last response received + { + r_config_fsm = CONFIG_RSP; + } + +#if DEBUG_MEMC_CONFIG +if(m_debug) +std::cout << " " + << " / lines to do = " << std::dec << r_config_rsp_lines.read() << std::endl; +#endif + break; + } + //////////////// + case CONFIG_RSP: // request TGT_RSP FSM to return response + { + if ( not r_config_to_tgt_rsp_req.read() ) + { + r_config_to_tgt_rsp_srcid = r_config_srcid.read(); + r_config_to_tgt_rsp_trdid = r_config_trdid.read(); + r_config_to_tgt_rsp_pktid = r_config_pktid.read(); + r_config_to_tgt_rsp_error = false; + r_config_to_tgt_rsp_req = true; + r_config_fsm = CONFIG_IDLE; + +#if DEBUG_MEMC_CONFIG +if(m_debug) +std::cout << " Request TGT_RSP FSM to return response:" + << " error = " << r_config_to_tgt_rsp_error.read() + << " / rsrcid = " << std::hex << r_config_srcid.read() + << " / rtrdid = " << std::hex << r_config_trdid.read() + << " / rpktid = " << std::hex << r_config_pktid.read() << std::endl; +#endif + } + break; + + } + //////////////////// case CONFIG_DIR_REQ: // Request directory lock @@ -1770,4 +1790,7 @@ case CONFIG_DIR_ACCESS: // Access directory and decode config command { + assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_CONFIG) and + "MEMC ERROR in CONFIG_DIR_ACCESS state: bad DIR allocation"); + size_t way = 0; DirectoryEntry entry = m_cache_directory.read(r_config_address.read(), way); @@ -1781,7 +1804,8 @@ r_config_dir_is_cnt = entry.is_cnt; r_config_dir_count = entry.count; - r_config_dir_next_ptr = entry.ptr; - - r_config_fsm = CONFIG_DIR_IVT_LOCK; + r_config_dir_lock = entry.lock; + r_config_dir_ptr = entry.ptr; + + r_config_fsm = CONFIG_IVT_LOCK; } else if ( entry.valid and // hit & sync command @@ -1789,13 +1813,13 @@ (r_config_cmd.read() == MEMC_CMD_SYNC) ) { - std::cout << "VCI_MEM_CACHE ERROR: " - << "SYNC config request not implemented yet" << std::endl; - exit(0); + r_config_fsm = CONFIG_TRT_LOCK; } else // return to LOOP { - r_config_nlines = r_config_nlines.read() - 1; - r_config_address = r_config_address.read() + (m_words<<2); - r_config_fsm = CONFIG_LOOP; + r_config_cmd_lines = r_config_cmd_lines.read() - 1; + r_config_rsp_lines = r_config_rsp_lines.read() - 1; + r_config_cmd_lines = r_config_cmd_lines.read() - 1; + r_config_address = r_config_address.read() + (m_words<<2); + r_config_fsm = CONFIG_LOOP; } @@ -1811,11 +1835,132 @@ break; } - ///////////////////////// - case CONFIG_DIR_IVT_LOCK: // enter this state in case of INVAL command - // Try to get both DIR & IVT locks, and return - // to LOOP state if IVT full. - // Register inval in IVT, and invalidate the - // directory if IVT not full. - { + ///////////////////// + case CONFIG_TRT_LOCK: // enter this state in case of SYNC command + // to a dirty cache line + // keep DIR lock, and try to get TRT lock + // return to LOOP state if TRT full + // reset dirty bit in DIR and register a PUT + // trabsaction in TRT if not full. + { + assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_CONFIG) and + "MEMC ERROR in CONFIG_TRT_LOCK state: bad DIR allocation"); + + if ( r_alloc_trt_fsm.read() == ALLOC_TRT_CONFIG ) + { + size_t index = 0; + bool wok = not m_trt.full(index); + + if ( not wok ) + { + r_config_fsm = CONFIG_LOOP; + } + else + { + size_t way = r_config_dir_way.read(); + size_t set = m_y[r_config_address.read()]; + + // reset dirty bit in DIR + DirectoryEntry entry; + entry.valid = true; + entry.dirty = false; + entry.tag = m_z[r_config_address.read()]; + entry.is_cnt = r_config_dir_is_cnt.read(); + entry.lock = r_config_dir_lock.read(); + entry.ptr = r_config_dir_ptr.read(); + entry.count = r_config_dir_count.read(); + entry.owner.inst = r_config_dir_copy_inst.read(); + entry.owner.srcid = r_config_dir_copy_srcid.read(); + m_cache_directory.write( set, + way, + entry ); + + r_config_trt_index = index; + r_config_fsm = CONFIG_TRT_SET; + } + +#if DEBUG_MEMC_CONFIG +if(m_debug) +std::cout << " Access TRT: " + << " wok = " << std::dec << wok + << " index = " << index << std::endl; +#endif + } + break; + } + //////////////////// + case CONFIG_TRT_SET: // read data in cache + // and post a PUT request in TRT + { + assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_CONFIG) and + "MEMC ERROR in CONFIG_TRT_SET state: bad DIR allocation"); + + assert( (r_alloc_trt_fsm.read() == ALLOC_TRT_CONFIG) and + "MEMC ERROR in CONFIG_TRT_SET state: bad TRT allocation"); + + // read data into cache + size_t way = r_config_dir_way.read(); + size_t set = m_y[r_config_address.read()]; + + sc_signal config_data[16]; + m_cache_data.read_line( way, + set, + config_data ); + + // post a PUT request in TRT + std::vector data_vector; + data_vector.clear(); + for(size_t i=0; i(m_words,0xF), + data_vector); + +#if DEBUG_MEMC_CONFIG +if(m_debug) + m_trt.print(0); +std::cout << " PUT request in TRT:" + << " address = " << std::hex << r_config_address.read() + << " index = " << std::dec << r_config_trt_index.read() << std::endl; +#endif + break; + } + //////////////////// + case CONFIG_PUT_REQ: // PUT request to IXR_CMD_FSM + { + if ( not r_config_to_ixr_cmd_req.read() ) + { + r_config_to_ixr_cmd_req = true; + r_config_to_ixr_cmd_index = r_config_trt_index.read(); + + // prepare next iteration + r_config_cmd_lines = r_config_cmd_lines.read() - 1; + r_config_address = r_config_address.read() + (m_words<<2); + r_config_fsm = CONFIG_LOOP; + +#if DEBUG_MEMC_CONFIG +if(m_debug) +std::cout << " PUT request to IXR_CMD_FSM" + << " / address = " << std::hex << r_config_address.read() << std::endl; +#endif + } + break; + } + ///////////////////// + case CONFIG_IVT_LOCK: // enter this state in case of INVAL command + // Keep DIR lock and Try to get IVT lock. + // Return to LOOP state if IVT full. + // Register inval in IVT, and invalidate the + // directory if IVT not full. + { + assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_CONFIG) and + "MEMC ERROR in CONFIG_IVT_LOCK state: bad DIR allocation"); + if ( r_alloc_ivt_fsm.read() == ALLOC_IVT_CONFIG ) { @@ -1826,11 +1971,12 @@ { m_cache_directory.inval( way, set ); - r_config_nlines = r_config_nlines.read() - 1; - r_config_address = r_config_address.read() + (m_words<<2); - r_config_fsm = CONFIG_LOOP; - -#if DEBUG_MEMC_CONFIG -if(m_debug) -std::cout << " " + r_config_cmd_lines = r_config_cmd_lines.read() - 1; + r_config_rsp_lines = r_config_rsp_lines.read() - 1; + r_config_address = r_config_address.read() + (m_words<<2); + r_config_fsm = CONFIG_LOOP; + + #if DEBUG_MEMC_CONFIG +if(m_debug) +std::cout << " " << " No copies in L1 : inval DIR entry" << std::endl; #endif @@ -1863,9 +2009,9 @@ r_config_ivt_index = index; if ( broadcast ) r_config_fsm = CONFIG_BC_SEND; - else r_config_fsm = CONFIG_INV_SEND; + else r_config_fsm = CONFIG_INVAL_SEND; #if DEBUG_MEMC_CONFIG if(m_debug) -std::cout << " " +std::cout << " " << " Inval DIR entry and register inval in IVT" << " : index = " << std::dec << index @@ -1879,5 +2025,5 @@ #if DEBUG_MEMC_CONFIG if(m_debug) -std::cout << " " +std::cout << " " << " IVT full : release DIR & IVT locks and retry" << std::endl; #endif @@ -1893,10 +2039,14 @@ not r_config_to_cc_send_brdcast_req.read() ) { + // post bc inval request r_config_to_cc_send_multi_req = false; r_config_to_cc_send_brdcast_req = true; r_config_to_cc_send_trdid = r_config_ivt_index.read(); r_config_to_cc_send_nline = m_nline[(addr_t)(r_config_address.read())]; - r_cleanup_to_config_ack = false; - r_config_fsm = CONFIG_BC_WAIT; + + // prepare next iteration + r_config_cmd_lines = r_config_cmd_lines.read() - 1; + r_config_address = r_config_address.read() + (m_words<<2); + r_config_fsm = CONFIG_LOOP; #if DEBUG_MEMC_CONFIG @@ -1909,24 +2059,6 @@ break; } - //////////////////// - case CONFIG_BC_WAIT: // wait broadcast completion to return to LOOP - { - if ( r_cleanup_to_config_ack.read() ) - { - r_config_fsm = CONFIG_LOOP; - r_config_nlines = r_config_nlines.read() - 1; - r_config_address = r_config_address.read() + (m_words<<2); - } - -#if DEBUG_MEMC_CONFIG -if(m_debug) -std::cout << " Waiting BC completion " - << " done = " << r_cleanup_to_config_ack.read() - << std::endl; -#endif - break; - } - ///////////////////// - case CONFIG_INV_SEND: // Post a multi inval request to CC_SEND FSM + /////////////////////// + case CONFIG_INVAL_SEND: // Post a multi inval request to CC_SEND FSM { if( not r_config_to_cc_send_multi_req.read() and @@ -1937,16 +2069,25 @@ r_config_to_cc_send_trdid = r_config_ivt_index.read(); r_config_to_cc_send_nline = m_nline[(addr_t)(r_config_address.read())]; - r_multi_ack_to_config_ack = false; - + + // post data into FIFO config_to_cc_send_fifo_srcid = r_config_dir_copy_srcid.read(); config_to_cc_send_fifo_inst = r_config_dir_copy_inst.read(); config_to_cc_send_fifo_put = true; - if ( r_config_dir_count.read() == 1 ) r_config_fsm = CONFIG_INV_WAIT; - else r_config_fsm = CONFIG_HEAP_REQ; - + if ( r_config_dir_count.read() == 1 ) // one copy + { + // prepare next iteration + r_config_cmd_lines = r_config_cmd_lines.read() - 1; + r_config_address = r_config_address.read() + (m_words<<2); + r_config_fsm = CONFIG_LOOP; + } + else // several copies + { + r_config_fsm = CONFIG_HEAP_REQ; + } + #if DEBUG_MEMC_CONFIG if(m_debug) -std::cout << " " +std::cout << " " << " Post multi inval request to CC_SEND FSM" << " / address = " << std::hex << r_config_address.read() @@ -1963,5 +2104,5 @@ { r_config_fsm = CONFIG_HEAP_SCAN; - r_config_heap_next = r_config_dir_next_ptr.read(); + r_config_heap_next = r_config_dir_ptr.read(); } @@ -2010,5 +2151,5 @@ if ( m_heap.is_full() ) { - last_entry.next = r_config_dir_next_ptr.read(); + last_entry.next = r_config_dir_ptr.read(); m_heap.unset_full(); } @@ -2018,7 +2159,11 @@ } - m_heap.write_free_ptr( r_config_dir_next_ptr.read() ); + m_heap.write_free_ptr( r_config_dir_ptr.read() ); m_heap.write( r_config_heap_next.read(), last_entry ); - r_config_fsm = CONFIG_INV_WAIT; + + // prepare next iteration + r_config_cmd_lines = r_config_cmd_lines.read() - 1; + r_config_address = r_config_address.read() + (m_words<<2); + r_config_fsm = CONFIG_LOOP; #if DEBUG_MEMC_CONFIG @@ -2028,45 +2173,4 @@ #endif break; - } - ///////////////////// - case CONFIG_INV_WAIT: // wait inval completion to return to LOOP - { - if ( r_multi_ack_to_config_ack.read() ) - { - r_config_fsm = CONFIG_LOOP; - r_config_nlines = r_config_nlines.read() - 1; - r_config_address = r_config_address.read() + (m_words<<2); - } - -#if DEBUG_MEMC_CONFIG -if(m_debug) -std::cout << " Waiting inval completion " - << " done = " << r_multi_ack_to_config_ack.read() - << std::endl; -#endif - break; - } - - //////////////// - case CONFIG_RSP: // request TGT_RSP FSM to return response - { - if ( not r_config_to_tgt_rsp_req.read() ) - { - r_config_to_tgt_rsp_srcid = r_config_srcid.read(); - r_config_to_tgt_rsp_trdid = r_config_trdid.read(); - r_config_to_tgt_rsp_pktid = r_config_pktid.read(); - r_config_to_tgt_rsp_error = false; - r_config_to_tgt_rsp_req = true; - r_config_fsm = CONFIG_IDLE; - -#if DEBUG_MEMC_CONFIG -if(m_debug) -std::cout << " Request TGT_RSP FSM to return response:" - << " error = " << r_config_to_tgt_rsp_error.read() - << " / rsrcid = " << std::hex << r_config_srcid.read() << std::endl; -#endif - } - break; - } } // end switch r_config_fsm @@ -2122,9 +2226,9 @@ case READ_DIR_REQ: // Get the lock to the directory { - if(r_alloc_dir_fsm.read() == ALLOC_DIR_READ) - { - r_read_fsm = READ_DIR_LOCK; - m_cpt_read_fsm_n_dir_lock++; - } + if(r_alloc_dir_fsm.read() == ALLOC_DIR_READ) + { + r_read_fsm = READ_DIR_LOCK; + m_cpt_read_fsm_n_dir_lock++; + } #if DEBUG_MEMC_READ @@ -2141,9 +2245,10 @@ case READ_DIR_LOCK: // check directory for hit / miss { - if(r_alloc_dir_fsm.read() == ALLOC_DIR_READ) - { + assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_READ) and + "MEMC ERROR in READ_DIR_LOCK state: Bad DIR allocation"); + size_t way = 0; DirectoryEntry entry = - m_cache_directory.read(m_cmd_read_addr_fifo.read(), way); + m_cache_directory.read(m_cmd_read_addr_fifo.read(), way); if(((m_cmd_read_pktid_fifo.read() & 0x7) == TYPE_LL) and not r_read_ll_done.read()) // access the global table ONLY when we have an LL cmd { @@ -2164,7 +2269,4 @@ r_read_copy = entry.owner.srcid; -#if L1_MULTI_CACHE - r_read_copy_cache = entry.owner.cache_id; -#endif r_read_copy_inst = entry.owner.inst; r_read_ptr = entry.ptr; // pointer to the heap @@ -2216,11 +2318,4 @@ } #endif - } - else - { - std::cout << "VCI_MEM_CACHE ERROR " << name() << " READ_DIR_LOCK state" - << "Bad DIR allocation" << std::endl; - exit(0); - } break; } @@ -2318,6 +2413,6 @@ { - if(r_alloc_dir_fsm.read() == ALLOC_DIR_READ) - { + assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_READ) and + "MEMC ERROR in READ_DIR_HIT state: Bad DIR allocation"); // check if this is an instruction read, this means pktid is either // TYPE_READ_INS_UNC 0bX010 with TSAR encoding @@ -2335,6 +2430,4 @@ m_cache_data.read_line(way, set, r_read_data); - - if(m_monitor_ok) check_monitor( m_cmd_read_addr_fifo.read(), r_read_data[0], true); // update the cache directory @@ -2353,7 +2446,4 @@ { entry.owner.srcid = m_cmd_read_srcid_fifo.read(); -#if L1_MULTI_CACHE - entry.owner.cache_id = m_cmd_read_pktid_fifo.read(); -#endif entry.owner.inst = inst_read; entry.count = r_read_count.read() + 1; @@ -2362,7 +2452,4 @@ { entry.owner.srcid = 0; -#if L1_MULTI_CACHE - entry.owner.cache_id = 0; -#endif entry.owner.inst = false; entry.count = r_read_count.read() + 1; @@ -2372,7 +2459,4 @@ { entry.owner.srcid = r_read_copy.read(); -#if L1_MULTI_CACHE - entry.owner.cache_id = r_read_copy_cache.read(); -#endif entry.owner.inst = r_read_copy_inst.read(); entry.count = r_read_count.read(); @@ -2394,6 +2478,5 @@ m_cache_directory.write(set, way, entry); r_read_fsm = READ_RSP; - } - break; + break; } /////////////////// @@ -2436,6 +2519,4 @@ m_cache_data.read_line(way, set, r_read_data); - - if(m_monitor_ok) check_monitor( m_cmd_read_addr_fifo.read(), r_read_data[0], true); // update the cache directory @@ -2452,7 +2533,4 @@ { entry.owner.srcid = r_read_copy.read(); -#if L1_MULTI_CACHE - entry.owner.cache_id = r_read_copy_cache.read(); -#endif entry.owner.inst = r_read_copy_inst.read(); entry.ptr = m_heap.next_free_ptr(); // set pointer on the heap @@ -2461,7 +2539,4 @@ { entry.owner.srcid = 0; -#if L1_MULTI_CACHE - entry.owner.cache_id = 0; -#endif entry.owner.inst = false; entry.ptr = 0; @@ -2529,7 +2604,4 @@ HeapEntry heap_entry; heap_entry.owner.srcid = m_cmd_read_srcid_fifo.read(); -#if L1_MULTI_CACHE - heap_entry.owner.cache_id = m_cmd_read_pktid_fifo.read(); -#endif heap_entry.owner.inst = ((m_cmd_read_pktid_fifo.read() & 0x2) != 0); @@ -2595,7 +2667,4 @@ HeapEntry last_entry; last_entry.owner.srcid = 0; -#if L1_MULTI_CACHE - last_entry.owner.cache_id = 0; -#endif last_entry.owner.inst = false; @@ -2718,5 +2787,6 @@ #if DEBUG_MEMC_READ if(m_debug) -std::cout << " Write in Transaction Table:" + m_trt.print(0); +std::cout << " Set a GET in TGT:" << " address = " << std::hex << m_cmd_read_addr_fifo.read() << " / srcid = " << std::hex << m_cmd_read_srcid_fifo.read() << std::endl; @@ -2734,6 +2804,6 @@ cmd_read_fifo_get = true; r_read_to_ixr_cmd_req = true; - r_read_to_ixr_cmd_nline = m_nline[(addr_t)(m_cmd_read_addr_fifo.read())]; - r_read_to_ixr_cmd_trdid = r_read_trt_index.read(); + //r_read_to_ixr_cmd_nline = m_nline[(addr_t)(m_cmd_read_addr_fifo.read())]; + r_read_to_ixr_cmd_index = r_read_trt_index.read(); r_read_fsm = READ_IDLE; @@ -2762,7 +2832,6 @@ // If the data is cached by other processors, a coherence transaction must // be launched (sc requests always require a coherence transaction): - // It is a multicast update if the line is not in counter mode, and the processor + // It is a multicast update if the line is not in counter mode: the processor // takes the lock protecting the Update Table (UPT) to register this transaction. - // It is a broadcast invalidate if the line is in counter mode. // If the UPT is full, it releases the lock(s) and retry. Then, it sends // a multi-update request to all owners of the line (but the writer), @@ -2770,9 +2839,12 @@ // does not respond to the writing processor, as this response will be sent by // the MULTI_ACK FSM when all update responses have been received. + // It is a broadcast invalidate if the line is in counter mode: The line + // should be erased in memory cache, and written in XRAM with a PUT transaction, + // after registration in TRT. // // - In case of MISS, the WRITE FSM takes the lock protecting the transaction // table (TRT). If a read transaction to the XRAM for this line already exists, // it writes in the TRT (write buffer). Otherwise, if a TRT entry is free, - // the WRITE FSM register a new transaction in TRT, and sends a read line request + // the WRITE FSM register a new transaction in TRT, and sends a GET request // to the XRAM. If the TRT is full, it releases the lock, and waits. // Finally, the WRITE FSM returns an aknowledge response to the writing processor. @@ -2849,12 +2921,7 @@ // check that the next word is in the same cache line - if((m_nline[(addr_t)(r_write_address.read())] != - m_nline[(addr_t)(m_cmd_write_addr_fifo.read())])) - { - std::cout << "VCI_MEM_CACHE ERROR " << name() << " WRITE_NEXT state" << std::endl - << "all words in a write burst must be in same cache line" << std::endl; - - exit(0); - } + assert( (m_nline[(addr_t)(r_write_address.read())] == + m_nline[(addr_t)(m_cmd_write_addr_fifo.read())]) and + "MEMC ERROR in WRITE_NEXT state: Illegal write burst"); // consume a word in the FIFO & write it in the local buffer @@ -2922,5 +2989,5 @@ // erase any possible new reservation when we release the lock on the // directory - m_llsc_table.sw(nline); + m_llsc_table.sw(m_nline[(addr_t)r_write_address.read()],r_write_word_index.read(),r_write_word_index.read()+r_write_word_count.read()); //m_llsc_table.sw(r_write_address.read()); @@ -2944,6 +3011,6 @@ case WRITE_DIR_LOCK: // access directory to check hit/miss { - if(r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE) - { + assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE) and + "MEMC ERROR in ALLOC_DIR_LOCK state: Bad DIR allocation"); size_t way = 0; DirectoryEntry entry(m_cache_directory.read(r_write_address.read(), way)); @@ -2956,7 +3023,4 @@ r_write_tag = entry.tag; r_write_copy = entry.owner.srcid; -#if L1_MULTI_CACHE - r_write_copy_cache = entry.owner.cache_id; -#endif r_write_copy_inst = entry.owner.inst; r_write_count = entry.count; @@ -2970,5 +3034,5 @@ if(entry.is_cnt && entry.count) { - r_write_fsm = WRITE_DIR_READ; + r_write_fsm = WRITE_BC_DIR_READ; } else @@ -3012,13 +3076,4 @@ } #endif - } - else - { - std::cout << "VCI_MEM_CACHE ERROR " << name() - << " WRITE_DIR_LOCK state" << std::endl - << "bad DIR allocation" << std::endl; - - exit(0); - } break; } @@ -3076,39 +3131,10 @@ } - - //////////////////// - case WRITE_DIR_READ: // read the cache and complete the buffer when be!=0xF - { - // update local buffer - size_t set = m_y[(addr_t)(r_write_address.read())]; - size_t way = r_write_way.read(); - for(size_t word=0 ; word" - << " Read the cache to complete local buffer" << std::endl; -#endif - break; - } - /////////////////// case WRITE_DIR_HIT: { + assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE) and + "MEMC ERROR in ALLOC_DIR_HIT state: Bad DIR allocation"); + // update the cache directory // update directory with Dirty bit @@ -3121,7 +3147,4 @@ entry.lock = r_write_lock.read(); entry.owner.srcid = r_write_copy.read(); -#if L1_MULTI_CACHE - entry.owner.cache_id = r_write_copy_cache.read(); -#endif entry.owner.inst = r_write_copy_inst.read(); entry.count = r_write_count.read(); @@ -3154,9 +3177,4 @@ m_cache_data.write(way, set, word, r_write_data[word].read(), r_write_be[word].read()); - if(m_monitor_ok) - { - addr_t address = (r_write_address.read() & ~(addr_t) 0x3F) | word<<2; - check_monitor( address, r_write_data[word].read(), false); - } } } @@ -3242,14 +3260,9 @@ r_write_be[word].read()); - if(m_monitor_ok) - { - addr_t address = (r_write_address.read() & ~(addr_t) 0x3F) | word<<2; - check_monitor( address, r_write_data[word].read(), false); - } } } #if DEBUG_MEMC_WRITE -if(m_debug) +if(m_debug and wok) { if(wok) @@ -3317,9 +3330,5 @@ for(size_t i=min ; i Set a new entry in TRT" << std::endl; #endif @@ -3662,6 +3662,6 @@ } m_trt.write_data_mask(r_write_trt_index.read(), - be_vector, - data_vector); + be_vector, + data_vector); r_write_fsm = WRITE_RSP; @@ -3677,10 +3677,9 @@ case WRITE_MISS_XRAM_REQ: // send a GET request to IXR_CMD FSM { - if(!r_write_to_ixr_cmd_req) + if(not r_write_to_ixr_cmd_req.read()) { r_write_to_ixr_cmd_req = true; - r_write_to_ixr_cmd_write = false; - r_write_to_ixr_cmd_nline = m_nline[(addr_t)(r_write_address.read())]; - r_write_to_ixr_cmd_trdid = r_write_trt_index.read(); + r_write_to_ixr_cmd_put = false; + r_write_to_ixr_cmd_index = r_write_trt_index.read(); r_write_fsm = WRITE_RSP; @@ -3694,10 +3693,47 @@ /////////////////////// - case WRITE_BC_TRT_LOCK: // Check TRT not full - { + case WRITE_BC_DIR_READ: // enter this state if a broadcast-inval is required + // the cache line must be erased in mem-cache, and written + // into XRAM. we read the cache and complete the buffer + { + assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE) and + "MEMC ERROR in WRITE_BC_DIR_READ state: Bad DIR allocation"); + + // update local buffer + size_t set = m_y[(addr_t)(r_write_address.read())]; + size_t way = r_write_way.read(); + for(size_t word=0 ; word" + << " Read the cache to complete local buffer" << std::endl; +#endif + break; + } + + /////////////////////// + case WRITE_BC_TRT_LOCK: // get TRT lock to check TRT not full + { + assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE) and + "MEMC ERROR in WRITE_BC_TRT_LOCK state: Bad DIR allocation"); + if(r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE) { size_t wok_index = 0; - bool wok = !m_trt.full(wok_index); + bool wok = not m_trt.full(wok_index); if(wok) // set a new entry in TRT { @@ -3726,4 +3762,10 @@ case WRITE_BC_IVT_LOCK: // register BC transaction in IVT { + assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE) and + "MEMC ERROR in WRITE_BC_IVT_LOCK state: Bad DIR allocation"); + + assert( (r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE) and + "MEMC ERROR in WRITE_BC_IVT_LOCK state: Bad TRT allocation"); + if(r_alloc_ivt_fsm.read() == ALLOC_IVT_WRITE) { @@ -3767,27 +3809,28 @@ case WRITE_BC_DIR_INVAL: { - // Register a put transaction to XRAM in TRT - // and invalidate the line in directory - if((r_alloc_trt_fsm.read() != ALLOC_TRT_WRITE) or - (r_alloc_ivt_fsm.read() != ALLOC_IVT_WRITE) or - (r_alloc_dir_fsm.read() != ALLOC_DIR_WRITE)) - { - std::cout << "VCI_MEM_CACHE ERROR " << name() << " WRITE_BC_DIR_INVAL state" << std::endl; - std::cout << "bad TRT, DIR, or IVT allocation" << std::endl; - exit(0); - } - - // register a write request to XRAM in TRT - m_trt.set(r_write_trt_index.read(), - false, // write request to XRAM - m_nline[(addr_t)(r_write_address.read())], - 0, - 0, - 0, - false, // not a processor read - 0, // not a single word - 0, // word index - std::vector (m_words,0), - std::vector (m_words,0)); + assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE) and + "MEMC ERROR in WRITE_BC_DIR_INVAL state: Bad DIR allocation"); + + assert( (r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE) and + "MEMC ERROR in WRITE_BC_DIR_INVAL state: Bad TRT allocation"); + + assert( (r_alloc_ivt_fsm.read() == ALLOC_IVT_WRITE) and + "MEMC ERROR in WRITE_BC_DIR_INVAL state: Bad IVT allocation"); + + // register PUT request in TRT + std::vector data_vector; + data_vector.clear(); + for(size_t i=0; i (m_words,0), + data_vector ); // invalidate directory entry @@ -3796,11 +3839,8 @@ entry.cache_coherent= false; entry.dirty = false; - entry.tag = 0; + entry.tag = 0; entry.is_cnt = false; entry.lock = false; entry.owner.srcid = 0; -#if L1_MULTI_CACHE - entry.owner.cache_id= 0; -#endif entry.owner.inst = false; entry.ptr = 0; @@ -3813,4 +3853,5 @@ #if DEBUG_MEMC_WRITE if(m_debug) + m_trt.print(0); std::cout << " Invalidate the directory entry: @ = " << r_write_address.read() << " / register the put transaction in TRT:" << std::endl; @@ -3851,13 +3892,9 @@ case WRITE_BC_XRAM_REQ: // Post a put request to IXR_CMD FSM { - if(!r_write_to_ixr_cmd_req) + if( not r_write_to_ixr_cmd_req.read() ) { r_write_to_ixr_cmd_req = true; - r_write_to_ixr_cmd_write = true; - r_write_to_ixr_cmd_nline = m_nline[(addr_t)(r_write_address.read())]; - r_write_to_ixr_cmd_trdid = r_write_trt_index.read(); - - for(size_t i=0; i WRITE > CAS > XRAM_RSP > CONFIG // - // - It sends a single flit VCI read request to the XRAM in case of MISS - // posted by the READ, WRITE or CAS FSMs : the TRDID field contains - // the Transaction Tab index. - // The VCI response is a multi-flit packet : the N cells contain - // the N data words. + // - It sends a single flit VCI read to the XRAM in case of + // GET request posted by the READ, WRITE or CAS FSMs. + // - It sends a multi-flit VCI write in case of PUT request posted by + // the XRAM_RSP, WRITE, CAS, or CONFIG FSMs. // - // - It sends a multi-flit VCI write when the XRAM_RSP FSM, WRITE FSM - // or CAS FSM request to save a dirty line to the XRAM. - // The VCI response is a single flit packet. + // For each client, there is three steps: + // - IXR_CMD_*_IDLE : round-robin allocation to a client + // - IXR_CMD_*_TRT : access to TRT for address and data + // - IXR_CMD_*_SEND : send the PUT or GET VCI command + // + // The address and data to be written (for a PUT) are stored in TRT. + // The trdid field contains always the TRT entry index. //////////////////////////////////////////////////////////////////////// @@ -3894,184 +3934,324 @@ //////////////////////// case IXR_CMD_READ_IDLE: - if (r_write_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_WRITE; - else if(r_cas_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_CAS; - else if(r_xram_rsp_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_XRAM; - else if(r_cleanup_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_CLEANUP_DATA; - else if(r_read_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_READ; + if (r_write_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_WRITE_TRT; + else if(r_cas_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CAS_TRT; + else if(r_cleanup_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CLEANUP_TRT; + else if(r_xram_rsp_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_XRAM_TRT; + else if(r_config_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CONFIG_TRT; + else if(r_read_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_READ_TRT; break; //////////////////////// case IXR_CMD_WRITE_IDLE: - if(r_cas_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_CAS; - else if(r_xram_rsp_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_XRAM; - else if(r_cleanup_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_CLEANUP_DATA; - else if(r_read_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_READ; - else if(r_write_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_WRITE; + if (r_cas_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CAS_TRT; + else if(r_cleanup_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CLEANUP_TRT; + else if(r_xram_rsp_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_XRAM_TRT; + else if(r_config_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CONFIG_TRT; + else if(r_read_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_READ_TRT; + else if(r_write_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_WRITE_TRT; break; //////////////////////// case IXR_CMD_CAS_IDLE: - if(r_xram_rsp_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_XRAM; - else if(r_cleanup_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_CLEANUP_DATA; - else if(r_read_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_READ; - else if(r_write_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_WRITE; - else if(r_cas_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_CAS; + if (r_cleanup_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CLEANUP_TRT; + else if(r_xram_rsp_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_XRAM_TRT; + else if(r_config_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CONFIG_TRT; + else if(r_read_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_READ_TRT; + else if(r_write_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_WRITE_TRT; + else if(r_cas_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CAS_TRT; break; //////////////////////// case IXR_CMD_XRAM_IDLE: - if(r_cleanup_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_CLEANUP_DATA; - else if(r_read_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_READ; - else if(r_write_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_WRITE; - else if(r_cas_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_CAS; - else if(r_xram_rsp_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_XRAM; + if (r_config_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CONFIG_TRT; + else if(r_read_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_READ_TRT; + else if(r_write_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_WRITE_TRT; + else if(r_cas_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CAS_TRT; + else if(r_cleanup_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CLEANUP_TRT; + else if(r_xram_rsp_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_XRAM_TRT; break; //////////////////////// case IXR_CMD_CLEANUP_IDLE: /*ODCCP*///std::cout << "IXR_CMD_CLEANUP_IDLE" << std::endl; - if(r_read_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_READ; - else if(r_write_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_WRITE; - else if(r_cas_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_CAS; - else if(r_xram_rsp_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_XRAM; - else if(r_cleanup_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_CLEANUP_DATA; + if (r_read_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_READ_TRT; + else if(r_write_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_WRITE_TRT; + else if(r_cas_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CAS_TRT; + else if(r_xram_rsp_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_XRAM_TRT; + else if(r_config_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CONFIG_TRT; + else if(r_cleanup_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_CLEANUP_TRT; break; - ////////////////// // send a get from READ FSM - case IXR_CMD_READ: - { - if(p_vci_ixr.cmdack) - { - r_ixr_cmd_fsm = IXR_CMD_READ_IDLE; - r_read_to_ixr_cmd_req = false; + ///////////////////////// + case IXR_CMD_CONFIG_IDLE: + { + if (r_read_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_READ_TRT; + else if(r_write_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_WRITE_TRT; + else if(r_cas_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CAS_TRT; + else if(r_cleanup_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_CLEANUP_TRT; + else if(r_xram_rsp_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_XRAM_TRT; + else if(r_config_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CONFIG_TRT; + break; + } + + ////////////////////// + case IXR_CMD_READ_TRT: // access TRT for a GET + { + if ( r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_CMD ) + { + TransactionTabEntry entry = m_trt.read( r_read_to_ixr_cmd_index.read() ); + r_ixr_cmd_address = entry.nline * (m_words<<2); + r_ixr_cmd_trdid = r_read_to_ixr_cmd_index.read(); + r_ixr_cmd_get = true; + r_ixr_cmd_word = 0; + r_ixr_cmd_fsm = IXR_CMD_READ_SEND; + for( size_t i=0 ; i" - << " Send a get request to xram / address = " << std::hex - << (addr_t)(r_read_to_ixr_cmd_nline.read()*m_words*4) << std::endl; -#endif - } - break; - } - /////////////////// - case IXR_CMD_WRITE: // send a put or get from WRITE FSM - { - if(p_vci_ixr.cmdack) - { - if(r_write_to_ixr_cmd_write.read()) // PUT - { - if(r_ixr_cmd_cpt.read() == (m_words - 2)) - { - r_ixr_cmd_cpt = 0; - r_ixr_cmd_fsm = IXR_CMD_WRITE_IDLE; - r_write_to_ixr_cmd_req = false; - } - else - { - r_ixr_cmd_cpt = r_ixr_cmd_cpt + 2; - } +std::cout << " TRT access" + << " index = " << std::dec << r_read_to_ixr_cmd_index.read() + << " / address = " << std::hex << (entry.nline*(m_words<<2)) << std::endl; +#endif + } + break; + } + /////////////////////// + case IXR_CMD_WRITE_TRT: // access TRT for a PUT or a GET + { + if ( r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_CMD ) + { + TransactionTabEntry entry = m_trt.read( r_write_to_ixr_cmd_index.read() ); + r_ixr_cmd_address = entry.nline * (m_words<<2); + r_ixr_cmd_trdid = r_write_to_ixr_cmd_index.read(); + r_ixr_cmd_get = entry.xram_read; + r_ixr_cmd_word = 0; + r_ixr_cmd_fsm = IXR_CMD_WRITE_SEND; + for( size_t i=0 ; i" - << " Send a put request to xram / address = " << std::hex - << (addr_t)((r_write_to_ixr_cmd_nline.read() * m_words + - r_ixr_cmd_cpt.read()) * 4 ) << std::endl; -#endif - } - else // GET - { - r_ixr_cmd_fsm = IXR_CMD_WRITE_IDLE; - r_write_to_ixr_cmd_req = false; +std::cout << " TRT access" + << " index = " << std::dec << r_write_to_ixr_cmd_index.read() + << " / address = " << std::hex << (entry.nline*(m_words<<2)) << std::endl; +#endif + } + break; + } + ///////////////////// + case IXR_CMD_CAS_TRT: // access TRT for a PUT or a GET + { + if ( r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_CMD ) + { + TransactionTabEntry entry = m_trt.read( r_cas_to_ixr_cmd_index.read() ); + r_ixr_cmd_address = entry.nline * (m_words<<2); + r_ixr_cmd_trdid = r_cas_to_ixr_cmd_index.read(); + r_ixr_cmd_get = entry.xram_read; + r_ixr_cmd_word = 0; + r_ixr_cmd_fsm = IXR_CMD_CAS_SEND; + for( size_t i=0 ; i" - << " Send a get request to xram / address = " << std::hex - << (addr_t)(r_write_to_ixr_cmd_nline.read()*m_words*4) << std::endl; -#endif - } - } - break; - } - ///////////////// - case IXR_CMD_CAS: // send a put or get command from CAS FSM - { - if(p_vci_ixr.cmdack) - { - if(r_cas_to_ixr_cmd_write.read()) // PUT - { - if(r_ixr_cmd_cpt.read() == (m_words - 2)) - { - r_ixr_cmd_cpt = 0; - r_ixr_cmd_fsm = IXR_CMD_CAS_IDLE; - r_cas_to_ixr_cmd_req = false; - } - else - { - r_ixr_cmd_cpt = r_ixr_cmd_cpt + 2; - } +std::cout << " TRT access" + << " index = " << std::dec << r_cas_to_ixr_cmd_index.read() + << " / address = " << std::hex << (entry.nline*(m_words<<2)) << std::endl; +#endif + } + break; + } + ////////////////////// + case IXR_CMD_XRAM_TRT: // access TRT for a PUT + { + if ( r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_CMD ) + { + TransactionTabEntry entry = m_trt.read( r_xram_rsp_to_ixr_cmd_index.read() ); + r_ixr_cmd_address = entry.nline * (m_words<<2); + r_ixr_cmd_trdid = r_xram_rsp_to_ixr_cmd_index.read(); + r_ixr_cmd_get = false; + r_ixr_cmd_word = 0; + r_ixr_cmd_fsm = IXR_CMD_XRAM_SEND; + for( size_t i=0 ; i" - << " Send a put request to xram / address = " << std::hex - << (addr_t)( (r_cas_to_ixr_cmd_nline.read() * m_words + - r_ixr_cmd_cpt.read()) * 4 ) << std::endl; -#endif - } - else // GET - { - r_ixr_cmd_fsm = IXR_CMD_CAS_IDLE; - r_cas_to_ixr_cmd_req = false; +std::cout << " TRT access" + << " index = " << std::dec << r_xram_rsp_to_ixr_cmd_index.read() + << " / address = " << std::hex << (entry.nline*(m_words<<2)) << std::endl; +#endif + } + break; + } + ////////////////////// + case IXR_CMD_CLEANUP_TRT: // access TRT for a PUT + { + if ( r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_CMD ) + { + + TransactionTabEntry entry = m_trt.read( r_cleanup_to_ixr_cmd_index.read() ); + r_ixr_cmd_address = entry.nline * (m_words<<2); + r_ixr_cmd_trdid = r_cleanup_to_ixr_cmd_index.read(); + r_ixr_cmd_get = false; + r_ixr_cmd_word = 0; + r_ixr_cmd_fsm = IXR_CMD_CLEANUP_DATA_SEND; + for( size_t i=0 ; i" - << " Send a get request to xram / address = " << std::hex - << (addr_t)(r_cas_to_ixr_cmd_nline.read()*m_words*4) << std::endl; -#endif - } - } - break; - } - ////////////////// - case IXR_CMD_XRAM: // send a put from XRAM_RSP FSM - { - if(p_vci_ixr.cmdack) - { - if(r_ixr_cmd_cpt.read() == (m_words - 2)) - { - r_ixr_cmd_cpt = 0; - r_ixr_cmd_fsm = IXR_CMD_XRAM_IDLE; - r_xram_rsp_to_ixr_cmd_req = false; +std::cout << " TRT access" + << " index = " << std::dec << r_cleanup_to_ixr_cmd_index.read() + << " / address = " << std::hex << (entry.nline*(m_words<<2)) << std::endl; +#endif + } + break; + } + //////////////////////// + case IXR_CMD_CONFIG_TRT: // access TRT for a PUT + { + if ( r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_CMD ) + { + TransactionTabEntry entry = m_trt.read( r_config_to_ixr_cmd_index.read() ); + r_ixr_cmd_address = entry.nline * (m_words<<2); + r_ixr_cmd_trdid = r_config_to_ixr_cmd_index.read(); + r_ixr_cmd_get = false; + r_ixr_cmd_word = 0; + r_ixr_cmd_fsm = IXR_CMD_CONFIG_SEND; + for( size_t i=0 ; i TRT access" + << " index = " << std::dec << r_config_to_ixr_cmd_index.read() + << " / address = " << std::hex << (entry.nline*(m_words<<2)) << std::endl; +#endif + } + break; + } + + /////////////////////// + case IXR_CMD_READ_SEND: // send a get from READ FSM + { + if(p_vci_ixr.cmdack) + { + r_ixr_cmd_fsm = IXR_CMD_READ_IDLE; + r_read_to_ixr_cmd_req = false; + +#if DEBUG_MEMC_IXR_CMD +if(m_debug) +std::cout << " GET request:" << std::hex + << " address = " << r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2) << std::endl; +#endif + } + break; + } + //////////////////////// + case IXR_CMD_WRITE_SEND: // send a put or get from WRITE FSM + { + if(p_vci_ixr.cmdack) + { + if(r_write_to_ixr_cmd_put.read()) // PUT + { + if(r_ixr_cmd_word.read() == (m_words - 2)) + { + r_ixr_cmd_fsm = IXR_CMD_WRITE_IDLE; + r_write_to_ixr_cmd_req = false; + } + else + { + r_ixr_cmd_word = r_ixr_cmd_word.read() + 2; + } + +#if DEBUG_MEMC_IXR_CMD +if(m_debug) +std::cout << " PUT request:" << std::hex + << " address = " << r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2) << std::endl; +#endif + } + else // GET + { + r_ixr_cmd_fsm = IXR_CMD_WRITE_IDLE; + r_write_to_ixr_cmd_req = false; + +#if DEBUG_MEMC_IXR_CMD +if(m_debug) +std::cout << " GET request:" << std::hex + << " address = " << r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2) << std::endl; +#endif + } + } + break; + } + ////////////////////// + case IXR_CMD_CAS_SEND: // send a put or get command from CAS FSM + { + if(p_vci_ixr.cmdack) + { + if(r_cas_to_ixr_cmd_put.read()) // PUT + { + if(r_ixr_cmd_word.read() == (m_words - 2)) + { + r_ixr_cmd_fsm = IXR_CMD_CAS_IDLE; + r_cas_to_ixr_cmd_req = false; + } + else + { + r_ixr_cmd_word = r_ixr_cmd_word.read() + 2; + } + +#if DEBUG_MEMC_IXR_CMD +if(m_debug) +std::cout << " PUT request:" << std::hex + << " address = " << r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2) << std::endl; +#endif + } + else // GET + { + r_ixr_cmd_fsm = IXR_CMD_CAS_IDLE; + r_cas_to_ixr_cmd_req = false; + +#if DEBUG_MEMC_IXR_CMD +if(m_debug) +std::cout << " GET request:" << std::hex + << " address = " << r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2) << std::endl; +#endif + } + } + break; + } + /////////////////////// + case IXR_CMD_XRAM_SEND: // send a put from XRAM_RSP FSM + { + if(p_vci_ixr.cmdack.read()) + { + if(r_ixr_cmd_word.read() == (m_words - 2)) + { + r_ixr_cmd_fsm = IXR_CMD_XRAM_IDLE; + r_xram_rsp_to_ixr_cmd_req = false; + } + else + { + r_ixr_cmd_word = r_ixr_cmd_word.read() + 2; + } +#if DEBUG_MEMC_IXR_CMD +if(m_debug) +std::cout << " PUT request:" << std::hex + << " address = " << r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2) << std::endl; +#endif + } + break; + } + + //////////////////////// + case IXR_CMD_CLEANUP_DATA_SEND: // send a put command to XRAM + { + if(p_vci_ixr.cmdack.read()) + { + /*ODCCP*/ //std::cout << "IXR_CMD_CLEANUP_DATA_SEND STATE at cycle : " << std::dec << m_cpt_cycles << std::endl; + if(r_ixr_cmd_word.read() == (m_words - 2)) + { + /*ODCCP*/ //std::cout << "IXR_CMD_CLEANUP_DATA_SEND GO TO IXR_CMD_CLEANUP_IDLE" << std::endl; + r_ixr_cmd_fsm = IXR_CMD_CLEANUP_IDLE; + r_cleanup_to_ixr_cmd_req = false; + //r_ixr_cmd_word = 0; + //r_xram_rsp_to_ixr_cmd_inval_ncc_pending = false; } else { - r_ixr_cmd_cpt = r_ixr_cmd_cpt + 2; - } - -#if DEBUG_MEMC_IXR_CMD -if(m_debug) -std::cout << " " - << " Send a put request to xram / address = " << std::hex - << (addr_t)( (r_xram_rsp_to_ixr_cmd_nline.read() * m_words + - r_ixr_cmd_cpt.read()) * 4 ) << std::endl; -#endif - } - break; - } - - //////////////////////// - case IXR_CMD_CLEANUP_DATA: // send a put command to XRAM - /*ODCCP*///std::cout << "IXR_CMD_CLEANUP_DATA" << std::endl; - if(p_vci_ixr.cmdack) - { - if(r_ixr_cmd_cpt.read() == (m_words - 2)) - { - r_ixr_cmd_cpt = 0; - r_ixr_cmd_fsm = IXR_CMD_CLEANUP_IDLE; - r_xram_rsp_to_ixr_cmd_inval_ncc_pending = false; - r_cleanup_to_ixr_cmd_req = false; - } - else - { - r_ixr_cmd_cpt = r_ixr_cmd_cpt.read() + 2; + r_ixr_cmd_word = r_ixr_cmd_word.read() + 2; } @@ -4079,10 +4259,34 @@ if(m_debug) { - std::cout << " Send a put request to xram" << std::endl; - } -#endif - } - break; - + std::cout << " Send a put request to xram" << std::endl; + } +#endif + } + break; + } + + ///////////////////////// + case IXR_CMD_CONFIG_SEND: // send a put from CONFIG FSM + { + if(p_vci_ixr.cmdack.read()) + { + if(r_ixr_cmd_word.read() == (m_words - 2)) + { + r_ixr_cmd_fsm = IXR_CMD_CONFIG_IDLE; + r_config_to_ixr_cmd_req = false; + } + else + { + r_ixr_cmd_word = r_ixr_cmd_word.read() + 2; + } + +#if DEBUG_MEMC_IXR_CMD +if(m_debug) +std::cout << " PUT request:" << std::hex + << " address = " << r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2) << std::endl; +#endif + } + break; + } } // end switch r_ixr_cmd_fsm @@ -4091,17 +4295,19 @@ //////////////////////////////////////////////////////////////////////////// // The IXR_RSP FSM receives the response packets from the XRAM, - // for both put transaction, and get transaction. + // for both PUT transaction, and GET transaction. // - // - A response to a put request is a single-cell VCI packet. - // The Transaction Tab index is contained in the RTRDID field. + // - A response to a PUT request is a single-cell VCI packet. + // The TRT index is contained in the RTRDID field. // The FSM takes the lock protecting the TRT, and the corresponding - // entry is erased. + // entry is erased. If an acknowledge was required (in case of software SYNC) + // the r_config_rsp_lines counter is decremented. // - // - A response to a get request is a multi-cell VCI packet. - // The Transaction Tab index is contained in the RTRDID field. + // - A response to a GET request is a multi-cell VCI packet. + // The TRT index is contained in the RTRDID field. // The N cells contain the N words of the cache line in the RDATA field. // The FSM takes the lock protecting the TRT to store the line in the TRT // (taking into account the write requests already stored in the TRT). - // When the line is completely written, the corresponding rok signal is set. + // When the line is completely written, the r_ixr_rsp_to_xram_rsp_rok[index] + // signal is set to inform the XRAM_RSP FSM. /////////////////////////////////////////////////////////////////////////////// @@ -4111,21 +4317,20 @@ case IXR_RSP_IDLE: // test transaction type: PUT/GET { - if(p_vci_ixr.rspval.read()) - { - r_ixr_rsp_cpt = 0; - r_ixr_rsp_trt_index = p_vci_ixr.rtrdid.read(); - if(p_vci_ixr.reop.read() and !(p_vci_ixr.rerror.read() &0x1)) // PUT transaction - { - r_ixr_rsp_fsm = IXR_RSP_ACK; - -#if DEBUG_MEMC_IXR_RSP -if(m_debug) -std::cout << " Response from XRAM to a put transaction" << std::endl; -#endif - } - else // GET transaction - { - r_ixr_rsp_fsm = IXR_RSP_TRT_READ; + if(p_vci_ixr.rspval.read()) + { + r_ixr_rsp_cpt = 0; + r_ixr_rsp_trt_index = p_vci_ixr.rtrdid.read(); + + assert( ((p_vci_ixr.rerror.read() & 0x1) == 0) and + "MEMC ERROR in IXR_RSP state: XRAM response error !"); + + if(p_vci_ixr.reop.read()) // PUT + { + r_ixr_rsp_fsm = IXR_RSP_TRT_ERASE; + } + + else // GET transaction + { + r_ixr_rsp_fsm = IXR_RSP_TRT_READ; #if DEBUG_MEMC_IXR_RSP @@ -4134,27 +4339,27 @@ << " IXR_RSP_IDLE> Response from XRAM to a get transaction" << std::endl; #endif - } - } - break; - } - ///////////////// - case IXR_RSP_ACK: // Aknowledge the VCI response for a PUT - { - if(p_vci_ixr.rspval.read()) r_ixr_rsp_fsm = IXR_RSP_TRT_ERASE; - -#if DEBUG_MEMC_IXR_RSP -if(m_debug) -std::cout << " " << std::endl; -#endif + } + } break; } //////////////////////// + case IXR_RSP_ACK: // Acknowledge PUT transaction + { + r_ixr_rsp_fsm = IXR_RSP_IDLE; + break; + } + + //////////////////////// case IXR_RSP_TRT_ERASE: // erase the entry in the TRT - { - if(r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP) - { - m_trt.erase(r_ixr_rsp_trt_index.read()); - r_ixr_rsp_fsm = IXR_RSP_IDLE; - + // decrease the line counter if config request + { + if(r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP) + { + size_t index = r_ixr_rsp_trt_index.read(); + if (m_trt.is_config(index) ) r_config_rsp_lines = r_config_rsp_lines.read() - 1; + m_trt.erase(index); + r_ixr_rsp_fsm = IXR_RSP_IDLE; + +// std::cout << "remove a valid slot in trt index = " << r_ixr_rsp_trt_index.read()<< std::endl; #if DEBUG_MEMC_IXR_RSP if(m_debug) @@ -4162,36 +4367,32 @@ << r_ixr_rsp_trt_index.read() << std::endl; #endif - m_cpt_ixr_fsm_n_trt_lock++; - } - - m_cpt_ixr_fsm_trt_lock++; - - break; + } + break; } ////////////////////// case IXR_RSP_TRT_READ: // write a 64 bits data in the TRT { - if((r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP) and p_vci_ixr.rspval) - { - size_t index = r_ixr_rsp_trt_index.read(); - bool eop = p_vci_ixr.reop.read(); - wide_data_t data = p_vci_ixr.rdata.read(); - bool error = ((p_vci_ixr.rerror.read() & 0x1) == 1); - - assert(((eop == (r_ixr_rsp_cpt.read() == (m_words-2))) or p_vci_ixr.rerror.read()) - and "Error in VCI_MEM_CACHE : invalid length for a response from XRAM"); - - m_trt.write_rsp( index, - r_ixr_rsp_cpt.read(), - data, - error); - - r_ixr_rsp_cpt = r_ixr_rsp_cpt.read() + 2; - - if(eop) - { - r_ixr_rsp_to_xram_rsp_rok[r_ixr_rsp_trt_index.read()]=true; - r_ixr_rsp_fsm = IXR_RSP_IDLE; - } + if((r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP) and p_vci_ixr.rspval) + { + size_t index = r_ixr_rsp_trt_index.read(); + size_t word = r_ixr_rsp_cpt.read(); + bool eop = p_vci_ixr.reop.read(); + wide_data_t data = p_vci_ixr.rdata.read(); + bool error = ((p_vci_ixr.rerror.read() & 0x1) == 1); + + assert(((eop == (word == (m_words-2))) or error) and + "MEMC ERROR in IXR_RSP_TRT_READ state : invalid response from XRAM"); + + m_trt.write_rsp( index, + word, + data ); + + r_ixr_rsp_cpt = word + 2; + + if(eop) + { + r_ixr_rsp_to_xram_rsp_rok[r_ixr_rsp_trt_index.read()]=true; + r_ixr_rsp_fsm = IXR_RSP_IDLE; + } #if DEBUG_MEMC_IXR_RSP @@ -4199,5 +4400,5 @@ std::cout << " Writing a word in TRT : " << " index = " << std::dec << index - << " / word = " << r_ixr_rsp_cpt.read() + << " / word = " << word << " / data = " << std::hex << data << std::endl; #endif @@ -4212,15 +4413,15 @@ // XRAM_RSP FSM //////////////////////////////////////////////////////////////////////////// - // The XRAM_RSP FSM handles the incoming cache lines from the XRAM. + // The XRAM_RSP FSM handles the incoming cache lines after an XRAM GET. // The cache line has been written in the TRT by the IXR_CMD_FSM. // As the IXR_RSP FSM and the XRAM_RSP FSM are running in parallel, - // there is as many flip-flops r_ixr_rsp_to_xram_rsp_rok[i] - // as the number of entries in the TRT, that are handled with - // a round-robin priority... + // there is as many flip-flops r_ixr_rsp_to_xram_rsp_rok[i] as the number + // of entries in the TRT, that are handled with a round-robin priority... // - // When a response is available, the corresponding TRT entry - // is copied in a local buffer to be written in the cache. - // The FSM takes the lock protecting the TRT, and the lock protecting the DIR. - // It selects a cache slot and writes the line in the cache. + // The FSM takes the lock protecting TRT, and the lock protecting DIR. + // The selected TRT entry is copied in the local buffer r_xram_rsp_trt_buf. + // It selects a cache slot and save the victim line in another local buffer + // r_xram_rsp_victim_***. + // It writes the line extracted from TRT in the cache. // If it was a read MISS, the XRAM_RSP FSM send a request to the TGT_RSP // FSM to return the cache line to the registered processor. @@ -4237,14 +4438,14 @@ case XRAM_RSP_IDLE: // scan the XRAM responses / select a TRT index (round robin) { - size_t ptr = r_xram_rsp_trt_index.read(); - size_t lines = m_trt_lines; - for(size_t i=0 ; i" - << " Select a slot: " + << " Select a victim slot: " << " way = " << std::dec << way << " / set = " << set << " / inval_required = " << inval << std::endl; #endif - } - else - { - std::cout << "VCI_MEM_CACHE ERROR " << name() << " XRAM_RSP_TRT_COPY" - << " bad TRT or DIR allocation" << std::endl; - exit(0); - } - break; - } - ///////////////////////// - case XRAM_RSP_INVAL_LOCK: // Take the IVT lock to check a possible pending inval - { - if(r_alloc_ivt_fsm == ALLOC_IVT_XRAM_RSP) - { - size_t index = 0; - size_t index_victim = 0; - if(m_ivt.search_inval(r_xram_rsp_trt_buf.nline, index) or - m_ivt.search_inval(r_xram_rsp_victim_nline.read(), index_victim)) - { - r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT; + break; + } + /////////////////////// + case XRAM_RSP_IVT_LOCK: // Keep DIR and TRT locks and take the IVT lock + // to check a possible pending inval + { + assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP) and + "MEMC ERROR in XRAM_RSP_IVT_LOCK state: Bad DIR allocation"); + + assert( (r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP) and + "MEMC ERROR in XRAM_RSP_IVT_LOCK state: Bad TRT allocation"); + + if(r_alloc_ivt_fsm == ALLOC_IVT_XRAM_RSP) + { + size_t index = 0; + if(m_ivt.search_inval(r_xram_rsp_trt_buf.nline, index)) // pending inval + { + r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT; #if DEBUG_MEMC_XRAM_RSP if(m_debug) -std::cout << " " +std::cout << " " << " Get acces to IVT, but line invalidation registered" - << " / nline = " << std::hex << r_xram_rsp_trt_buf.nline + << " / address = " << std::hex << r_xram_rsp_trt_buf.nline*m_words*4 << " / index = " << std::dec << index << std::endl; #endif - } - else if(m_ivt.is_full() and r_xram_rsp_victim_inval.read()) // IVT full - { - r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT; - m_upt.print(); + } + else if(m_ivt.is_full() and r_xram_rsp_victim_inval.read()) // IVT full + { + r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT; #if DEBUG_MEMC_XRAM_RSP if(m_debug) -std::cout << " " +std::cout << " " << " Get acces to IVT, but inval required and IVT full" << std::endl; #endif - } - else - { - r_xram_rsp_fsm = XRAM_RSP_DIR_UPDT; + } + else + { + r_xram_rsp_fsm = XRAM_RSP_DIR_UPDT; #if DEBUG_MEMC_XRAM_RSP if(m_debug) -std::cout << " " - << " Get acces to IVT" << std::endl; -#endif - } - m_cpt_xram_rsp_fsm_n_upt_lock++; - } - - m_cpt_xram_rsp_fsm_upt_lock++; - - break; +std::cout << " " + << " Get acces to IVT / no pending inval request" << std::endl; +#endif + } + } + break; } ///////////////////////// @@ -4415,34 +4597,39 @@ } /////////////////////// - case XRAM_RSP_DIR_UPDT: // updates the cache (both data & directory) - // and possibly set an inval request in IVT - { - // check if this is an instruction read, this means pktid is either - // TYPE_READ_INS_UNC 0bX010 with TSAR encoding - // TYPE_READ_INS_MISS 0bX011 with TSAR encoding - bool inst_read = (r_xram_rsp_trt_buf.pktid & 0x2) and r_xram_rsp_trt_buf.proc_read; - - // check if this is a cached read, this means pktid is either - // TYPE_READ_DATA_MISS 0bX001 with TSAR encoding - // TYPE_READ_INS_MISS 0bX011 with TSAR encoding - bool cached_read = (r_xram_rsp_trt_buf.pktid & 0x1) and r_xram_rsp_trt_buf.proc_read; - - bool dirty = false; - - // update cache data - size_t set = r_xram_rsp_victim_set.read(); - size_t way = r_xram_rsp_victim_way.read(); - for(size_t word=0; word (m_words,0), - std::vector (m_words,0)); - -#if DEBUG_MEMC_XRAM_RSP -if(m_debug) + if(r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP) + { + std::vector data_vector; + data_vector.clear(); + for(size_t i=0; i(m_words,0xF), + data_vector); + #if DEBUG_MEMC_XRAM_RSP +if(m_debug) + m_trt.print(0); std::cout << " " << " Set TRT entry for the put transaction" << " / dirty victim line = " << r_xram_rsp_victim_nline.read() << std::endl; #endif + + if( not r_xram_rsp_victim_coherent ) + std::cout << "a victim coherent not sent trt index =" << r_xram_rsp_trt_index.read() << std::endl; if(r_xram_rsp_trt_buf.proc_read) r_xram_rsp_fsm = XRAM_RSP_DIR_RSP; else if(r_xram_rsp_victim_inval.read()) r_xram_rsp_fsm = XRAM_RSP_INVAL; @@ -4573,5 +4759,5 @@ case XRAM_RSP_DIR_RSP: // Request a response to TGT_RSP FSM { - if(!r_xram_rsp_to_tgt_rsp_req.read()) + if( not r_xram_rsp_to_tgt_rsp_req.read()) { r_xram_rsp_to_tgt_rsp_srcid = r_xram_rsp_trt_buf.srcid; @@ -4627,19 +4813,17 @@ xram_rsp_to_cc_send_fifo_srcid = r_xram_rsp_victim_copy.read(); xram_rsp_to_cc_send_fifo_inst = r_xram_rsp_victim_copy_inst.read(); -#if L1_MULTI_CACHE - xram_rsp_to_cc_send_fifo_cache_id = r_xram_rsp_victim_copy_cache.read(); -#endif xram_rsp_to_cc_send_fifo_put = multi_req; - r_xram_rsp_next_ptr = r_xram_rsp_victim_ptr.read(); - - if(r_xram_rsp_victim_dirty) r_xram_rsp_fsm = XRAM_RSP_WRITE_DIRTY; + r_xram_rsp_next_ptr = r_xram_rsp_victim_ptr.read(); + + if(r_xram_rsp_victim_dirty and r_xram_rsp_victim_coherent) r_xram_rsp_fsm = XRAM_RSP_WRITE_DIRTY; else if(not_last_multi_req) r_xram_rsp_fsm = XRAM_RSP_HEAP_REQ; else r_xram_rsp_fsm = XRAM_RSP_IDLE; +// std::cout << "cleanup sent for trt index =" << r_xram_rsp_trt_index.read() << std::endl; #if DEBUG_MEMC_XRAM_RSP if(m_debug) std::cout << " " << " Send an inval request to CC_SEND FSM" - << " / victim line = " << r_xram_rsp_victim_nline.read() << std::endl; + << " / address = " << r_xram_rsp_victim_nline.read()*m_words*4 << std::endl; #endif } @@ -4649,29 +4833,17 @@ case XRAM_RSP_WRITE_DIRTY: // send a write request to IXR_CMD FSM { - if(!r_xram_rsp_to_ixr_cmd_req.read() and !r_xram_rsp_to_ixr_cmd_inval_ncc_pending.read()) - { - r_xram_rsp_to_ixr_cmd_req = true; - r_xram_rsp_to_ixr_cmd_nline = r_xram_rsp_victim_nline.read(); - r_xram_rsp_to_ixr_cmd_trdid = r_xram_rsp_trt_index.read(); - for(size_t i=0; i 0) and + "MEMC ERROR in CLEANUP_IVT_CLEAR state"); + + r_config_rsp_lines = r_config_rsp_lines.read() - 1; + } + if ( r_cleanup_need_rsp.read() ) r_cleanup_fsm = CLEANUP_WRITE_RSP; - else if ( r_cleanup_need_ack.read() ) r_cleanup_fsm = CLEANUP_CONFIG_ACK; else if ( r_cleanup_ncc.read() ) r_cleanup_fsm = CLEANUP_IXR_REQ; else r_cleanup_fsm = CLEANUP_SEND_CLACK; @@ -5799,6 +5815,6 @@ << " IVT_index = " << r_cleanup_index.read() << std::endl; #endif - break; - } + break; + } /////////////////////// case CLEANUP_WRITE_RSP: // response to a previous write on the direct network @@ -5812,5 +5828,5 @@ r_cleanup_to_tgt_rsp_trdid = r_cleanup_write_trdid.read(); r_cleanup_to_tgt_rsp_pktid = r_cleanup_write_pktid.read(); - r_cleanup_to_tgt_rsp_type = true; + r_cleanup_to_tgt_rsp_type = true; if (r_cleanup_ncc.read()) @@ -5833,29 +5849,11 @@ break; } - //////////////////////// - case CLEANUP_CONFIG_ACK: // signals inval completion to CONFIG FSM - // wait if pending request - { - if ( r_cleanup_to_config_ack.read() ) break; - - r_cleanup_to_config_ack = true; - r_cleanup_fsm = CLEANUP_SEND_CLACK; - -#if DEBUG_MEMC_CLEANUP -if(m_debug) -std::cout << " " - << " Acknowledge broacast inval completion" << std::endl; -#endif - break; - } - ///////////////////////// case CLEANUP_IXR_REQ: { - //Send a request to the ixr to write the data in the XRAM using the prereserved TRT entry if (r_alloc_trt_fsm.read() == ALLOC_TRT_CLEANUP) { - if(!r_cleanup_to_ixr_cmd_req.read()) + if( not r_cleanup_to_ixr_cmd_req.read()) { size_t index = 0; @@ -5864,19 +5862,39 @@ assert (hit and "CLEANUP_IXR_REQ found no matching entry in TRT"); - r_cleanup_to_ixr_cmd_req = true; - - for(size_t i = 0; i < m_words; i++){ - r_cleanup_to_ixr_cmd_data[i] = r_cleanup_data[i]; + r_cleanup_to_ixr_cmd_req = true; + + if (r_cleanup_contains_data.read()) + { + std::vector data_vector; + data_vector.clear(); + + for(size_t i=0; i (m_words,0), + data_vector); + } +//std::cout << "cleanup with a non coherent ligne in trt index = " << index << std::endl; + r_cleanup_to_ixr_cmd_srcid = r_cleanup_srcid.read(); + r_cleanup_to_ixr_cmd_index = index; + r_cleanup_to_ixr_cmd_pktid = r_cleanup_pktid.read(); + r_cleanup_to_ixr_cmd_nline = r_cleanup_nline.read(); + //r_cleanup_to_ixr_cmd_l1_dirty_ncc = r_cleanup_contains_data.read(); + r_cleanup_fsm = CLEANUP_SEND_CLACK; #if DEBUG_MEMC_CLEANUP if(m_debug) { + m_trt.print(0); std::cout << " 3) // more than 4 flits... - { - std::cout << "VCI_MEM_CACHE ERROR in CAS_IDLE state : illegal CAS command" - << std::endl; - exit(0); - } - - if(r_cas_cpt.read() ==2) + assert( (r_cas_cpt.read() <= 3) and // no more than 4 flits... + "MEMC ERROR in CAS_IDLE state: illegal CAS command"); + + if(r_cas_cpt.read() ==2) r_cas_wdata = m_cmd_cas_wdata_fifo.read(); @@ -6034,6 +6048,7 @@ case CAS_DIR_LOCK: // Read the directory { - if(r_alloc_dir_fsm.read() == ALLOC_DIR_CAS) - { + assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_CAS) and + "MEMC ERROR in CAS_DIR_LOCK: Bad DIR allocation"); + size_t way = 0; DirectoryEntry entry(m_cache_directory.read(m_cmd_cas_addr_fifo.read(), way)); @@ -6045,7 +6060,4 @@ r_cas_way = way; r_cas_copy = entry.owner.srcid; -#if L1_MULTI_CACHE - r_cas_copy_cache = entry.owner.cache_id; -#endif r_cas_copy_inst = entry.owner.inst; r_cas_ptr = entry.ptr; @@ -6065,16 +6077,5 @@ } #endif - } - else - { - std::cout - << "VCI_MEM_CACHE ERROR " << name() - << " CAS_DIR_LOCK state" << std::endl - << "Bad DIR allocation" << std::endl; - - exit(0); - } - - break; + break; } ///////////////////// @@ -6094,7 +6095,4 @@ entry.tag = r_cas_tag.read(); entry.owner.srcid = r_cas_copy.read(); -#if L1_MULTI_CACHE - entry.owner.cache_id = r_cas_copy_cache.read(); -#endif entry.owner.inst = r_cas_copy_inst.read(); entry.count = r_cas_count.read(); @@ -6156,11 +6154,9 @@ { // The CAS is a success => sw access to the llsc_global_table - // BUG LLSC - addr_t nline = m_nline[(addr_t)(m_cmd_cas_addr_fifo.read())]; - m_llsc_table.sw(nline); //m_llsc_table.sw(m_cmd_cas_addr_fifo.read()); /**//*std::cout << "MEMCACHE : from proc " << m_cmd_cas_srcid_fifo.read() << " | @ " << std::hex << m_cmd_cas_addr_fifo.read() << " | WRITE (cas triggered)" << std::endl;*/ + m_llsc_table.sw(m_nline[(addr_t)m_cmd_cas_addr_fifo.read()],m_x[(addr_t)(m_cmd_cas_addr_fifo.read())],m_x[(addr_t)(m_cmd_cas_addr_fifo.read())]); // test coherence request @@ -6170,4 +6166,11 @@ { r_cas_fsm = CAS_BC_TRT_LOCK; // broadcast invalidate required +#if DEBUG_MEMC_CAS +if(m_debug) +std::cout << " " + << " Broacast Inval required" + << " / copies = " << r_cas_count.read() << std::endl; +#endif + } else if(!r_cas_to_cc_send_multi_req.read() and @@ -6175,8 +6178,19 @@ { r_cas_fsm = CAS_UPT_LOCK; // multi update required +#if DEBUG_MEMC_CAS +if(m_debug) +std::cout << " " + << " Multi Inval required" + << " / copies = " << r_cas_count.read() << std::endl; +#endif } else { r_cas_fsm = CAS_WAIT; +#if DEBUG_MEMC_CAS +if(m_debug) +std::cout << " " + << " CC_SEND FSM busy: release all locks and retry" << std::endl; +#endif } } @@ -6193,14 +6207,4 @@ r_cas_fsm = CAS_RSP_SUCCESS; - - // monitor - if(m_monitor_ok) - { - addr_t address = m_cmd_cas_addr_fifo.read(); - check_monitor( address, r_cas_wdata.read(), false); - - if(r_cas_cpt.read() == 4) - check_monitor( address+4, m_cmd_cas_wdata_fifo.read(), false); - } #if DEBUG_MEMC_CAS @@ -6256,13 +6260,4 @@ r_cas_fsm = CAS_UPT_HEAP_LOCK; - // monitor - if(m_monitor_ok) - { - addr_t address = m_cmd_cas_addr_fifo.read(); - check_monitor( address, r_cas_wdata.read(), false); - - if(r_cas_cpt.read() ==4) - check_monitor( address+4, m_cmd_cas_wdata_fifo.read(), false); - } } else // releases the locks protecting UPT and DIR UPT full @@ -6350,7 +6345,4 @@ cas_to_cc_send_fifo_inst = r_cas_copy_inst.read(); cas_to_cc_send_fifo_srcid = r_cas_copy.read(); -#if L1_MULTI_CACHE - cas_to_cc_send_fifo_cache_id= r_cas_copy_cache.read(); -#endif if(r_cas_count.read() == 1) // one single copy { @@ -6387,7 +6379,4 @@ HeapEntry entry = m_heap.read(r_cas_ptr.read()); cas_to_cc_send_fifo_srcid = entry.owner.srcid; -#if L1_MULTI_CACHE - cas_to_cc_send_fifo_cache_id = entry.owner.cache_id; -#endif cas_to_cc_send_fifo_inst = entry.owner.inst; cas_to_cc_send_fifo_put = true; @@ -6421,44 +6410,28 @@ case CAS_BC_TRT_LOCK: // check the TRT to register a PUT transaction { - if(r_alloc_trt_fsm.read() == ALLOC_TRT_CAS) - { - if(!r_cas_to_ixr_cmd_req) // we can transfer the request to IXR_CMD FSM - { - // fill the data buffer - size_t word = m_x[(addr_t)(m_cmd_cas_addr_fifo.read())]; - for(size_t i = 0; i Check TRT" + << " : wok = " << wok << " / index = " << wok_index << std::endl; +#endif + } m_cpt_cas_fsm_trt_lock++; @@ -6502,13 +6475,4 @@ m_cache_data.write(way, set, word+1, m_cmd_cas_wdata_fifo.read()); - // monitor - if(m_monitor_ok) - { - addr_t address = m_cmd_cas_addr_fifo.read(); - check_monitor( address, r_cas_wdata.read(), false); - - if(r_cas_cpt.read() ==4) - check_monitor( address+4, m_cmd_cas_wdata_fifo.read(), false); - } r_cas_upt_index = index; r_cas_fsm = CAS_BC_DIR_INVAL; @@ -6537,20 +6501,36 @@ case CAS_BC_DIR_INVAL: // Register the PUT transaction in TRT, and inval the DIR entry { - if((r_alloc_trt_fsm.read() == ALLOC_TRT_CAS) and - (r_alloc_ivt_fsm.read() == ALLOC_IVT_CAS) and - (r_alloc_dir_fsm.read() == ALLOC_DIR_CAS)) - { - // set TRT - m_trt.set(r_cas_trt_index.read(), - false, // PUT request to XRAM - m_nline[(addr_t)(m_cmd_cas_addr_fifo.read())], - 0, - 0, - 0, - false, // not a processor read - 0, - 0, - std::vector (m_words,0), - std::vector (m_words,0)); + assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_CAS) and + "MEMC ERROR in CAS_BC_DIR_INVAL state: Bad DIR allocation"); + + assert( (r_alloc_trt_fsm.read() == ALLOC_TRT_CAS) and + "MEMC ERROR in CAS_BC_DIR_INVAL state: Bad TRT allocation"); + + assert( (r_alloc_ivt_fsm.read() == ALLOC_IVT_CAS) and + "MEMC ERROR in CAS_BC_DIR_INVAL state: Bad IVT allocation"); + + std::vector data_vector; + data_vector.clear(); + size_t word = m_x[(addr_t)(m_cmd_cas_addr_fifo.read())]; + for(size_t i=0; i (m_words,0), + data_vector ); // invalidate directory entry @@ -6558,12 +6538,9 @@ entry.valid = false; entry.dirty = false; - entry.tag = 0; + entry.tag = 0; entry.is_cnt = false; entry.lock = false; entry.count = 0; entry.owner.srcid = 0; -#if L1_MULTI_CACHE - entry.owner.cache_id= 0; -#endif entry.owner.inst = false; entry.ptr = 0; @@ -6576,14 +6553,8 @@ #if DEBUG_MEMC_CAS if(m_debug) -std::cout << " Register the PUT in TRT and invalidate DIR entry" - << " / nline = " << std::hex << m_nline[(addr_t)(m_cmd_cas_addr_fifo.read())] - << " / set = " << std::dec << set << " / way = " << way << std::endl; -#endif - } - else - { - assert(false and "LOCK ERROR in CAS_FSM, STATE = CAS_BC_DIR_INVAL"); - } + m_trt.print(0); +std::cout << " Inval DIR & register in TRT:" + << " address = " << m_cmd_cas_addr_fifo.read() << std::endl; +#endif break; } @@ -6591,6 +6562,6 @@ case CAS_BC_CC_SEND: // Request the broadcast inval to CC_SEND FSM { - if(!r_cas_to_cc_send_multi_req.read() and - !r_cas_to_cc_send_brdcast_req.read()) + if( not r_cas_to_cc_send_multi_req.read() and + not r_cas_to_cc_send_brdcast_req.read()) { r_cas_to_cc_send_multi_req = false; @@ -6608,10 +6579,9 @@ case CAS_BC_XRAM_REQ: // request the IXR FSM to start a put transaction { - if(!r_cas_to_ixr_cmd_req) + if( not r_cas_to_ixr_cmd_req.read() ) { r_cas_to_ixr_cmd_req = true; - r_cas_to_ixr_cmd_write = true; - r_cas_to_ixr_cmd_nline = m_nline[(addr_t)(m_cmd_cas_addr_fifo.read())]; - r_cas_to_ixr_cmd_trdid = r_cas_trt_index.read(); + r_cas_to_ixr_cmd_put = true; + r_cas_to_ixr_cmd_index = r_cas_trt_index.read(); r_cas_fsm = CAS_IDLE; cmd_cas_fifo_get = true; @@ -6622,13 +6592,9 @@ std::cout << " Request a PUT transaction to IXR_CMD FSM" << std::hex - << " / nline = " << m_nline[(addr_t) m_cmd_cas_addr_fifo.read()] + << " / address = " << (addr_t) m_cmd_cas_addr_fifo.read() << " / trt_index = " << r_cas_trt_index.read() << std::endl; #endif } - else - { - std::cout << "ERROR in MEM_CACHE / CAS_BC_XRAM_REQ state" - << " : request should not have been previously set" << std::endl; - } + break; } @@ -6636,9 +6602,9 @@ case CAS_RSP_FAIL: // request TGT_RSP FSM to send a failure response { - if(!r_cas_to_tgt_rsp_req) - { - cmd_cas_fifo_get = true; + if( not r_cas_to_tgt_rsp_req.read() ) + { + cmd_cas_fifo_get = true; r_cas_cpt = 0; - r_cas_to_tgt_rsp_req = true; + r_cas_to_tgt_rsp_req = true; r_cas_to_tgt_rsp_data = 1; r_cas_to_tgt_rsp_srcid = m_cmd_cas_srcid_fifo.read(); @@ -6658,5 +6624,5 @@ case CAS_RSP_SUCCESS: // request TGT_RSP FSM to send a success response { - if(!r_cas_to_tgt_rsp_req) + if( not r_cas_to_tgt_rsp_req.read() ) { cmd_cas_fifo_get = true; @@ -6687,5 +6653,5 @@ bool hit_write = m_trt.hit_write( m_nline[(addr_t) m_cmd_cas_addr_fifo.read()]); - bool wok = !m_trt.full(index); + bool wok = not m_trt.full(index); #if DEBUG_MEMC_CAS @@ -6719,6 +6685,7 @@ case CAS_MISS_TRT_SET: // register the GET transaction in TRT { - if(r_alloc_trt_fsm.read() == ALLOC_TRT_CAS) - { + assert( (r_alloc_trt_fsm.read() == ALLOC_TRT_CAS) and + "MEMC ERROR in CAS_MISS_TRT_SET state: Bad TRT allocation"); + std::vector be_vector; std::vector data_vector; @@ -6732,14 +6699,14 @@ m_trt.set(r_cas_trt_index.read(), - true, // read request - m_nline[(addr_t) m_cmd_cas_addr_fifo.read()], - m_cmd_cas_srcid_fifo.read(), - m_cmd_cas_trdid_fifo.read(), - m_cmd_cas_pktid_fifo.read(), - false, // write request from processor - 0, - 0, - be_vector, - data_vector); + true, // read request + m_nline[(addr_t) m_cmd_cas_addr_fifo.read()], + m_cmd_cas_srcid_fifo.read(), + m_cmd_cas_trdid_fifo.read(), + m_cmd_cas_pktid_fifo.read(), + false, // write request from processor + 0, + 0, + be_vector, + data_vector); r_cas_fsm = CAS_MISS_XRAM_REQ; @@ -6747,4 +6714,5 @@ if(m_debug) { + m_trt.print(0); std::cout << " Register a GET transaction in TRT" << std::hex << " / nline = " << m_nline[(addr_t) m_cmd_cas_addr_fifo.read()] @@ -6752,5 +6720,4 @@ } #endif - } break; } @@ -6758,19 +6725,16 @@ case CAS_MISS_XRAM_REQ: // request the IXR_CMD FSM to fetch the missing line { - if(!r_cas_to_ixr_cmd_req) + if( not r_cas_to_ixr_cmd_req.read() ) { r_cas_to_ixr_cmd_req = true; - r_cas_to_ixr_cmd_write = false; - r_cas_to_ixr_cmd_trdid = r_cas_trt_index.read(); - r_cas_to_ixr_cmd_nline = m_nline[(addr_t) m_cmd_cas_addr_fifo.read()]; + r_cas_to_ixr_cmd_put = false; + r_cas_to_ixr_cmd_index = r_cas_trt_index.read(); r_cas_fsm = CAS_WAIT; #if DEBUG_MEMC_CAS - if(m_debug) - { - std::cout << " Request a GET transaction to IXR_CMD FSM" << std::hex - << " / nline = " << m_nline[(addr_t) m_cmd_cas_addr_fifo.read()] - << " / trt_index = " << r_cas_trt_index.read() << std::endl; - } +if(m_debug) +std::cout << " Request a GET transaction" + << " / address = " << std::hex << (addr_t) m_cmd_cas_addr_fifo.read() + << " / trt_index = " << std::dec << r_cas_trt_index.read() << std::endl; #endif } @@ -7643,5 +7607,4 @@ r_tgt_rsp_cpt = r_cleanup_to_tgt_rsp_first_word.read(); } - else if(r_config_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CONFIG; else if(r_tgt_cmd_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_TGT_CMD; @@ -7780,5 +7743,5 @@ } ///////////////////// - case TGT_RSP_TGT_CMD: // send the response for a segmentation violation + case TGT_RSP_TGT_CMD: // send the response for a configuration access { if ( p_vci_tgt.rspack ) @@ -7792,8 +7755,9 @@ std::cout << " Segmentation violation response" + << " TGT_RSP_TGT_CMD> Send response for a configuration access" << " / rsrcid = " << std::hex << r_tgt_cmd_to_tgt_rsp_srcid.read() << " / rtrdid = " << r_tgt_cmd_to_tgt_rsp_trdid.read() << " / rpktid = " << r_tgt_cmd_to_tgt_rsp_pktid.read() + << " / error = " << r_tgt_cmd_to_tgt_rsp_error.read() << std::endl; } @@ -7916,5 +7880,4 @@ #endif - uint32_t last_word_idx = r_cleanup_to_tgt_rsp_first_word.read() + r_cleanup_to_tgt_rsp_length.read() - 1; bool is_ll = ((r_cleanup_to_tgt_rsp_pktid.read() & 0x7) == TYPE_LL); @@ -7972,5 +7935,4 @@ } } - } break; @@ -8114,5 +8076,4 @@ else if (r_multi_ack_fsm.read() == MULTI_ACK_UPT_LOCK) r_alloc_upt_fsm = ALLOC_UPT_MULTI_ACK; - else m_cpt_upt_unused++; @@ -8145,5 +8106,4 @@ else if (r_cas_fsm.read() == CAS_UPT_LOCK) r_alloc_upt_fsm = ALLOC_UPT_CAS; - else m_cpt_upt_unused++; @@ -8178,5 +8138,5 @@ r_alloc_ivt_fsm = ALLOC_IVT_READ; - else if (r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK) + else if (r_xram_rsp_fsm.read() == XRAM_RSP_IVT_LOCK) r_alloc_ivt_fsm = ALLOC_IVT_XRAM_RSP; @@ -8188,5 +8148,5 @@ r_alloc_ivt_fsm = ALLOC_IVT_CAS; - else if (r_config_fsm.read() == CONFIG_DIR_IVT_LOCK) + else if (r_config_fsm.read() == CONFIG_IVT_LOCK) r_alloc_ivt_fsm = ALLOC_IVT_CONFIG; @@ -8200,5 +8160,5 @@ if (r_read_fsm.read() != READ_IVT_LOCK) { - if (r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK) + if (r_xram_rsp_fsm.read() == XRAM_RSP_IVT_LOCK) r_alloc_ivt_fsm = ALLOC_IVT_XRAM_RSP; @@ -8210,5 +8170,5 @@ r_alloc_ivt_fsm = ALLOC_IVT_CAS; - else if (r_config_fsm.read() == CONFIG_DIR_IVT_LOCK) + else if (r_config_fsm.read() == CONFIG_IVT_LOCK) r_alloc_ivt_fsm = ALLOC_IVT_CONFIG; @@ -8217,5 +8177,4 @@ (r_write_fsm.read() == WRITE_MISS_IVT_LOCK)) r_alloc_ivt_fsm = ALLOC_IVT_WRITE; - else m_cpt_ivt_unused++; @@ -8225,5 +8184,5 @@ ////////////////////////// case ALLOC_IVT_XRAM_RSP: // allocated to XRAM_RSP FSM - if(r_xram_rsp_fsm.read() != XRAM_RSP_INVAL_LOCK) + if(r_xram_rsp_fsm.read() != XRAM_RSP_IVT_LOCK) { if ((r_cleanup_fsm.read() == CLEANUP_IVT_LOCK) or @@ -8234,5 +8193,5 @@ r_alloc_ivt_fsm = ALLOC_IVT_CAS; - else if (r_config_fsm.read() == CONFIG_DIR_IVT_LOCK) + else if (r_config_fsm.read() == CONFIG_IVT_LOCK) r_alloc_ivt_fsm = ALLOC_IVT_CONFIG; @@ -8259,5 +8218,5 @@ r_alloc_ivt_fsm = ALLOC_IVT_CAS; - else if (r_config_fsm.read() == CONFIG_DIR_IVT_LOCK) + else if (r_config_fsm.read() == CONFIG_IVT_LOCK) r_alloc_ivt_fsm = ALLOC_IVT_CONFIG; @@ -8270,5 +8229,5 @@ r_alloc_ivt_fsm = ALLOC_IVT_READ; - else if (r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK) + else if (r_xram_rsp_fsm.read() == XRAM_RSP_IVT_LOCK) r_alloc_ivt_fsm = ALLOC_IVT_XRAM_RSP; @@ -8282,5 +8241,5 @@ if (r_cas_fsm.read() != CAS_BC_IVT_LOCK) { - if (r_config_fsm.read() == CONFIG_DIR_IVT_LOCK) + if (r_config_fsm.read() == CONFIG_IVT_LOCK) r_alloc_ivt_fsm = ALLOC_IVT_CONFIG; @@ -8293,5 +8252,5 @@ r_alloc_ivt_fsm = ALLOC_IVT_READ; - else if (r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK) + else if (r_xram_rsp_fsm.read() == XRAM_RSP_IVT_LOCK) r_alloc_ivt_fsm = ALLOC_IVT_XRAM_RSP; @@ -8307,5 +8266,5 @@ ////////////////////////// case ALLOC_IVT_CONFIG: // allocated to CONFIG FSM - if (r_config_fsm.read() != CONFIG_DIR_IVT_LOCK) + if (r_config_fsm.read() != CONFIG_IVT_LOCK) { if ((r_write_fsm.read() == WRITE_BC_IVT_LOCK) or @@ -8317,5 +8276,5 @@ r_alloc_ivt_fsm = ALLOC_IVT_READ; - else if (r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK) + else if (r_xram_rsp_fsm.read() == XRAM_RSP_IVT_LOCK) r_alloc_ivt_fsm = ALLOC_IVT_XRAM_RSP; @@ -8326,5 +8285,4 @@ else if(r_cas_fsm.read() == CAS_BC_IVT_LOCK) r_alloc_ivt_fsm = ALLOC_IVT_CAS; - else m_cpt_ivt_unused++; @@ -8361,5 +8319,7 @@ if ( (r_config_fsm.read() != CONFIG_DIR_REQ) and (r_config_fsm.read() != CONFIG_DIR_ACCESS) and - (r_config_fsm.read() != CONFIG_DIR_IVT_LOCK) ) + (r_config_fsm.read() != CONFIG_TRT_LOCK) and + (r_config_fsm.read() != CONFIG_TRT_SET) and + (r_config_fsm.read() != CONFIG_IVT_LOCK) ) { if(r_read_fsm.read() == READ_DIR_REQ) @@ -8417,5 +8377,5 @@ if(((r_write_fsm.read() != WRITE_DIR_REQ) and (r_write_fsm.read() != WRITE_DIR_LOCK) and - (r_write_fsm.read() != WRITE_DIR_READ) and + (r_write_fsm.read() != WRITE_BC_DIR_READ) and (r_write_fsm.read() != WRITE_DIR_HIT) and (r_write_fsm.read() != WRITE_BC_TRT_LOCK) and @@ -8530,5 +8490,5 @@ if( (r_xram_rsp_fsm.read() != XRAM_RSP_DIR_LOCK) and (r_xram_rsp_fsm.read() != XRAM_RSP_TRT_COPY) and - (r_xram_rsp_fsm.read() != XRAM_RSP_INVAL_LOCK)) + (r_xram_rsp_fsm.read() != XRAM_RSP_IVT_LOCK)) { if(r_config_fsm.read() == CONFIG_DIR_REQ) @@ -8579,4 +8539,12 @@ r_alloc_trt_fsm = ALLOC_TRT_CAS; + else if((r_ixr_cmd_fsm.read() == IXR_CMD_READ_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_WRITE_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_CAS_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_XRAM_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_CLEANUP_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_CONFIG_TRT) ) + r_alloc_trt_fsm = ALLOC_TRT_IXR_CMD; + else if((r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) and (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP)) @@ -8587,4 +8555,7 @@ r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP; + else if( r_config_fsm.read() == CONFIG_TRT_LOCK ) + r_alloc_trt_fsm = ALLOC_TRT_CONFIG; + else if (r_cleanup_fsm.read() == CLEANUP_IXR_REQ) r_alloc_trt_fsm = ALLOC_TRT_CLEANUP; @@ -8607,4 +8578,12 @@ r_alloc_trt_fsm = ALLOC_TRT_CAS; + else if((r_ixr_cmd_fsm.read() == IXR_CMD_READ_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_WRITE_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_CAS_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_XRAM_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_CLEANUP_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_CONFIG_TRT) ) + r_alloc_trt_fsm = ALLOC_TRT_IXR_CMD; + else if((r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) and (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP)) @@ -8618,4 +8597,7 @@ r_alloc_trt_fsm = ALLOC_TRT_CLEANUP; + else if( r_config_fsm.read() == CONFIG_TRT_LOCK ) + r_alloc_trt_fsm = ALLOC_TRT_CONFIG; + else if(r_read_fsm.read() == READ_TRT_LOCK) r_alloc_trt_fsm = ALLOC_TRT_READ; @@ -8634,6 +8616,14 @@ (r_cas_fsm.read() != CAS_BC_IVT_LOCK)) { - if((r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) and - (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP)) + if((r_ixr_cmd_fsm.read() == IXR_CMD_READ_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_WRITE_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_CAS_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_XRAM_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_CLEANUP_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_CONFIG_TRT) ) + r_alloc_trt_fsm = ALLOC_TRT_IXR_CMD; + + else if((r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) and + (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP)) r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP; @@ -8645,4 +8635,7 @@ r_alloc_trt_fsm = ALLOC_TRT_CLEANUP; + else if( r_config_fsm.read() == CONFIG_TRT_LOCK ) + r_alloc_trt_fsm = ALLOC_TRT_CONFIG; + else if(r_read_fsm.read() == READ_TRT_LOCK) r_alloc_trt_fsm = ALLOC_TRT_READ; @@ -8658,4 +8651,40 @@ m_cpt_cas_fsm_trt_used++; break; + /////////////////////// + case ALLOC_TRT_IXR_CMD: + if((r_ixr_cmd_fsm.read() != IXR_CMD_READ_TRT) and + (r_ixr_cmd_fsm.read() != IXR_CMD_WRITE_TRT) and + (r_ixr_cmd_fsm.read() != IXR_CMD_CAS_TRT) and + (r_ixr_cmd_fsm.read() != IXR_CMD_XRAM_TRT) and + (r_ixr_cmd_fsm.read() != IXR_CMD_CLEANUP_TRT) and + (r_ixr_cmd_fsm.read() != IXR_CMD_CONFIG_TRT)) + { + if((r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) and + (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP)) + r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP; + + else if((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) or + (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ)) + r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP; + + else if (r_cleanup_fsm.read() == CLEANUP_IXR_REQ) + r_alloc_trt_fsm = ALLOC_TRT_CLEANUP; + + + else if( r_config_fsm.read() == CONFIG_TRT_LOCK ) + r_alloc_trt_fsm = ALLOC_TRT_CONFIG; + + else if(r_read_fsm.read() == READ_TRT_LOCK) + r_alloc_trt_fsm = ALLOC_TRT_READ; + + else if((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) or + (r_write_fsm.read() == WRITE_BC_TRT_LOCK)) + r_alloc_trt_fsm = ALLOC_TRT_WRITE; + + else if((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) or + (r_cas_fsm.read() == CAS_BC_TRT_LOCK)) + r_alloc_trt_fsm = ALLOC_TRT_CAS; + } + break; //////////////////////// @@ -8665,5 +8694,5 @@ (r_xram_rsp_fsm.read() != XRAM_RSP_TRT_COPY) and (r_xram_rsp_fsm.read() != XRAM_RSP_DIR_UPDT) and - (r_xram_rsp_fsm.read() != XRAM_RSP_INVAL_LOCK)) + (r_xram_rsp_fsm.read() != XRAM_RSP_IVT_LOCK)) { if((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) or @@ -8685,4 +8714,15 @@ r_alloc_trt_fsm = ALLOC_TRT_CAS; + else if( r_config_fsm.read() == CONFIG_TRT_LOCK ) + r_alloc_trt_fsm = ALLOC_TRT_CONFIG; + + else if((r_ixr_cmd_fsm.read() == IXR_CMD_READ_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_WRITE_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_CAS_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_XRAM_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_CLEANUP_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_CONFIG_TRT) ) + r_alloc_trt_fsm = ALLOC_TRT_IXR_CMD; + else m_cpt_trt_unused++; @@ -8697,6 +8737,8 @@ (r_ixr_rsp_fsm.read() != IXR_RSP_TRT_READ)) { + if( r_config_fsm.read() == CONFIG_TRT_LOCK ) + r_alloc_trt_fsm = ALLOC_TRT_CONFIG; - if (r_cleanup_fsm.read() == CLEANUP_IXR_REQ) + else if (r_cleanup_fsm.read() == CLEANUP_IXR_REQ) r_alloc_trt_fsm = ALLOC_TRT_CLEANUP; @@ -8711,4 +8753,12 @@ (r_cas_fsm.read() == CAS_BC_TRT_LOCK)) r_alloc_trt_fsm = ALLOC_TRT_CAS; + + else if((r_ixr_cmd_fsm.read() == IXR_CMD_READ_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_WRITE_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_CAS_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_XRAM_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_CLEANUP_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_CONFIG_TRT) ) + r_alloc_trt_fsm = ALLOC_TRT_IXR_CMD; else if((r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) && @@ -8746,6 +8796,54 @@ (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ)) r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP; - } - break; + + else if( r_config_fsm.read() == CONFIG_TRT_LOCK ) + r_alloc_trt_fsm = ALLOC_TRT_CONFIG; + + else if((r_ixr_cmd_fsm.read() == IXR_CMD_READ_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_WRITE_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_CAS_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_XRAM_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_CLEANUP_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_CONFIG_TRT) ) + r_alloc_trt_fsm = ALLOC_TRT_IXR_CMD; + } + break; + ////////////////////// + case ALLOC_TRT_CONFIG: + if((r_config_fsm.read() != CONFIG_TRT_LOCK) and + (r_config_fsm.read() != CONFIG_TRT_SET)) + { + if(r_read_fsm.read() == READ_TRT_LOCK) + r_alloc_trt_fsm = ALLOC_TRT_READ; + + else if((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) or + (r_write_fsm.read() == WRITE_BC_TRT_LOCK)) + r_alloc_trt_fsm = ALLOC_TRT_WRITE; + + else if((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) or + (r_cas_fsm.read() == CAS_BC_TRT_LOCK)) + r_alloc_trt_fsm = ALLOC_TRT_CAS; + + else if((r_ixr_cmd_fsm.read() == IXR_CMD_READ_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_WRITE_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_CAS_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_XRAM_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_CLEANUP_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_CONFIG_TRT) ) + r_alloc_trt_fsm = ALLOC_TRT_IXR_CMD; + + else if((r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) and + (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP)) + r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP; + + else if (r_cleanup_fsm.read() == CLEANUP_IXR_REQ) + r_alloc_trt_fsm = ALLOC_TRT_CLEANUP; + + else if((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) or + (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ)) + r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP; + } + break; + } // end switch alloc_trt_fsm @@ -9034,8 +9132,4 @@ m_write_to_cc_send_srcid_fifo.update( write_to_cc_send_fifo_get, write_to_cc_send_fifo_put, write_to_cc_send_fifo_srcid ); -#if L1_MULTI_CACHE - m_write_to_cc_send_cache_id_fifo.update( write_to_cc_send_fifo_get, write_to_cc_send_fifo_put, - write_to_cc_send_fifo_cache_id ); -#endif //////////////////////////////////////////////////////////////////////////////////// @@ -9047,8 +9141,4 @@ m_config_to_cc_send_srcid_fifo.update( config_to_cc_send_fifo_get, config_to_cc_send_fifo_put, config_to_cc_send_fifo_srcid ); -#if L1_MULTI_CACHE - m_config_to_cc_send_cache_id_fifo.update( config_to_cc_send_fifo_get, config_to_cc_send_fifo_put, - config_to_cc_send_fifo_cache_id ); -#endif //////////////////////////////////////////////////////////////////////////////////// @@ -9060,8 +9150,4 @@ m_xram_rsp_to_cc_send_srcid_fifo.update( xram_rsp_to_cc_send_fifo_get, xram_rsp_to_cc_send_fifo_put, xram_rsp_to_cc_send_fifo_srcid ); -#if L1_MULTI_CACHE - m_xram_rsp_to_cc_send_cache_id_fifo.update( xram_rsp_to_cc_send_fifo_get, xram_rsp_to_cc_send_fifo_put, - xram_rsp_to_cc_send_fifo_cache_id ); -#endif //////////////////////////////////////////////////////////////////////////////////// @@ -9073,9 +9159,4 @@ m_cas_to_cc_send_srcid_fifo.update( cas_to_cc_send_fifo_get, cas_to_cc_send_fifo_put, cas_to_cc_send_fifo_srcid ); -#if L1_MULTI_CACHE - m_cas_to_cc_send_cache_id_fifo.update( cas_to_cc_send_fifo_get, cas_to_cc_send_fifo_put, - cas_to_cc_send_fifo_cache_id ); -#endif - m_cpt_cycles++; @@ -9089,8 +9170,20 @@ // Command signals on the p_vci_ixr port //////////////////////////////////////////////////////////// - - p_vci_ixr.be = 0xFF; // nor transmited to external ram + // DATA width is 8 bytes + // The following values are not transmitted to XRAM + // p_vci_ixr.be + // p_vci_ixr.pktid + // p_vci_ixr.cons + // p_vci_ixr.wrap + // p_vci_ixr.contig + // p_vci_ixr.clen + // p_vci_ixr.cfixed + + p_vci_ixr.plen = 64; + p_vci_ixr.srcid = m_srcid_x; + p_vci_ixr.trdid = r_ixr_cmd_trdid.read(); + p_vci_ixr.address = (addr_t)r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2); + p_vci_ixr.be = 0xFF; p_vci_ixr.pktid = 0; - p_vci_ixr.srcid = m_srcid_x; p_vci_ixr.cons = false; p_vci_ixr.wrap = false; @@ -9098,102 +9191,44 @@ p_vci_ixr.clen = 0; p_vci_ixr.cfixed = false; - p_vci_ixr.plen = 64; - - if(r_ixr_cmd_fsm.read() == IXR_CMD_READ) - { - p_vci_ixr.cmd = vci_param_ext::CMD_READ; - p_vci_ixr.cmdval = true; - p_vci_ixr.address = (addr_t)(r_read_to_ixr_cmd_nline.read() * m_words * 4); - p_vci_ixr.wdata = 0; - p_vci_ixr.trdid = r_read_to_ixr_cmd_trdid.read(); - p_vci_ixr.eop = true; + + if ( (r_ixr_cmd_fsm.read() == IXR_CMD_READ_SEND) or + (r_ixr_cmd_fsm.read() == IXR_CMD_WRITE_SEND) or + (r_ixr_cmd_fsm.read() == IXR_CMD_CAS_SEND) or + (r_ixr_cmd_fsm.read() == IXR_CMD_XRAM_SEND) or + (r_ixr_cmd_fsm.read() == IXR_CMD_CONFIG_SEND) ) + { + p_vci_ixr.cmdval = true; + + if ( r_ixr_cmd_get.read() ) // GET + { + p_vci_ixr.cmd = vci_param_ext::CMD_READ; + p_vci_ixr.wdata = 0; + p_vci_ixr.eop = true; + } + else // PUT + { + size_t word = r_ixr_cmd_word.read(); + p_vci_ixr.cmd = vci_param_ext::CMD_WRITE; + p_vci_ixr.wdata = ((wide_data_t)(r_ixr_cmd_wdata[word].read())) | + ((wide_data_t)(r_ixr_cmd_wdata[word+1].read()) << 32); + p_vci_ixr.eop = (word == (m_words-2)); + } } - else if(r_ixr_cmd_fsm.read() == IXR_CMD_CAS) - { - if(r_cas_to_ixr_cmd_write.read()) - { - size_t word = r_ixr_cmd_cpt.read(); - p_vci_ixr.cmd = vci_param_ext::CMD_WRITE; - p_vci_ixr.cmdval = true; - p_vci_ixr.address = (addr_t)( (r_cas_to_ixr_cmd_nline.read() * m_words + word) * 4 ); - p_vci_ixr.wdata = ((wide_data_t)(r_cas_to_ixr_cmd_data[word].read())) | - ((wide_data_t)(r_cas_to_ixr_cmd_data[word+1].read()) << 32); - p_vci_ixr.trdid = r_cas_to_ixr_cmd_trdid.read(); - p_vci_ixr.eop = (r_ixr_cmd_cpt == (m_words-2)); - } - else - { - p_vci_ixr.cmd = vci_param_ext::CMD_READ; - p_vci_ixr.cmdval = true; - p_vci_ixr.address = (addr_t)(r_cas_to_ixr_cmd_nline.read() *m_words*4); - p_vci_ixr.wdata = 0; - p_vci_ixr.trdid = r_cas_to_ixr_cmd_trdid.read(); - p_vci_ixr.eop = true; - } - } - else if(r_ixr_cmd_fsm.read() == IXR_CMD_WRITE) - { - if(r_write_to_ixr_cmd_write.read()) - { - p_vci_ixr.cmd = vci_param_ext::CMD_WRITE; - p_vci_ixr.cmdval = true; - p_vci_ixr.address = (addr_t)( (r_write_to_ixr_cmd_nline.read() * m_words + - r_ixr_cmd_cpt.read()) * 4 ); - p_vci_ixr.wdata = ((wide_data_t)(r_write_to_ixr_cmd_data[r_ixr_cmd_cpt.read()].read()) | - ((wide_data_t)(r_write_to_ixr_cmd_data[r_ixr_cmd_cpt.read()+1].read()) << 32)); - p_vci_ixr.trdid = r_write_to_ixr_cmd_trdid.read(); - p_vci_ixr.eop = (r_ixr_cmd_cpt == (m_words-2)); - } - else - { - p_vci_ixr.cmd = vci_param_ext::CMD_READ; - p_vci_ixr.cmdval = true; - p_vci_ixr.address = (addr_t)(r_write_to_ixr_cmd_nline.read() *m_words*4); - p_vci_ixr.wdata = 0; - p_vci_ixr.trdid = r_write_to_ixr_cmd_trdid.read(); - p_vci_ixr.eop = true; - } - } - else if(r_ixr_cmd_fsm.read() == IXR_CMD_XRAM) - { - p_vci_ixr.cmd = vci_param_ext::CMD_WRITE; - p_vci_ixr.cmdval = true; - p_vci_ixr.address = (addr_t)( (r_xram_rsp_to_ixr_cmd_nline.read() * m_words + - r_ixr_cmd_cpt.read()) * 4 ); - p_vci_ixr.wdata = ((wide_data_t)(r_xram_rsp_to_ixr_cmd_data[r_ixr_cmd_cpt.read()].read()) | - ((wide_data_t)(r_xram_rsp_to_ixr_cmd_data[r_ixr_cmd_cpt.read()+1].read()) << 32)); - p_vci_ixr.trdid = r_xram_rsp_to_ixr_cmd_trdid.read(); - p_vci_ixr.eop = (r_ixr_cmd_cpt == (m_words-2)); - } - else if (r_ixr_cmd_fsm.read() == IXR_CMD_CLEANUP_DATA) + else if (r_ixr_cmd_fsm.read() == IXR_CMD_CLEANUP_DATA_SEND) { p_vci_ixr.cmd = vci_param_ext::CMD_WRITE; p_vci_ixr.cmdval = true; - p_vci_ixr.address = (addr_t)((r_cleanup_to_ixr_cmd_nline.read() * m_words + r_ixr_cmd_cpt.read()) * 4); - if (r_cleanup_to_ixr_cmd_ncc_l1_dirty.read()) //if L1 was dirty, the correct data is in the cleanup - { - p_vci_ixr.wdata = ((wide_data_t)(r_cleanup_to_ixr_cmd_data[r_ixr_cmd_cpt.read()].read()) | - ((wide_data_t)(r_cleanup_to_ixr_cmd_data[r_ixr_cmd_cpt.read()+1].read()) << 32)); - if(r_cleanup_to_ixr_cmd_nline.read() == 0x12bb) - std::cout << "IXR data dirty = " << std::hex << p_vci_ixr.wdata << std::dec << std::endl; - } - else //if L1 was not dirty, the data is in the L2 - { - p_vci_ixr.wdata = ((wide_data_t)(r_xram_rsp_to_ixr_cmd_data[r_ixr_cmd_cpt.read()].read()) | - ((wide_data_t)(r_xram_rsp_to_ixr_cmd_data[r_ixr_cmd_cpt.read()+1].read()) << 32)); - if(r_cleanup_to_ixr_cmd_nline.read() == 0x12bb) - std::cout << "IXR data not dirty = " << std::hex << p_vci_ixr.wdata << std::dec << std::endl; - } - p_vci_ixr.trdid = r_cleanup_to_ixr_cmd_trdid.read(); - p_vci_ixr.eop = (r_ixr_cmd_cpt == (m_words - 2)); + /*p_vci_ixr.address = (addr_t)((r_cleanup_to_ixr_cmd_nline.read() * m_words + + r_ixr_cmd_word.read()) * 4);*/ + p_vci_ixr.address = (addr_t)r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2); + p_vci_ixr.wdata = ((wide_data_t)(r_ixr_cmd_wdata[r_ixr_cmd_word.read()].read()) | + ((wide_data_t)(r_ixr_cmd_wdata[r_ixr_cmd_word.read() + 1].read()) << 32)); + p_vci_ixr.trdid = r_cleanup_to_ixr_cmd_index.read(); + p_vci_ixr.eop = (r_ixr_cmd_word == (m_words - 2)); } + else { - p_vci_ixr.cmdval = false; - p_vci_ixr.cmd = vci_param_ext::CMD_READ; - p_vci_ixr.address = 0; - p_vci_ixr.wdata = 0; - p_vci_ixr.trdid = 0; - p_vci_ixr.eop = false; + p_vci_ixr.cmdval = false; } @@ -9202,12 +9237,17 @@ //////////////////////////////////////////////////// - if(((r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP) and - (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ)) or - (r_ixr_rsp_fsm.read() == IXR_RSP_ACK)) - - p_vci_ixr.rspack = true; - - else - p_vci_ixr.rspack = false; + if( (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ) or + (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) ) + { + p_vci_ixr.rspack = (r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP); + } + else if (r_ixr_rsp_fsm.read() == IXR_RSP_ACK) + { + p_vci_ixr.rspack = true; + } + else // r_ixr_rsp_fsm == IXR_RSP_IDLE + { + p_vci_ixr.rspack = false; + } //////////////////////////////////////////////////// @@ -9279,5 +9319,5 @@ { p_vci_tgt.rspval = true; - p_vci_tgt.rdata = 0; + p_vci_tgt.rdata = r_tgt_cmd_to_tgt_rsp_rdata.read(); p_vci_tgt.rsrcid = r_tgt_cmd_to_tgt_rsp_srcid.read(); p_vci_tgt.rtrdid = r_tgt_cmd_to_tgt_rsp_trdid.read(); @@ -9904,42 +9944,18 @@ //////////////////////////////////////////////////////////////////// - switch(r_cleanup_fsm.read()) + if ( r_cleanup_fsm.read() == CLEANUP_SEND_CLACK ) { - case CLEANUP_IDLE: - case CLEANUP_GET_NLINE: - case CLEANUP_DIR_REQ: - case CLEANUP_DIR_LOCK: - case CLEANUP_DIR_WRITE: - case CLEANUP_HEAP_REQ: - case CLEANUP_HEAP_LOCK: - case CLEANUP_HEAP_SEARCH: - case CLEANUP_HEAP_CLEAN: - case CLEANUP_HEAP_FREE: - case CLEANUP_IVT_LOCK: - case CLEANUP_IVT_DECREMENT: - case CLEANUP_IVT_CLEAR: - case CLEANUP_WRITE_RSP: - case CLEANUP_CONFIG_ACK: - p_dspin_clack.write = false; - p_dspin_clack.eop = false; - p_dspin_clack.data = 0; - - break; - - case CLEANUP_SEND_CLACK: - { - uint8_t cleanup_ack_type; - if(r_cleanup_inst.read()) - { + uint8_t cleanup_ack_type; + if(r_cleanup_inst.read()) + { cleanup_ack_type = DspinDhccpParam::TYPE_CLACK_INST; - } - else - { + } + else + { cleanup_ack_type = DspinDhccpParam::TYPE_CLACK_DATA; - } - - uint64_t flit = 0; - uint64_t dest = - r_cleanup_srcid.read() << + } + + uint64_t flit = 0; + uint64_t dest = r_cleanup_srcid.read() << (DspinDhccpParam::SRCID_WIDTH - vci_param_int::S); @@ -9964,11 +9980,14 @@ DspinDhccpParam::CLACK_TYPE); - p_dspin_clack.eop = true; - p_dspin_clack.write = true; - p_dspin_clack.data = flit; - } - break; + p_dspin_clack.eop = true; + p_dspin_clack.write = true; + p_dspin_clack.data = flit; } - + else + { + p_dspin_clack.write = false; + p_dspin_clack.eop = false; + p_dspin_clack.data = 0; + } /////////////////////////////////////////////////////////////////// // p_dspin_p2m port (CC_RECEIVE FSM)