Ignore:
Timestamp:
Jun 13, 2010, 11:16:35 AM (14 years ago)
Author:
gao
Message:

Activity counter update

Location:
trunk/modules/vci_cc_vcache_wrapper2_v1/caba/source
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • trunk/modules/vci_cc_vcache_wrapper2_v1/caba/source/include/vci_cc_vcache_wrapper2_v1.h

    r48 r50  
    482482    uint32_t m_cpt_ins_tlb_occup_cache;     // number of instruction tlb occupy data cache line
    483483    uint32_t m_cpt_data_tlb_occup_cache;    // number of data tlb occupy data cache line
    484     uint32_t m_cpt_tlb_occupy_dcache;
     484    uint32_t m_cpt_tlb_occup_dcache;
    485485   
    486486    uint32_t m_cost_ins_tlb_miss_frz;       // number of frozen cycles related to instruction tlb miss
     
    514514    uint32_t m_cpt_cc_inval_data;               // number of coherence inval data packets
    515515    uint32_t m_cpt_cc_broadcast;                // number of coherence broadcast packets
     516    uint32_t m_cpt_cc_cleanup_ins;              // number of coherence cleanup packets
     517    uint32_t m_cpt_cc_cleanup_data;             // number of coherence cleanup packets
     518
     519    uint32_t m_cpt_icleanup_transaction;        // number of instruction cleanup transactions
     520    uint32_t m_cpt_dcleanup_transaction;        // number of instructinumber of data cleanup transactions
     521    uint32_t m_cost_icleanup_transaction;       // cumulated duration for VCI instruction cleanup transactions
     522    uint32_t m_cost_dcleanup_transaction;       // cumulated duration for VCI data cleanup transactions
    516523
    517524    uint32_t m_cost_ins_tlb_inval_frz;      // number of frozen cycles related to checking ins tlb invalidate
  • trunk/modules/vci_cc_vcache_wrapper2_v1/caba/source/src/vci_cc_vcache_wrapper2_v1.cpp

    r48 r50  
    938938        if (r_dcache_xtn_req)
    939939        {
    940             if ( ireq.valid ) m_cost_ins_waste_wait_frz++;
    941            
    942940            if ((int)r_dcache_type_save == (int)iss_t::XTN_PTPR ) 
    943941            {
     
    19961994        }
    19971995        if( (( r_icache_fsm_save == ICACHE_TLB1_READ )   || ( r_icache_fsm_save == ICACHE_TLB2_READ )    ||
    1998              ( r_icache_fsm_save == ICACHE_TLB1_WRITR )  || ( r_icache_fsm_save == ICACHE_TLB2_WRITE ) ||
     1996             ( r_icache_fsm_save == ICACHE_TLB1_WRITE )  || ( r_icache_fsm_save == ICACHE_TLB2_WRITE ) ||
    19991997             ( r_icache_fsm_save == ICACHE_TLB1_UPDT )   || ( r_icache_fsm_save == ICACHE_TLB2_UPDT ))   && (ireq.valid) )
    20001998        {
     
    20272025        }
    20282026        if( (( r_icache_fsm_save == ICACHE_TLB1_READ )   || ( r_icache_fsm_save == ICACHE_TLB2_READ )    ||
    2029              ( r_icache_fsm_save == ICACHE_TLB1_WRITR )  || ( r_icache_fsm_save == ICACHE_TLB2_WRITE ) ||
     2027             ( r_icache_fsm_save == ICACHE_TLB1_WRITE )  || ( r_icache_fsm_save == ICACHE_TLB2_WRITE ) ||
    20302028             ( r_icache_fsm_save == ICACHE_TLB1_UPDT )   || ( r_icache_fsm_save == ICACHE_TLB2_UPDT ))   && (ireq.valid) )
    20312029        {
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