Index: trunk/modules/vci_cc_vcache_wrapper2_v1/caba/source/include/vci_cc_vcache_wrapper2_v1.h
===================================================================
--- trunk/modules/vci_cc_vcache_wrapper2_v1/caba/source/include/vci_cc_vcache_wrapper2_v1.h	(revision 49)
+++ trunk/modules/vci_cc_vcache_wrapper2_v1/caba/source/include/vci_cc_vcache_wrapper2_v1.h	(revision 50)
@@ -482,5 +482,5 @@
     uint32_t m_cpt_ins_tlb_occup_cache;     // number of instruction tlb occupy data cache line 
     uint32_t m_cpt_data_tlb_occup_cache;    // number of data tlb occupy data cache line
-    uint32_t m_cpt_tlb_occupy_dcache;
+    uint32_t m_cpt_tlb_occup_dcache;
     
     uint32_t m_cost_ins_tlb_miss_frz;       // number of frozen cycles related to instruction tlb miss
@@ -514,4 +514,11 @@
     uint32_t m_cpt_cc_inval_data;               // number of coherence inval data packets
     uint32_t m_cpt_cc_broadcast;                // number of coherence broadcast packets
+    uint32_t m_cpt_cc_cleanup_ins;              // number of coherence cleanup packets
+    uint32_t m_cpt_cc_cleanup_data;             // number of coherence cleanup packets
+
+    uint32_t m_cpt_icleanup_transaction;        // number of instruction cleanup transactions
+    uint32_t m_cpt_dcleanup_transaction;        // number of instructinumber of data cleanup transactions
+    uint32_t m_cost_icleanup_transaction;       // cumulated duration for VCI instruction cleanup transactions
+    uint32_t m_cost_dcleanup_transaction;       // cumulated duration for VCI data cleanup transactions
 
     uint32_t m_cost_ins_tlb_inval_frz;      // number of frozen cycles related to checking ins tlb invalidate
Index: trunk/modules/vci_cc_vcache_wrapper2_v1/caba/source/src/vci_cc_vcache_wrapper2_v1.cpp
===================================================================
--- trunk/modules/vci_cc_vcache_wrapper2_v1/caba/source/src/vci_cc_vcache_wrapper2_v1.cpp	(revision 49)
+++ trunk/modules/vci_cc_vcache_wrapper2_v1/caba/source/src/vci_cc_vcache_wrapper2_v1.cpp	(revision 50)
@@ -938,6 +938,4 @@
         if (r_dcache_xtn_req)
         {
-            if ( ireq.valid ) m_cost_ins_waste_wait_frz++;
-            
             if ((int)r_dcache_type_save == (int)iss_t::XTN_PTPR )  
             {
@@ -1996,5 +1994,5 @@
         }
         if( (( r_icache_fsm_save == ICACHE_TLB1_READ )   || ( r_icache_fsm_save == ICACHE_TLB2_READ )    ||
-             ( r_icache_fsm_save == ICACHE_TLB1_WRITR )  || ( r_icache_fsm_save == ICACHE_TLB2_WRITE ) ||
+             ( r_icache_fsm_save == ICACHE_TLB1_WRITE )  || ( r_icache_fsm_save == ICACHE_TLB2_WRITE ) ||
              ( r_icache_fsm_save == ICACHE_TLB1_UPDT )   || ( r_icache_fsm_save == ICACHE_TLB2_UPDT ))   && (ireq.valid) )
         {
@@ -2027,5 +2025,5 @@
         }
         if( (( r_icache_fsm_save == ICACHE_TLB1_READ )   || ( r_icache_fsm_save == ICACHE_TLB2_READ )    ||
-             ( r_icache_fsm_save == ICACHE_TLB1_WRITR )  || ( r_icache_fsm_save == ICACHE_TLB2_WRITE ) ||
+             ( r_icache_fsm_save == ICACHE_TLB1_WRITE )  || ( r_icache_fsm_save == ICACHE_TLB2_WRITE ) ||
              ( r_icache_fsm_save == ICACHE_TLB1_UPDT )   || ( r_icache_fsm_save == ICACHE_TLB2_UPDT ))   && (ireq.valid) )
         {