Changeset 525 for branches

Timestamp:

Sep 16, 2013, 4:27:16 PM (11 years ago)

Author:

haoliu

Message:

bug fixed in the component memcache(RWT):
There was some confusions when use the ivt and upt table

File:

• branches/RWT/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp (modified) (17 diffs)

branches/RWT/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp

@@ -1925 +1925 @@
 #if DEBUG_MEMC_CONFIG
 if(m_debug)
-          m_trt.print(0);
 std::cout << "  <MEMC " << name() << " CONFIG_TRT_SET> PUT request in TRT:"
           << " address = " << std::hex << r_config_address.read()
@@ -2333 +2332 @@
                   << "CC_SEND req = " << r_read_to_cc_send_req.read() << std::endl
                   << "CLENAUP req = " <<r_read_to_cleanup_req.read() << std::endl;*/
-        if(m_upt.search_inval(nline, index) or m_upt.is_full() or r_read_to_cc_send_req.read() or r_read_to_cleanup_req.read()) //Check pending inval
+        if(m_ivt.search_inval(nline, index) or m_ivt.is_full() or r_read_to_cc_send_req.read() or r_read_to_cleanup_req.read()) //Check pending inval
         {
           r_read_fsm = READ_WAIT;
@@ -2363 +2362 @@
           //std::cout << "cleanup req (read) on line " << nline << " /on proc " << r_read_copy.read() << std::endl;
 
-          m_upt.set(false,  // it's an inval transaction
-                          false,     // it's not a broadcast
-                          false,     // it needs a read response
-                          false,     // no acknowledge required
-                          m_cmd_read_srcid_fifo.read(),
-                          m_cmd_read_trdid_fifo.read(),
-                          m_cmd_read_pktid_fifo.read(),
-                          nline,
-                          0x1, //Expect only one answer
-                          index);
+          m_ivt.set(false,     // it's an inval transaction
+                    false,     // it's not a broadcast
+                    false,     // it needs a read response
+                    false,     // no acknowledge required
+                    m_cmd_read_srcid_fifo.read(),
+                    m_cmd_read_trdid_fifo.read(),
+                    m_cmd_read_pktid_fifo.read(),
+                    nline,
+                    0x1, //Expect only one answer
+                    index);
 
           cmd_read_fifo_get = true;
@@ -2787 +2786 @@
 #if DEBUG_MEMC_READ
 if(m_debug)
-          m_trt.print(0);
 std::cout << "  <MEMC " << name() << " READ_TRT_SET> Set a GET in TGT:"
           << " address = " << std::hex << m_cmd_read_addr_fifo.read()
@@ -3089 +3087 @@
 
         //std::cout << "WRITE on NCC on line" << std::hex << nline << std::dec << std::endl;
-
-        match_inval = m_upt.search_inval(nline, index);
+        //if there is a matched updt req, we should wait until it is over. Because 
+        //we need the lastest updt data.
+        match_inval = m_ivt.search_inval(nline, index);
+        
         assert ((r_write_count.read() == 1) and "NCC to CC req without copy");
         if(!match_inval and !r_write_to_cc_send_req.read())
@@ -3100 +3100 @@
           r_write_to_cleanup_nline = nline;
 
-          m_upt.set(false,  // it's an inval transaction
-                          false,     // it's not a broadcast
-                          true,      // it needs no read response
-                          false,     // no acknowledge required
-                          m_cmd_write_srcid_fifo.read(), //never read, used for debug
-                          m_cmd_write_trdid_fifo.read(), //never read, used for debug
-                          m_cmd_write_pktid_fifo.read(), //never read, used for debug
-                          nline,
-                          0x1, //Expect only one answer
-                          index);
+          m_ivt.set(false,  // it's an inval transaction
+                    false,     // it's not a broadcast
+                    true,      // it needs no read response
+                    false,     // no acknowledge required
+                    m_cmd_write_srcid_fifo.read(), //never read, used for debug
+                    m_cmd_write_trdid_fifo.read(), //never read, used for debug
+                    m_cmd_write_pktid_fifo.read(), //never read, used for debug
+                    nline,
+                    0x1, //Expect only one answer
+                    index);
         }
         r_write_fsm = WRITE_WAIT;
@@ -3159 +3159 @@
       // owner is true when the  the first registered copy is the writer itself
       bool owner = (((r_write_copy.read() == r_write_srcid.read())
-#if L1_MULTI_CACHE
-                     and(r_write_copy_cache.read() ==r_write_pktid.read())
-#endif
                     ) and not r_write_copy_inst.read());
 
@@ -3540 +3537 @@
     }
     ///////////////////////// RWT
-    case WRITE_MISS_IVT_LOCK: // Miss : check UPT 
+    case WRITE_MISS_IVT_LOCK: 
     {
       if (r_alloc_ivt_fsm.read() == ALLOC_IVT_WRITE)
       {
         size_t index;
-        if(m_upt.search_inval(m_nline[(addr_t)(r_write_address.read())], index))
+        if(m_ivt.search_inval(m_nline[(addr_t)(r_write_address.read())], index))
         {
           r_write_fsm = WRITE_WAIT;
@@ -3626 +3623 @@
         }
         m_trt.set(r_write_trt_index.read(),
-                              true,     // read request to XRAM
-                              m_nline[(addr_t)(r_write_address.read())],
-                              r_write_srcid.read(),
-                              r_write_trdid.read(),
-                              r_write_pktid.read(),
-                              false,      // not a processor read
-                              0,        // not a single word
-                              0,            // word index
-                              be_vector,
-                              data_vector);
+                  true,     // read request to XRAM
+                  m_nline[(addr_t)(r_write_address.read())],
+                  r_write_srcid.read(),
+                  r_write_trdid.read(),
+                  r_write_pktid.read(),
+                  false,      // not a processor read
+                  0,        // not a single word
+                  0,            // word index
+                  be_vector,
+                  data_vector);
         r_write_fsm = WRITE_MISS_XRAM_REQ;
 
 #if DEBUG_MEMC_WRITE
 if(m_debug)
-        m_trt.print(0);
 std::cout << "  <MEMC " << name() << " WRITE_MISS_TRT_SET> Set a new entry in TRT" << std::endl;
 #endif
@@ -3853 +3849 @@
 #if DEBUG_MEMC_WRITE
 if(m_debug)
-          m_trt.print(0);
 std::cout << "  <MEMC " << name() << " WRITE_BC_DIR_INVAL> Invalidate the directory entry: @ = "
           << r_write_address.read() << " / register the put transaction in TRT:" << std::endl;
@@ -4738 +4733 @@
  #if DEBUG_MEMC_XRAM_RSP
 if(m_debug)
-            m_trt.print(0);
 std::cout << "  <MEMC " << name() << " XRAM_RSP_TRT_DIRTY>"
           << " Set TRT entry for the put transaction"
@@ -4744 +4738 @@
 #endif
         
-        if( not r_xram_rsp_victim_coherent )
-            std::cout << "a victim coherent not sent trt index =" << r_xram_rsp_trt_index.read() << std::endl;
+//        if( not r_xram_rsp_victim_coherent )
+//            std::cout << "a victim coherent not sent trt index =" << r_xram_rsp_trt_index.read() << std::endl;
         if(r_xram_rsp_trt_buf.proc_read)         r_xram_rsp_fsm = XRAM_RSP_DIR_RSP;
         else if(r_xram_rsp_victim_inval.read())  r_xram_rsp_fsm = XRAM_RSP_INVAL;
@@ -5368 +5362 @@
         bool   match_inval;
 
-        match_inval = m_upt.search_inval(r_cleanup_nline.read(), index);
+        match_inval = m_ivt.search_inval(r_cleanup_nline.read(), index);
         assert (match_inval && "VCI MEM CACHE ERROR: In CLEANUP_IVT_LOCK_DATA, NO CORRESPONDING INVAL");
-        r_cleanup_read_srcid    = m_upt.srcid(index);
-        r_cleanup_read_trdid    = m_upt.trdid(index);
-        r_cleanup_read_pktid    = 0x0 + m_upt.pktid(index);
-        r_cleanup_read_need_rsp = !m_upt.need_rsp(index);
+        r_cleanup_read_srcid    = m_ivt.srcid(index);
+        r_cleanup_read_trdid    = m_ivt.trdid(index);
+        r_cleanup_read_pktid    = 0x0 + m_ivt.pktid(index);
+        r_cleanup_read_need_rsp = !m_ivt.need_rsp(index);
         r_cleanup_index         = index;
 
@@ -5393 +5387 @@
     case CLEANUP_IVT_CLEAR_DATA://RWT
     {
-      m_upt.clear(r_cleanup_index.read());
+      m_ivt.clear(r_cleanup_index.read());
       assert ((r_cleanup_read_need_rsp.read() == (r_read_to_cleanup_req.read() && (r_cleanup_nline.read() == r_read_to_cleanup_nline.read()))) && "condition pending read");
       if (r_cleanup_read_need_rsp.read())
@@ -5896 +5890 @@
       if(m_debug)
       {
-        m_trt.print(0);
         std::cout
             << "  <MEMC " << name()
@@ -6553 +6546 @@
 #if DEBUG_MEMC_CAS
 if(m_debug)
-        m_trt.print(0);
 std::cout << "  <MEMC " << name() << " CAS_BC_DIR_INVAL> Inval DIR & register in TRT:"
           << " address = " << m_cmd_cas_addr_fifo.read() << std::endl;
@@ -6714 +6706 @@
         if(m_debug)
         {
-          m_trt.print(0);
           std::cout << "  <MEMC " << name() << " CAS_MISS_TRT_SET> Register a GET transaction in TRT" << std::hex
                     << " / nline = " << m_nline[(addr_t) m_cmd_cas_addr_fifo.read()]