Changeset 527
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- Unmodified
- Added
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trunk/lib/generic_llsc_global_table/include/generic_llsc_global_table.h
r524 r527 28 28 #define SOCLIB_GENERIC_LLSC_GLOBAL_TABLE_H 29 29 30 #include <systemc>31 #include <arithmetics.h>32 30 #include <cassert> 33 31 #include <cstring> … … 35 33 #include <iostream> 36 34 #include <iomanip> 35 #include <stdint.h> 37 36 38 37 namespace soclib … … 70 69 71 70 uint32_t r_next_key ; // value of the next key 72 sc_dt::sc_uint<nb_slots>r_block_mask ; // mask for the slots blocks73 sc_dt::sc_uint<nb_slots>r_last_counter ; // mask for the slots blocks71 uint64_t r_block_mask ; // mask for the slots blocks 72 uint64_t r_last_counter ; // mask for the slots blocks 74 73 size_t r_write_ptr ; // index of next slot to replace 75 74 size_t r_last_empty ; // index of last empty slot used 76 75 77 uint32_t m_cpt_evic ; // number of eviction in the table 78 uint32_t m_cpt_ll ; // number of ll accesses to the table 79 uint32_t m_cpt_ll_update ; // number of ll accesses to the table that trigger an update TODO check that 80 uint32_t m_cpt_sc ; // number of sc accesses to the table 81 uint32_t m_cpt_sc_success ; // number of sc accesses to the table that are successful 82 uint32_t m_cpt_sw ; // number of sw accesses to the table 76 mutable uint32_t m_cpt_evic ; // number of eviction in the table 77 mutable uint32_t m_cpt_ll ; // number of ll accesses to the table 78 mutable uint32_t m_cpt_ll_update ; // number of ll accesses to the table that trigger an update TODO check that 79 mutable uint32_t m_cpt_sc ; // number of sc accesses to the table 80 mutable uint32_t m_cpt_sc_success ; // number of sc accesses to the table that are successful 81 mutable uint32_t m_cpt_check ; // number of check accesses to the table 82 mutable uint32_t m_cpt_sw ; // number of sw accesses to the table 83 83 84 84 //////////////////////////////////////////////////////////////////////////// … … 121 121 // This is done by updating the value of r_write_ptr 122 122 { 123 sc_dt::sc_uint<nb_slots>new_counter;124 sc_dt::sc_uint<nb_slots>xor_counter;123 uint64_t new_counter; 124 uint64_t xor_counter; 125 125 126 126 new_counter = newCounter(r_block_mask, r_last_counter); … … 129 129 for (size_t i = nb_slots - 1; i >= 0; --i) 130 130 { 131 if(xor_counter [i])131 if(xor_counter & (1 << i)) 132 132 { 133 133 r_write_ptr = i; … … 140 140 141 141 //////////////////////////////////////////////////////////////////////////// 142 inline sc_dt::sc_uint<nb_slots> newCounter(const sc_dt::sc_uint<nb_slots>& mask,143 const sc_dt::sc_uint<nb_slots>& counter)142 inline uint64_t newCounter(const uint64_t& mask, 143 const uint64_t& counter) const 144 144 // This function generates the new counter //TODO comment more 145 145 { 146 //147 146 return ((((~counter) & (counter << 1)) & mask) | (counter + 1)); 148 147 } … … 164 163 { 165 164 case 12: 166 r_block_mask = sc_dt::sc_uint<nb_slots>("0x000");165 r_block_mask = (uint64_t)0x000ULL; 167 166 break; 168 167 case 16 : 169 r_block_mask = sc_dt::sc_uint<nb_slots>("0xA800");168 r_block_mask = (uint64_t)0xA800ULL; 170 169 break; 171 170 case 20 : 172 r_block_mask = sc_dt::sc_uint<nb_slots>("0xD5500");171 r_block_mask = (uint64_t)0xD5500ULL; 173 172 break; 174 173 case 24 : 175 r_block_mask = sc_dt::sc_uint<nb_slots>("0xDB5540");174 r_block_mask = (uint64_t)0xDB5540ULL; 176 175 break; 177 176 case 28 : 178 r_block_mask = sc_dt::sc_uint<nb_slots>("0xEEDAAA0");177 r_block_mask = (uint64_t)0xEEDAAA0ULL; 179 178 break; 180 179 case 32 : 181 r_block_mask = sc_dt::sc_uint<nb_slots>("0xF776D550");180 r_block_mask = (uint64_t)0xF776D550ULL; 182 181 break; 183 182 case 36 : 184 r_block_mask = sc_dt::sc_uint<nb_slots>("0xFBDDDB550");183 r_block_mask = (uint64_t)0xFBDDDB550ULL; 185 184 break; 186 185 case 40 : 187 r_block_mask = sc_dt::sc_uint<nb_slots>("0xFDF7BB6D50");186 r_block_mask = (uint64_t)0xFDF7BB6D50ULL; 188 187 break; 189 188 case 44 : 190 r_block_mask = sc_dt::sc_uint<nb_slots>("0xFEFBDEEDAA8");189 r_block_mask = (uint64_t)0xFEFBDEEDAA8ULL; 191 190 break; 192 191 case 48 : 193 r_block_mask = sc_dt::sc_uint<nb_slots>("0xFF7EFBDDDAA8");192 r_block_mask = (uint64_t)0xFF7EFBDDDAA8ULL; 194 193 break; 195 194 case 52 : 196 r_block_mask = sc_dt::sc_uint<nb_slots>("0xFFBFBF7BBB6A8");195 r_block_mask = (uint64_t)0xFFBFBF7BBB6A8ULL; 197 196 break; 198 197 case 56 : 199 r_block_mask = sc_dt::sc_uint<nb_slots>("0xFFDFEFDF7BB6A8");198 r_block_mask = (uint64_t)0xFFDFEFDF7BB6A8ULL; 200 199 break; 201 200 case 60 : 202 r_block_mask = sc_dt::sc_uint<nb_slots>("0xFFF7FDFDF7BB6A8");201 r_block_mask = (uint64_t)0xFFF7FDFDF7BB6A8ULL; 203 202 break; 204 203 case 64 : 205 r_block_mask = sc_dt::sc_uint<nb_slots>("0xFFFBFF7FBF7BB6A8");204 r_block_mask = (uint64_t)0xFFFBFF7FBF7BB6A8ULL; 206 205 break; 207 206 default: … … 211 210 212 211 //////////////////////////////////////////////////////////////////////////// 213 inline int nextEmptySlot() 212 inline int nextEmptySlot() const 214 213 // This function returns : 215 214 // - the position of the first next empty slot in the table … … 218 217 // - -1 if the table is full 219 218 { 220 size_t i = r_last_empty; 221 do 222 { 223 // checking if current slot is empty 224 if(!r_val[i]) 225 { 226 // updating last empty slot and returning its position 227 r_last_empty = i; 228 return i; 229 } 230 // selecting next slot 231 i = (i+1) % nb_slots; 232 } 233 // stop if all slots have been tested 234 while(i != r_last_empty); 235 236 // the table is full 219 uint64_t i; 220 for(i = 0; i < nb_slots; i++) 221 { 222 if (!r_val[i]) return i; 223 } 224 237 225 return -1; 238 226 } 239 227 240 228 //////////////////////////////////////////////////////////////////////////// 241 inline int hitAddr(const addr_t ad) 229 inline int hitAddr(const addr_t ad) const 242 230 // HIT on the address only 243 231 // This function takes an addr_t ad … … 259 247 260 248 //////////////////////////////////////////////////////////////////////////// 261 inline int hitAddrKey(const addr_t ad, const uint32_t key) 249 inline int hitAddrKey(const addr_t ad, const uint32_t key) const 262 250 // HIT on the address AND the on the signature 263 251 // This function takes an addr_t ad and a uint32_t key … … 291 279 m_cpt_sc = 0; 292 280 m_cpt_sc_success = 0; 281 m_cpt_check = 0; 293 282 m_cpt_sw = 0; 294 283 } … … 301 290 : name(n) 302 291 { 303 #define L2 soclib::common::uint32_log2304 292 assert(nb_procs > 1); 305 assert((int)nb_slots >= L2(nb_procs));306 #undef L2307 293 init(); 308 294 init_block_mask(); … … 362 348 if (pos >= 0) 363 349 { 364 if(r_key[pos] - r_next_key > life_span) 365 return r_key[pos]; 350 uint32_t absdiff = ( r_key[pos] > r_next_key) ? 351 r_key[pos] - r_next_key : 352 r_next_key - r_key[pos]; 353 354 if(absdiff < life_span) return r_key[pos]; 355 366 356 r_key[pos] = r_next_key; 367 357 upNextKey(); 368 358 m_cpt_ll_update++; 359 369 360 return r_key[pos]; 370 361 } … … 377 368 if (pos == -1) 378 369 { 370 // update the victim slot for the next eviction 371 updateVictimSlot(); 372 379 373 // get the position of the evicted registration 380 374 pos = r_write_ptr; 381 // update the victim slot for the next eviction 382 updateVictimSlot(); 375 383 376 // increment the eviction counter (for stats) 384 377 m_cpt_evic++; … … 434 427 435 428 //////////////////////////////////////////////////////////////////////////// 429 inline bool check(const addr_t ad, const uint32_t key) const 430 // This method checks if there is a valid registration for the SC (ad && 431 // key) 432 // The return value can be used to tell if the SC is atomic 433 { 434 // increment the check access counter (for stats) 435 m_cpt_check++; 436 437 return (hitAddrKey(ad, key) >= 0); 438 } 439 440 //////////////////////////////////////////////////////////////////////////// 436 441 /* 437 442 inline void sw(const addr_t ad) … … 489 494 inline void print_trace(std::ostream& out = std::cout) 490 495 { 491 out << " ___________________________________" << std::endl492 << "| " << std::setw(33) << "generic_llsc_global_table" << " |" << std::endl493 << "| " << std::setw(33) << name << " |" << std::endl494 << " ===================================" << std::endl495 << "| "496 << std::setw(11) << "addr" << " | "497 << std::setw(11) << "key" << " | "498 << std::setw(5) << "val"499 << " |" << std::endl500 << " -----------------------------------" << std::endl;501 496 for ( size_t i = 0; i < nb_slots ; i++ ) 502 497 { 503 out << "| " 504 << std::showbase 505 << std::setw(11) << std::setfill('0') << std::hex << r_addr[i] << " | " 498 out << std::setw(3) << std::setfill(' ') << std::dec << i 506 499 << std::noshowbase 507 << std::setw(11) << std::setfill('0') << std::dec << r_key[i] << " | " 508 << std::setw(5) << std::setfill(' ') << std::boolalpha << r_val[i] << " |" << std::endl ; 509 } 510 out << " -----------------------------------" << std::endl 511 << std::noshowbase << std::dec << std::endl ; 500 << " VLD_RX = " << r_val[i] 501 << std::uppercase 502 << " ADR_RX = 0x" << std::setw(8) << std::setfill('0') << std::hex << (r_addr[i] >> 2) 503 << " SGN_RX = 0x" << std::setw(8) << std::setfill('0') << std::hex << r_key[i] 504 << std::endl; 505 } 506 out << "NEXT_SGN_RX = 0x" << std::setw(8) << std::setfill('0') << std::hex << r_next_key << std::endl 507 << "CNT_RX = 0x" << std::setw(8) << std::setfill('0') << std::hex << r_last_counter << std::endl; 512 508 } 513 509 -
trunk/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h
r507 r527 702 702 sc_signal<size_t> r_write_upt_index; // index in Update Table 703 703 sc_signal<bool> r_write_sc_fail; // sc command failed 704 sc_signal< bool> r_write_pending_sc; // sc command pending704 sc_signal<data_t> r_write_sc_key; // sc command key 705 705 706 706 // Buffer between WRITE fsm and TGT_RSP fsm (acknowledge a write command from L1) -
trunk/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp
r524 r527 2654 2654 case WRITE_IDLE: // copy first word of a write burst in local buffer 2655 2655 { 2656 if (m_cmd_write_addr_fifo.rok()) 2657 { 2658 // consume a word in the FIFO & write it in the local buffer 2659 cmd_write_fifo_get = true; 2660 size_t index = m_x[(addr_t)(m_cmd_write_addr_fifo.read())]; 2661 2662 r_write_address = (addr_t)(m_cmd_write_addr_fifo.read()); 2663 r_write_word_index = index; 2664 r_write_word_count = 1; 2665 r_write_data[index] = m_cmd_write_data_fifo.read(); 2666 r_write_srcid = m_cmd_write_srcid_fifo.read(); 2667 r_write_trdid = m_cmd_write_trdid_fifo.read(); 2668 r_write_pktid = m_cmd_write_pktid_fifo.read(); 2669 r_write_pending_sc = false; 2670 2671 // initialize the be field for all words 2672 for(size_t word=0 ; word<m_words ; word++) 2673 { 2674 if (word == index) r_write_be[word] = m_cmd_write_be_fifo.read(); 2675 else r_write_be[word] = 0x0; 2676 } 2677 2678 if (m_cmd_write_eop_fifo.read() or ((m_cmd_write_pktid_fifo.read() & 0x7) == TYPE_SC)) 2679 { 2680 r_write_fsm = WRITE_DIR_REQ; 2681 } 2682 else 2683 { 2684 r_write_fsm = WRITE_NEXT; 2685 } 2656 if (not m_cmd_write_addr_fifo.rok()) break; 2657 2658 // consume a word in the FIFO & write it in the local buffer 2659 cmd_write_fifo_get = true; 2660 size_t index = m_x[(addr_t)(m_cmd_write_addr_fifo.read())]; 2661 2662 r_write_address = (addr_t)(m_cmd_write_addr_fifo.read()); 2663 r_write_word_index = index; 2664 r_write_word_count = 0; 2665 r_write_data[index] = m_cmd_write_data_fifo.read(); 2666 r_write_srcid = m_cmd_write_srcid_fifo.read(); 2667 r_write_trdid = m_cmd_write_trdid_fifo.read(); 2668 r_write_pktid = m_cmd_write_pktid_fifo.read(); 2669 2670 // if SC command, get the SC key 2671 if ((m_cmd_write_pktid_fifo.read() & 0x7) == TYPE_SC) 2672 { 2673 assert( not m_cmd_write_eop_fifo.read() && 2674 "MEMC ERROR in WRITE_IDLE state: " 2675 "invalid packet format for SC command"); 2676 2677 r_write_sc_key = m_cmd_write_data_fifo.read(); 2678 } 2679 2680 // initialize the be field for all words 2681 for(size_t word=0 ; word<m_words ; word++) 2682 { 2683 if (word == index) r_write_be[word] = m_cmd_write_be_fifo.read(); 2684 else r_write_be[word] = 0x0; 2685 } 2686 2687 if (m_cmd_write_eop_fifo.read()) 2688 { 2689 r_write_fsm = WRITE_DIR_REQ; 2690 } 2691 else 2692 { 2693 r_write_fsm = WRITE_NEXT; 2694 } 2686 2695 2687 2696 #if DEBUG_MEMC_WRITE 2688 if (m_debug) 2689 std::cout << " <MEMC " << name() << " WRITE_IDLE> Write request " 2690 << " srcid = " << std::hex << m_cmd_write_srcid_fifo.read() 2691 << " / address = " << std::hex << m_cmd_write_addr_fifo.read() 2692 << " / data = " << m_cmd_write_data_fifo.read() << std::endl; 2693 #endif 2694 } 2697 if (m_debug) 2698 std::cout << " <MEMC " << name() << " WRITE_IDLE> Write request " 2699 << " srcid = " << std::hex << m_cmd_write_srcid_fifo.read() 2700 << " / address = " << std::hex << m_cmd_write_addr_fifo.read() 2701 << " / data = " << m_cmd_write_data_fifo.read() << std::endl; 2702 #endif 2695 2703 break; 2696 2704 } … … 2698 2706 case WRITE_NEXT: // copy next word of a write burst in local buffer 2699 2707 { 2700 if (m_cmd_write_addr_fifo.rok()) 2701 { 2708 if (not m_cmd_write_addr_fifo.rok()) break; 2709 2710 // check that the next word is in the same cache line 2711 assert((m_nline[(addr_t)(r_write_address.read())] == 2712 m_nline[(addr_t)(m_cmd_write_addr_fifo.read())]) && 2713 "MEMC ERROR in WRITE_NEXT state: Illegal write burst"); 2714 2715 size_t index = m_x[(addr_t)(m_cmd_write_addr_fifo.read())]; 2716 bool is_sc = ((m_cmd_write_pktid_fifo.read() & 0x7) == TYPE_SC); 2717 2718 // check that SC command has constant address 2719 assert( not is_sc or (index == r_write_word_index) && 2720 "MEMC ERROR in WRITE_NEXT state: " 2721 "the address must be constant on a SC command"); 2722 2723 // check that SC command has two flits 2724 assert( not is_sc or m_cmd_write_eop_fifo.read() && 2725 "MEMC ERROR in WRITE_NEXT state: " 2726 "invalid packet format for SC command"); 2727 2728 // consume a word in the FIFO & write it in the local buffer 2729 cmd_write_fifo_get = true; 2730 2731 r_write_be[index] = m_cmd_write_be_fifo.read(); 2732 r_write_data[index] = m_cmd_write_data_fifo.read(); 2733 r_write_word_count = r_write_word_count.read() + 1; 2734 2735 if (m_cmd_write_eop_fifo.read()) r_write_fsm = WRITE_DIR_REQ; 2702 2736 2703 2737 #if DEBUG_MEMC_WRITE 2704 if (m_debug) 2705 std::cout << " <MEMC " << name() 2706 << " WRITE_NEXT> Write another word in local buffer" 2707 << std::endl; 2708 #endif 2709 2710 // check that the next word is in the same cache line 2711 assert((m_nline[(addr_t)(r_write_address.read())] == 2712 m_nline[(addr_t)(m_cmd_write_addr_fifo.read())]) and 2713 "MEMC ERROR in WRITE_NEXT state: Illegal write burst"); 2714 2715 // consume a word in the FIFO & write it in the local buffer 2716 cmd_write_fifo_get = true; 2717 size_t index = r_write_word_index.read() + r_write_word_count.read(); 2718 2719 r_write_be[index] = m_cmd_write_be_fifo.read(); 2720 r_write_data[index] = m_cmd_write_data_fifo.read(); 2721 r_write_word_count = r_write_word_count.read() + 1; 2722 2723 if (m_cmd_write_eop_fifo.read()) r_write_fsm = WRITE_DIR_REQ; 2724 } 2738 if (m_debug) 2739 std::cout << " <MEMC " << name() 2740 << " WRITE_NEXT> Write another word in local buffer" 2741 << std::endl; 2742 #endif 2725 2743 break; 2726 2744 } 2727 2745 /////////////////// 2728 case WRITE_DIR_REQ: // Get the lock to the directory 2729 // and access the llsc_global_table 2730 { 2731 if (r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE ) 2732 { 2733 if (((r_write_pktid.read() & 0x7) == TYPE_SC) and not r_write_pending_sc.read()) 2734 { 2735 // We enter here if it is a new SC command 2736 // If r_write_pending_sc is set the SC is not new and has already been tested 2737 2738 if (not m_cmd_write_addr_fifo.rok()) break; 2739 2740 assert( m_cmd_write_eop_fifo.read() and 2741 "MEMC ERROR in WRITE_DIR_REQ state: invalid packet format for SC command"); 2742 2743 size_t index = r_write_word_index.read(); 2744 bool sc_success = m_llsc_table.sc(r_write_address.read(), 2745 r_write_data[index].read()); 2746 2747 // consume a word in the FIFO & write it in the local buffer 2748 cmd_write_fifo_get = true; 2749 r_write_data[index] = m_cmd_write_data_fifo.read(); 2750 r_write_sc_fail = not sc_success; 2751 r_write_pending_sc = true; 2752 2753 if (not sc_success) r_write_fsm = WRITE_RSP; 2754 else r_write_fsm = WRITE_DIR_LOCK; 2755 } 2756 else 2757 { 2758 // We enter here if it is a SW command or an already tested SC command 2746 case WRITE_DIR_REQ: // Get the lock to the directory 2747 // and access the llsc_global_table 2748 { 2749 if (r_alloc_dir_fsm.read() != ALLOC_DIR_WRITE ) break; 2750 2751 if ((r_write_pktid.read() & 0x7) == TYPE_SC) 2752 { 2753 // test address and key match of the SC command on the 2754 // LL/SC table without removing reservation. The reservation 2755 // will be erased after in this FSM. 2756 bool sc_success = m_llsc_table.check(r_write_address.read(), 2757 r_write_sc_key.read()); 2758 2759 r_write_sc_fail = not sc_success; 2760 2761 if (not sc_success) r_write_fsm = WRITE_RSP; 2762 else r_write_fsm = WRITE_DIR_LOCK; 2763 } 2764 else 2765 { 2766 // write burst 2759 2767 #define L2 soclib::common::uint32_log2 2760 2761 2762 ((r_write_word_count.read()-1) << L2(vci_param_int::B));2768 addr_t min = r_write_address.read(); 2769 addr_t max = r_write_address.read() + 2770 (r_write_word_count.read() << L2(vci_param_int::B)); 2763 2771 #undef L2 2764 2772 2765 2766 2767 2768 2773 m_llsc_table.sw(min, max); 2774 2775 r_write_fsm = WRITE_DIR_LOCK; 2776 } 2769 2777 2770 2778 #if DEBUG_MEMC_WRITE 2771 if (m_debug) 2772 std::cout << " <MEMC " << name() << " WRITE_DIR_REQ> Requesting DIR lock " 2773 << std::endl; 2774 #endif 2775 } 2779 if (m_debug) 2780 std::cout << " <MEMC " << name() << " WRITE_DIR_REQ> Requesting DIR lock " 2781 << std::endl; 2782 #endif 2776 2783 break; 2777 2784 } … … 2798 2805 2799 2806 if (entry.is_cnt and entry.count) r_write_fsm = WRITE_BC_DIR_READ; 2800 else r_write_fsm = WRITE_DIR_HIT;2807 else r_write_fsm = WRITE_DIR_HIT; 2801 2808 } 2802 2809 else // miss … … 2851 2858 // no_update is true when there is no need for coherence transaction 2852 2859 bool no_update = ( (r_write_count.read() == 0) or 2853 (owner and (r_write_count.read() == 1) and2854 ( r_write_pktid.read() != TYPE_SC)));2860 (owner and (r_write_count.read() == 1) and 2861 ((r_write_pktid.read() & 0x7) != TYPE_SC))); 2855 2862 2856 2863 // write data in the cache if no coherence transaction 2857 2864 if (no_update) 2858 2865 { 2866 // SC command but zero copies 2867 if ((r_write_pktid.read() & 0x7) == TYPE_SC) 2868 { 2869 m_llsc_table.sc(r_write_address.read(), 2870 r_write_sc_key.read()); 2871 } 2872 2859 2873 for(size_t word=0 ; word<m_words ; word++) 2860 2874 { … … 2867 2881 } 2868 2882 2869 if (owner and not no_update and (r_write_pktid.read() != TYPE_SC))2883 if (owner and not no_update and ((r_write_pktid.read() & 0x7) != TYPE_SC)) 2870 2884 { 2871 2885 r_write_count = r_write_count.read() - 1; … … 2936 2950 if (wok ) // write data in cache 2937 2951 { 2952 2953 if ((r_write_pktid.read() & 0x7) == TYPE_SC) 2954 { 2955 m_llsc_table.sc(r_write_address.read(), 2956 r_write_sc_key.read()); 2957 } 2958 2938 2959 for(size_t word=0 ; word<m_words ; word++) 2939 2960 { … … 2999 3020 size_t min = r_write_word_index.read(); 3000 3021 size_t max = r_write_word_index.read() + r_write_word_count.read(); 3001 for(size_t i=min ; i< max ; i++) r_write_to_cc_send_data[i] = r_write_data[i];3022 for(size_t i=min ; i<=max ; i++) r_write_to_cc_send_data[i] = r_write_data[i]; 3002 3023 3003 3024 if ((r_write_copy.read() != r_write_srcid.read()) or 3004 (r_write_pktid.read() == TYPE_SC) or r_write_copy_inst.read()) 3025 ((r_write_pktid.read() & 0x7) == TYPE_SC) or 3026 r_write_copy_inst.read()) 3005 3027 { 3006 3028 // put the first srcid in the fifo … … 3060 3082 // put the next srcid in the fifo 3061 3083 if ((entry.owner.srcid != r_write_srcid.read()) or 3062 (r_write_pktid.read() == TYPE_SC) or entry.owner.inst) 3084 ((r_write_pktid.read() & 0x7) == TYPE_SC) or 3085 entry.owner.inst) 3063 3086 { 3064 3087 dec_upt_counter = false; … … 3140 3163 // a new request in the write FIFO 3141 3164 { 3142 if ( !r_write_to_tgt_rsp_req.read())3165 if (not r_write_to_tgt_rsp_req.read()) 3143 3166 { 3144 3167 // post the request to TGT_RSP_FSM … … 3150 3173 3151 3174 // try to get a new write request from the FIFO 3152 if (m_cmd_write_addr_fifo.rok()) 3175 if (not m_cmd_write_addr_fifo.rok()) 3176 { 3177 r_write_fsm = WRITE_IDLE; 3178 } 3179 else 3153 3180 { 3154 3181 // consume a word in the FIFO & write it in the local buffer … … 3158 3185 r_write_address = (addr_t) (m_cmd_write_addr_fifo.read()); 3159 3186 r_write_word_index = index; 3160 r_write_word_count = 1;3187 r_write_word_count = 0; 3161 3188 r_write_data[index] = m_cmd_write_data_fifo.read(); 3162 3189 r_write_srcid = m_cmd_write_srcid_fifo.read(); 3163 3190 r_write_trdid = m_cmd_write_trdid_fifo.read(); 3164 3191 r_write_pktid = m_cmd_write_pktid_fifo.read(); 3165 r_write_pending_sc = false; 3192 3193 // if SC command, get the SC key 3194 if ((m_cmd_write_pktid_fifo.read() & 0x7) == TYPE_SC) 3195 { 3196 assert( not m_cmd_write_eop_fifo.read() && 3197 "MEMC ERROR in WRITE_RSP state: " 3198 "invalid packet format for SC command"); 3199 3200 r_write_sc_key = m_cmd_write_data_fifo.read(); 3201 } 3166 3202 3167 3203 // initialize the be field for all words … … 3169 3205 { 3170 3206 if (word == index) r_write_be[word] = m_cmd_write_be_fifo.read(); 3171 else 3207 else r_write_be[word] = 0x0; 3172 3208 } 3173 3209 3174 if (m_cmd_write_eop_fifo.read() or ((m_cmd_write_pktid_fifo.read() & 0x7) == TYPE_SC))3210 if (m_cmd_write_eop_fifo.read()) 3175 3211 { 3176 3212 r_write_fsm = WRITE_DIR_REQ; … … 3180 3216 r_write_fsm = WRITE_NEXT; 3181 3217 } 3182 }3183 else3184 {3185 r_write_fsm = WRITE_IDLE;3186 3218 } 3187 3219 … … 3221 3253 bool wok = not m_trt.full(wok_index); 3222 3254 3223 if (hit_read) // register the modified data in TRT 3255 // wait an empty entry in TRT 3256 if(not hit_read and (not wok or hit_write)) 3257 { 3258 r_write_fsm = WRITE_WAIT; 3259 m_cpt_trt_full++; 3260 3261 break; 3262 } 3263 3264 if ((r_write_pktid.read() & 0x7) == TYPE_SC) 3265 { 3266 m_llsc_table.sc(r_write_address.read(), 3267 r_write_sc_key.read()); 3268 } 3269 3270 // register the modified data in TRT 3271 if (hit_read) 3224 3272 { 3225 3273 r_write_trt_index = hit_index; 3226 3274 r_write_fsm = WRITE_MISS_TRT_DATA; 3227 3275 m_cpt_write_miss++; 3228 } 3229 else if (wok and !hit_write) // set a new entry in TRT 3276 break; 3277 } 3278 3279 // set a new entry in TRT 3280 if (wok and not hit_write) 3230 3281 { 3231 3282 r_write_trt_index = wok_index; 3232 3283 r_write_fsm = WRITE_MISS_TRT_SET; 3233 3284 m_cpt_write_miss++; 3234 } 3235 else // wait an empty entry in TRT 3236 { 3237 r_write_fsm = WRITE_WAIT; 3238 m_cpt_trt_full++; 3239 } 3285 break; 3286 } 3287 3288 assert(false && "VCI_MEM_CACHE ERROR: this part must not be reached"); 3240 3289 } 3241 3290 break; … … 3477 3526 3478 3527 m_cache_directory.write(set, way, entry); 3528 3529 if ((r_write_pktid.read() & 0x7) == TYPE_SC) 3530 { 3531 m_llsc_table.sc(r_write_address.read(), 3532 r_write_sc_key.read()); 3533 } 3479 3534 3480 3535 #if DEBUG_MEMC_WRITE … … 6284 6339 { 6285 6340 if (not p_dspin_m2p.read) break; 6286 if (r_cc_send_cpt.read() == (r_write_to_cc_send_count.read() - 1))6341 if (r_cc_send_cpt.read() == r_write_to_cc_send_count.read()) 6287 6342 { 6288 6343 write_to_cc_send_fifo_get = true; … … 8306 8361 8307 8362 p_dspin_m2p.write = true; 8308 p_dspin_m2p.eop = (r_cc_send_cpt.read() == (r_write_to_cc_send_count.read()-1));8363 p_dspin_m2p.eop = (r_cc_send_cpt.read() == r_write_to_cc_send_count.read()); 8309 8364 p_dspin_m2p.data = flit; 8310 8365
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