Index: trunk/modules/vci_ethernet_tsar/caba/metadata/vci_ethernet.sd =================================================================== --- trunk/modules/vci_ethernet_tsar/caba/metadata/vci_ethernet.sd (revision 528) +++ trunk/modules/vci_ethernet_tsar/caba/metadata/vci_ethernet.sd (revision 528) @@ -0,0 +1,35 @@ + +# -*- python -*- + +Module('caba:vci_ethernet_tsar', + classname = 'soclib::caba::VciEthernet', + tmpl_parameters = [ + parameter.Module('vci_param', default = 'caba:vci_param'), + ], + header_files = ['../source/include/vci_ethernet.h', + ], + interface_files = [ + '../../include/soclib/ethernet.h' + ], + implementation_files = ['../source/src/vci_ethernet.cpp',], + ports = [ + Port('caba:vci_target', 'p_vci_target'), + Port('caba:vci_initiator', 'p_vci_initiator'), + Port('caba:bit_out', 'p_irq'), + Port('caba:bit_in', 'p_resetn', auto = 'resetn'), + Port('caba:clock_in', 'p_clk', auto = 'clock'), + ], + uses = [ + Uses('caba:base_module'), + Uses('caba:vci_target_fsm', default_target = 'true', support_llsc = 'false'), + Uses('caba:vci_initiator_simple_read_req'), + Uses('caba:vci_initiator_simple_write_req'), + Uses('caba:vci_initiator_fsm'), + ], + instance_parameters = [ + parameter.Module('mt', typename = 'common:mapping_table'), + parameter.IntTab('srcid'), + parameter.IntTab('tgtid'), + parameter.String('filename'), + ], +) Index: trunk/modules/vci_ethernet_tsar/caba/source/include/vci_ethernet.h =================================================================== --- trunk/modules/vci_ethernet_tsar/caba/source/include/vci_ethernet.h (revision 528) +++ trunk/modules/vci_ethernet_tsar/caba/source/include/vci_ethernet.h (revision 528) @@ -0,0 +1,149 @@ +/* -*- c++ -*- + * + * SOCLIB_LGPL_HEADER_BEGIN + * + * This file is part of SoCLib, GNU LGPLv2.1. + * + * SoCLib is free software; you can redistribute it and/or modify it + * under the terms of the GNU Lesser General Public License as published + * by the Free Software Foundation; version 2.1 of the License. + * + * SoCLib is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with SoCLib; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301 USA + * + * SOCLIB_LGPL_HEADER_END + * + * Copyright (c) Telecom ParisTech + * Alexandre Becoulet , 2012 + * + * Maintainers: becoulet + * + * Maintainers: nipo + */ + +#ifndef SOCLIB_VCI_ETHERNET_H +#define SOCLIB_VCI_ETHERNET_H + +#include +#include + +#include +#include +#include +#include +#include + +#include "vci_target_fsm.h" +#include "vci_initiator_fsm.h" +#include "caba_base_module.h" +#include "mapping_table.h" + +#define VCI_ETHERNET_FIFO_SIZE 8 +#define VCI_ETHERNET_MAX_PKT_SIZE 1500 + +namespace soclib { +namespace caba { + +using namespace sc_core; + +template +class VciEthernet + : public caba::BaseModule +{ +private: + soclib::caba::VciTargetFsm m_vci_target_fsm; + soclib::caba::VciInitiatorFsm m_vci_init_fsm; + typedef typename soclib::caba::VciInitiatorReq req_t; + + bool on_write(int seg, typename vci_param::addr_t addr, typename vci_param::data_t data, int be); + bool on_read(int seg, typename vci_param::addr_t addr, typename vci_param::data_t &data); + void read_finish( req_t *req ); + void write_finish( req_t *req ); + void transition(); + void genMoore(); + void cleanup_fifos(); + + struct fifo_entry_t + { + uint32_t addr; + uint32_t size; + uint32_t status; + uint8_t *data; + int dma_offset; + union { + VciInitSimpleReadReq *rd_req; + VciInitSimpleWriteReq *wr_req; + }; + }; + + int _rx_start; //< index of first available rx buffer + int _rx_free; //< number of yet unused rx buffers + int _rx_done; //< number of rx buffers ready to pop + int _rx_count; //< total number of rx buffers + + int _tx_start; //< index of first tx buffer + int _tx_waiting; //< number of yet unprocessed tx buffers + int _tx_done; //< number of tx buffers ready to pop + int _tx_count; //< total number of tx buffers + + int _link_check_counter; + + bool _dma_busy; + bool _link_up; + bool _link_changed; + + fifo_entry_t _tx_fifo[VCI_ETHERNET_FIFO_SIZE]; + fifo_entry_t _rx_fifo[VCI_ETHERNET_FIFO_SIZE]; + + uint32_t _tx_size; //< next tx buffer size + uint32_t _rx_size; //< next rx buffer size + + bool _rx_irq_en; + bool _tx_irq_en; + bool _link_irq_en; + bool _soft_reset; + + int _fd; + uint8_t _mac[6]; + + struct ifreq _tap_ifr; + + inline void ended(int status); + +protected: + SC_HAS_PROCESS(VciEthernet); + +public: + sc_in p_clk; + sc_in p_resetn; + soclib::caba::VciTarget p_vci_target; + soclib::caba::VciInitiator p_vci_initiator; + sc_out p_irq; + + VciEthernet(sc_module_name name, const soclib::common::MappingTable &mt, + const soclib::common::IntTab &srcid, const soclib::common::IntTab &tgtid, + const std::string &if_name = "soclib0"); + + ~VciEthernet(); +}; + +}} + +#endif /* SOCLIB_VCI_ETHERNET_H */ + +// Local Variables: +// tab-width: 4 +// c-basic-offset: 4 +// c-file-offsets:((innamespace . 0)(inline-open . 0)) +// indent-tabs-mode: nil +// End: + +// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 + Index: trunk/modules/vci_ethernet_tsar/caba/source/src/.tags =================================================================== --- trunk/modules/vci_ethernet_tsar/caba/source/src/.tags (revision 528) +++ trunk/modules/vci_ethernet_tsar/caba/source/src/.tags (revision 528) @@ -0,0 +1,137 @@ +!_TAG_FILE_FORMAT 2 /extended format; --format=1 will not append ;" to lines/ +!_TAG_FILE_SORTED 1 /0=unsorted, 1=sorted, 2=foldcase/ +!_TAG_PROGRAM_AUTHOR Darren Hiebert /dhiebert@users.sourceforge.net/ +!_TAG_PROGRAM_NAME Exuberant Ctags // +!_TAG_PROGRAM_URL http://ctags.sourceforge.net /official site/ +!_TAG_PROGRAM_VERSION 5.9~svn20110310 // +CHUNCK_SIZE /home/lambert/Documents/stage/almos-tsarv5/tsar_almos_generic_xbar_mono/vci_ethernet_tsar/caba/source/src/vci_ethernet.cpp 41;" d file: +SC_HAS_PROCESS /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ SC_HAS_PROCESS(VciEthernet);$/;" p class:soclib::caba::VciEthernet access:protected signature:(VciEthernet) +SOCLIB_VCI_ETHERNET_H /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h 32;" d +VCI_ETHERNET_FIFO_SIZE /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h 48;" d +VCI_ETHERNET_MAX_PKT_SIZE /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h 49;" d +VciEthernet /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ VciEthernet(sc_module_name name, const soclib::common::MappingTable &mt,$/;" p class:soclib::caba::VciEthernet access:public signature:(sc_module_name name, const soclib::common::MappingTable &mt, const soclib::common::IntTab &srcid, const soclib::common::IntTab &tgtid, const std::string &if_name = Ó) +VciEthernet /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^class VciEthernet$/;" c namespace:soclib::caba inherits:caba::BaseModule +_dma_busy /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ bool _dma_busy;$/;" m class:soclib::caba::VciEthernet access:private +_fd /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ int _fd;$/;" m class:soclib::caba::VciEthernet access:private +_link_changed /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ bool _link_changed;$/;" m class:soclib::caba::VciEthernet access:private +_link_check_counter /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ int _link_check_counter;$/;" m class:soclib::caba::VciEthernet access:private +_link_irq_en /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ bool _link_irq_en;$/;" m class:soclib::caba::VciEthernet access:private +_link_up /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ bool _link_up;$/;" m class:soclib::caba::VciEthernet access:private +_mac /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ uint8_t _mac[6];$/;" m class:soclib::caba::VciEthernet access:private +_rx_count /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ int _rx_count; \/\/< total number of rx buffers$/;" m class:soclib::caba::VciEthernet access:private +_rx_done /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ int _rx_done; \/\/< number of rx buffers ready to pop$/;" m class:soclib::caba::VciEthernet access:private +_rx_fifo /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ fifo_entry_t _rx_fifo[VCI_ETHERNET_FIFO_SIZE];$/;" m class:soclib::caba::VciEthernet access:private +_rx_free /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ int _rx_free; \/\/< number of yet unused rx buffers$/;" m class:soclib::caba::VciEthernet access:private +_rx_irq_en /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ bool _rx_irq_en;$/;" m class:soclib::caba::VciEthernet access:private +_rx_size /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ uint32_t _rx_size; \/\/< next rx buffer size$/;" m class:soclib::caba::VciEthernet access:private +_rx_start /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ int _rx_start; \/\/< index of first available rx buffer$/;" m class:soclib::caba::VciEthernet access:private +_soft_reset /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ bool _soft_reset;$/;" m class:soclib::caba::VciEthernet access:private +_tap_ifr /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ struct ifreq _tap_ifr;$/;" m class:soclib::caba::VciEthernet typeref:struct:soclib::caba::VciEthernet::ifreq access:private +_tx_count /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ int _tx_count; \/\/< total number of tx buffers$/;" m class:soclib::caba::VciEthernet access:private +_tx_done /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ int _tx_done; \/\/< number of tx buffers ready to pop$/;" m class:soclib::caba::VciEthernet access:private +_tx_fifo /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ fifo_entry_t _tx_fifo[VCI_ETHERNET_FIFO_SIZE];$/;" m class:soclib::caba::VciEthernet access:private +_tx_irq_en /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ bool _tx_irq_en;$/;" m class:soclib::caba::VciEthernet access:private +_tx_size /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ uint32_t _tx_size; \/\/< next tx buffer size$/;" m class:soclib::caba::VciEthernet access:private +_tx_start /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ int _tx_start; \/\/< index of first tx buffer$/;" m class:soclib::caba::VciEthernet access:private +_tx_waiting /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ int _tx_waiting; \/\/< number of yet unprocessed tx buffers$/;" m class:soclib::caba::VciEthernet access:private +addr /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ uint32_t addr;$/;" m struct:soclib::caba::VciEthernet::fifo_entry_t access:public +caba /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^namespace caba {$/;" n namespace:soclib +caba /home/lambert/Documents/stage/almos-tsarv5/tsar_almos_generic_xbar_mono/vci_ethernet_tsar/caba/source/src/vci_ethernet.cpp /^namespace soclib { namespace caba {$/;" n namespace:soclib file: +cleanup_fifos /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ void cleanup_fifos();$/;" p class:soclib::caba::VciEthernet access:private signature:() +data /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ uint8_t *data;$/;" m struct:soclib::caba::VciEthernet::fifo_entry_t access:public +dma_offset /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ int dma_offset;$/;" m struct:soclib::caba::VciEthernet::fifo_entry_t access:public +ended /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ inline void ended(int status);$/;" p class:soclib::caba::VciEthernet access:private signature:(int status) +fifo_entry_t /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ struct fifo_entry_t$/;" s class:soclib::caba::VciEthernet access:private +genMoore /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ void genMoore();$/;" p class:soclib::caba::VciEthernet access:private signature:() +m_vci_init_fsm /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ soclib::caba::VciInitiatorFsm m_vci_init_fsm;$/;" m class:soclib::caba::VciEthernet access:private +m_vci_target_fsm /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ soclib::caba::VciTargetFsm m_vci_target_fsm;$/;" m class:soclib::caba::VciEthernet access:private +on_read /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ bool on_read(int seg, typename vci_param::addr_t addr, typename vci_param::data_t &data);$/;" p class:soclib::caba::VciEthernet access:private signature:(int seg, typename vci_param::addr_t addr, typename vci_param::data_t &data) +on_write /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ bool on_write(int seg, typename vci_param::addr_t addr, typename vci_param::data_t data, int be);$/;" p class:soclib::caba::VciEthernet access:private signature:(int seg, typename vci_param::addr_t addr, typename vci_param::data_t data, int be) +p_clk /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ sc_in p_clk;$/;" m class:soclib::caba::VciEthernet access:public +p_irq /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ sc_out p_irq;$/;" m class:soclib::caba::VciEthernet access:public +p_resetn /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ sc_in p_resetn;$/;" m class:soclib::caba::VciEthernet access:public +p_vci_initiator /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ soclib::caba::VciInitiator p_vci_initiator;$/;" m class:soclib::caba::VciEthernet access:public +p_vci_target /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ soclib::caba::VciTarget p_vci_target;$/;" m class:soclib::caba::VciEthernet access:public +rd_req /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ VciInitSimpleReadReq *rd_req;$/;" m union:soclib::caba::VciEthernet::fifo_entry_t::__anon1 access:public +read_finish /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ void read_finish( req_t *req );$/;" p class:soclib::caba::VciEthernet access:private signature:( req_t *req ) +req_t /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ typedef typename soclib::caba::VciInitiatorReq req_t;$/;" t class:soclib::caba::VciEthernet access:private +size /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ uint32_t size;$/;" m struct:soclib::caba::VciEthernet::fifo_entry_t access:public +soclib /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^namespace soclib {$/;" n +soclib /home/lambert/Documents/stage/almos-tsarv5/tsar_almos_generic_xbar_mono/vci_ethernet_tsar/caba/source/src/vci_ethernet.cpp /^namespace soclib { namespace caba {$/;" n file: +soclib::caba /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^namespace caba {$/;" n namespace:soclib +soclib::caba /home/lambert/Documents/stage/almos-tsarv5/tsar_almos_generic_xbar_mono/vci_ethernet_tsar/caba/source/src/vci_ethernet.cpp /^namespace soclib { namespace caba {$/;" n namespace:soclib file: +soclib::caba::VciEthernet /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^class VciEthernet$/;" c namespace:soclib::caba inherits:caba::BaseModule +soclib::caba::VciEthernet::SC_HAS_PROCESS /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ SC_HAS_PROCESS(VciEthernet);$/;" p class:soclib::caba::VciEthernet access:protected signature:(VciEthernet) +soclib::caba::VciEthernet::VciEthernet /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ VciEthernet(sc_module_name name, const soclib::common::MappingTable &mt,$/;" p class:soclib::caba::VciEthernet access:public signature:(sc_module_name name, const soclib::common::MappingTable &mt, const soclib::common::IntTab &srcid, const soclib::common::IntTab &tgtid, const std::string &if_name = Ó) +soclib::caba::VciEthernet::_dma_busy /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ bool _dma_busy;$/;" m class:soclib::caba::VciEthernet access:private +soclib::caba::VciEthernet::_fd /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ int _fd;$/;" m class:soclib::caba::VciEthernet access:private +soclib::caba::VciEthernet::_link_changed /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ bool _link_changed;$/;" m class:soclib::caba::VciEthernet access:private +soclib::caba::VciEthernet::_link_check_counter /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ int _link_check_counter;$/;" m class:soclib::caba::VciEthernet access:private +soclib::caba::VciEthernet::_link_irq_en /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ bool _link_irq_en;$/;" m class:soclib::caba::VciEthernet access:private +soclib::caba::VciEthernet::_link_up /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ bool _link_up;$/;" m class:soclib::caba::VciEthernet access:private +soclib::caba::VciEthernet::_mac /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ uint8_t _mac[6];$/;" m class:soclib::caba::VciEthernet access:private +soclib::caba::VciEthernet::_rx_count /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ int _rx_count; \/\/< total number of rx buffers$/;" m class:soclib::caba::VciEthernet access:private +soclib::caba::VciEthernet::_rx_done /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ int _rx_done; \/\/< number of rx buffers ready to pop$/;" m class:soclib::caba::VciEthernet access:private +soclib::caba::VciEthernet::_rx_fifo /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ fifo_entry_t _rx_fifo[VCI_ETHERNET_FIFO_SIZE];$/;" m class:soclib::caba::VciEthernet access:private +soclib::caba::VciEthernet::_rx_free /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ int _rx_free; \/\/< number of yet unused rx buffers$/;" m class:soclib::caba::VciEthernet access:private +soclib::caba::VciEthernet::_rx_irq_en /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ bool _rx_irq_en;$/;" m class:soclib::caba::VciEthernet access:private +soclib::caba::VciEthernet::_rx_size /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ uint32_t _rx_size; \/\/< next rx buffer size$/;" m class:soclib::caba::VciEthernet access:private +soclib::caba::VciEthernet::_rx_start /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ int _rx_start; \/\/< index of first available rx buffer$/;" m class:soclib::caba::VciEthernet access:private +soclib::caba::VciEthernet::_soft_reset /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ bool _soft_reset;$/;" m class:soclib::caba::VciEthernet access:private +soclib::caba::VciEthernet::_tap_ifr /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ struct ifreq _tap_ifr;$/;" m class:soclib::caba::VciEthernet typeref:struct:soclib::caba::VciEthernet::ifreq access:private +soclib::caba::VciEthernet::_tx_count /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ int _tx_count; \/\/< total number of tx buffers$/;" m class:soclib::caba::VciEthernet access:private +soclib::caba::VciEthernet::_tx_done /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ int _tx_done; \/\/< number of tx buffers ready to pop$/;" m class:soclib::caba::VciEthernet access:private +soclib::caba::VciEthernet::_tx_fifo /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ fifo_entry_t _tx_fifo[VCI_ETHERNET_FIFO_SIZE];$/;" m class:soclib::caba::VciEthernet access:private +soclib::caba::VciEthernet::_tx_irq_en /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ bool _tx_irq_en;$/;" m class:soclib::caba::VciEthernet access:private +soclib::caba::VciEthernet::_tx_size /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ uint32_t _tx_size; \/\/< next tx buffer size$/;" m class:soclib::caba::VciEthernet access:private +soclib::caba::VciEthernet::_tx_start /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ int _tx_start; \/\/< index of first tx buffer$/;" m class:soclib::caba::VciEthernet access:private +soclib::caba::VciEthernet::_tx_waiting /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ int _tx_waiting; \/\/< number of yet unprocessed tx buffers$/;" m class:soclib::caba::VciEthernet access:private +soclib::caba::VciEthernet::cleanup_fifos /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ void cleanup_fifos();$/;" p class:soclib::caba::VciEthernet access:private signature:() +soclib::caba::VciEthernet::ended /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ inline void ended(int status);$/;" p class:soclib::caba::VciEthernet access:private signature:(int status) +soclib::caba::VciEthernet::fifo_entry_t /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ struct fifo_entry_t$/;" s class:soclib::caba::VciEthernet access:private +soclib::caba::VciEthernet::fifo_entry_t::__anon1::rd_req /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ VciInitSimpleReadReq *rd_req;$/;" m union:soclib::caba::VciEthernet::fifo_entry_t::__anon1 access:public +soclib::caba::VciEthernet::fifo_entry_t::__anon1::wr_req /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ VciInitSimpleWriteReq *wr_req;$/;" m union:soclib::caba::VciEthernet::fifo_entry_t::__anon1 access:public +soclib::caba::VciEthernet::fifo_entry_t::addr /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ uint32_t addr;$/;" m struct:soclib::caba::VciEthernet::fifo_entry_t access:public +soclib::caba::VciEthernet::fifo_entry_t::data /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ uint8_t *data;$/;" m struct:soclib::caba::VciEthernet::fifo_entry_t access:public +soclib::caba::VciEthernet::fifo_entry_t::dma_offset /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ int dma_offset;$/;" m struct:soclib::caba::VciEthernet::fifo_entry_t access:public +soclib::caba::VciEthernet::fifo_entry_t::size /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ uint32_t size;$/;" m struct:soclib::caba::VciEthernet::fifo_entry_t access:public +soclib::caba::VciEthernet::fifo_entry_t::status /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ uint32_t status;$/;" m struct:soclib::caba::VciEthernet::fifo_entry_t access:public +soclib::caba::VciEthernet::genMoore /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ void genMoore();$/;" p class:soclib::caba::VciEthernet access:private signature:() +soclib::caba::VciEthernet::m_vci_init_fsm /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ soclib::caba::VciInitiatorFsm m_vci_init_fsm;$/;" m class:soclib::caba::VciEthernet access:private +soclib::caba::VciEthernet::m_vci_target_fsm /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ soclib::caba::VciTargetFsm m_vci_target_fsm;$/;" m class:soclib::caba::VciEthernet access:private +soclib::caba::VciEthernet::on_read /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ bool on_read(int seg, typename vci_param::addr_t addr, typename vci_param::data_t &data);$/;" p class:soclib::caba::VciEthernet access:private signature:(int seg, typename vci_param::addr_t addr, typename vci_param::data_t &data) +soclib::caba::VciEthernet::on_write /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ bool on_write(int seg, typename vci_param::addr_t addr, typename vci_param::data_t data, int be);$/;" p class:soclib::caba::VciEthernet access:private signature:(int seg, typename vci_param::addr_t addr, typename vci_param::data_t data, int be) +soclib::caba::VciEthernet::p_clk /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ sc_in p_clk;$/;" m class:soclib::caba::VciEthernet access:public +soclib::caba::VciEthernet::p_irq /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ sc_out p_irq;$/;" m class:soclib::caba::VciEthernet access:public +soclib::caba::VciEthernet::p_resetn /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ sc_in p_resetn;$/;" m class:soclib::caba::VciEthernet access:public +soclib::caba::VciEthernet::p_vci_initiator /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ soclib::caba::VciInitiator p_vci_initiator;$/;" m class:soclib::caba::VciEthernet access:public +soclib::caba::VciEthernet::p_vci_target /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ soclib::caba::VciTarget p_vci_target;$/;" m class:soclib::caba::VciEthernet access:public +soclib::caba::VciEthernet::read_finish /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ void read_finish( req_t *req );$/;" p class:soclib::caba::VciEthernet access:private signature:( req_t *req ) +soclib::caba::VciEthernet::req_t /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ typedef typename soclib::caba::VciInitiatorReq req_t;$/;" t class:soclib::caba::VciEthernet access:private +soclib::caba::VciEthernet::transition /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ void transition();$/;" p class:soclib::caba::VciEthernet access:private signature:() +soclib::caba::VciEthernet::write_finish /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ void write_finish( req_t *req );$/;" p class:soclib::caba::VciEthernet access:private signature:( req_t *req ) +soclib::caba::VciEthernet::~VciEthernet /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ ~VciEthernet();$/;" p class:soclib::caba::VciEthernet access:public signature:() +soclib::caba::tmpl /home/lambert/Documents/stage/almos-tsarv5/tsar_almos_generic_xbar_mono/vci_ethernet_tsar/caba/source/src/vci_ethernet.cpp /^ tmpl(\/**\/)::VciEthernet(sc_module_name name, const MappingTable &mt,$/;" f namespace:soclib::caba signature:( ) +soclib::caba::tmpl /home/lambert/Documents/stage/almos-tsarv5/tsar_almos_generic_xbar_mono/vci_ethernet_tsar/caba/source/src/vci_ethernet.cpp /^ tmpl(\/**\/)::~VciEthernet()$/;" f namespace:soclib::caba signature:( ) +soclib::caba::tmpl /home/lambert/Documents/stage/almos-tsarv5/tsar_almos_generic_xbar_mono/vci_ethernet_tsar/caba/source/src/vci_ethernet.cpp /^ tmpl(bool)::on_read(int seg, typename vci_param::addr_t addr, typename vci_param::data_t &data)$/;" f namespace:soclib::caba signature:(bool) +soclib::caba::tmpl /home/lambert/Documents/stage/almos-tsarv5/tsar_almos_generic_xbar_mono/vci_ethernet_tsar/caba/source/src/vci_ethernet.cpp /^ tmpl(bool)::on_write(int seg, typename vci_param::addr_t addr, typename vci_param::data_t data, int be)$/;" f namespace:soclib::caba signature:(bool) +soclib::caba::tmpl /home/lambert/Documents/stage/almos-tsarv5/tsar_almos_generic_xbar_mono/vci_ethernet_tsar/caba/source/src/vci_ethernet.cpp /^ tmpl(void)::cleanup_fifos()$/;" f namespace:soclib::caba signature:(void) +soclib::caba::tmpl /home/lambert/Documents/stage/almos-tsarv5/tsar_almos_generic_xbar_mono/vci_ethernet_tsar/caba/source/src/vci_ethernet.cpp /^ tmpl(void)::genMoore()$/;" f namespace:soclib::caba signature:(void) +soclib::caba::tmpl /home/lambert/Documents/stage/almos-tsarv5/tsar_almos_generic_xbar_mono/vci_ethernet_tsar/caba/source/src/vci_ethernet.cpp /^ tmpl(void)::read_finish( req_t *req )$/;" f namespace:soclib::caba signature:(void) +soclib::caba::tmpl /home/lambert/Documents/stage/almos-tsarv5/tsar_almos_generic_xbar_mono/vci_ethernet_tsar/caba/source/src/vci_ethernet.cpp /^ tmpl(void)::transition()$/;" f namespace:soclib::caba signature:(void) +soclib::caba::tmpl /home/lambert/Documents/stage/almos-tsarv5/tsar_almos_generic_xbar_mono/vci_ethernet_tsar/caba/source/src/vci_ethernet.cpp /^ tmpl(void)::write_finish( req_t *req )$/;" f namespace:soclib::caba signature:(void) +status /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ uint32_t status;$/;" m struct:soclib::caba::VciEthernet::fifo_entry_t access:public +tmpl /home/lambert/Documents/stage/almos-tsarv5/tsar_almos_generic_xbar_mono/vci_ethernet_tsar/caba/source/src/vci_ethernet.cpp /^ tmpl(\/**\/)::VciEthernet(sc_module_name name, const MappingTable &mt,$/;" f namespace:soclib::caba signature:( ) +tmpl /home/lambert/Documents/stage/almos-tsarv5/tsar_almos_generic_xbar_mono/vci_ethernet_tsar/caba/source/src/vci_ethernet.cpp /^ tmpl(\/**\/)::~VciEthernet()$/;" f namespace:soclib::caba signature:( ) +tmpl /home/lambert/Documents/stage/almos-tsarv5/tsar_almos_generic_xbar_mono/vci_ethernet_tsar/caba/source/src/vci_ethernet.cpp /^ tmpl(bool)::on_read(int seg, typename vci_param::addr_t addr, typename vci_param::data_t &data)$/;" f namespace:soclib::caba signature:(bool) +tmpl /home/lambert/Documents/stage/almos-tsarv5/tsar_almos_generic_xbar_mono/vci_ethernet_tsar/caba/source/src/vci_ethernet.cpp /^ tmpl(bool)::on_write(int seg, typename vci_param::addr_t addr, typename vci_param::data_t data, int be)$/;" f namespace:soclib::caba signature:(bool) +tmpl /home/lambert/Documents/stage/almos-tsarv5/tsar_almos_generic_xbar_mono/vci_ethernet_tsar/caba/source/src/vci_ethernet.cpp /^ tmpl(void)::cleanup_fifos()$/;" f namespace:soclib::caba signature:(void) +tmpl /home/lambert/Documents/stage/almos-tsarv5/tsar_almos_generic_xbar_mono/vci_ethernet_tsar/caba/source/src/vci_ethernet.cpp /^ tmpl(void)::genMoore()$/;" f namespace:soclib::caba signature:(void) +tmpl /home/lambert/Documents/stage/almos-tsarv5/tsar_almos_generic_xbar_mono/vci_ethernet_tsar/caba/source/src/vci_ethernet.cpp /^ tmpl(void)::read_finish( req_t *req )$/;" f namespace:soclib::caba signature:(void) +tmpl /home/lambert/Documents/stage/almos-tsarv5/tsar_almos_generic_xbar_mono/vci_ethernet_tsar/caba/source/src/vci_ethernet.cpp /^ tmpl(void)::transition()$/;" f namespace:soclib::caba signature:(void) +tmpl /home/lambert/Documents/stage/almos-tsarv5/tsar_almos_generic_xbar_mono/vci_ethernet_tsar/caba/source/src/vci_ethernet.cpp /^ tmpl(void)::write_finish( req_t *req )$/;" f namespace:soclib::caba signature:(void) +tmpl /home/lambert/Documents/stage/almos-tsarv5/tsar_almos_generic_xbar_mono/vci_ethernet_tsar/caba/source/src/vci_ethernet.cpp 47;" d file: +transition /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ void transition();$/;" p class:soclib::caba::VciEthernet access:private signature:() +wr_req /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ VciInitSimpleWriteReq *wr_req;$/;" m union:soclib::caba::VciEthernet::fifo_entry_t::__anon1 access:public +write_finish /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ void write_finish( req_t *req );$/;" p class:soclib::caba::VciEthernet access:private signature:( req_t *req ) +~VciEthernet /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ ~VciEthernet();$/;" p class:soclib::caba::VciEthernet access:public signature:() Index: trunk/modules/vci_ethernet_tsar/caba/source/src/vci_ethernet.cpp =================================================================== --- trunk/modules/vci_ethernet_tsar/caba/source/src/vci_ethernet.cpp (revision 528) +++ trunk/modules/vci_ethernet_tsar/caba/source/src/vci_ethernet.cpp (revision 528) @@ -0,0 +1,478 @@ +/* -*- c++ -*- + * + * SOCLIB_LGPL_HEADER_BEGIN + * + * This file is part of SoCLib, GNU LGPLv2.1. + * + * SoCLib is free software; you can redistribute it and/or modify it + * under the terms of the GNU Lesser General Public License as published + * by the Free Software Foundation; version 2.1 of the License. + * + * SoCLib is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with SoCLib; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301 USA + * + * SOCLIB_LGPL_HEADER_END + * + * Copyright (c) Telecom ParisTech + * Alexandre Becoulet , 2012 + * + * Maintainers: becoulet + */ + +#include +#include +#include +#include +#include + +#include + +#include "register.h" +#include "../include/vci_ethernet.h" +#include "ethernet.h" + +#define CHUNCK_SIZE (64) // Width of a cache line +#define CHUNCK_MASK ((~0ULL) << (6)) // MASK of a cache line + +//#define SOCLIB_MODULE_DEBUG + +namespace soclib { namespace caba { + +#define tmpl(t) template t VciEthernet + + tmpl(bool)::on_write(int seg, typename vci_param::addr_t addr, typename vci_param::data_t data, int be) + { + int cell = (int)addr / vci_param::B; + +#ifdef SOCLIB_MODULE_DEBUG + std::cout + << name() + << ": write config register " + << cell + << " with data 0x" + << std::hex << data + << std::dec + << std::endl; +#endif + + fifo_entry_t *f; + + switch ((enum SoclibEthernetRegisters)cell) + { + case ETHERNET_TX_SIZE: + _tx_size = std::min((int)data, VCI_ETHERNET_MAX_PKT_SIZE); + return true; + + case ETHERNET_TX_FIFO: + if (_tx_count >= VCI_ETHERNET_FIFO_SIZE) { + std::cout << name() << ": TX fifo full, can not push more packets!" << std::endl; + return false; + } + + f = _tx_fifo + (_tx_start + _tx_count++) % VCI_ETHERNET_FIFO_SIZE; + _tx_waiting++; + + f->addr = data; + f->size = _tx_size; + f->status = 0; + f->data = (uint8_t*)malloc(_tx_size); + return true; + + case ETHERNET_RX_SIZE: + _rx_size = std::min((int)data, VCI_ETHERNET_MAX_PKT_SIZE); + return true; + + case ETHERNET_RX_FIFO: + if (_rx_count >= VCI_ETHERNET_FIFO_SIZE) { + std::cout << name() << ": RX fifo full, can not push more packet buffers!" << std::endl; + return false; + } + + f = _rx_fifo + (_rx_start + _rx_count++) % VCI_ETHERNET_FIFO_SIZE; + _rx_free++; + + f->addr = data; + f->size = _rx_size; + f->status = 0; + f->data = (uint8_t*)malloc(_rx_size); + return true; + + case ETHERNET_CTRL: + if (data & ETHERNET_CTRL_RESET) + _soft_reset = true; + if (data & ETHERNET_CTRL_TX_IRQ) + _tx_irq_en = true; + else + _tx_irq_en = false; + if (data & ETHERNET_CTRL_RX_IRQ) + _rx_irq_en = true; + else + _rx_irq_en = false; + if (data & ETHERNET_CTRL_LINK_IRQ) + _link_irq_en = true; + else + _link_irq_en = false; + return true; + + default: + return false; + } + } + + tmpl(bool)::on_read(int seg, typename vci_param::addr_t addr, typename vci_param::data_t &data) + { + int cell = (int)addr / vci_param::B; + +#ifdef SOCLIB_MODULE_DEBUG + std::cout + << name() + << ": read config register " + << cell + << std::endl; +#endif + + fifo_entry_t *f; + + switch ((enum SoclibEthernetRegisters)cell) { + case ETHERNET_TX_FIFO: + if (_tx_done == 0) { + data = 0; + } else { + f = _tx_fifo + _tx_start++ % VCI_ETHERNET_FIFO_SIZE; + _tx_count--; + _tx_done--; + data = f->status; + free(f->data); + } + return true; + + case ETHERNET_RX_SIZE: + if (_rx_done == 0) { + data = 0; + } else { + f = _rx_fifo + _rx_start % VCI_ETHERNET_FIFO_SIZE; + data = f->size; + } + return true; + + case ETHERNET_RX_FIFO: + if (_rx_done == 0) { + data = 0; + } else { + f = _rx_fifo + _rx_start++ % VCI_ETHERNET_FIFO_SIZE; + _rx_count--; + _rx_done--; + free(f->data); + data = f->status; + } + return true; + + case ETHERNET_STATUS: + data = 0; + _link_changed = false; + if (_link_up) + data |= ETHERNET_ST_LINK_UP; + if (_rx_done > 0) + data |= ETHERNET_ST_RX_DONE; + if (_tx_done > 0) + data |= ETHERNET_ST_TX_DONE; + return true; + + case ETHERNET_FIFO_SIZE: + data = VCI_ETHERNET_FIFO_SIZE; + return true; + + case ETHERNET_MAC_LOW: + data = _mac[0] | (_mac[1] << 8) | (_mac[2] << 16) | (_mac[3] << 24); + return true; + + case ETHERNET_MAC_HIGH: + data = _mac[4] | (_mac[5] << 8); + return true; + + default: + return false; + } + } + + tmpl(void)::write_finish( req_t *req ) + { + fifo_entry_t *f = _rx_fifo + (_rx_start + _rx_count - _rx_free - 1) % VCI_ETHERNET_FIFO_SIZE; + + assert(req == f->rd_req); + delete req; + + if (req->failed()) { + std::cout << name() << ": RX dma write error for packet @" << f->addr << std::endl; + f->status = ETHERNET_RX_DMA_ERR; + _rx_done++; + _dma_busy = false; + + } else if ((unsigned)f->dma_offset >= f->size) { +#ifdef SOCLIB_MODULE_DEBUG + std::cout << name() << ": RX dma done for packet @" << f->addr << std::endl; +#endif + f->status = ETHERNET_RX_DONE; + _rx_done++; + _dma_busy = false; + + } else { + int chunck_size = std::min((unsigned)CHUNCK_SIZE, f->size - f->dma_offset); + f->wr_req = new VciInitSimpleWriteReq(f->addr + f->dma_offset, f->data + f->dma_offset, chunck_size); + f->dma_offset += chunck_size; + f->wr_req->setDone(this, ON_T(write_finish)); + f->wr_req->setPacket(0x4); + m_vci_init_fsm.doReq(f->wr_req); + } + } + + tmpl(void)::read_finish( req_t *req ) + { + fifo_entry_t *f = _tx_fifo + (_tx_start + _tx_count - _tx_waiting - 1) % VCI_ETHERNET_FIFO_SIZE; + + assert(req == f->rd_req); + delete req; + + if (req->failed()) { + std::cout << name() << ": TX dma read error for packet @" << f->addr << std::endl; + f->status = ETHERNET_TX_DMA_ERR; + _tx_done++; + _dma_busy = false; + + } else if ((unsigned)f->dma_offset >= f->size) { +#ifdef SOCLIB_MODULE_DEBUG + std::cout << name() << ": TX dma done for packet @" << f->addr << std::endl; +#endif + f->status = ETHERNET_TX_DONE; + + if (!_link_up || ::write(_fd, f->data, f->size) != f->size) { + std::cout << name() << ": TX tap write error for packet @" << f->addr << std::endl; + f->status = ETHERNET_TX_PHY_ERR; + _link_check_counter = 1; + } + + _tx_done++; + _dma_busy = false; + + } else { + int chunck_size = std::min((unsigned)CHUNCK_SIZE, f->size - f->dma_offset); + f->rd_req = new VciInitSimpleReadReq(f->data + f->dma_offset, f->addr + f->dma_offset, chunck_size); + f->dma_offset += chunck_size; + f->rd_req->setDone(this, ON_T(read_finish)); + m_vci_init_fsm.doReq(f->rd_req); + } + } + + tmpl(void)::cleanup_fifos() + { + for (int i = 0; i < _rx_count; i++) { + fifo_entry_t *f = _rx_fifo + (_rx_start + i) % VCI_ETHERNET_FIFO_SIZE; + free(f->data); + } + + for (int i = 0; i < _tx_count; i++) { + fifo_entry_t *f = _tx_fifo + (_tx_start + i) % VCI_ETHERNET_FIFO_SIZE; + free(f->data); + } + } + + tmpl(void)::transition() + { + if (!p_resetn || _soft_reset) { + m_vci_target_fsm.reset(); + m_vci_init_fsm.reset(); + _soft_reset = false; + + cleanup_fifos(); + + _rx_start = _rx_free = _rx_done = _rx_count = 0; + _tx_start = _tx_waiting = _tx_done = _tx_count = 0; + _rx_irq_en = _tx_irq_en = _link_irq_en = false; + _link_check_counter = 1; + _link_changed = _link_up = false; + _dma_busy = false; + return; + } + + if (_fd >= 0 && --_link_check_counter <= 0) { + _link_check_counter = 100000; + + int sock = socket(AF_INET, SOCK_DGRAM, 0); + + if (sock >= 0) { + if (ioctl(sock, SIOCGIFFLAGS, &_tap_ifr) < 0) { + std::cout << name() << ": link status check error: " << _tap_ifr.ifr_flags << std::endl; + } else if (_link_up != !!(_tap_ifr.ifr_flags & IFF_UP)) { + _link_up = !_link_up; + _link_changed = true; +#ifdef SOCLIB_MODULE_DEBUG + std::cout << name() << ": link status changed to: " << (_link_up ? "up" : "down") << std::endl; +#endif + } + close(sock); + } + } + + if (!_dma_busy) { + + if (_tx_waiting > 0) { + + fifo_entry_t *f = _tx_fifo + (_tx_start + _tx_count - _tx_waiting--) % VCI_ETHERNET_FIFO_SIZE; + + // start DMA read + int chunck_size = std::min((unsigned)CHUNCK_SIZE, f->size); + if ((f->addr & CHUNCK_MASK) != ((f->addr + chunck_size) & CHUNCK_MASK)) { + chunck_size = ((f->addr & CHUNCK_MASK) + CHUNCK_SIZE) - f->addr; + } + f->rd_req = new VciInitSimpleReadReq(f->data, f->addr, chunck_size); + f->dma_offset = chunck_size; + f->rd_req->setDone(this, ON_T(read_finish)); + m_vci_init_fsm.doReq(f->rd_req); + _dma_busy = true; + +#ifdef SOCLIB_MODULE_DEBUG + std::cout << name() << ": started TX dma read @" << f->addr << ", " << f->size << " bytes " << std::endl; +#endif + } else if (_rx_free > 0 && _link_up) { + + fifo_entry_t *f = _rx_fifo + (_rx_start + _rx_count - _rx_free) % VCI_ETHERNET_FIFO_SIZE; + int rd = ::read(_fd, f->data, f->size); + + if (rd < 0 && errno != EAGAIN) { + f->status = ETHERNET_RX_PHY_ERR; + _rx_done++; + std::cout << name() << ": tap read error on RX" << std::endl; + _link_check_counter = 1; + + } else if (rd > 0) { + if (_rx_free > 0) { + f->size = rd; + _rx_free--; + + // start DMA write + int chunck_size = std::min((unsigned)CHUNCK_SIZE, f->size); + if ((f->addr & CHUNCK_MASK) != ((f->addr + chunck_size) & CHUNCK_MASK)) { + chunck_size = ((f->addr & CHUNCK_MASK) + CHUNCK_SIZE) - f->addr; + } + f->wr_req = new VciInitSimpleWriteReq(f->addr, f->data, chunck_size); + f->dma_offset = chunck_size; + f->wr_req->setDone(this, ON_T(write_finish)); + f->wr_req->setPacket(0x4); + m_vci_init_fsm.doReq(f->wr_req); + _dma_busy = true; + +#ifdef SOCLIB_MODULE_DEBUG + std::cout << name() << ": started RX dma write @" << f->addr << ", " << f->size << " bytes " << std::endl; +#endif + } + else { + std::cout << name() << ": No rx buffer free so paquet is dropped" << std::endl; + } + } + } + } + + m_vci_target_fsm.transition(); + m_vci_init_fsm.transition(); + } + + tmpl(void)::genMoore() + { + m_vci_target_fsm.genMoore(); + m_vci_init_fsm.genMoore(); + + p_irq = (_rx_irq_en && _rx_done > 0) || (_tx_irq_en && _tx_done > 0) || (_link_changed && _link_irq_en); + } + + tmpl(/**/)::VciEthernet(sc_module_name name, const MappingTable &mt, + const IntTab &srcid, const IntTab &tgtid, + const std::string &if_name) + : caba::BaseModule(name), + m_vci_target_fsm(p_vci_target, mt.getSegmentList(tgtid)), + m_vci_init_fsm(p_vci_initiator, mt.indexForId(srcid)), + p_clk("clk"), + p_resetn("resetn"), + p_vci_target("vci_target"), + p_vci_initiator("vci_initiator"), + p_irq("irq") + { + m_vci_target_fsm.on_read_write(on_read, on_write); + _fd = open("/dev/net/tun", O_RDWR); + + if ( _fd < 0 ) { + std::cerr << name << ": Unable to open /dev/net/tun" << std::endl; + } else { + int flags = fcntl(_fd, F_GETFL, 0); + fcntl(_fd, F_SETFL, flags | O_NONBLOCK); + + memset((void*)&_tap_ifr, 0, sizeof(_tap_ifr)); + _tap_ifr.ifr_flags = IFF_TAP | IFF_NO_PI; + strncpy(_tap_ifr.ifr_name, if_name.c_str(), IFNAMSIZ); + + + if (ioctl(_fd, TUNSETIFF, (void *) &_tap_ifr) < 0) { + close(_fd); + _fd = -1; + std::cerr << name << ": Unable to setup tap interface, check privileges." +#ifdef __linux__ + << " (try: sudo setcap cap_net_admin=eip ./system.x)" +#endif + << std::endl; + } + flags = 2; + if (ioctl(_fd, TUNSETDEBUG, (void *) &flags) < 0) { + std::cerr << "Warning couldn't use debug option for TAP" << std::endl; + } + + /* ioctl(_fd, SIOCGIFHWADDR, &_tap_ifr); + memcpy(_mac, _tap_ifr.ifr_hwaddr.sa_data, 6);*/ + srand(time(0) * getpid()); + _mac[0] = 0x00; + _mac[1] = 0x16; + _mac[2] = 0x3e; + _mac[3] = rand(); + _mac[4] = rand(); + _mac[5] = rand(); + } + + _link_check_counter = 1; + _rx_start = _rx_free = _rx_done = _rx_count = 0; + _tx_start = _tx_waiting = _tx_done = _tx_count = 0; + _dma_busy = false; + _link_up = false; + + SC_METHOD(transition); + dont_initialize(); + sensitive << p_clk.pos(); + + SC_METHOD(genMoore); + dont_initialize(); + sensitive << p_clk.neg(); + } + + tmpl(/**/)::~VciEthernet() + { + cleanup_fifos(); + + if (_fd >= 0) + close(_fd); + } + +}} + +// Local Variables: +// tab-width: 4 +// c-basic-offset: 4 +// c-file-offsets:((innamespace . 0)(inline-open . 0)) +// indent-tabs-mode: nil +// End: + +// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 + Index: trunk/modules/vci_ethernet_tsar/doc/README =================================================================== --- trunk/modules/vci_ethernet_tsar/doc/README (revision 528) +++ trunk/modules/vci_ethernet_tsar/doc/README (revision 528) @@ -0,0 +1,10 @@ +This files describes the differences between vci_ethernet_tsar and +vci_ethernet + +* Added f->wr_req->setPacket(0x4); for every Write command from vci_ethernet in + order to respect overloading of vci CMD in pktid of Tsar architecture + +* Added overlapping detection in read and write vci CMD. First, vci CMD is now + made at maximum with the boundary of a cache line (64 alignement) + +* Added set and reset for IRQ lines enable Index: trunk/modules/vci_ethernet_tsar/include/soclib/ethernet.h =================================================================== --- trunk/modules/vci_ethernet_tsar/include/soclib/ethernet.h (revision 528) +++ trunk/modules/vci_ethernet_tsar/include/soclib/ethernet.h (revision 528) @@ -0,0 +1,83 @@ +/* + * SOCLIB_LGPL_HEADER_BEGIN + * + * This file is part of SoCLib, GNU LGPLv2.1. + * + * SoCLib is free software; you can redistribute it and/or modify it + * under the terms of the GNU Lesser General Public License as published + * by the Free Software Foundation; version 2.1 of the License. + * + * SoCLib is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with SoCLib; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301 USA + * + * SOCLIB_LGPL_HEADER_END + * + * Copyright (c) Telecom ParisTech + * Alexandre Becoulet , 2012 + * + * Maintainers: becoulet + */ + +#ifndef ETHERNET_REGS_H +#define ETHERNET_REGS_H + +enum SoclibEthernetRegisters { + ETHERNET_TX_SIZE = 0, /*< on write: set size of packet to send for next adress push */ + ETHERNET_TX_FIFO = 1, /*< on write: push address and size of packet to send on tx fifo, + on read: pop status of sent packet from tx fifo. 0 if empty */ + ETHERNET_RX_SIZE = 2, /*< on write: set size of rx buffer for next adress push, + on read: get size of last rx packet, 0 if empty. */ + ETHERNET_RX_FIFO = 3, /*< on write: push address and size of buffer on rx fifo, + on read: pop status of last rx packet. 0 if empty */ + ETHERNET_STATUS = 4, /*< on read: contains device status flags */ + ETHERNET_CTRL = 4, /*< on write: device control actions */ + ETHERNET_FIFO_SIZE = 5, /*< contains size of TX & RX FIFOs */ + ETHERNET_MAC_LOW = 6, /*< contains mac address bytes 0, 1, 2 and 3 */ + ETHERNET_MAC_HIGH = 7, /*< contains mac address bytes 4 and 5 */ +}; + +enum SoclibEthernetRxStatus { + ETHERNET_RX_EMPTY = 0, + ETHERNET_RX_DONE = 1, + ETHERNET_RX_DMA_ERR = 2, + ETHERNET_RX_PHY_ERR = 3, +}; + +enum SoclibEthernetTxStatus { + ETHERNET_TX_EMPTY = 0, + ETHERNET_TX_DONE = 1, + ETHERNET_TX_DMA_ERR = 2, + ETHERNET_TX_PHY_ERR = 3, +}; + +enum SoclibEthernetStatus { + ETHERNET_ST_LINK_UP = 1, + ETHERNET_ST_TX_DONE = 2, /*< The ETHERNET_TX_FIFO register content is valid */ + ETHERNET_ST_RX_DONE = 4, /*< The ETHERNET_RX_FIFO register content is valid */ +}; + +enum SoclibEthernetCtrl { + ETHERNET_CTRL_RESET = 1, //< fifos become empty, disable interrupts + ETHERNET_CTRL_TX_IRQ = 2, //< enable TX irq when written to 1 + ETHERNET_CTRL_RX_IRQ = 4, //< enable RX irq when written to 1 + ETHERNET_CTRL_LINK_IRQ = 8, //< enable link status change irq when written to 1 +}; + +#endif /* ETHERNET_REGS_H */ + +// Local Variables: +// tab-width: 4 +// c-basic-offset: 4 +// c-file-offsets:((innamespace . 0)(inline-open . 0)) +// indent-tabs-mode: nil +// End: + +// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 +