Changeset 535 for trunk/modules
- Timestamp:
- Sep 26, 2013, 11:43:56 AM (11 years ago)
- Location:
- trunk/modules/vci_mem_cache/caba/source
- Files:
-
- 2 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h
r530 r535 449 449 uint32_t m_cpt_write_miss; // Number of MISS WRITE 450 450 uint32_t m_cpt_write_dirty; // Cumulated length for WRITE transactions 451 uint32_t m_cpt_write_broadcast;// Number of BROADCAST INVAL because write 451 452 452 453 uint32_t m_cpt_trt_rb; // Read blocked by a hit in trt … … 724 725 sc_signal<bool> r_write_sc_fail; // sc command failed 725 726 sc_signal<data_t> r_write_sc_key; // sc command key 727 sc_signal<bool> r_write_bc_data_we; // Write enable for data buffer 726 728 727 729 // Buffer between WRITE fsm and TGT_RSP fsm (acknowledge a write command from L1) -
trunk/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp
r531 r535 739 739 << "[036] PUT (UNIMPLEMENTED) = " << m_cpt_put << std::endl 740 740 << "[037] GET (UNIMPLEMENTED) = " << m_cpt_get << std::endl 741 << "[038] WRITE BROADCAST = " << m_cpt_write_broadcast << std::endl 741 742 << std::endl; 742 743 } … … 974 975 m_cpt_cleanup_cost = 0; 975 976 976 m_cpt_read_miss = 0; 977 m_cpt_write_miss = 0; 978 m_cpt_write_dirty = 0; 979 m_cpt_trt_rb = 0; 980 m_cpt_trt_full = 0; 981 m_cpt_get = 0; 982 m_cpt_put = 0; 977 m_cpt_read_miss = 0; 978 m_cpt_write_miss = 0; 979 m_cpt_write_dirty = 0; 980 m_cpt_write_broadcast = 0; 981 m_cpt_trt_rb = 0; 982 m_cpt_trt_full = 0; 983 m_cpt_get = 0; 984 m_cpt_put = 0; 983 985 984 986 return; … … 3402 3404 #if DEBUG_MEMC_WRITE 3403 3405 if (m_debug) 3404 std::cout << " <MEMC " << name() << " WRITE_MISS_XRAM_REQ> Post a GET request to the IXR_CMD FSM" << std::endl; 3406 std::cout << " <MEMC " << name() 3407 << " WRITE_MISS_XRAM_REQ> Post a GET request to the" 3408 << " IXR_CMD FSM" << std::endl; 3405 3409 #endif 3406 3410 } … … 3409 3413 /////////////////////// 3410 3414 case WRITE_BC_DIR_READ: // enter this state if a broadcast-inval is required 3411 // the cache line must be erased in mem-cache, and written3412 // into XRAM. we read the cache and complete the buffer3415 // the cache line must be erased in mem-cache, and written 3416 // into XRAM. 3413 3417 { 3414 3418 assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE) and 3415 3419 "MEMC ERROR in WRITE_BC_DIR_READ state: Bad DIR allocation"); 3416 3420 3417 // update local buffer 3418 size_t set = m_y[(addr_t)(r_write_address.read())]; 3419 size_t way = r_write_way.read(); 3420 for(size_t word=0 ; word<m_words ; word++) 3421 { 3422 data_t mask = 0; 3423 if (r_write_be[word].read() & 0x1) mask = mask | 0x000000FF; 3424 if (r_write_be[word].read() & 0x2) mask = mask | 0x0000FF00; 3425 if (r_write_be[word].read() & 0x4) mask = mask | 0x00FF0000; 3426 if (r_write_be[word].read() & 0x8) mask = mask | 0xFF000000; 3427 3428 // complete only if mask is not null (for energy consumption) 3429 r_write_data[word] = (r_write_data[word].read() & mask) | 3430 (m_cache_data.read(way, set, word) & ~mask); 3431 } // end for 3421 m_cpt_write_broadcast++; 3422 3423 // write enable signal for data buffer. 3424 r_write_bc_data_we = true; 3432 3425 3433 3426 r_write_fsm = WRITE_BC_TRT_LOCK; … … 3436 3429 if (m_debug) 3437 3430 std::cout << " <MEMC " << name() << " WRITE_BC_DIR_READ>" 3438 << " Read the cache to complete local buffer" << std::endl;3431 << " Read the cache to complete local buffer" << std::endl; 3439 3432 #endif 3440 3433 break; … … 3446 3439 "MEMC ERROR in WRITE_BC_TRT_LOCK state: Bad DIR allocation"); 3447 3440 3448 if (r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE) 3449 { 3450 size_t wok_index = 0; 3451 bool wok = not m_trt.full(wok_index); 3452 if (wok ) 3453 { 3454 r_write_trt_index = wok_index; 3455 r_write_fsm = WRITE_BC_IVT_LOCK; 3456 } 3457 else // wait an empty slot in TRT 3458 { 3459 r_write_fsm = WRITE_WAIT; 3460 } 3461 3441 // We read the cache and complete the buffer. As the DATA cache uses a 3442 // synchronous RAM, the read DATA request has been performed in the 3443 // WRITE_BC_DIR_READ state but the data is available in this state. 3444 if (r_write_bc_data_we.read()) 3445 { 3446 size_t set = m_y[(addr_t)(r_write_address.read())]; 3447 size_t way = r_write_way.read(); 3448 for(size_t word=0 ; word<m_words ; word++) 3449 { 3450 data_t mask = 0; 3451 if (r_write_be[word].read() & 0x1) mask = mask | 0x000000FF; 3452 if (r_write_be[word].read() & 0x2) mask = mask | 0x0000FF00; 3453 if (r_write_be[word].read() & 0x4) mask = mask | 0x00FF0000; 3454 if (r_write_be[word].read() & 0x8) mask = mask | 0xFF000000; 3455 3456 // complete only if mask is not null (for energy consumption) 3457 r_write_data[word] = 3458 (r_write_data[word].read() & mask) | 3459 (m_cache_data.read(way, set, word) & ~mask); 3460 } 3462 3461 #if DEBUG_MEMC_WRITE 3463 3462 if (m_debug) 3464 std::cout << " <MEMC " << name() << " WRITE_BC_TRT_LOCK> Check TRT" 3465 << " : wok = " << wok << " / index = " << wok_index << std::endl; 3466 #endif 3467 } 3463 std::cout 3464 << " <MEMC " << name() 3465 << " WRITE_BC_TRT_LOCK> Complete data buffer" << std::endl; 3466 #endif 3467 } 3468 3469 if (r_alloc_trt_fsm.read() != ALLOC_TRT_WRITE) 3470 { 3471 // if we loop in this state, the data does not need to be 3472 // rewritten (for energy consuption) 3473 r_write_bc_data_we = false; 3474 break; 3475 } 3476 3477 size_t wok_index = 0; 3478 bool wok = not m_trt.full(wok_index); 3479 if (wok ) 3480 { 3481 r_write_trt_index = wok_index; 3482 r_write_fsm = WRITE_BC_IVT_LOCK; 3483 } 3484 else // wait an empty slot in TRT 3485 { 3486 r_write_fsm = WRITE_WAIT; 3487 } 3488 3489 #if DEBUG_MEMC_WRITE 3490 if (m_debug) 3491 std::cout << " <MEMC " << name() 3492 << " WRITE_BC_TRT_LOCK> Check TRT : wok = " << wok 3493 << " / index = " << wok_index << std::endl; 3494 #endif 3468 3495 break; 3469 3496 }
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