Changeset 538 for branches/RWT/modules/vci_cc_vcache_wrapper/caba/source

Timestamp:

Oct 2, 2013, 4:03:11 PM (11 years ago)

Author:

haoliu

Message:

RWT - bug fixed in vci_cc_vcache_wrapper:
Add the treatment of late cleanup in icache fsm.
Fix the bug in dcache fsm : utilize the correct register of nline address for scan tlb
in the state DCACHE_MISS_CLEAN

File:

• branches/RWT/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp (modified) (11 diffs)

branches/RWT/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp

@@ -357 +357 @@
       r_dcache_cleanup_victim_req("r_dcache_cleanup_victim_req"),
       r_dcache_cleanup_victim_nline("r_dcache_cleanup_victim_nline"),
+
+      r_icache_cleanup_victim_req("r_icache_cleanup_victim_req"),
+      r_icache_cleanup_victim_nline("r_icache_cleanup_victim_nline"),
   
       r_dcache_cc_send_req("r_dcache_cc_send_req"),
@@ -1601 +1604 @@
         }
 
-        if ( not r_icache_cc_send_req.read() ) // wait for previous cc_send request to be sent
-        {
-            bool        found;
-            bool        cleanup;
-            size_t      way;
-            size_t      set;
-            paddr_t     victim;
+        bool        found;
+        bool        cleanup;
+        size_t          way;
+        size_t          set;
+        paddr_t         victim;
 
 #ifdef INSTRUMENTATION
 m_cpt_icache_dir_read++;
 #endif
-            r_icache.read_select(r_icache_vci_paddr.read(),
-                                 &victim,
-                                 &way,
-                                 &set,
-                                 &found,
-                                 &cleanup );
-            if ( found )
-            {
-                r_icache_miss_way     = way;
-                r_icache_miss_set     = set;
-
-                if ( cleanup )
+        r_icache.read_select(r_icache_vci_paddr.read(),
+                             &victim,
+                             &way,
+                             &set,
+                             &found,
+                             &cleanup );
+        if ( found )
+        {
+            r_icache_miss_way     = way;
+            r_icache_miss_set     = set;
+
+            if ( cleanup )
+            {
+                if ( not r_icache_cc_send_req.read() )
                 {
-                    r_icache_fsm           = ICACHE_MISS_CLEAN;
-                    r_icache_miss_clack    = true;
-                    // request cleanup
-                    r_icache_cc_send_req   = true;
-                    r_icache_cc_send_nline = victim;
-                    r_icache_cc_send_way   = way;
-                    r_icache_cc_send_type  = CC_TYPE_CLEANUP;
+                    r_icache_cc_send_req    = true;
+                    r_icache_cc_send_nline  = victim;
+                    r_icache_cc_send_way    = way;
+                    r_icache_cc_send_type   = CC_TYPE_CLEANUP;    
                 }
                 else
                 {
-                    r_icache_fsm          = ICACHE_MISS_WAIT;
+                    r_icache_cleanup_victim_req   = true;
+                    r_icache_cleanup_victim_nline = victim;
                 }
+
+                r_icache_miss_clack           = true;
+                r_icache_fsm                  = ICACHE_MISS_CLEAN;
+            }
+            else
+            {
+                r_icache_fsm          = ICACHE_MISS_WAIT;
+            }
 
 #if DEBUG_ICACHE
@@ -1649 +1658 @@
 }
 #endif
-            }
         }
         break;
@@ -1682 +1690 @@
         if (m_ireq.valid) m_cost_ins_miss_frz++;
 
+        if ( r_icache_cleanup_victim_req.read() and not r_icache_cc_send_req.read() )
+        {
+            r_icache_cc_send_req        = true;
+            r_icache_cc_send_nline      = r_icache_cleanup_victim_nline;
+            r_icache_cc_send_way        = r_icache_miss_way;
+            r_icache_cc_send_type       = CC_TYPE_CLEANUP; 
+            r_icache_cleanup_victim_req = false;
+        }   
+
         // coherence clack interrupt
         if ( r_icache_clack_req.read() )
@@ -1689 +1706 @@
             break;
         }
-
+        
         // coherence interrupt
-        if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read())
+        if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read() and not r_icache_cleanup_victim_req.read() )
         {
             r_icache_fsm = ICACHE_CC_CHECK;
@@ -1761 +1778 @@
         if ( m_ireq.valid ) m_cost_ins_miss_frz++;
 
+        if ( r_icache_cleanup_victim_req.read() and not r_icache_cc_send_req.read() )
+        {
+            r_icache_cc_send_req        = true;
+            r_icache_cc_send_nline      = r_icache_cleanup_victim_nline;
+            r_icache_cc_send_way        = r_icache_miss_way;
+            r_icache_cc_send_type       = CC_TYPE_CLEANUP; 
+            r_icache_cleanup_victim_req = false;
+        }   
+
         // coherence clack interrupt
         if ( r_icache_clack_req.read() )
@@ -1770 +1796 @@
 
         // coherence interrupt
-        if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read())
+        if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read() and not r_icache_cleanup_victim_req.read() )
         {
             r_icache_fsm = ICACHE_CC_CHECK;
@@ -2019 +2045 @@
             }
         }
+#if DEBUG_ICACHE
+if ( m_debug_activated )
+{
+    std::cout << "  <PROC " << name()
+              << " ICACHE_CC_CHECK> Coherence request received:"
+              << " PADDR = " << std::hex << paddr
+              << " / TYPE = " << std::dec << r_cc_receive_dcache_type.read()
+              << " / HIT = " << ((state == CACHE_SLOT_STATE_VALID_CC) or (state == CACHE_SLOT_STATE_VALID_NCC)) << std::endl;
+}
+#endif
+
         break;
     }
@@ -3790 +3827 @@
                                 // to avoid dead-lock in case of simultaneous ITLB miss
     {
+        // coherence clack request (from DSPIN CLACK)
+        if ( r_dcache_clack_req.read() )
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_cc_save = r_dcache_fsm.read();
+            break;
+        }
+
+        // coherence request (from CC_RECEIVE FSM)
+        if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_cc_save = r_dcache_fsm.read();
+            break;
+        }
+
         // itlb miss request
         if ( r_icache_tlb_miss_req.read() )
@@ -4514 +4567 @@
             //r_dcache_in_tlb[way*m_dcache_sets+set] = false;
             r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_DIRTY;
-            r_dcache_tlb_inval_line  = r_dcache_cc_send_nline;
+            if( not r_dcache_cleanup_victim_req.read() )
+            {
+                r_dcache_tlb_inval_line = r_dcache_cc_send_nline.read();
+            }
+            else
+            {
+                r_dcache_tlb_inval_line = r_dcache_cleanup_victim_nline.read();
+            }
             r_dcache_tlb_inval_set   = 0;
             r_dcache_fsm_scan_save   = DCACHE_MISS_WAIT;
@@ -5101 +5161 @@
         paddr_t  mask = ~((m_dcache_words<<2)-1);
 
-#if DEBUG_DCACHE
-if ( m_debug_activated )
-{
-    std::cout << "  <PROC " << name() << std::hex
-              << " DCACHE_CC_CHECK> paddr = " << paddr
-              << " r_dcache_vci_paddr = " << r_dcache_vci_paddr.read()
-              << " mask = " << mask 
-              << " (r_dcache_fsm_cc_save == DCACHE_MISS_WAIT) = " 
-              << (r_dcache_fsm_cc_save == DCACHE_MISS_WAIT)
-              << " (r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT) = " 
-              << (r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT)
-              << " ((r_dcache_vci_paddr.read() & mask) == (paddr & mask)) = " 
-              << ((r_dcache_vci_paddr.read() & mask) == (paddr & mask))
-              << std::dec <<std::endl;
-}
-#endif
+//#if DEBUG_DCACHE
+//if ( m_debug_activated )
+//{
+//    std::cout << "  <PROC " << name() << std::hex
+//              << " DCACHE_CC_CHECK> paddr = " << paddr
+//              << " r_dcache_vci_paddr = " << r_dcache_vci_paddr.read()
+//              << " mask = " << mask 
+//              << " (r_dcache_fsm_cc_save == DCACHE_MISS_WAIT) = " 
+//              << (r_dcache_fsm_cc_save == DCACHE_MISS_WAIT)
+//              << " (r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT) = " 
+//              << (r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT)
+//              << " ((r_dcache_vci_paddr.read() & mask) == (paddr & mask)) = " 
+//              << ((r_dcache_vci_paddr.read() & mask) == (paddr & mask))
+//              << std::dec <<std::endl;
+//}
+//#endif
         // CLACK handler
         // We switch the directory slot to EMPTY state and reset