Index: branches/ODCCP/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp
===================================================================
--- branches/ODCCP/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp	(revision 494)
+++ branches/ODCCP/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp	(revision 541)
@@ -36,5 +36,5 @@
 #define DEBUG_CLEANUP		  1
 #define INSTRUMENTATION       1
-#define FETCH_ON_WRITE_ENABLE 1
+#define FETCH_ON_WRITE_ENABLE 0
 #define DEBUG_CMD   		  0
 
@@ -596,6 +596,6 @@
     float run_cycles = (float)(m_cpt_total_cycles - m_cpt_frz_cycles);
     std::cout << name() << std::endl
-        << "- CPI                     = " << (float)m_cpt_total_cycles/run_cycles << std::endl
-        << "- READ RATE               = " << (float)m_cpt_data_read/run_cycles << std::endl
+        << "- CPI                     = " << (float)m_cpt_total_cycles/run_cycles << std::endl;
+        /*<< "- READ RATE               = " << (float)m_cpt_data_read/run_cycles << std::endl
         << "- WRITE RATE              = " << (float)m_cpt_data_write/run_cycles << std::endl
         << "- IMISS_RATE              = " << (float)m_cpt_ins_miss/m_cpt_ins_read << std::endl
@@ -643,7 +643,7 @@
         << "- WRITE LENGTH            = " << (float)m_length_write_transaction/m_cpt_write_transaction << std::endl
         << "- ITLB MISS TRANSACTION   = " << (float)m_cost_itlbmiss_transaction/m_cpt_itlbmiss_transaction << std::endl
-        << "- DTLB MISS TRANSACTION   = " << (float)m_cost_dtlbmiss_transaction/m_cpt_dtlbmiss_transaction << std::endl;
+        << "- DTLB MISS TRANSACTION   = " << (float)m_cost_dtlbmiss_transaction/m_cpt_dtlbmiss_transaction << std::endl;*/
 }
-/*
+
 ////////////////////////
 tmpl(void)::clear_stats()
@@ -660,9 +660,9 @@
 
     m_cpt_frz_cycles        = 0;
-    m_cpt_dcache_frz_cycles = 0;
+    //m_cpt_dcache_frz_cycles = 0;
     m_cpt_total_cycles      = 0;
 
-    m_cpt_read         = 0;
-    m_cpt_write        = 0;
+    //m_cpt_read         = 0;
+    //m_cpt_write        = 0;
     m_cpt_data_miss    = 0;
     m_cpt_ins_miss     = 0;
@@ -728,7 +728,7 @@
     m_cost_dtlb_sc_dirty_transaction = 0;
 
-    m_cpt_cc_update_data = 0;
-    m_cpt_cc_inval_ins   = 0;
-    m_cpt_cc_inval_data  = 0;
+    //m_cpt_cc_update_data = 0;
+    //m_cpt_cc_inval_ins   = 0;
+    //m_cpt_cc_inval_data  = 0;
     m_cpt_cc_broadcast   = 0;
 
@@ -742,5 +742,5 @@
 }
 
-*/
+
 
 /////////////////////////
@@ -1171,5 +1171,4 @@
 
             // We register processor request
-            ///*ODCCP*/ std::cout << "DEBUG IREQ.ADDR = " << std::hex << m_ireq.addr << std::dec << " | on " << name() << std::endl;
             r_icache_vaddr_save = m_ireq.addr;
 
@@ -1632,5 +1631,5 @@
             r_icache_miss_way     = way;
             r_icache_miss_set     = set;
-
+       
             if ( cleanup )
             {
@@ -1924,4 +1923,23 @@
         paddr_t  paddr = r_cc_receive_icache_nline.read() * m_icache_words * 4;
         paddr_t  mask  = ~((m_icache_words<<2)-1);
+       
+#if DEBUG_DCACHE
+if ( m_debug_activated )
+{
+    std::cout << "  <PROC " << name()
+              << std::hex
+              << " ICACHE_CC_CHECK> paddr = " << paddr
+              << " r_icache_vci_paddr = " << r_icache_vci_paddr.read()
+              << " mask = " << mask 
+              << " (r_icache_fsm_save == ICACHE_MISS_WAIT) = " 
+              << (r_icache_fsm_save == ICACHE_MISS_WAIT)
+              << " (r_icache_fsm_save == ICACHE_MISS_DIR_UPDT) = " 
+              << (r_icache_fsm_save == ICACHE_MISS_DIR_UPDT)
+              << " ((r_icache_vci_paddr.read() & mask) == (paddr & mask)) = " 
+              << ((r_icache_vci_paddr.read() & mask) == (paddr & mask))
+              << std::dec
+              << std::endl;
+}
+#endif
 
         // CLACK handler
@@ -2070,6 +2088,5 @@
 
         // Switch slot state to ZOMBI and send CLEANUP command 
-        r_icache.write_dir( 0,
-                            r_icache_cc_way.read(),
+        r_icache.write_dir( r_icache_cc_way.read(),
                             r_icache_cc_set.read(),
                             CACHE_SLOT_STATE_ZOMBI );
@@ -4013,7 +4030,4 @@
                               &word);
 
-        /*if (m_proc_id == 1) { std::cout << "rdata XTN_FLUSH_DATA = " << std::hex << rdata << std::dec << " | at cycle = " << m_cpt_total_cycles << std::endl; }
-        if (m_proc_id == 1) { r_cc_send_data_fifo.print(); }*/
-
         if(r_cc_send_data_fifo.wok())
         {
@@ -4281,7 +4295,4 @@
                               &word);
 
-        /*if (m_proc_id == 1) { std::cout << "rdata XTN_INVAL_DATA = " << std::hex << rdata << std::dec << " | at cycle = " << m_cpt_total_cycles << std::endl; }
-        if (m_proc_id == 1) { r_cc_send_data_fifo.print(); }*/
-
         if(r_cc_send_data_fifo.wok())
         {
@@ -4472,7 +4483,4 @@
                               &set,
                               &word);
-
-        /*if (m_proc_id == 1) { std::cout << "rdata MISS_DATA = " << std::hex << rdata << std::dec << " | at cycle = " << m_cpt_total_cycles << std::endl; }
-        if (m_proc_id == 1) { r_cc_send_data_fifo.print(); }*/
 
         if(r_cc_send_data_fifo.wok())
@@ -5355,7 +5363,4 @@
                               &word);
        
-        /*if (m_proc_id == 1) { std::cout << "rdata CC_INVAL_DATA = " << std::hex << rdata << std::dec << " | at cycle = " << m_cpt_total_cycles << std::endl; }
-        if (m_proc_id == 1) { r_cc_send_data_fifo.print(); }*/
-        
         if(r_cc_send_data_fifo.wok())
         {
