Changeset 545 for branches/RWT/modules/vci_mem_cache/caba/source/include
- Timestamp:
- Oct 4, 2013, 4:31:55 PM (11 years ago)
- File:
-
- 1 edited
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branches/RWT/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h
r542 r545 80 80 { 81 81 TGT_CMD_IDLE, 82 TGT_CMD_ERROR,83 82 TGT_CMD_READ, 84 83 TGT_CMD_WRITE, 85 84 TGT_CMD_CAS, 85 TGT_CMD_ERROR, 86 86 TGT_CMD_CONFIG 87 87 }; … … 90 90 enum tgt_rsp_fsm_state_e 91 91 { 92 TGT_RSP_CONFIG_IDLE,93 TGT_RSP_TGT_CMD_IDLE,94 92 TGT_RSP_READ_IDLE, 95 93 TGT_RSP_WRITE_IDLE, … … 98 96 TGT_RSP_MULTI_ACK_IDLE, 99 97 TGT_RSP_CLEANUP_IDLE, 100 TGT_RSP_CONFIG ,101 TGT_RSP_TGT_CMD ,98 TGT_RSP_CONFIG_IDLE, 99 TGT_RSP_TGT_CMD_IDLE, 102 100 TGT_RSP_READ, 103 101 TGT_RSP_WRITE, … … 105 103 TGT_RSP_XRAM, 106 104 TGT_RSP_MULTI_ACK, 107 TGT_RSP_CLEANUP 105 TGT_RSP_CLEANUP, 106 TGT_RSP_CONFIG, 107 TGT_RSP_TGT_CMD 108 108 }; 109 109 … … 120 120 enum cc_send_fsm_state_e 121 121 { 122 CC_SEND_CONFIG_IDLE,123 122 CC_SEND_XRAM_RSP_IDLE, 124 123 CC_SEND_WRITE_IDLE, 125 124 CC_SEND_CAS_IDLE, 126 CC_SEND_CONFIG_INVAL_HEADER, 127 CC_SEND_CONFIG_INVAL_NLINE, 128 CC_SEND_CONFIG_BRDCAST_HEADER, 129 CC_SEND_CONFIG_BRDCAST_NLINE, 125 CC_SEND_CONFIG_IDLE, 130 126 CC_SEND_XRAM_RSP_BRDCAST_HEADER, 131 127 CC_SEND_XRAM_RSP_BRDCAST_NLINE, … … 146 142 CC_SEND_CAS_UPDT_NLINE, 147 143 CC_SEND_CAS_UPDT_DATA, 148 CC_SEND_CAS_UPDT_DATA_HIGH 144 CC_SEND_CAS_UPDT_DATA_HIGH, 145 CC_SEND_CONFIG_INVAL_HEADER, 146 CC_SEND_CONFIG_INVAL_NLINE, 147 CC_SEND_CONFIG_BRDCAST_HEADER, 148 CC_SEND_CONFIG_BRDCAST_NLINE 149 149 }; 150 150 … … 335 335 { 336 336 ALLOC_DIR_RESET, 337 ALLOC_DIR_CONFIG,338 337 ALLOC_DIR_READ, 339 338 ALLOC_DIR_WRITE, 340 339 ALLOC_DIR_CAS, 341 340 ALLOC_DIR_CLEANUP, 342 ALLOC_DIR_XRAM_RSP 341 ALLOC_DIR_XRAM_RSP, 342 ALLOC_DIR_CONFIG 343 343 }; 344 344 … … 426 426 uint32_t m_cpt_cycles; // Counter of cycles 427 427 428 uint32_t m_cpt_read; // Number of READ transactions 428 // Counters accessible in software (not yet but eventually) 429 uint32_t m_cpt_read_local; // Number of local READ transactions 429 430 uint32_t m_cpt_read_remote; // number of remote READ transactions 430 uint32_t m_cpt_read_flits; // number of flits for READs431 431 uint32_t m_cpt_read_cost; // Number of (flits * distance) for READs 432 432 433 uint32_t m_cpt_read_miss; // Number of MISS READ 434 435 uint32_t m_cpt_write; // Number of WRITE transactions 433 uint32_t m_cpt_write_local; // Number of local WRITE transactions 436 434 uint32_t m_cpt_write_remote; // number of remote WRITE transactions 437 uint32_t m_cpt_write_flits; // number of flits for WRITEs 435 uint32_t m_cpt_write_flits_local; // number of flits for local WRITEs 436 uint32_t m_cpt_write_flits_remote; // number of flits for remote WRITEs 438 437 uint32_t m_cpt_write_cost; // Number of (flits * distance) for WRITEs 439 438 439 uint32_t m_cpt_ll_local; // Number of local LL transactions 440 uint32_t m_cpt_ll_remote; // number of remote LL transactions 441 uint32_t m_cpt_ll_cost; // Number of (flits * distance) for LLs 442 443 uint32_t m_cpt_sc_local; // Number of local SC transactions 444 uint32_t m_cpt_sc_remote; // number of remote SC transactions 445 uint32_t m_cpt_sc_cost; // Number of (flits * distance) for SCs 446 447 uint32_t m_cpt_cas_local; // Number of local SC transactions 448 uint32_t m_cpt_cas_remote; // number of remote SC transactions 449 uint32_t m_cpt_cas_cost; // Number of (flits * distance) for SCs 450 451 uint32_t m_cpt_update; // Number of requests causing an UPDATE 452 uint32_t m_cpt_update_local; // Number of local UPDATE transactions 453 uint32_t m_cpt_update_remote; // Number of remote UPDATE transactions 454 uint32_t m_cpt_update_cost; // Number of (flits * distance) for UPDT 455 456 uint32_t m_cpt_m_inval; // Number of requests causing M_INV 457 uint32_t m_cpt_m_inval_local; // Number of local M_INV transactions 458 uint32_t m_cpt_m_inval_remote; // Number of remote M_INV transactions 459 uint32_t m_cpt_m_inval_cost; // Number of (flits * distance) for M_INV 460 461 uint32_t m_cpt_br_inval; // Number of BROADCAST INVAL 462 463 uint32_t m_cpt_cleanup_local; // Number of local CLEANUP transactions 464 uint32_t m_cpt_cleanup_remote; // Number of remote CLEANUP transactions 465 uint32_t m_cpt_cleanup_cost; // Number of (flits * distance) for CLEANUPs 466 467 // Counters not accessible by software 468 uint32_t m_cpt_read_miss; // Number of MISS READ 440 469 uint32_t m_cpt_write_miss; // Number of MISS WRITE 441 uint32_t m_cpt_write_cells; // Cumulated length for WRITE transactions442 470 uint32_t m_cpt_write_dirty; // Cumulated length for WRITE transactions 443 uint32_t m_cpt_update; // Number of UPDATE transactions 471 uint32_t m_cpt_write_broadcast;// Number of BROADCAST INVAL because write 472 444 473 uint32_t m_cpt_trt_rb; // Read blocked by a hit in trt 445 474 uint32_t m_cpt_trt_full; // Transaction blocked due to a full trt 446 uint32_t m_cpt_update_mult; // Number of targets for UPDATE447 uint32_t m_cpt_inval; // Number of INVAL transactions448 uint32_t m_cpt_inval_mult; // Number of targets for INVAL449 uint32_t m_cpt_inval_brdcast; // Number of BROADCAST INVAL450 uint32_t m_cpt_cleanup; // Number of CLEANUP transactions451 uint32_t m_cpt_ll; // Number of LL transactions452 uint32_t m_cpt_sc; // Number of SC transactions453 uint32_t m_cpt_cas; // Number of CAS transactions454 475 455 476 uint32_t m_cpt_read_fsm_dir_lock; // wait DIR LOCK … … 547 568 uint32_t m_cpt_read_WTF; 548 569 549 uint32_t m_cpt_cleanup_cost; // Number of (flits * distance) for CLEANUPs550 551 570 uint32_t m_cpt_update_flits; // Number of flits for UPDATEs 552 uint32_t m_cpt_update_cost; // Number of (flits * distance) for UPDATEs553 554 571 uint32_t m_cpt_inval_cost; // Number of (flits * distance) for INVALs 555 572 556 573 uint32_t m_cpt_get; 557 558 574 uint32_t m_cpt_put; 559 575 … … 573 589 soclib::caba::DspinOutput<dspin_out_width> p_dspin_clack; 574 590 591 #if MONITOR_MEMCACHE_FSM == 1 592 sc_out<int> p_read_fsm; 593 sc_out<int> p_write_fsm; 594 sc_out<int> p_xram_rsp_fsm; 595 sc_out<int> p_cas_fsm; 596 sc_out<int> p_cleanup_fsm; 597 sc_out<int> p_config_fsm; 598 sc_out<int> p_alloc_heap_fsm; 599 sc_out<int> p_alloc_dir_fsm; 600 sc_out<int> p_alloc_trt_fsm; 601 sc_out<int> p_alloc_upt_fsm; 602 sc_out<int> p_alloc_ivt_fsm; 603 sc_out<int> p_tgt_cmd_fsm; 604 sc_out<int> p_tgt_rsp_fsm; 605 sc_out<int> p_ixr_cmd_fsm; 606 sc_out<int> p_ixr_rsp_fsm; 607 sc_out<int> p_cc_send_fsm; 608 sc_out<int> p_cc_receive_fsm; 609 sc_out<int> p_multi_ack_fsm; 610 #endif 611 575 612 VciMemCache( 576 613 sc_module_name name, // Instance Name … … 580 617 const soclib::common::IntTab &tgtid_d, // global index INT network 581 618 const size_t cc_global_id, // global index CC network 619 const size_t x_width, // X width in platform 620 const size_t y_width, // Y width in platform 582 621 const size_t nways, // Number of ways per set 583 622 const size_t nsets, // Number of sets … … 593 632 ~VciMemCache(); 594 633 595 void clear_stats(); 596 void print_stats(); 634 void print_stats(bool activity_counters, bool stats); 597 635 void print_trace(); 598 636 void cache_monitor(addr_t addr); … … 605 643 void genMoore(); 606 644 void check_monitor(addr_t addr, data_t data, bool read); 645 uint32_t req_distance(uint32_t req_srcid); 646 bool is_local_req(uint32_t req_srcid); 607 647 608 648 // Component attributes … … 618 658 const size_t m_words; // Number of words in a line 619 659 const size_t m_cc_global_id; // global_index on cc network 660 const size_t m_xwidth; // number of x bits in platform 661 const size_t m_ywidth; // number of y bits in platform 620 662 size_t m_debug_start_cycle; 621 663 bool m_debug_ok; … … 692 734 693 735 sc_signal<int> r_tgt_cmd_fsm; 694 sc_signal<size_t> r_tgt_cmd_srcid; // srcid for response to config695 sc_signal<size_t> r_tgt_cmd_trdid; // trdid for response to config696 sc_signal<size_t> r_tgt_cmd_pktid; // pktid for response to config697 736 698 737 /////////////////////////////////////////////////////// … … 723 762 sc_signal<bool> r_config_to_ixr_cmd_req; // valid request 724 763 sc_signal<size_t> r_config_to_ixr_cmd_index; // TRT index 725 726 764 727 765 // Buffer between CONFIG fsm and TGT_RSP fsm (send a done response to L1 cache) … … 824 862 sc_signal<size_t> r_write_upt_index; // index in Update Table 825 863 sc_signal<bool> r_write_sc_fail; // sc command failed 826 //sc_signal<bool> r_write_pending_sc; // sc command pending827 sc_signal< data_t> r_write_sc_key; // sc key864 sc_signal<data_t> r_write_sc_key; // sc command key 865 sc_signal<bool> r_write_bc_data_we; // Write enable for data buffer 828 866 829 867 // Buffer between WRITE fsm and TGT_RSP fsm (acknowledge a write command from L1) … … 836 874 // Buffer between WRITE fsm and IXR_CMD fsm 837 875 sc_signal<bool> r_write_to_ixr_cmd_req; // valid request 838 sc_signal<bool> r_write_to_ixr_cmd_put; // request type (GET/PUT)839 876 sc_signal<size_t> r_write_to_ixr_cmd_index; // TRT index 840 877 … … 965 1002 // Buffer between CAS fsm and IXR_CMD fsm (XRAM write) 966 1003 sc_signal<bool> r_cas_to_ixr_cmd_req; // valid request 967 sc_signal<bool> r_cas_to_ixr_cmd_put; // request type (GET/PUT)968 1004 sc_signal<size_t> r_cas_to_ixr_cmd_index; // TRT index 969 1005
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