Index: branches/RWT/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h
===================================================================
--- branches/RWT/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h	(revision 542)
+++ branches/RWT/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h	(revision 545)
@@ -80,8 +80,8 @@
       {
         TGT_CMD_IDLE,
-        TGT_CMD_ERROR,
         TGT_CMD_READ,
         TGT_CMD_WRITE,
         TGT_CMD_CAS,
+        TGT_CMD_ERROR,
         TGT_CMD_CONFIG
       };
@@ -90,6 +90,4 @@
       enum tgt_rsp_fsm_state_e
       {
-        TGT_RSP_CONFIG_IDLE,
-        TGT_RSP_TGT_CMD_IDLE,
         TGT_RSP_READ_IDLE,
         TGT_RSP_WRITE_IDLE,
@@ -98,6 +96,6 @@
         TGT_RSP_MULTI_ACK_IDLE,
         TGT_RSP_CLEANUP_IDLE,
-        TGT_RSP_CONFIG,
-        TGT_RSP_TGT_CMD,
+        TGT_RSP_CONFIG_IDLE,
+        TGT_RSP_TGT_CMD_IDLE,
         TGT_RSP_READ,
         TGT_RSP_WRITE,
@@ -105,5 +103,7 @@
         TGT_RSP_XRAM,
         TGT_RSP_MULTI_ACK,
-        TGT_RSP_CLEANUP
+        TGT_RSP_CLEANUP,
+        TGT_RSP_CONFIG,
+        TGT_RSP_TGT_CMD
       };
 
@@ -120,12 +120,8 @@
       enum cc_send_fsm_state_e
       {
-        CC_SEND_CONFIG_IDLE,
         CC_SEND_XRAM_RSP_IDLE,
         CC_SEND_WRITE_IDLE,
         CC_SEND_CAS_IDLE,
-        CC_SEND_CONFIG_INVAL_HEADER,
-        CC_SEND_CONFIG_INVAL_NLINE,
-        CC_SEND_CONFIG_BRDCAST_HEADER,
-        CC_SEND_CONFIG_BRDCAST_NLINE,
+        CC_SEND_CONFIG_IDLE,
         CC_SEND_XRAM_RSP_BRDCAST_HEADER,
         CC_SEND_XRAM_RSP_BRDCAST_NLINE,
@@ -146,5 +142,9 @@
         CC_SEND_CAS_UPDT_NLINE,
         CC_SEND_CAS_UPDT_DATA,
-        CC_SEND_CAS_UPDT_DATA_HIGH
+        CC_SEND_CAS_UPDT_DATA_HIGH,
+        CC_SEND_CONFIG_INVAL_HEADER,
+        CC_SEND_CONFIG_INVAL_NLINE,
+        CC_SEND_CONFIG_BRDCAST_HEADER,
+        CC_SEND_CONFIG_BRDCAST_NLINE
       };
 
@@ -335,10 +335,10 @@
       {
         ALLOC_DIR_RESET,
-        ALLOC_DIR_CONFIG,
         ALLOC_DIR_READ,
         ALLOC_DIR_WRITE,
         ALLOC_DIR_CAS,
         ALLOC_DIR_CLEANUP,
-        ALLOC_DIR_XRAM_RSP
+        ALLOC_DIR_XRAM_RSP,
+        ALLOC_DIR_CONFIG
       };
 
@@ -426,30 +426,51 @@
       uint32_t     m_cpt_cycles;        // Counter of cycles
 
-      uint32_t     m_cpt_read;          // Number of READ transactions
+      // Counters accessible in software (not yet but eventually)
+      uint32_t     m_cpt_read_local;     // Number of local READ transactions
       uint32_t     m_cpt_read_remote;   // number of remote READ transactions
-      uint32_t     m_cpt_read_flits;    // number of flits for READs
       uint32_t     m_cpt_read_cost;     // Number of (flits * distance) for READs
 
-      uint32_t     m_cpt_read_miss;     // Number of MISS READ
-
-      uint32_t     m_cpt_write;         // Number of WRITE transactions
+      uint32_t     m_cpt_write_local;    // Number of local WRITE transactions
       uint32_t     m_cpt_write_remote;  // number of remote WRITE transactions
-      uint32_t     m_cpt_write_flits;   // number of flits for WRITEs
+      uint32_t     m_cpt_write_flits_local;  // number of flits for local WRITEs
+      uint32_t     m_cpt_write_flits_remote; // number of flits for remote WRITEs
       uint32_t     m_cpt_write_cost;    // Number of (flits * distance) for WRITEs
 
+      uint32_t     m_cpt_ll_local;       // Number of local LL transactions
+      uint32_t     m_cpt_ll_remote;      // number of remote LL transactions
+      uint32_t     m_cpt_ll_cost;        // Number of (flits * distance) for LLs
+
+      uint32_t     m_cpt_sc_local;       // Number of local SC transactions
+      uint32_t     m_cpt_sc_remote;      // number of remote SC transactions
+      uint32_t     m_cpt_sc_cost;        // Number of (flits * distance) for SCs
+
+      uint32_t     m_cpt_cas_local;      // Number of local SC transactions
+      uint32_t     m_cpt_cas_remote;     // number of remote SC transactions
+      uint32_t     m_cpt_cas_cost;       // Number of (flits * distance) for SCs
+
+      uint32_t     m_cpt_update;         // Number of requests causing an UPDATE
+      uint32_t     m_cpt_update_local;   // Number of local UPDATE transactions
+      uint32_t     m_cpt_update_remote;  // Number of remote UPDATE transactions
+      uint32_t     m_cpt_update_cost;    // Number of (flits * distance) for UPDT
+
+      uint32_t     m_cpt_m_inval;        // Number of requests causing M_INV
+      uint32_t     m_cpt_m_inval_local;  // Number of local M_INV transactions
+      uint32_t     m_cpt_m_inval_remote; // Number of remote M_INV transactions
+      uint32_t     m_cpt_m_inval_cost;   // Number of (flits * distance) for M_INV
+
+      uint32_t     m_cpt_br_inval;       // Number of BROADCAST INVAL
+
+      uint32_t     m_cpt_cleanup_local;  // Number of local CLEANUP transactions
+      uint32_t     m_cpt_cleanup_remote; // Number of remote CLEANUP transactions
+      uint32_t     m_cpt_cleanup_cost;   // Number of (flits * distance) for CLEANUPs
+
+      // Counters not accessible by software
+      uint32_t     m_cpt_read_miss;      // Number of MISS READ
       uint32_t     m_cpt_write_miss;    // Number of MISS WRITE
-      uint32_t     m_cpt_write_cells;   // Cumulated length for WRITE transactions
       uint32_t     m_cpt_write_dirty;   // Cumulated length for WRITE transactions
-      uint32_t     m_cpt_update;        // Number of UPDATE transactions
+      uint32_t     m_cpt_write_broadcast;// Number of BROADCAST INVAL because write
+
       uint32_t     m_cpt_trt_rb;        // Read blocked by a hit in trt
       uint32_t     m_cpt_trt_full;      // Transaction blocked due to a full trt
-      uint32_t     m_cpt_update_mult;   // Number of targets for UPDATE
-      uint32_t     m_cpt_inval;         // Number of INVAL  transactions
-      uint32_t     m_cpt_inval_mult;    // Number of targets for INVAL
-      uint32_t     m_cpt_inval_brdcast; // Number of BROADCAST INVAL
-      uint32_t     m_cpt_cleanup;       // Number of CLEANUP transactions
-      uint32_t     m_cpt_ll;            // Number of LL transactions
-      uint32_t     m_cpt_sc;            // Number of SC transactions
-      uint32_t     m_cpt_cas;           // Number of CAS transactions
       
       uint32_t     m_cpt_read_fsm_dir_lock;        // wait DIR LOCK
@@ -547,13 +568,8 @@
       uint32_t     m_cpt_read_WTF;
 
-      uint32_t     m_cpt_cleanup_cost;  // Number of (flits * distance) for CLEANUPs
-
       uint32_t     m_cpt_update_flits;  // Number of flits for UPDATEs
-      uint32_t     m_cpt_update_cost;   // Number of (flits * distance) for UPDATEs
-
       uint32_t     m_cpt_inval_cost;    // Number of (flits * distance) for INVALs
 
       uint32_t     m_cpt_get;
-
       uint32_t     m_cpt_put;
 
@@ -573,4 +589,25 @@
       soclib::caba::DspinOutput<dspin_out_width>  p_dspin_clack;
 
+#if MONITOR_MEMCACHE_FSM == 1
+      sc_out<int> p_read_fsm; 
+      sc_out<int> p_write_fsm; 
+      sc_out<int> p_xram_rsp_fsm; 
+      sc_out<int> p_cas_fsm; 
+      sc_out<int> p_cleanup_fsm; 
+      sc_out<int> p_config_fsm; 
+      sc_out<int> p_alloc_heap_fsm; 
+      sc_out<int> p_alloc_dir_fsm; 
+      sc_out<int> p_alloc_trt_fsm; 
+      sc_out<int> p_alloc_upt_fsm; 
+      sc_out<int> p_alloc_ivt_fsm; 
+      sc_out<int> p_tgt_cmd_fsm; 
+      sc_out<int> p_tgt_rsp_fsm; 
+      sc_out<int> p_ixr_cmd_fsm; 
+      sc_out<int> p_ixr_rsp_fsm; 
+      sc_out<int> p_cc_send_fsm; 
+      sc_out<int> p_cc_receive_fsm; 
+      sc_out<int> p_multi_ack_fsm; 
+#endif
+
       VciMemCache(
           sc_module_name name,                                // Instance Name
@@ -580,4 +617,6 @@
           const soclib::common::IntTab       &tgtid_d,        // global index INT network
           const size_t                       cc_global_id,    // global index CC network
+          const size_t                       x_width,         // X width in platform
+          const size_t                       y_width,         // Y width in platform
           const size_t                       nways,           // Number of ways per set
           const size_t                       nsets,           // Number of sets
@@ -593,6 +632,5 @@
       ~VciMemCache();
 
-      void clear_stats();
-      void print_stats();
+      void print_stats(bool activity_counters, bool stats);
       void print_trace();
       void cache_monitor(addr_t addr);
@@ -605,4 +643,6 @@
       void genMoore();
       void check_monitor(addr_t addr, data_t data, bool read);
+      uint32_t req_distance(uint32_t req_srcid);
+      bool is_local_req(uint32_t req_srcid);
 
       // Component attributes
@@ -618,4 +658,6 @@
       const size_t                       m_words;            // Number of words in a line
       const size_t                       m_cc_global_id;     // global_index on cc network
+      const size_t                       m_xwidth;           // number of x bits in platform
+      const size_t                       m_ywidth;           // number of y bits in platform
       size_t                             m_debug_start_cycle;
       bool                               m_debug_ok;
@@ -692,7 +734,4 @@
 
       sc_signal<int>         r_tgt_cmd_fsm;
-      sc_signal<size_t>      r_tgt_cmd_srcid;           // srcid for response to config
-      sc_signal<size_t>      r_tgt_cmd_trdid;           // trdid for response to config
-      sc_signal<size_t>      r_tgt_cmd_pktid;           // pktid for response to config
 
       ///////////////////////////////////////////////////////
@@ -723,5 +762,4 @@
       sc_signal<bool>     r_config_to_ixr_cmd_req;    // valid request
       sc_signal<size_t>   r_config_to_ixr_cmd_index;  // TRT index
-
 
       // Buffer between CONFIG fsm and TGT_RSP fsm (send a done response to L1 cache)
@@ -824,6 +862,6 @@
       sc_signal<size_t>   r_write_upt_index;          // index in Update Table
       sc_signal<bool>     r_write_sc_fail;            // sc command failed
-      //sc_signal<bool>     r_write_pending_sc;         // sc command pending
-      sc_signal<data_t>   r_write_sc_key;             // sc key
+      sc_signal<data_t>   r_write_sc_key;             // sc command key
+      sc_signal<bool>     r_write_bc_data_we;         // Write enable for data buffer
  
       // Buffer between WRITE fsm and TGT_RSP fsm (acknowledge a write command from L1)
@@ -836,5 +874,4 @@
       // Buffer between WRITE fsm and IXR_CMD fsm 
       sc_signal<bool>     r_write_to_ixr_cmd_req;     // valid request
-      sc_signal<bool>     r_write_to_ixr_cmd_put;     // request type (GET/PUT)
       sc_signal<size_t>   r_write_to_ixr_cmd_index;   // TRT index 
 
@@ -965,5 +1002,4 @@
       // Buffer between CAS fsm and IXR_CMD fsm (XRAM write)
       sc_signal<bool>     r_cas_to_ixr_cmd_req;   // valid request
-      sc_signal<bool>     r_cas_to_ixr_cmd_put;   // request type (GET/PUT)
       sc_signal<size_t>   r_cas_to_ixr_cmd_index; // TRT index 
 
