Ignore:
Timestamp:
Oct 17, 2013, 8:50:46 PM (11 years ago)
Author:
alain
Message:

Compliance with mapping_table defined in release 2462
Introducing the dspin_router_tsar component used in tsar_generic_iob
platform to implement the RAM networt (between L2 & L3).

Location:
trunk/modules/vci_cc_vcache_wrapper/caba/source
Files:
2 edited

Legend:

Unmodified
Added
Removed

  • trunk/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h

    r487 r549  
    296296
    297297    // STRUCTURAL PARAMETERS
    298     soclib::common::AddressDecodingTable<uint32_t, bool> m_cacheability_table;
     298    soclib::common::AddressDecodingTable<uint64_t, bool> m_cacheability_table;
    299299
    300300    const size_t                        m_srcid;
    … …  
    394394    // communication between ICACHE FSM and CC_SEND FSM
    395395    sc_signal<bool>         r_icache_cc_send_req;           // ICACHE cc_send request
    396     sc_signal<cc_send_t>    r_icache_cc_send_type;          // ICACHE cc_send request type
     396    sc_signal<int>          r_icache_cc_send_type;          // ICACHE cc_send request type
    397397    sc_signal<paddr_t>      r_icache_cc_send_nline;         // ICACHE cc_send nline
    398398    sc_signal<size_t>       r_icache_cc_send_way;           // ICACHE cc_send way
    … …  
    491491    // communication between DCACHE FSM and CC_SEND FSM
    492492    sc_signal<bool>         r_dcache_cc_send_req;           // DCACHE cc_send request
    493     sc_signal<cc_send_t>    r_dcache_cc_send_type;          // DCACHE cc_send request type
     493    sc_signal<int>          r_dcache_cc_send_type;          // DCACHE cc_send request type
    494494    sc_signal<paddr_t>      r_dcache_cc_send_nline;         // DCACHE cc_send nline
    495495    sc_signal<size_t>       r_dcache_cc_send_way;           // DCACHE cc_send way
    … …  
    542542    // communication between CC_RECEIVE FSM and ICACHE FSM
    543543    sc_signal<bool>         r_cc_receive_icache_req;        // cc_receive to icache request
    544     sc_signal<cc_receive_t> r_cc_receive_icache_type;       // cc_receive type of request
     544    sc_signal<int>          r_cc_receive_icache_type;       // cc_receive type of request
    545545    sc_signal<size_t>       r_cc_receive_icache_way;        // cc_receive to icache way
    546546    sc_signal<size_t>       r_cc_receive_icache_set;        // cc_receive to icache set
    … …  
    550550    // communication between CC_RECEIVE FSM and DCACHE FSM
    551551    sc_signal<bool>         r_cc_receive_dcache_req;        // cc_receive to dcache request
    552     sc_signal<cc_receive_t> r_cc_receive_dcache_type;       // cc_receive type of request
     552    sc_signal<int>          r_cc_receive_dcache_type;       // cc_receive type of request
    553553    sc_signal<size_t>       r_cc_receive_dcache_way;        // cc_receive to dcache way
    554554    sc_signal<size_t>       r_cc_receive_dcache_set;        // cc_receive to dcache set

  • trunk/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp

    r532 r549  
    11551155                // cacheability
    11561156                if ( not (r_mmu_mode.read() & INS_CACHE_MASK) ) cacheable = false;
    1157                 else     cacheable = m_cacheability_table[m_ireq.addr];
     1157                else     cacheable = m_cacheability_table[(uint64_t)m_ireq.addr];
    11581158            }
    11591159            else                                                        // itlb activated
    … …  
    26472647
    26482648                    if ( not (r_mmu_mode.read() & DATA_CACHE_MASK) ) cacheable = false;
    2649                     else cacheable = m_cacheability_table[m_dreq.addr];
     2649                    else cacheable = m_cacheability_table[(uint64_t)m_dreq.addr];
    26502650                }
    26512651                else                                                                       // dtlb activated
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