Ignore:
Timestamp:
Oct 17, 2013, 8:50:46 PM (11 years ago)
Author:
alain
Message:

Compliance with mapping_table defined in release 2462
Introducing the dspin_router_tsar component used in tsar_generic_iob
platform to implement the RAM networt (between L2 & L3).

File:
1 edited

Legend:

Unmodified
Added
Removed
  • trunk/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp

    r532 r549  
    11551155                // cacheability
    11561156                if ( not (r_mmu_mode.read() & INS_CACHE_MASK) ) cacheable = false;
    1157                 else     cacheable = m_cacheability_table[m_ireq.addr];
     1157                else     cacheable = m_cacheability_table[(uint64_t)m_ireq.addr];
    11581158            }
    11591159            else                                                        // itlb activated
     
    26472647
    26482648                    if ( not (r_mmu_mode.read() & DATA_CACHE_MASK) ) cacheable = false;
    2649                     else cacheable = m_cacheability_table[m_dreq.addr];
     2649                    else cacheable = m_cacheability_table[(uint64_t)m_dreq.addr];
    26502650                }
    26512651                else                                                                       // dtlb activated
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