Changeset 549 for trunk/modules/vci_cc_vcache_wrapper/caba/source/src

Timestamp:

Oct 17, 2013, 8:50:46 PM (11 years ago)

Author:

alain

Message:

Compliance with mapping_table defined in release 2462
Introducing the dspin_router_tsar component used in tsar_generic_iob
platform to implement the RAM networt (between L2 & L3).

File:

• trunk/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp (modified) (2 diffs)

trunk/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp

@@ -1155 +1155 @@
                 // cacheability
                 if ( not (r_mmu_mode.read() & INS_CACHE_MASK) ) cacheable = false;
-                else     cacheable = m_cacheability_table[m_ireq.addr];
+                else     cacheable = m_cacheability_table[(uint64_t)m_ireq.addr];
             }
             else                                                        // itlb activated
@@ -2647 +2647 @@
 
                     if ( not (r_mmu_mode.read() & DATA_CACHE_MASK) ) cacheable = false;
-                    else cacheable = m_cacheability_table[m_dreq.addr];
+                    else cacheable = m_cacheability_table[(uint64_t)m_dreq.addr];
                 }
                 else                                                                       // dtlb activated