Index: trunk/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h
===================================================================
--- trunk/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h	(revision 532)
+++ trunk/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h	(revision 549)
@@ -296,5 +296,5 @@
 
     // STRUCTURAL PARAMETERS
-    soclib::common::AddressDecodingTable<uint32_t, bool> m_cacheability_table;
+    soclib::common::AddressDecodingTable<uint64_t, bool> m_cacheability_table;
 
     const size_t                        m_srcid;
@@ -394,5 +394,5 @@
     // communication between ICACHE FSM and CC_SEND FSM
     sc_signal<bool>         r_icache_cc_send_req;           // ICACHE cc_send request
-    sc_signal<cc_send_t>    r_icache_cc_send_type;          // ICACHE cc_send request type
+    sc_signal<int>          r_icache_cc_send_type;          // ICACHE cc_send request type
     sc_signal<paddr_t>      r_icache_cc_send_nline;         // ICACHE cc_send nline
     sc_signal<size_t>       r_icache_cc_send_way;           // ICACHE cc_send way
@@ -491,5 +491,5 @@
     // communication between DCACHE FSM and CC_SEND FSM
     sc_signal<bool>         r_dcache_cc_send_req;           // DCACHE cc_send request
-    sc_signal<cc_send_t>    r_dcache_cc_send_type;          // DCACHE cc_send request type
+    sc_signal<int>          r_dcache_cc_send_type;          // DCACHE cc_send request type
     sc_signal<paddr_t>      r_dcache_cc_send_nline;         // DCACHE cc_send nline
     sc_signal<size_t>       r_dcache_cc_send_way;           // DCACHE cc_send way
@@ -542,5 +542,5 @@
     // communication between CC_RECEIVE FSM and ICACHE FSM
     sc_signal<bool>         r_cc_receive_icache_req;        // cc_receive to icache request
-    sc_signal<cc_receive_t> r_cc_receive_icache_type;       // cc_receive type of request
+    sc_signal<int>          r_cc_receive_icache_type;       // cc_receive type of request
     sc_signal<size_t>       r_cc_receive_icache_way;        // cc_receive to icache way
     sc_signal<size_t>       r_cc_receive_icache_set;        // cc_receive to icache set
@@ -550,5 +550,5 @@
     // communication between CC_RECEIVE FSM and DCACHE FSM
     sc_signal<bool>         r_cc_receive_dcache_req;        // cc_receive to dcache request
-    sc_signal<cc_receive_t> r_cc_receive_dcache_type;       // cc_receive type of request
+    sc_signal<int>          r_cc_receive_dcache_type;       // cc_receive type of request
     sc_signal<size_t>       r_cc_receive_dcache_way;        // cc_receive to dcache way
     sc_signal<size_t>       r_cc_receive_dcache_set;        // cc_receive to dcache set
Index: trunk/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp
===================================================================
--- trunk/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp	(revision 532)
+++ trunk/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp	(revision 549)
@@ -1155,5 +1155,5 @@
                 // cacheability
                 if ( not (r_mmu_mode.read() & INS_CACHE_MASK) ) cacheable = false;
-                else     cacheable = m_cacheability_table[m_ireq.addr];
+                else     cacheable = m_cacheability_table[(uint64_t)m_ireq.addr];
             }
             else						        // itlb activated
@@ -2647,5 +2647,5 @@
 
                     if ( not (r_mmu_mode.read() & DATA_CACHE_MASK) ) cacheable = false;
-                    else cacheable = m_cacheability_table[m_dreq.addr];
+                    else cacheable = m_cacheability_table[(uint64_t)m_dreq.addr];
                 }
                 else 							                   // dtlb activated