Index: trunk/modules/dspin_router_tsar/caba/metadata/dspin_router_tsar.sd =================================================================== --- trunk/modules/dspin_router_tsar/caba/metadata/dspin_router_tsar.sd (revision 549) +++ trunk/modules/dspin_router_tsar/caba/metadata/dspin_router_tsar.sd (revision 549) @@ -0,0 +1,30 @@ +# -*- python -*- + +Module('caba:dspin_router_tsar', + classname = 'soclib::caba::DspinRouterTsar', + tmpl_parameters = [ parameter.Int('flit_width'), ], + header_files = ['../source/include/dspin_router_tsar.h',], + implementation_files = ['../source/src/dspin_router_tsar.cpp',], + ports = [ + Port('caba:bit_in', 'p_resetn', auto = 'resetn'), + Port('caba:clock_in', 'p_clk', auto = 'clock'), + Port('caba:dspin_output', 'p_out', 5, dspin_data_size = parameter.Reference('flit_width')), + Port('caba:dspin_input', 'p_in', 5, dspin_data_size = parameter.Reference('flit_width')), + ], + instance_parameters = [ + parameter.Int('x'), + parameter.Int('y'), + parameter.Int('x_width'), + parameter.Int('y_width'), + parameter.Int('in_fifo_depth'), + parameter.Int('out_fifo_depth'), + parameter.Int('cluster_iob0'), + parameter.Int('cluster_iob1'), + parameter.Int('l_width'), + parameter.Int('iob_local_id'), + ], + uses = [ + Uses('caba:base_module'), + Uses('caba:generic_fifo'), + ], +) Index: trunk/modules/dspin_router_tsar/caba/source/include/dspin_router_tsar.h =================================================================== --- trunk/modules/dspin_router_tsar/caba/source/include/dspin_router_tsar.h (revision 549) +++ trunk/modules/dspin_router_tsar/caba/source/include/dspin_router_tsar.h (revision 549) @@ -0,0 +1,157 @@ +/* -*- c++ -*- + * + * File : dspin_router_tsar.h + * Copyright (c) UPMC, Lip6 + * Authors : Alain Greiner + * + * SOCLIB_LGPL_HEADER_BEGIN + * + * This file is part of SoCLib, GNU LGPLv2.1. + * + * SoCLib is free software; you can redistribute it and/or modify it + * under the terms of the GNU Lesser General Public License as published + * by the Free Software Foundation; version 2.1 of the License. + * + * SoCLib is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with SoCLib; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301 USA + * + * SOCLIB_LGPL_HEADER_END + * + */ + +//////////////////////////////////////////////////////////////////////////////// +// This component implements a variant of the standard (SocLib) DSPIN router: +// The routing function has been modified to handle the special case of +// cluster_iob0 (containing component IOB0) and cluster_iob1 (containing +// component IOB1). In those two cluster, the response router must decode +// both the SRCID global bits AND the SRCID local bits to distinguish +// between the IOB and MEMC initiators. +// This component contains the following modifications: +// - 4 extra constructor arguments, +// - 6 new member variables +// - a modified routing function +//////////////////////////////////////////////////////////////////////////////// + +#ifndef DSPIN_ROUTER_TSAR_H_ +#define DSPIN_ROUTER_TSAR_H_ + +#include +#include "caba_base_module.h" +#include "generic_fifo.h" +#include "dspin_interface.h" +#include "alloc_elems.h" + +namespace soclib { namespace caba { + +using namespace sc_core; + +template +class DspinRouterTsar +: public soclib::caba::BaseModule +{ + // Port indexing + enum + { + DSPIN_NORTH = 0, + DSPIN_SOUTH = 1, + DSPIN_EAST = 2, + DSPIN_WEST = 3, + DSPIN_LOCAL = 4, + }; + + // Input Port FSM + enum + { + INFSM_IDLE, + INFSM_REQ, + INFSM_ALLOC, + }; + + protected: + SC_HAS_PROCESS(DspinRouterTsar); + + public: + + // ports + sc_in p_clk; + sc_in p_resetn; + DspinInput *p_in; + DspinOutput *p_out; + + // constructor + DspinRouterTsar( + sc_module_name name, + const size_t x, // x coordinate + const size_t y, // y cordinate + const size_t x_width, // x field width in first flit + const size_t y_width, // y field width in first flit + const size_t in_fifo_depth, // input fifo depth + const size_t out_fifo_depth, // output fifo depth + const size_t cluster_iob0, // cluster containing IOB0 + const size_t cluster_iob1, // cluster containing IOB0 + const size_t l_width, // local field width in first flit + const size_t iob_local_id ); // IOB local index + private: + + // define the FIFO flit + typedef struct internal_flit_s + { + sc_uint data; + bool eop; + } internal_flit_t; + + // registers + sc_signal *r_alloc_out; + sc_signal *r_index_out; + sc_signal *r_fsm_in; + sc_signal *r_index_in; + + // fifos + soclib::caba::GenericFifo* r_fifo_in; + soclib::caba::GenericFifo* r_fifo_out; + + // structural parameters + size_t m_local_x; + size_t m_local_y; + size_t m_x_width; + size_t m_x_shift; + size_t m_x_mask; + size_t m_y_width; + size_t m_y_shift; + size_t m_y_mask; + size_t m_l_width; + size_t m_l_shift; + size_t m_l_mask; + bool m_is_iob0; + bool m_is_iob1; + size_t m_iob_local_id; + + // methods + void transition(); + void genMoore(); + size_t route( sc_uint data ); + + public: + + void print_trace(); +}; + +}} // end namespace + +#endif // DSPIN_ROUTER_TSAR_H_ + +// Local Variables: +// tab-width: 4 +// c-basic-offset: 4 +// c-file-offsets:((innamespace . 0)(inline-open . 0)) +// indent-tabs-mode: nil +// End: + +// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 Index: trunk/modules/dspin_router_tsar/caba/source/src/dspin_router_tsar.cpp =================================================================== --- trunk/modules/dspin_router_tsar/caba/source/src/dspin_router_tsar.cpp (revision 549) +++ trunk/modules/dspin_router_tsar/caba/source/src/dspin_router_tsar.cpp (revision 549) @@ -0,0 +1,372 @@ +/* -*- c++ -*- + * + * File : dspin_router_tsar.cpp + * Copyright (c) UPMC, Lip6 + * Authors : Alain Greiner, Abbas Sheibanyrad, Ivan Miro, Zhen Zhang + * + * SOCLIB_LGPL_HEADER_BEGIN + * + * This file is part of SoCLib, GNU LGPLv2.1. + * + * SoCLib is free software; you can redistribute it and/or modify it + * under the terms of the GNU Lesser General Public License as published + * by the Free Software Foundation; version 2.1 of the License. + * + * SoCLib is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with SoCLib; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301 USA + * + * SOCLIB_LGPL_HEADER_END + * + */ + +//////////////////////////////////////////////////////////////////////////////// +// This component implements a variant of the standard (SocLib) DSPIN router: +// The routing function has been modified to handle the special case of +// cluster_iob0 (containing component IOB0) and cluster_iob1 (containing +// component IOB1). In those two cluster, the response router must decode +// both the SRCID global bits AND the SRCID local bits to distinguish +// between the IOB and MEMC initiators. +// This component contains the following modifications: +// - 4 extra constructor arguments, +// - 6 new member variables +// - a modified routing function +//////////////////////////////////////////////////////////////////////////////// + +#include "../include/dspin_router_tsar.h" + +namespace soclib { namespace caba { + +using namespace soclib::common; +using namespace soclib::caba; + +#define tmpl(x) template x DspinRouterTsar + + //////////////////////////////////////////////// + // constructor + //////////////////////////////////////////////// + tmpl(/**/)::DspinRouterTsar( + sc_module_name name, + const size_t x, // x coordinate + const size_t y, // y cordinate + const size_t x_width, // x field width in first flit + const size_t y_width, // y field width in first flit + const size_t in_fifo_depth, // input fifo depth + const size_t out_fifo_depth, // output fifo depth + const size_t cluster_iob0, // cluster containing IOB0 + const size_t cluster_iob1, // cluster containing IOB0 + const size_t l_width, // local field width in first flit + const size_t iob_local_id ) // IOB local index + : soclib::caba::BaseModule(name), + + p_clk( "p_clk" ), + p_resetn( "p_resetn" ), + p_in( alloc_elems >("p_in", 5) ), + p_out( alloc_elems >("p_out", 5) ), + + r_alloc_out( alloc_elems >("r_alloc_out", 5)), + r_index_out( soclib::common::alloc_elems >("r_index_out", 5)), + r_fsm_in( alloc_elems >("r_fsm_in", 5)), + r_index_in( alloc_elems >("r_index_in", 5)), + + m_local_x( x ), + m_local_y( y ), + + m_x_width( x_width ), + m_x_shift( flit_width - x_width ), + m_x_mask( (0x1 << x_width) - 1 ), + + m_y_width( y_width ), + m_y_shift( flit_width - x_width - y_width ), + m_y_mask( (0x1 << y_width) - 1 ), + + m_l_width( l_width ), + m_l_shift( flit_width - x_width - y_width - l_width ), + m_l_mask( (0x1 << l_width) - 1 ), + + m_is_iob0( cluster_iob0 == ((x<*) + malloc(sizeof(GenericFifo)*5); + r_fifo_out = (GenericFifo*) + malloc(sizeof(GenericFifo)*5); + + for( size_t i = 0 ; i < 5 ; i++ ) + { + std::ostringstream stri; + stri << "r_in_fifo_" << i; + new(&r_fifo_in[i]) + GenericFifo(stri.str(), in_fifo_depth); + + std::ostringstream stro; + stro << "r_out_fifo_" << i; + new(&r_fifo_out[i]) + GenericFifo(stro.str(), out_fifo_depth); + } + } // end constructor + + ////////////////////////////////////////////////// + tmpl(size_t)::route( sc_uint data ) + { + size_t xdest = (size_t)(data >> m_x_shift) & m_x_mask; + size_t ydest = (size_t)(data >> m_y_shift) & m_y_mask; + size_t ldest = (size_t)(data >> m_l_shift) & m_l_mask; + + if (xdest < m_local_x ) return DSPIN_WEST; + else if (xdest > m_local_x ) return DSPIN_EAST; + else if (ydest < m_local_y ) return DSPIN_SOUTH; + else if (ydest > m_local_y ) return DSPIN_NORTH; + else // handling IOB0 & IOB1 special cases + { + if ((m_is_iob0) and (ldest > 0xA)) return DSPIN_WEST; + else if ((m_is_iob1) and (ldest > 0xA)) return DSPIN_EAST; + else return DSPIN_LOCAL; + } + } // end route() + + ///////////////////////// + tmpl(void)::print_trace() + { + const char* port_name[] = {"NORTH","SOUTH","EAST ","WEST ","LOCAL"}; + + std::cout << "DSPIN_ROUTER " << name() << std::hex; + for ( size_t out=0 ; out<5 ; out++) // loop on output ports + { + if ( r_alloc_out[out].read() ) + { + int in = r_index_out[out]; + std::cout << " / " << port_name[in] << " -> " << port_name[out] ; + } + } + std::cout << std::endl; + } + + //////////////////////// + tmpl(void)::transition() + { + // Long wires connecting input and output ports + size_t req_in[5]; // input ports -> output ports + size_t get_out[5]; // output ports -> input ports + bool put_in[5]; // input ports -> output ports + internal_flit_t flit_in[5]; // input ports -> output ports + + // control signals for the input fifos + bool fifo_in_write[5]; + bool fifo_in_read[5]; + internal_flit_t fifo_in_wdata[5]; + + // control signals for the output fifos + bool fifo_out_write[5]; + bool fifo_out_read[5]; + internal_flit_t fifo_out_wdata[5]; + + // Reset + if ( p_resetn == false ) + { + for(size_t i = 0 ; i < 5 ; i++) + { + r_alloc_out[i] = false; + r_index_out[i] = 0; + r_index_in[i] = 0; + r_fsm_in[i] = INFSM_IDLE; + r_fifo_in[i].init(); + r_fifo_out[i].init(); + } + return; + } + + // fifos signals default values + for(size_t i = 0 ; i < 5 ; i++) + { + fifo_in_read[i] = false; + fifo_in_write[i] = p_in[i].write.read(); + fifo_in_wdata[i].data = p_in[i].data.read(); + fifo_in_wdata[i].eop = p_in[i].eop.read(); + + fifo_out_read[i] = p_out[i].read.read(); + fifo_out_write[i] = false; + } + + // loop on the output ports: + // compute get_out[j] depending on the output port state + // and combining fifo_out[j].wok and r_alloc_out[j] + for ( size_t j = 0 ; j < 5 ; j++ ) + { + if( r_alloc_out[j].read() and (r_fifo_out[j].wok()) ) + { + get_out[j] = r_index_out[j].read(); + } + else + { + get_out[j] = 0xFFFFFFFF; + } + } + + // loop on the input ports : + // The port state is defined by r_fsm_in[i], r_index_in[i] + // The req_in[i] computation implements the X-FIRST algorithm. + // Both put_in[i] and req_in[i] depend on the input port state. + + for ( size_t i = 0 ; i < 5 ; i++ ) + { + switch ( r_fsm_in[i].read() ) + { + case INFSM_IDLE: // no output port allocated + { + put_in[i] = false; + if ( r_fifo_in[i].rok() ) // packet available in input fifo + { + req_in[i] = route( r_fifo_in[i].read().data ); + r_index_in[i] = req_in[i]; + r_fsm_in[i] = INFSM_REQ; + } + else + { + req_in[i] = 0xFFFFFFFF; // no request + } + break; + } + case INFSM_REQ: // waiting output port allocation + { + flit_in[i] = r_fifo_in[i].read(); + put_in[i] = r_fifo_in[i].rok(); + req_in[i] = r_index_in[i]; + if ( get_out[r_index_in[i].read()] == i ) // first flit transfered + { + if ( r_fifo_in[i].read().eop ) r_fsm_in[i] = INFSM_IDLE; + else r_fsm_in[i] = INFSM_ALLOC; + } + break; + } + case INFSM_ALLOC: // output port allocated + { + flit_in[i] = r_fifo_in[i].read(); + put_in[i] = r_fifo_in[i].rok(); + req_in[i] = 0xFFFFFFFF; // no request + if ( r_fifo_in[i].read().eop and r_fifo_in[i].rok() and + (get_out[r_index_in[i].read()] == i) ) // last flit transfered + { + r_fsm_in[i] = INFSM_IDLE; + } + break; + } + } // end switch + } // end for input ports + + // loop on the output ports : + // The r_alloc_out[j] and r_index_out[j] computation + // implements the round-robin allocation policy. + // These two registers implement a 10 states FSM. + for( size_t j = 0 ; j < 5 ; j++ ) + { + if( not r_alloc_out[j].read() ) // not allocated: possible new allocation + { + for( size_t k = r_index_out[j].read() + 1 ; + k < (r_index_out[j] + 6) ; k++) + { + size_t i = k % 5; + + if( req_in[i] == j ) + { + r_alloc_out[j] = true; + r_index_out[j] = i; + break; + } + } // end loop on input ports + } + else // allocated: possible desallocation + { + if ( flit_in[r_index_out[j]].eop and + r_fifo_out[j].wok() and + put_in[r_index_out[j]] ) + { + r_alloc_out[j] = false; + } + } + } // end loop on output ports + + // loop on input ports : + // fifo_in_read[i] computation (get data from fifo_in[i] + // (computed here because it depends on get_out[]) + for( size_t i = 0 ; i < 5 ; i++ ) + { + if ( r_fsm_in[i].read() != INFSM_IDLE ) + { + fifo_in_read[i] = (get_out[r_index_in[i].read()] == i); + } + else + { + fifo_in_read[i] = false; + } + } // end loop on input ports + + // loop on the output ports : + // The fifo_out_write[j] and fifo_out_wdata[j] computation + // implements the output port mux. + for( size_t j = 0 ; j < 5 ; j++ ) + { + if( r_alloc_out[j] ) // output port allocated + { + fifo_out_write[j] = put_in[r_index_out[j]]; + fifo_out_wdata[j] = flit_in[r_index_out[j]]; + } + } // end loop on the output ports + + // FIFOS update + for(size_t i = 0 ; i < 5 ; i++) + { + r_fifo_in[i].update(fifo_in_read[i], + fifo_in_write[i], + fifo_in_wdata[i]); + r_fifo_out[i].update(fifo_out_read[i], + fifo_out_write[i], + fifo_out_wdata[i]); + } + } // end transition + + //////////////////////////////// + // genMoore + //////////////////////////////// + tmpl(void)::genMoore() + { + for(size_t i = 0 ; i < 5 ; i++) + { + // input ports : READ signals + p_in[i].read = r_fifo_in[i].wok(); + + // output ports : DATA & WRITE signals + p_out[i].data = r_fifo_out[i].read().data; + p_out[i].eop = r_fifo_out[i].read().eop; + p_out[i].write = r_fifo_out[i].rok(); + } + } // end genMoore + +}} // end namespace + +// Local Variables: +// tab-width: 4 +// c-basic-offset: 4 +// c-file-offsets:((innamespace . 0)(inline-open . 0)) +// indent-tabs-mode: nil +// End: + +// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 Index: trunk/modules/vci_block_device_tsar/caba/metadata/vci_block_device_tsar.sd =================================================================== --- trunk/modules/vci_block_device_tsar/caba/metadata/vci_block_device_tsar.sd (revision 537) +++ trunk/modules/vci_block_device_tsar/caba/metadata/vci_block_device_tsar.sd (revision 549) @@ -39,7 +39,7 @@ parameter.IntTab('tgtid'), parameter.String('filename'), - parameter.Int('block_size'), - parameter.Int('burst_size'), - parameter.Int('latency'), + parameter.Int('block_size', default=512), + parameter.Int('burst_size', default=64), + parameter.Int('latency', default=0), ], Index: trunk/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h =================================================================== --- trunk/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h (revision 537) +++ trunk/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h (revision 549) @@ -296,5 +296,5 @@ // STRUCTURAL PARAMETERS - soclib::common::AddressDecodingTable m_cacheability_table; + soclib::common::AddressDecodingTable m_cacheability_table; const size_t m_srcid; @@ -394,5 +394,5 @@ // communication between ICACHE FSM and CC_SEND FSM sc_signal r_icache_cc_send_req; // ICACHE cc_send request - sc_signal r_icache_cc_send_type; // ICACHE cc_send request type + sc_signal r_icache_cc_send_type; // ICACHE cc_send request type sc_signal r_icache_cc_send_nline; // ICACHE cc_send nline sc_signal r_icache_cc_send_way; // ICACHE cc_send way @@ -491,5 +491,5 @@ // communication between DCACHE FSM and CC_SEND FSM sc_signal r_dcache_cc_send_req; // DCACHE cc_send request - sc_signal r_dcache_cc_send_type; // DCACHE cc_send request type + sc_signal r_dcache_cc_send_type; // DCACHE cc_send request type sc_signal r_dcache_cc_send_nline; // DCACHE cc_send nline sc_signal r_dcache_cc_send_way; // DCACHE cc_send way @@ -542,5 +542,5 @@ // communication between CC_RECEIVE FSM and ICACHE FSM sc_signal r_cc_receive_icache_req; // cc_receive to icache request - sc_signal r_cc_receive_icache_type; // cc_receive type of request + sc_signal r_cc_receive_icache_type; // cc_receive type of request sc_signal r_cc_receive_icache_way; // cc_receive to icache way sc_signal r_cc_receive_icache_set; // cc_receive to icache set @@ -550,5 +550,5 @@ // communication between CC_RECEIVE FSM and DCACHE FSM sc_signal r_cc_receive_dcache_req; // cc_receive to dcache request - sc_signal r_cc_receive_dcache_type; // cc_receive type of request + sc_signal r_cc_receive_dcache_type; // cc_receive type of request sc_signal r_cc_receive_dcache_way; // cc_receive to dcache way sc_signal r_cc_receive_dcache_set; // cc_receive to dcache set Index: trunk/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp =================================================================== --- trunk/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp (revision 537) +++ trunk/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp (revision 549) @@ -1155,5 +1155,5 @@ // cacheability if ( not (r_mmu_mode.read() & INS_CACHE_MASK) ) cacheable = false; - else cacheable = m_cacheability_table[m_ireq.addr]; + else cacheable = m_cacheability_table[(uint64_t)m_ireq.addr]; } else // itlb activated @@ -2647,5 +2647,5 @@ if ( not (r_mmu_mode.read() & DATA_CACHE_MASK) ) cacheable = false; - else cacheable = m_cacheability_table[m_dreq.addr]; + else cacheable = m_cacheability_table[(uint64_t)m_dreq.addr]; } else // dtlb activated Index: trunk/modules/vci_io_bridge/caba/source/src/vci_io_bridge.cpp =================================================================== --- trunk/modules/vci_io_bridge/caba/source/src/vci_io_bridge.cpp (revision 537) +++ trunk/modules/vci_io_bridge/caba/source/src/vci_io_bridge.cpp (revision 549) @@ -93,10 +93,14 @@ }; -const char *miss_wti_fsm_state_str[] = { - "MISS_WTI_IDLE_MISS", - "MISS_WTI_IDLE_WTI", +const char *miss_wti_cmd_state_str[] = + { + "MISS_WTI_CMD_IDLE", "MISS_WTI_CMD_WTI", + "MISS_WTI_CMD_MISS", + }; +const char *miss_wti_rsp_state_str[] = + { + "MISS_WTI_RSP_IDLE", "MISS_WTI_RSP_WTI", - "MISS_WTI_CMD_MISS", "MISS_WTI_RSP_MISS", }; @@ -268,5 +272,6 @@ std::cout << " => segment " << int_seg->name() << " / base = " << std::hex << int_seg->baseAddress() - << " / size = " << int_seg->size() << std::endl; + << " / size = " << int_seg->size() + << " / special = " << int_seg->special() << std::endl; } @@ -332,5 +337,5 @@ //////////////////////////////////// { - // b0 : IOtlb trace + // b0 : IOTLB trace std::cout << std::dec << "IO_BRIDGE " << name() << std::endl; @@ -341,5 +346,6 @@ << " | " << config_cmd_fsm_state_str[r_config_cmd_fsm.read()] << " | " << config_rsp_fsm_state_str[r_config_rsp_fsm.read()] - << " | " << miss_wti_fsm_state_str[r_miss_wti_cmd_fsm.read()] + << " | " << miss_wti_cmd_state_str[r_miss_wti_cmd_fsm.read()] + << " | " << miss_wti_rsp_state_str[r_miss_wti_rsp_fsm.read()] << std::endl; @@ -348,8 +354,4 @@ std::cout << " IOTLB" << std::endl; r_iotlb.printTrace(); - } - if(mode & 0x02) - { - } } @@ -1248,12 +1250,17 @@ // chek segments std::list::iterator seg; - bool found = false; + bool found = false; + bool special = false; for ( seg = m_int_seglist.begin() ; seg != m_int_seglist.end() and not found ; seg++ ) { - if ( seg->contains(paddr) ) found = true; + if ( seg->contains(paddr) ) + { + found = true; + special = seg->special(); + } } - if ( found and seg->special() ) // IO_BRIDGE itself + if ( found and special ) // IO_BRIDGE itself { uint32_t rdata = 0; @@ -1988,5 +1995,7 @@ // VCI initiator command on INT network - // it depends on the MISS_WTI_CMD FSM state + // it depends on the MISS_WTI_CMD FSM state + // - WTI : single flit WRITE + // - MISS TLB : multi-flit READ for a complete cache line // default values @@ -1997,7 +2006,7 @@ p_vci_ini_int.wrap = false; p_vci_ini_int.clen = 0; - p_vci_ini_int.contig = false; - p_vci_ini_int.cons = true; - p_vci_ini_int.be = 0xFF; + p_vci_ini_int.contig = true; + p_vci_ini_int.cons = false; + p_vci_ini_int.be = 0xF; switch ( r_miss_wti_cmd_fsm.read() ) Index: trunk/modules/vci_iox_network/caba/source/include/vci_iox_network.h =================================================================== --- trunk/modules/vci_iox_network/caba/source/include/vci_iox_network.h (revision 537) +++ trunk/modules/vci_iox_network/caba/source/include/vci_iox_network.h (revision 549) @@ -27,20 +27,22 @@ */ -////////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////// // This component emulates an external IO bus such as PCIe or Hypertransport, -// but respect the VCI protocol. -// It is considered as a local interconnect that must be attached to -// one OR SEVERAL clusters in a global interconnect. -// It uses two different routing table: -// - the cmd_routing_table decodes the local field of the VCI address -// to return the target port -// - The rsp_routing_table decodes the local field of the VCI srcid +// but respect the VCI protocol. It can be attached to one OR SEVERAL clusters, +// using a vci_io_bridge component. +// It is considered as a local interconnect, for the ADDRESS or SRCID +// decoding tables: +// - the CMD routing_table decodes the local field of the VCI ADDRESS +// to return the local target port +// - The RSP routing_table decodes the local field of the VCI SRCID // to return the initator port // It is implemented as two independant crossbars, for VCI commands and // VCI responses respectively. -// - The CMD crossbar has nb_ini input ports, and nb_tgt output ports. +// - The CMD crossbar has nb_ini input ports, and nb_tgt output ports, +// including the ports to the vci_io_bridge component(s). // - The RSP crossbar has nb_tgt input ports, and nb_ini output ports. +// including the ports to the vci_io_bridge component(s). // For both crossbars, output ports allocation policy is round robin. -////////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////// #ifndef VCI_IOX_NETWORK_H @@ -91,5 +93,5 @@ AddressDecodingTable m_cmd_rt; // routing table for CMD - AddressDecodingTable m_rsp_rt; // routing table for RSP + AddressDecodingTable m_rsp_rt; // routing table for RSP void transition(); @@ -108,5 +110,4 @@ VciIoxNetwork( sc_module_name name, const soclib::common::MappingTable &mt, - size_t cluster_id, size_t nb_tgt, size_t nb_ini ); Index: trunk/modules/vci_iox_network/caba/source/src/vci_iox_network.cpp =================================================================== --- trunk/modules/vci_iox_network/caba/source/src/vci_iox_network.cpp (revision 537) +++ trunk/modules/vci_iox_network/caba/source/src/vci_iox_network.cpp (revision 549) @@ -26,4 +26,23 @@ */ +//////////////////////////////////////////////////////////////////////////////// +// This component emulates an external IO bus such as PCIe or Hypertransport, +// but respect the VCI protocol. It can be attached to one OR SEVERAL clusters, +// using a vci_io_bridge component. +// It is considered as a local interconnect, for the ADDRESS or SRCID +// decoding tables: +// - the CMD routing_table decodes the local field of the VCI ADDRESS +// to return the local target port +// - The RSP routing_table decodes the local field of the VCI SRCID +// to return the initator port +// It is implemented as two independant crossbars, for VCI commands and +// VCI responses respectively. +// - The CMD crossbar has nb_ini input ports, and nb_tgt output ports, +// including the ports to the vci_io_bridge component(s). +// - The RSP crossbar has nb_tgt input ports, and nb_ini output ports. +// including the ports to the vci_io_bridge component(s). +// For both crossbars, output ports allocation policy is round robin. +//////////////////////////////////////////////////////////////////////////////// + #include #include @@ -50,20 +69,20 @@ typedef typename pkt_t::output_port_t output_port_t; - const bool m_is_cmd; // CMD XBAR if true - const size_t m_inputs; // number of inputs - const size_t m_outputs; // number of outputs - AddressDecodingTable* m_rt; // pointer on routing table (CMD or RSP) - - sc_signal* r_out_allocated; // for each output: allocation state - sc_signal* r_out_origin; // for each output: input port index - sc_signal* r_in_allocated; // for each input: allocation state - sc_signal* r_in_dest; // for each input: output port index + const bool m_is_cmd; // CMD XBAR if true + const size_t m_inputs; // number of inputs + const size_t m_outputs; // number of outputs + void* m_rt; // pointer on routing table (CMD or RSP) + + sc_signal* r_out_allocated; // for each output: allocation state + sc_signal* r_out_origin; // for each output: input port index + sc_signal* r_in_allocated; // for each input: allocation state + sc_signal* r_in_dest; // for each input: output port index public: /////////////////////// - IoXbar( bool is_cmd, - size_t nb_inputs, - size_t nb_outputs, - AddressDecodingTable* rt ) + IoXbar( bool is_cmd, + size_t nb_inputs, + size_t nb_outputs, + void* rt ) : m_is_cmd( is_cmd ), m_inputs( nb_inputs ), @@ -150,11 +169,13 @@ if ( m_is_cmd ) { - req = ((AddressDecodingTable*)m_rt)->get_value( - (uint64_t)(input_port[in]->address.read()) ); + AddressDecodingTable* rt = + (AddressDecodingTable*)m_rt; + req = rt->get_value((uint64_t)(input_port[in]->address.read())); } else { - req = ((AddressDecodingTable*)m_rt)->get_value( - (uint64_t)(input_port[in]->rsrcid.read()) ); + AddressDecodingTable* rt = + (AddressDecodingTable*)m_rt; + req = rt->get_value((uint32_t)(input_port[in]->rsrcid.read())); } // allocate the output port if requested @@ -260,5 +281,4 @@ tmpl(/**/)::VciIoxNetwork( sc_core::sc_module_name name, const soclib::common::MappingTable &mt, - size_t cluster_id, size_t nb_tgt, size_t nb_ini ) @@ -274,6 +294,6 @@ m_nb_ini( nb_ini ), - m_cmd_rt( mt.getPortidFromAddress(cluster_id) ), - m_rsp_rt( mt.getPortidFromSrcid(cluster_id) ) + m_cmd_rt( mt.getLocalIndexFromAddress(0) ), + m_rsp_rt( mt.getLocalIndexFromSrcid(0) ) { std::cout << " Building VciIoxNetwork : " << name << std::endl; Index: trunk/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h =================================================================== --- trunk/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h (revision 537) +++ trunk/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h (revision 549) @@ -516,5 +516,5 @@ void print_stats(bool activity_counters, bool stats); - void print_trace(); + void print_trace( size_t detailed = 0 ); void cache_monitor(addr_t addr); void start_monitor(addr_t addr, addr_t length); Index: trunk/modules/vci_mem_cache/caba/source/include/xram_transaction.h =================================================================== --- trunk/modules/vci_mem_cache/caba/source/include/xram_transaction.h (revision 537) +++ trunk/modules/vci_mem_cache/caba/source/include/xram_transaction.h (revision 549) @@ -29,5 +29,5 @@ bool proc_read; // read request from processor size_t read_length; // length of the read (for the response) - size_t word_index; // index of the first read word (for the response) + size_t word_index; // index of the first read word (for response) std::vector wdata; // write buffer (one cache line) std::vector wdata_be; // be for each data in the write buffer @@ -48,6 +48,5 @@ ///////////////////////////////////////////////////////////////////// // The alloc() function initializes the vectors of an entry - // Its arguments are : - // - n_words : number of words per line in the cache + // The "n_words" argument is the number of words in a cache line. ///////////////////////////////////////////////////////////////////// void alloc(size_t n_words) @@ -64,6 +63,4 @@ //////////////////////////////////////////////////////////////////// // The copy() function copies an existing entry - // Its arguments are : - // - source : the transaction tab entry to copy //////////////////////////////////////////////////////////////////// void copy(const TransactionTabEntry &source) @@ -86,32 +83,30 @@ //////////////////////////////////////////////////////////////////// - // The print() function prints the entry - //////////////////////////////////////////////////////////////////// - void print() - { - std::cout << "------- TRT entry -------" << std::endl; - std::cout << "valid = " << valid << std::endl; - std::cout << "xram_read = " << xram_read << std::endl; - std::cout << "nline = " << std::hex << nline << std::endl; - std::cout << "srcid = " << srcid << std::endl; - std::cout << "trdid = " << trdid << std::endl; - std::cout << "pktid = " << pktid << std::endl; - std::cout << "proc_read = " << proc_read << std::endl; - std::cout << "read_length = " << read_length << std::endl; - std::cout << "word_index = " << word_index << std::endl; - for(size_t i=0; i" << std::endl; + for ( size_t id = 0 ; id < size_tab ; id++ ) + { + tab[id].print( id , detailed ); + } } ///////////////////////////////////////////////////////////////////// Index: trunk/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp =================================================================== --- trunk/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp (revision 537) +++ trunk/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp (revision 549) @@ -654,5 +654,5 @@ ////////////////////////////////////////////////// - tmpl(void)::print_trace() + tmpl(void)::print_trace( size_t detailed ) ////////////////////////////////////////////////// { @@ -676,4 +676,6 @@ << " | " << alloc_ivt_fsm_str[r_alloc_ivt_fsm.read()] << " | " << alloc_heap_fsm_str[r_alloc_heap_fsm.read()] << std::endl; + + if ( detailed ) m_trt.print(0); } @@ -4011,5 +4013,5 @@ assert( ((p_vci_ixr.rerror.read() & 0x1) == 0) and - "MEMC ERROR in IXR_RSP state: XRAM response error !"); + "MEMC ERROR in IXR_RSP state: XRAM response error !"); if (p_vci_ixr.reop.read()) // PUT @@ -4018,7 +4020,7 @@ #if DEBUG_MEMC_IXR_RSP - if (m_debug) - std::cout << " Response from XRAM to a put transaction" << std::endl; +if (m_debug) +std::cout << " Response from XRAM to a put transaction" << std::endl; #endif } @@ -4028,67 +4030,66 @@ #if DEBUG_MEMC_IXR_RSP - if (m_debug) - std::cout << " Response from XRAM to a get transaction" << std::endl; -#endif - } - } - break; - } - //////////////////////// +if (m_debug) +std::cout << " Response from XRAM to a get transaction" << std::endl; +#endif + } + } + break; + } + //////////////////////// case IXR_RSP_TRT_ERASE: // erase the entry in the TRT - // decrease the line counter if config request - { - if (r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP) - { - size_t index = r_ixr_rsp_trt_index.read(); - if (m_trt.is_config(index)) r_config_rsp_lines = r_config_rsp_lines.read() - 1; - m_trt.erase(index); + // decrease the line counter if config request + { + if (r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP) + { + size_t index = r_ixr_rsp_trt_index.read(); + if (m_trt.is_config(index)) + r_config_rsp_lines = r_config_rsp_lines.read() - 1; + m_trt.erase(index); + r_ixr_rsp_fsm = IXR_RSP_IDLE; + +#if DEBUG_MEMC_IXR_RSP +if (m_debug) +std::cout << " Erase TRT entry " + << r_ixr_rsp_trt_index.read() << std::endl; +#endif + } + break; + } + ////////////////////// + case IXR_RSP_TRT_READ: // write a 64 bits data word in TRT + { + if ((r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP) and p_vci_ixr.rspval) + { + size_t index = r_ixr_rsp_trt_index.read(); + size_t word = r_ixr_rsp_cpt.read(); + bool eop = p_vci_ixr.reop.read(); + wide_data_t data = p_vci_ixr.rdata.read(); + bool error = ((p_vci_ixr.rerror.read() & 0x1) == 1); + + assert(((eop == (word == (m_words-2))) or error) and + "MEMC ERROR in IXR_RSP_TRT_READ state : invalid response from XRAM"); + + m_trt.write_rsp( index, word, data ); + + r_ixr_rsp_cpt = word + 2; + + if (eop ) + { + r_ixr_rsp_to_xram_rsp_rok[r_ixr_rsp_trt_index.read()] = true; r_ixr_rsp_fsm = IXR_RSP_IDLE; + } #if DEBUG_MEMC_IXR_RSP - if (m_debug) - std::cout << " Erase TRT entry " - << r_ixr_rsp_trt_index.read() << std::endl; -#endif - } - break; - } - ////////////////////// - case IXR_RSP_TRT_READ: // write a 64 bits data word in TRT - { - if ((r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP) and p_vci_ixr.rspval) - { - size_t index = r_ixr_rsp_trt_index.read(); - size_t word = r_ixr_rsp_cpt.read(); - bool eop = p_vci_ixr.reop.read(); - wide_data_t data = p_vci_ixr.rdata.read(); - bool error = ((p_vci_ixr.rerror.read() & 0x1) == 1); - - assert(((eop == (word == (m_words-2))) or error) and - "MEMC ERROR in IXR_RSP_TRT_READ state : invalid response from XRAM"); - - m_trt.write_rsp( index, - word, - data ); - - r_ixr_rsp_cpt = word + 2; - - if (eop ) - { - r_ixr_rsp_to_xram_rsp_rok[r_ixr_rsp_trt_index.read()] = true; - r_ixr_rsp_fsm = IXR_RSP_IDLE; - } - -#if DEBUG_MEMC_IXR_RSP - if (m_debug) - std::cout << " Writing 2 words in TRT : " - << " index = " << std::dec << index - << " / word = " << word - << " / data = " << std::hex << data << std::endl; -#endif - } - break; - } +if (m_debug) +std::cout << " Writing 2 words in TRT : " + << " index = " << std::dec << index + << " / word = " << word + << " / data = " << std::hex << data << std::endl; +#endif + } + break; + } } // end swich r_ixr_rsp_fsm