Changeset 55 for trunk/modules/vci_cc_vcache_wrapper2_v1
- Timestamp:
- Jun 16, 2010, 12:24:08 PM (14 years ago)
- File:
-
- 1 edited
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- Added
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trunk/modules/vci_cc_vcache_wrapper2_v1/caba/source/src/vci_cc_vcache_wrapper2_v1.cpp
r53 r55 32 32 namespace caba { 33 33 34 #define SOCLIB_MODULE_DEBUG 34 //#define SOCLIB_MODULE_DEBUG 35 #define DEBUG_START_CYCLE 33069000 35 36 #ifdef SOCLIB_MODULE_DEBUG 36 37 namespace { … … 611 612 612 613 #ifdef SOCLIB_MODULE_DEBUG 613 std::cout << name() << "cycle = " << m_cpt_total_cycles 614 if(m_cpt_total_cycles > DEBUG_START_CYCLE && m_srcid_rw==0){ 615 std::cout << name() << " cycle = " << std::dec << m_cpt_total_cycles 614 616 << " tgt fsm: " << tgt_fsm_state_str[r_vci_tgt_fsm] 615 617 << " dcache fsm: " << dcache_fsm_state_str[r_dcache_fsm] … … 619 621 << " inval itlb fsm: " << inval_itlb_fsm_state_str[r_inval_itlb_fsm] 620 622 << " inval dtlb fsm: " << inval_dtlb_fsm_state_str[r_inval_dtlb_fsm] << std::endl; 623 } 621 624 #endif 622 625 … … 632 635 633 636 #ifdef SOCLIB_MODULE_DEBUG 637 if(m_cpt_total_cycles > DEBUG_START_CYCLE && m_srcid_rw==0){ 634 638 std::cout << name() << " Instruction Request: " << ireq << std::endl; 635 639 std::cout << name() << " Data Request: " << dreq << std::endl; 640 } 636 641 #endif 637 642 … … 2053 2058 2054 2059 #ifdef SOCLIB_MODULE_DEBUG 2060 if(m_cpt_total_cycles > DEBUG_START_CYCLE && m_srcid_rw==0){ 2055 2061 std::cout << name() << " Instruction Response: " << irsp << std::endl; 2062 } 2056 2063 #endif 2057 2064 … … 4397 4404 if(dreq.type == iss_t::DATA_SC) 4398 4405 { 4406 if(r_dcache_cleanup_req) break; 4399 4407 size_t way = 0; 4400 4408 size_t set = 0; 4401 4409 // Simulate an invalidate request 4402 r_dcache_cleanup_req = r_dcache.inval(r_dcache_paddr_save, &way, &set); 4410 r_dcache_cleanup_req = r_dcache.inval(r_dcache_paddr_save, &way, &set); // !!!!!!!!! 4403 4411 r_dcache_cleanup_line = r_dcache_paddr_save.read() >> (uint32_log2(m_dcache_words)+2); 4404 4412 m_cpt_cc_cleanup_data++; … … 4993 5001 4994 5002 #ifdef SOCLIB_MODULE_DEBUG 5003 if(m_cpt_total_cycles > DEBUG_START_CYCLE && m_srcid_rw==0){ 4995 5004 std::cout << name() << " Data Response: " << drsp << std::endl; 5005 } 4996 5006 #endif 4997 5007 … … 5909 5919 5910 5920 #ifdef SOCLIB_MODULE_DEBUG 5921 if(m_cpt_total_cycles > DEBUG_START_CYCLE && m_srcid_rw==0){ 5911 5922 std::cout << name() 5912 << " Moore R/W:" << std::hex5923 << " Moore R/W:" << std::hex 5913 5924 << " p_vci_ini_rw.cmdval: " << p_vci_ini_rw.cmdval 5914 5925 << " p_vci_ini_rw.address: " << p_vci_ini_rw.address … … 5919 5930 5920 5931 std::cout << name() 5921 << " Moore TGT:" << std::hex5932 << " Moore TGT:" << std::hex 5922 5933 << " p_vci_tgt.rspval: " << p_vci_tgt.rspval 5923 5934 << std::endl; 5924 5935 5925 5936 std::cout << name() 5926 << " Moore Cleanup:" << std::hex5937 << " Moore Cleanup:" << std::hex 5927 5938 << " p_vci_ini_c.cmdval: " << p_vci_ini_c.cmdval 5928 5939 << " p_vci_ini_c.address: " << p_vci_ini_c.address … … 5931 5942 << " p_vci_ini_c.eop: " << p_vci_ini_c.eop 5932 5943 << std::endl; 5933 5944 } 5934 5945 #endif 5935 5946 }
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