Index: /trunk/modules/vci_spi/caba/source/include/vci_spi.h =================================================================== --- /trunk/modules/vci_spi/caba/source/include/vci_spi.h (revision 557) +++ /trunk/modules/vci_spi/caba/source/include/vci_spi.h (revision 558) @@ -80,6 +80,4 @@ sc_signal r_ctrl_char_len; // number of bits in xfer - sc_signal r_txrx_addr; - sc_signal r_bit_count; sc_signal r_clk_counter; @@ -105,5 +103,6 @@ sc_signal r_trdid; // save trdid sc_signal r_pktid; // save pktid - sc_signal r_tdata; // save wdata + + sc_signal r_rdata; // save reply uint32_t* r_local_buffer; // capacity is one block @@ -142,14 +141,8 @@ enum { T_IDLE = 0, - T_WRITE_TXRX = 1, - T_READ_TXRX = 2, - T_WRITE_CTRL = 3, - T_READ_CTRL = 4, - T_WRITE_DIVIDER = 5, - T_READ_DIVIDER = 6, - T_WRITE_SS = 7, - T_READ_SS = 8, - T_WRITE_ERROR = 9, - T_READ_ERROR = 10, + T_RSP_READ = 1, + T_RSP_WRITE = 2, + T_ERROR_READ = 3, + T_ERROR_WRITE = 4 }; Index: /trunk/modules/vci_spi/caba/source/src/vci_spi.cpp =================================================================== --- /trunk/modules/vci_spi/caba/source/src/vci_spi.cpp (revision 557) +++ /trunk/modules/vci_spi/caba/source/src/vci_spi.cpp (revision 558) @@ -22,5 +22,5 @@ * * Copyright (c) UPMC, Lip6, SoC - * manuel.bouyer@lip6.fr october 2013 + * manuel.bouyer@lip6.fr october 2013 * * Maintainers: bouyer @@ -45,22 +45,22 @@ if(p_resetn.read() == false) { - r_initiator_fsm = M_IDLE; - r_target_fsm = T_IDLE; - r_spi_fsm = S_IDLE; - r_ss = 0; - r_divider = 0xffff; - r_ctrl_char_len = 0; - r_ctrl_ass = false; - r_ctrl_ie = false; - r_ctrl_cpol = false; - r_ctrl_cpha = false; - r_ctrl_go_bsy = false; + r_initiator_fsm = M_IDLE; + r_target_fsm = T_IDLE; + r_spi_fsm = S_IDLE; + r_ss = 0; + r_divider = 0xffff; + r_ctrl_char_len = 0; + r_ctrl_ass = false; + r_ctrl_ie = false; + r_ctrl_cpol = false; + r_ctrl_cpha = false; + r_ctrl_go_bsy = false; r_clk_counter = 0xffff; - r_spi_clk = 0; + r_spi_clk = 0; r_irq = false; r_read = false; - return; + return; } @@ -74,175 +74,135 @@ case T_IDLE: { - if ( p_vci_target.cmdval.read() ) - { - r_srcid = p_vci_target.srcid.read(); - r_trdid = p_vci_target.trdid.read(); - r_pktid = p_vci_target.pktid.read(); - r_tdata = p_vci_target.wdata.read(); - sc_dt::sc_uint address = p_vci_target.address.read(); - - bool found = false; - std::list::iterator seg; - for ( seg = m_seglist.begin() ; seg != m_seglist.end() ; seg++ ) - { - if ( seg->contains(address) ) found = true; - } + if ( p_vci_target.cmdval.read() ) + { + r_srcid = p_vci_target.srcid.read(); + r_trdid = p_vci_target.trdid.read(); + r_pktid = p_vci_target.pktid.read(); + uint32_t wdata = p_vci_target.wdata.read(); + sc_dt::sc_uint address = p_vci_target.address.read(); + + bool found = false; + std::list::iterator seg; + for ( seg = m_seglist.begin() ; seg != m_seglist.end() ; seg++ ) + { + if ( seg->contains(address) ) found = true; + } - bool read = (p_vci_target.cmd.read() == vci_param::CMD_READ); - uint32_t cell = (uint32_t)((address & 0x3F)>>2); - - if (read) { - if (not found) { - r_target_fsm = T_READ_ERROR; - } else { - switch(cell) { - case SPI_DATA_TXRX0: - case SPI_DATA_TXRX1: - case SPI_DATA_TXRX2: - case SPI_DATA_TXRX3: - r_target_fsm = T_READ_TXRX; - r_txrx_addr = cell; - break; - case SPI_CTRL: - r_target_fsm = T_READ_CTRL; - break; - case SPI_DIVIDER: - r_target_fsm = T_READ_DIVIDER; - break; - case SPI_SS: - r_target_fsm = T_READ_SS; - break; - default: - r_target_fsm = T_READ_ERROR; - break; + + if (not found) { + if (p_vci_target.cmd.read() == vci_param::CMD_WRITE) + r_target_fsm = T_ERROR_WRITE; + else + r_target_fsm = T_ERROR_READ; + } else if (p_vci_target.cmd.read() != vci_param::CMD_READ && + p_vci_target.cmd.read() != vci_param::CMD_WRITE) { + r_target_fsm = T_ERROR_READ; + } else { + bool write = (p_vci_target.cmd.read() == vci_param::CMD_WRITE) & !r_ctrl_go_bsy; + uint32_t cell = (uint32_t)((address & 0x3F)>>2); + switch(cell) { + case SPI_DATA_TXRX0: + r_rdata = r_txrx[0] & (uint64_t)0x00000000ffffffffULL; + if (write) { + r_txrx[0] = + (r_txrx[0] & (uint64_t)0xffffffff00000000ULL) | + ((uint64_t)wdata); + } + r_target_fsm = (p_vci_target.cmd.read() == vci_param::CMD_WRITE) ? T_RSP_WRITE : T_RSP_READ; + break; + case SPI_DATA_TXRX1: + r_rdata = r_txrx[0] >> 32; + if (write) { + r_txrx[0] = + (r_txrx[0] & (uint64_t)0x00000000ffffffffULL) | + ((uint64_t)wdata << 32); + } + r_target_fsm = (p_vci_target.cmd.read() == vci_param::CMD_WRITE) ? T_RSP_WRITE : T_RSP_READ; + break; + case SPI_DATA_TXRX2: + r_rdata = r_txrx[1] & (uint64_t)0x00000000ffffffffULL; + if (write) { + r_txrx[1] = + (r_txrx[1] & (uint64_t)0xffffffff00000000ULL) | + ((uint64_t)wdata); + } + r_target_fsm = (p_vci_target.cmd.read() == vci_param::CMD_WRITE) ? T_RSP_WRITE : T_RSP_READ; + break; + case SPI_DATA_TXRX3: + r_rdata = r_txrx[1] >> 32; + if (write) { + r_txrx[1] = + (r_txrx[1] & (uint64_t)0x00000000ffffffffULL) | + ((uint64_t)wdata << 32); + } + r_target_fsm = (p_vci_target.cmd.read() == vci_param::CMD_WRITE) ? T_RSP_WRITE : T_RSP_READ; + break; + case SPI_CTRL: + { + uint32_t data = 0; + if (r_ctrl_cpol.read()) + data |= SPI_CTRL_CPOL; + if (r_ctrl_cpha.read()) + data |= SPI_CTRL_CPHA; + if (r_ctrl_ass.read()) + data |= SPI_CTRL_ASS_EN; + if (r_ctrl_ie.read()) + data |= SPI_CTRL_IE_EN; + if (r_ctrl_go_bsy.read()) + data |= SPI_CTRL_GO_BSY; + data |= (uint32_t)r_ctrl_char_len.read(); + r_rdata = data; + if (write) { + r_ctrl_cpol = ((wdata & SPI_CTRL_CPOL) != 0); + r_ctrl_cpha = ((wdata & SPI_CTRL_CPHA) != 0); + r_ctrl_ass = ((wdata & SPI_CTRL_ASS_EN) != 0); + r_ctrl_ie = ((wdata & SPI_CTRL_IE_EN) != 0); + r_ctrl_go_bsy = ((wdata & SPI_CTRL_GO_BSY) != 0); + r_ctrl_char_len = (wdata & SPI_CTRL_CHAR_LEN_MASK); +#ifdef SOCLIB_MODULE_DEBUG + if ((wdata & SPI_CTRL_GO_BSY) != 0) { + std::cout << name() << " start xfer " << std::dec << (int)r_ctrl_char_len.read() << " data " << std::hex << r_txrx[1] << " " << r_txrx[0] << std::endl; } - } - } else { // write - if (not found) { - r_target_fsm = T_WRITE_ERROR; - } else { - switch(cell) { - case SPI_DATA_TXRX0: - case SPI_DATA_TXRX1: - case SPI_DATA_TXRX2: - case SPI_DATA_TXRX3: - r_target_fsm = T_WRITE_TXRX; - r_txrx_addr = cell; - break; - case SPI_CTRL: - r_target_fsm = T_WRITE_CTRL; - break; - case SPI_DIVIDER: - r_target_fsm = T_WRITE_DIVIDER; - break; - case SPI_SS: - r_target_fsm = T_WRITE_SS; - break; - default: - r_target_fsm = T_WRITE_ERROR; - break; - } - } - } - - } - break; +#endif + } else { + r_irq = r_irq & r_ctrl_go_bsy; + } + r_target_fsm = (p_vci_target.cmd.read() == vci_param::CMD_WRITE) ? T_RSP_WRITE : T_RSP_READ; + break; + } + case SPI_DIVIDER: + r_rdata = r_divider.read(); + if (write) { +#ifdef SOCLIB_MODULE_DEBUG + std::cout << name() << " divider set to " << std::dec << wdata << std::endl; +#endif + r_divider = wdata; + } + r_target_fsm = (p_vci_target.cmd.read() == vci_param::CMD_WRITE) ? T_RSP_WRITE : T_RSP_READ; + break; + case SPI_SS: + r_rdata = r_ss.read(); + if (write) { + r_ss = wdata; + } + r_target_fsm = (p_vci_target.cmd.read() == vci_param::CMD_WRITE) ? T_RSP_WRITE : T_RSP_READ; + break; + default: + r_target_fsm = (p_vci_target.cmd.read() == vci_param::CMD_WRITE) ? T_ERROR_WRITE : T_ERROR_READ; + break; + } + } + } + break; } //////////////////// - case T_WRITE_TXRX: - { + case T_RSP_READ: + case T_RSP_WRITE: + case T_ERROR_READ: + case T_ERROR_WRITE: if (p_vci_target.rspack.read() ) { - if (r_ctrl_go_bsy.read() == false) - { - switch(r_txrx_addr.read()) { - case 0: - r_txrx[0] = (r_txrx[0] & (uint64_t)0xffffffff00000000ULL) | - ((uint64_t)r_tdata.read() & (uint64_t)0x00000000ffffffffULL); - break; - case 1: - r_txrx[0] = (r_txrx[0] & (uint64_t)0x00000000ffffffffULL) | - ((uint64_t)r_tdata.read() << 32); - break; - case 2: - r_txrx[1] = (r_txrx[1] & (uint64_t)0xffffffff00000000ULL) | - ((uint64_t)r_tdata.read() & (uint64_t)0x00000000ffffffffULL); - break; - case 3: - r_txrx[1] = (r_txrx[1] & (uint64_t)0x00000000ffffffffULL) | - ((uint64_t)r_tdata.read() << 32); - break; - } - r_target_fsm = T_IDLE; - } - break; - } - //////////////////////// - case T_WRITE_CTRL: - { - if (p_vci_target.rspack.read() ) { - if (r_ctrl_go_bsy.read() == false) - { - r_ctrl_cpol = ((r_tdata.read() & SPI_CTRL_CPOL) != 0); - r_ctrl_cpha = ((r_tdata.read() & SPI_CTRL_CPHA) != 0); - r_ctrl_ass = ((r_tdata.read() & SPI_CTRL_ASS_EN) != 0); - r_ctrl_ie = ((r_tdata.read() & SPI_CTRL_IE_EN) != 0); - r_ctrl_go_bsy = ((r_tdata.read() & SPI_CTRL_GO_BSY) != 0); - r_ctrl_char_len = (r_tdata.read() & SPI_CTRL_CHAR_LEN_MASK); -#ifdef SOCLIB_MODULE_DEBUG - if ((r_tdata.read() & SPI_CTRL_GO_BSY) != 0) { - std::cout << name() << " start xfer " << std::dec << (int)r_ctrl_char_len.read() << " data " << std::hex << r_txrx[1] << " " << r_txrx[0] << std::endl; - } -#endif - } - r_target_fsm = T_IDLE; - } - break; - } - /////////////////// - case T_WRITE_DIVIDER: - { - if (p_vci_target.rspack.read() ) { - if (r_ctrl_go_bsy.read() == false) - { - r_divider = (uint32_t)r_tdata.read(); -#ifdef SOCLIB_MODULE_DEBUG - std::cout << name() << " divider set to " << std::dec << (uint32_t)r_tdata.read() << std::endl; -#endif - } - r_target_fsm = T_IDLE; - } - break; - } - ///////////////// - case T_WRITE_SS: - { - if (p_vci_target.rspack.read() ) { - if (r_ctrl_go_bsy.read() == false) - r_ss = (uint32_t)r_tdata.read(); - } - r_target_fsm = T_IDLE; - } - break; - } - /////////////////// - case T_READ_TXRX: - case T_READ_DIVIDER: - case T_READ_SS: - case T_WRITE_ERROR: - case T_READ_ERROR: - { - if ( p_vci_target.rspack.read() ) r_target_fsm = T_IDLE; - break; - } - /////////////////// - case T_READ_CTRL: - { - if ( p_vci_target.rspack.read() ) - { - r_target_fsm = T_IDLE; - r_irq = r_irq & r_ctrl_go_bsy; - } - break; - } + r_target_fsm = T_IDLE; + } + break; } // end switch target fsm @@ -271,15 +231,15 @@ if (!r_spi_clk_ignore) { if (r_spi_clk_previous == 0 && s_clk_sample == 1) { - // low to high transition: shift and sample - r_txrx[1] = (r_txrx[1] << 1) | (r_txrx[0] >> 63); - r_txrx[0] = (r_txrx[0] << 1) | p_spi_miso; - r_bit_count = r_bit_count - 1; + // low to high transition: shift and sample + r_txrx[1] = (r_txrx[1] << 1) | (r_txrx[0] >> 63); + r_txrx[0] = (r_txrx[0] << 1) | p_spi_miso; + r_bit_count = r_bit_count - 1; } else if (r_spi_clk_previous == 1 && s_clk_sample == 0) { - // high to low transition: change output, or stop - if (r_bit_count == 0) { + // high to low transition: change output, or stop + if (r_bit_count == 0) { r_spi_fsm = S_IDLE; r_irq = r_ctrl_ie; r_ctrl_go_bsy = false; -#ifdef SOCLIB_MODULE_DEBUG +#ifdef SOCLIB_MODULE_DEBUG0 std::cout << name() << " end xfer " << std::dec << (int)r_ctrl_char_len.read() << " data " << std::hex << r_txrx[1] << " " << r_txrx[0] << std::endl; #endif @@ -290,5 +250,5 @@ } r_spi_clk_previous = s_clk_sample; - // generate the SPI clock + // generate the SPI clock if (r_clk_counter.read() == 0) { r_clk_counter = r_divider.read(); @@ -319,140 +279,140 @@ case M_IDLE: // check buffer alignment to compute the number of bursts { - if ( false ) // XXX - { - r_index = 0; - r_block_count = 0; - r_burst_count = 0; - r_words_count = 0; - - // compute r_burst_offset (zero when buffer aligned) - r_burst_offset = (uint32_t)((r_buf_address.read()>>2) % m_words_per_burst); - - // start tranfer - if ( r_read.read() ) r_initiator_fsm = M_READ_BLOCK; - else r_initiator_fsm = M_WRITE_BURST; - } - break; + if ( false ) // XXX + { + r_index = 0; + r_block_count = 0; + r_burst_count = 0; + r_words_count = 0; + + // compute r_burst_offset (zero when buffer aligned) + r_burst_offset = (uint32_t)((r_buf_address.read()>>2) % m_words_per_burst); + + // start tranfer + if ( r_read.read() ) r_initiator_fsm = M_READ_BLOCK; + else r_initiator_fsm = M_WRITE_BURST; + } + break; } ////////////////// case M_READ_BLOCK: // read one block from disk after waiting m_latency cycles { - r_burst_count = 0; - r_words_count = 0; - r_initiator_fsm = M_READ_BURST; - break; + r_burst_count = 0; + r_words_count = 0; + r_initiator_fsm = M_READ_BURST; + break; } ////////////////// case M_READ_BURST: // Compute the number of words and the number of flits in the burst - // The number of flits can be smaller than the number of words - // in case of 8 bytes flits... - { - uint32_t nwords; - uint32_t offset = r_burst_offset.read(); - - if ( offset ) // buffer not aligned - { - if ( r_burst_count.read() == 0 ) nwords = m_words_per_burst - offset; - else if ( r_burst_count.read() == m_bursts_per_block ) nwords = offset; - else nwords = m_words_per_burst; - } - else // buffer aligned - { - nwords = m_words_per_burst; - } - - r_burst_nwords = nwords; - r_initiator_fsm = M_READ_CMD; - break; + // The number of flits can be smaller than the number of words + // in case of 8 bytes flits... + { + uint32_t nwords; + uint32_t offset = r_burst_offset.read(); + + if ( offset ) // buffer not aligned + { + if ( r_burst_count.read() == 0 ) nwords = m_words_per_burst - offset; + else if ( r_burst_count.read() == m_bursts_per_block ) nwords = offset; + else nwords = m_words_per_burst; + } + else // buffer aligned + { + nwords = m_words_per_burst; + } + + r_burst_nwords = nwords; + r_initiator_fsm = M_READ_CMD; + break; } //////////////// case M_READ_CMD: // Send a multi-flits VCI WRITE command { - if ( p_vci_initiator.cmdack.read() ) - { - uint32_t nwords = r_burst_nwords.read() - r_words_count.read(); - - if ( vci_param::B == 4 ) // one word per flit - { - if ( nwords <= 1 ) // last flit - { - r_initiator_fsm = M_READ_RSP; - r_words_count = 0; - } - else // not the last flit - { - r_words_count = r_words_count.read() + 1; - } - - // compute next word address and next local buffer index - r_buf_address = r_buf_address.read() + 4; - r_index = r_index.read() + 1; - } - else // 2 words per flit - { - if ( nwords <= 2 ) // last flit - { - r_initiator_fsm = M_READ_RSP; - r_words_count = 0; - } - else // not the last flit - { - r_words_count = r_words_count.read() + 2; - } - - // compute next word address and next local buffer index - if ( nwords == 1 ) - { - r_buf_address = r_buf_address.read() + 4; - r_index = r_index.read() + 1; - } - else - { - r_buf_address = r_buf_address.read() + 8; - r_index = r_index.read() + 2; - } - } - } - break; + if ( p_vci_initiator.cmdack.read() ) + { + uint32_t nwords = r_burst_nwords.read() - r_words_count.read(); + + if ( vci_param::B == 4 ) // one word per flit + { + if ( nwords <= 1 ) // last flit + { + r_initiator_fsm = M_READ_RSP; + r_words_count = 0; + } + else // not the last flit + { + r_words_count = r_words_count.read() + 1; + } + + // compute next word address and next local buffer index + r_buf_address = r_buf_address.read() + 4; + r_index = r_index.read() + 1; + } + else // 2 words per flit + { + if ( nwords <= 2 ) // last flit + { + r_initiator_fsm = M_READ_RSP; + r_words_count = 0; + } + else // not the last flit + { + r_words_count = r_words_count.read() + 2; + } + + // compute next word address and next local buffer index + if ( nwords == 1 ) + { + r_buf_address = r_buf_address.read() + 4; + r_index = r_index.read() + 1; + } + else + { + r_buf_address = r_buf_address.read() + 8; + r_index = r_index.read() + 2; + } + } + } + break; } //////////////// case M_READ_RSP: // Wait a single flit VCI WRITE response { - if ( p_vci_initiator.rspval.read() ) - { - bool aligned = (r_burst_offset.read() == 0); - - if ( (p_vci_initiator.rerror.read()&0x1) != 0 ) - { - r_initiator_fsm = M_READ_ERROR; + if ( p_vci_initiator.rspval.read() ) + { + bool aligned = (r_burst_offset.read() == 0); + + if ( (p_vci_initiator.rerror.read()&0x1) != 0 ) + { + r_initiator_fsm = M_READ_ERROR; #ifdef SOCLIB_MODULE_DEBUG std::cout << "vci_bd M_READ_ERROR" << std::endl; #endif - } - else if ( (not aligned and (r_burst_count.read() == m_bursts_per_block)) or - (aligned and (r_burst_count.read() == (m_bursts_per_block-1))) ) - { - if ( r_block_count.read() == (r_nblocks.read()-1) ) // last burst of last block - { - r_initiator_fsm = M_READ_SUCCESS; + } + else if ( (not aligned and (r_burst_count.read() == m_bursts_per_block)) or + (aligned and (r_burst_count.read() == (m_bursts_per_block-1))) ) + { + if ( r_block_count.read() == (r_nblocks.read()-1) ) // last burst of last block + { + r_initiator_fsm = M_READ_SUCCESS; #ifdef SOCLIB_MODULE_DEBUG std::cout << "vci_bd M_READ_SUCCESS" << std::endl; #endif - } - else // last burst not last block - { - r_index = 0; - r_burst_count = 0; - r_block_count = r_block_count.read() + 1; - r_initiator_fsm = M_READ_BLOCK; - } - } - else // not the last burst - { - r_burst_count = r_burst_count.read() + 1; - r_initiator_fsm = M_READ_BURST; - } - } - break; + } + else // last burst not last block + { + r_index = 0; + r_burst_count = 0; + r_block_count = r_block_count.read() + 1; + r_initiator_fsm = M_READ_BLOCK; + } + } + else // not the last burst + { + r_burst_count = r_burst_count.read() + 1; + r_initiator_fsm = M_READ_BURST; + } + } + break; } /////////////////// @@ -460,27 +420,27 @@ case M_READ_ERROR: { - if( !r_go ) r_initiator_fsm = M_IDLE; - break; + if( !r_go ) r_initiator_fsm = M_IDLE; + break; } /////////////////// case M_WRITE_BURST: // Compute the number of words in the burst { - uint32_t nwords; - uint32_t offset = r_burst_offset.read(); - - if ( offset ) // buffer not aligned - { - if ( r_burst_count.read() == 0 ) nwords = m_words_per_burst - offset; - else if ( r_burst_count.read() == m_bursts_per_block ) nwords = offset; - else nwords = m_words_per_burst; - } - else // buffer aligned - { - nwords = m_words_per_burst; - } - - r_burst_nwords = nwords; - r_initiator_fsm = M_WRITE_CMD; - break; + uint32_t nwords; + uint32_t offset = r_burst_offset.read(); + + if ( offset ) // buffer not aligned + { + if ( r_burst_count.read() == 0 ) nwords = m_words_per_burst - offset; + else if ( r_burst_count.read() == m_bursts_per_block ) nwords = offset; + else nwords = m_words_per_burst; + } + else // buffer aligned + { + nwords = m_words_per_burst; + } + + r_burst_nwords = nwords; + r_initiator_fsm = M_WRITE_CMD; + break; } ///////////////// @@ -488,73 +448,73 @@ { if ( p_vci_initiator.cmdack.read() ) r_initiator_fsm = M_WRITE_RSP; - break; + break; } ///////////////// case M_WRITE_RSP: // This is actually a multi-words VCI READ response { - if ( p_vci_initiator.rspval.read() ) - { - bool aligned = (r_burst_offset.read() == 0); - - if ( (vci_param::B == 8) and (r_burst_nwords.read() > 1) ) - { - r_local_buffer[r_index.read()] = (uint32_t)p_vci_initiator.rdata.read(); - r_local_buffer[r_index.read()+1] = (uint32_t)(p_vci_initiator.rdata.read()>>32); - r_index = r_index.read() + 2; - } - else - { - r_local_buffer[r_index.read()] = (uint32_t)p_vci_initiator.rdata.read(); - r_index = r_index.read() + 1; - } - - if ( p_vci_initiator.reop.read() ) // last flit of the burst - { - r_words_count = 0; - r_buf_address = r_buf_address.read() + (r_burst_nwords.read()<<2); - - if( (p_vci_initiator.rerror.read()&0x1) != 0 ) - { - r_initiator_fsm = M_WRITE_ERROR; + if ( p_vci_initiator.rspval.read() ) + { + bool aligned = (r_burst_offset.read() == 0); + + if ( (vci_param::B == 8) and (r_burst_nwords.read() > 1) ) + { + r_local_buffer[r_index.read()] = (uint32_t)p_vci_initiator.rdata.read(); + r_local_buffer[r_index.read()+1] = (uint32_t)(p_vci_initiator.rdata.read()>>32); + r_index = r_index.read() + 2; + } + else + { + r_local_buffer[r_index.read()] = (uint32_t)p_vci_initiator.rdata.read(); + r_index = r_index.read() + 1; + } + + if ( p_vci_initiator.reop.read() ) // last flit of the burst + { + r_words_count = 0; + r_buf_address = r_buf_address.read() + (r_burst_nwords.read()<<2); + + if( (p_vci_initiator.rerror.read()&0x1) != 0 ) + { + r_initiator_fsm = M_WRITE_ERROR; #ifdef SOCLIB_MODULE_DEBUG std::cout << "vci_bd M_WRITE_ERROR" << std::endl; #endif - } - else if ( (not aligned and (r_burst_count.read() == m_bursts_per_block)) or - (aligned and (r_burst_count.read() == (m_bursts_per_block-1))) ) // last burst - { - r_initiator_fsm = M_WRITE_BLOCK; - } - else // not the last burst - { - r_burst_count = r_burst_count.read() + 1; - r_initiator_fsm = M_WRITE_BURST; - } - } - else - { - r_words_count = r_words_count.read() + 1; - } - } - break; + } + else if ( (not aligned and (r_burst_count.read() == m_bursts_per_block)) or + (aligned and (r_burst_count.read() == (m_bursts_per_block-1))) ) // last burst + { + r_initiator_fsm = M_WRITE_BLOCK; + } + else // not the last burst + { + r_burst_count = r_burst_count.read() + 1; + r_initiator_fsm = M_WRITE_BURST; + } + } + else + { + r_words_count = r_words_count.read() + 1; + } + } + break; } /////////////////// case M_WRITE_BLOCK: // write a block to disk after waiting m_latency cycles { - if ( r_block_count.read() == r_nblocks.read() - 1 ) - { - r_initiator_fsm = M_WRITE_SUCCESS; + if ( r_block_count.read() == r_nblocks.read() - 1 ) + { + r_initiator_fsm = M_WRITE_SUCCESS; #ifdef SOCLIB_MODULE_DEBUG std::cout << "vci_bd M_WRITE_SUCCESS" << std::endl; #endif - } - else - { - r_burst_count = 0; - r_index = 0; - r_block_count = r_block_count.read() + 1; - r_initiator_fsm = M_WRITE_BURST; - } - break; + } + else + { + r_burst_count = 0; + r_index = 0; + r_block_count = r_block_count.read() + 1; + r_initiator_fsm = M_WRITE_BURST; + } + break; } ///////////////////// @@ -562,6 +522,6 @@ case M_WRITE_ERROR: { - r_initiator_fsm = M_IDLE; - break; + r_initiator_fsm = M_IDLE; + break; } } // end switch r_initiator_fsm @@ -579,78 +539,32 @@ switch(r_target_fsm) { case T_IDLE: - p_vci_target.cmdack = true; - p_vci_target.rspval = false; - p_vci_target.rdata = 0; - break; - case T_READ_TXRX: - p_vci_target.cmdack = false; - p_vci_target.rspval = true; - switch(r_txrx_addr.read()) { - case 0: - p_vci_target.rdata = r_txrx[0] & (uint64_t)0x00000000ffffffffULL; - break; - case 1: - p_vci_target.rdata = r_txrx[0] >> 32; - break; - case 2: - p_vci_target.rdata = r_txrx[1] & (uint64_t)0x00000000ffffffffULL; - break; - case 3: - p_vci_target.rdata = r_txrx[1] >> 32; - break; - } - p_vci_target.rerror = VCI_READ_OK; - break; - case T_READ_CTRL: - { - uint32_t data = 0; - if (r_ctrl_cpol.read()) - data |= SPI_CTRL_CPOL; - if (r_ctrl_cpha.read()) - data |= SPI_CTRL_CPHA; - if (r_ctrl_ass.read()) - data |= SPI_CTRL_ASS_EN; - if (r_ctrl_ie.read()) - data |= SPI_CTRL_IE_EN; - if (r_ctrl_go_bsy.read()) - data |= SPI_CTRL_GO_BSY; - data |= (uint32_t)r_ctrl_char_len.read(); - - p_vci_target.cmdack = false; - p_vci_target.rspval = true; - p_vci_target.rdata = data; - p_vci_target.rerror = VCI_READ_OK; - break; - } - case T_READ_DIVIDER: - p_vci_target.cmdack = false; - p_vci_target.rspval = true; - p_vci_target.rdata = r_divider.read(); - p_vci_target.rerror = VCI_READ_OK; - break; - case T_READ_SS: - p_vci_target.cmdack = false; - p_vci_target.rspval = true; - p_vci_target.rdata = r_ss.read(); - p_vci_target.rerror = VCI_READ_OK; - break; - case T_READ_ERROR: - p_vci_target.cmdack = false; - p_vci_target.rspval = true; - p_vci_target.rdata = 0; - p_vci_target.rerror = VCI_READ_ERROR; - break; - case T_WRITE_ERROR: - p_vci_target.cmdack = false; - p_vci_target.rspval = true; - p_vci_target.rdata = 0; - p_vci_target.rerror = VCI_WRITE_ERROR; - break; - default: - p_vci_target.cmdack = false; - p_vci_target.rspval = true; - p_vci_target.rdata = 0; - p_vci_target.rerror = VCI_WRITE_OK; - break; + p_vci_target.cmdack = true; + p_vci_target.rspval = false; + p_vci_target.rdata = 0; + break; + case T_RSP_READ: + p_vci_target.cmdack = false; + p_vci_target.rspval = true; + p_vci_target.rdata = r_rdata; + p_vci_target.rerror = VCI_READ_OK; + break; + case T_RSP_WRITE: + p_vci_target.cmdack = false; + p_vci_target.rspval = true; + p_vci_target.rdata = 0; + p_vci_target.rerror = VCI_WRITE_OK; + break; + case T_ERROR_READ: + p_vci_target.cmdack = false; + p_vci_target.rspval = true; + p_vci_target.rdata = 0; + p_vci_target.rerror = VCI_READ_ERROR; + break; + case T_ERROR_WRITE: + p_vci_target.cmdack = false; + p_vci_target.rspval = true; + p_vci_target.rdata = 0; + p_vci_target.rerror = VCI_WRITE_ERROR; + break; } // end switch target fsm @@ -666,44 +580,44 @@ switch (r_initiator_fsm) { case M_WRITE_CMD: // It is actually a single flit VCI read command - p_vci_initiator.rspack = false; - p_vci_initiator.cmdval = true; - p_vci_initiator.address = (sc_dt::sc_uint)r_buf_address.read(); - p_vci_initiator.cmd = vci_param::CMD_READ; - p_vci_initiator.pktid = TYPE_READ_DATA_UNC; - p_vci_initiator.wdata = 0; - p_vci_initiator.be = 0; - p_vci_initiator.plen = (sc_dt::sc_uint)(r_burst_nwords.read()<<2); - p_vci_initiator.eop = true; - break; + p_vci_initiator.rspack = false; + p_vci_initiator.cmdval = true; + p_vci_initiator.address = (sc_dt::sc_uint)r_buf_address.read(); + p_vci_initiator.cmd = vci_param::CMD_READ; + p_vci_initiator.pktid = TYPE_READ_DATA_UNC; + p_vci_initiator.wdata = 0; + p_vci_initiator.be = 0; + p_vci_initiator.plen = (sc_dt::sc_uint)(r_burst_nwords.read()<<2); + p_vci_initiator.eop = true; + break; case M_READ_CMD: // It is actually a multi-words VCI WRITE command - p_vci_initiator.rspack = false; - p_vci_initiator.cmdval = true; - p_vci_initiator.address = (sc_dt::sc_uint)r_buf_address.read(); - p_vci_initiator.cmd = vci_param::CMD_WRITE; - p_vci_initiator.pktid = TYPE_WRITE; - p_vci_initiator.plen = (sc_dt::sc_uint)(r_burst_nwords.read()<<2); - if ( (vci_param::B == 8) and ((r_burst_nwords.read() - r_words_count.read()) > 1) ) - { - p_vci_initiator.wdata = ((uint64_t)r_local_buffer[r_index.read() ]) + - (((uint64_t)r_local_buffer[r_index.read()+1]) << 32); - p_vci_initiator.be = 0xFF; - p_vci_initiator.eop = ( (r_burst_nwords.read() - r_words_count.read()) <= 2 ); - } - else - { - p_vci_initiator.wdata = r_local_buffer[r_index.read()]; - p_vci_initiator.be = 0xF; - p_vci_initiator.eop = ( r_words_count.read() == (r_burst_nwords.read() - 1) ); - } - break; + p_vci_initiator.rspack = false; + p_vci_initiator.cmdval = true; + p_vci_initiator.address = (sc_dt::sc_uint)r_buf_address.read(); + p_vci_initiator.cmd = vci_param::CMD_WRITE; + p_vci_initiator.pktid = TYPE_WRITE; + p_vci_initiator.plen = (sc_dt::sc_uint)(r_burst_nwords.read()<<2); + if ( (vci_param::B == 8) and ((r_burst_nwords.read() - r_words_count.read()) > 1) ) + { + p_vci_initiator.wdata = ((uint64_t)r_local_buffer[r_index.read() ]) + + (((uint64_t)r_local_buffer[r_index.read()+1]) << 32); + p_vci_initiator.be = 0xFF; + p_vci_initiator.eop = ( (r_burst_nwords.read() - r_words_count.read()) <= 2 ); + } + else + { + p_vci_initiator.wdata = r_local_buffer[r_index.read()]; + p_vci_initiator.be = 0xF; + p_vci_initiator.eop = ( r_words_count.read() == (r_burst_nwords.read() - 1) ); + } + break; case M_READ_RSP: case M_WRITE_RSP: - p_vci_initiator.rspack = true; - p_vci_initiator.cmdval = false; - break; + p_vci_initiator.rspack = true; + p_vci_initiator.cmdval = false; + break; default: - p_vci_initiator.rspack = false; - p_vci_initiator.cmdval = false; - break; + p_vci_initiator.rspack = false; + p_vci_initiator.cmdval = false; + break; } @@ -726,9 +640,9 @@ ////////////////////////////////////////////////////////////////////////////// -tmpl(/**/)::VciSpi( sc_core::sc_module_name name, - const soclib::common::MappingTable &mt, - const soclib::common::IntTab &srcid, - const soclib::common::IntTab &tgtid, - const uint32_t burst_size) +tmpl(/**/)::VciSpi( sc_core::sc_module_name name, + const soclib::common::MappingTable &mt, + const soclib::common::IntTab &srcid, + const soclib::common::IntTab &tgtid, + const uint32_t burst_size) : caba::BaseModule(name), @@ -762,11 +676,11 @@ for ( seg = m_seglist.begin() ; seg != m_seglist.end() ; seg++ ) { - nbsegs++; - + nbsegs++; + if ( (seg->baseAddress() & 0x0000003F) != 0 ) { std::cout << "Error in component VciSpi : " << name - << "The base address of segment " << seg->name() - << " must be multiple of 64 bytes" << std::endl; + << "The base address of segment " << seg->name() + << " must be multiple of 64 bytes" << std::endl; exit(1); } @@ -774,11 +688,11 @@ { std::cout << "Error in component VciSpi : " << name - << "The size of segment " << seg->name() - << " cannot be smaller than 64 bytes" << std::endl; + << "The size of segment " << seg->name() + << " cannot be smaller than 64 bytes" << std::endl; exit(1); } - std::cout << " => segment " << seg->name() - << " / base = " << std::hex << seg->baseAddress() - << " / size = " << seg->size() << std::endl; + std::cout << " => segment " << seg->name() + << " / base = " << std::hex << seg->baseAddress() + << " / size = " << seg->size() << std::endl; } @@ -786,5 +700,5 @@ { std::cout << "Error in component VciSpi : " << name - << " No segment allocated" << std::endl; + << " No segment allocated" << std::endl; exit(1); } @@ -796,5 +710,5 @@ { std::cout << "Error in component VciSpi : " << name - << " The burst size must be 8, 16, 32 or 64 bytes" << std::endl; + << " The burst size must be 8, 16, 32 or 64 bytes" << std::endl; exit(1); } @@ -802,6 +716,6 @@ if ( (vci_param::B != 4) and (vci_param::B != 8) ) { - std::cout << "Error in component VciSpi : " << name - << " The VCI data fields must have 32 bits or 64 bits" << std::endl; + std::cout << "Error in component VciSpi : " << name + << " The VCI data fields must have 32 bits or 64 bits" << std::endl; exit(1); } @@ -839,19 +753,13 @@ }; const char* target_str[] = - { + { "T_IDLE", - "T_WRITE_TXRX", - "T_READ_TXRX", - "T_WRITE_CTRL", - "T_READ_CTRL", - "T_WRITE_DIVIDER", - "T_READ_DIVIDER", - "T_WRITE_SS", - "T_READ_SS", - "T_WRITE_ERROR", - "T_READ_ERROR", + "T_RSP_READ", + "T_RSP_WRITE", + "T_ERROR_READ", + "T_ERROR_WRITE", }; const char* spi_str[] = - { + { "S_IDLE", "S_XMIT", @@ -872,5 +780,5 @@ << std::endl; std::cout << name() << " _INI : " << initiator_str[r_initiator_fsm.read()] - << " buf = " << std::hex << r_buf_address.read() + << " buf = " << std::hex << r_buf_address.read() << " block = " << std::dec << r_block_count.read() << " burst = " << r_burst_count.read()