Index: /trunk/softs/tsar_boot/include/mips32_registers.h
===================================================================
--- /trunk/softs/tsar_boot/include/mips32_registers.h	(revision 566)
+++ /trunk/softs/tsar_boot/include/mips32_registers.h	(revision 567)
@@ -54,3 +54,28 @@
 #define CP0_EBASE       $15,1
 
+/* CP2 registers */
+
+#define CP2_PTPR             $0 
+#define CP2_MODE             $1
+#define CP2_ICACHE_FLUSH     $2
+#define CP2_DCACHE_FLUSH     $3
+#define CP2_ITLB_INVAL       $4 
+#define CP2_DTLB_INVAL       $5 
+#define CP2_ICACHE_INVAL     $6 
+#define CP2_DCACHE_INVAL     $7
+#define CP2_ICACHE_PREFETCH  $8 
+#define CP2_DCACHE_PREFETCH  $9 
+#define CP2_SYNC             $10 
+#define CP2_IETR             $11 
+#define CP2_DETR             $12 
+#define CP2_IBVAR            $13
+#define CP2_DBVAR            $14
+#define CP2_PARAMS           $15 
+#define CP2_RELEASE          $16 
+#define CP2_DATA_LO          $17     
+#define CP2_DATA_HI          $18         
+#define CP2_ICACHE_INVAL_PA  $19         
+#define CP2_DCACHE_INVAL_PA  $20 
+#define CP2_PADDR_EXT        $24
+
 #endif
Index: /trunk/softs/tsar_boot/src/reset.S
===================================================================
--- /trunk/softs/tsar_boot/src/reset.S	(revision 566)
+++ /trunk/softs/tsar_boot/src/reset.S	(revision 567)
@@ -83,29 +83,20 @@
 
     la      k0,     NB_CLUSTERS
-    li      t3,     0x80000000
-    divu    t3,     k0
-    mflo    t4
-    sll     t4,     1               /* t4 <= cluster_increment = 4G / NB_CLUSTERS */
-
-    mult    t4,     t2 
-    mflo    t5                      /* t5 <= cluster_id * cluster_increment       */
- 
+    sll     k1,     t2,     8       /* k1 <= 256*cluster_id                       */
+    div     k1,     k0              /* LO <= cluster_id * 256 / NB_CLUSTERS       */
+    mflo    k1                      /* k1 <= physical address extension (8 MSB)   */
+
     /* Initialization of the count register in the coprocessor 0 */
 
     mtc0    zero,   CP0_COUNT
-
-    /* In each cluster, the ICU base address depends on the cluster_id */
-
-    la      t3,     ICU_BASE
-    addu    t3,     t3,     t5      /* t3 <= ICU_BASE +                       */
-                                    /*       (cluster_id * cluster_increment) */
 
     /**
      * Compute the output index for the Write Triggered Interruption mask. 
      * Each processor enable the WTI for its irq output 
-     * Each processor may have IRQ_PER_PROC private irq outputs from
-     * the XICU
-     */
-
+     * Each processor may have IRQ_PER_PROC private irq outputs from the XICU
+     * In each cluster, the ICU base address depends on the cluster_id 
+     */
+
+    la      t3,     ICU_BASE
     move    t4,     t1              /* t4 <= local_id                   */
     li      t5,     IRQ_PER_PROC    /* t5 <= IRQ_PER_PROC               */
@@ -118,9 +109,12 @@
     or      t5,     t3,     t4      /* t5 <= &XICU[MSK_WTI][OUT_INDEX]  */
     
-    /* Compute and set WTI mask */
+    /* Compute and set WTI mask using the physical address extension    */
 
     li      t4,     1
     sllv    t4,     t4,     t1      /* Set XICU[MSK_WTI][INDEX][local_id] */
-    sw      t4,     0(t5)           /* XICU[MSK_WTI][INDEX] <= t4         */
+
+    mtc2    k1,     CP2_PADDR_EXT   /* set PADDR extension                */
+    sw      t4,     0(t3)           /* XICU[MSK_WTI][INDEX] <= t4         */
+    mtc2    zero,   CP2_PADDR_EXT   /* reset PADDR extension              */
 
     /**
@@ -130,4 +124,5 @@
      * t2: cluster id
      * t3: xicu base address
+     * k1: Paddr extension depending on cluster_id
      * 
      * Only processor 0 in cluster 0 executes the boot loader 
@@ -193,4 +188,5 @@
      * t2: cluster id
      * t3: xicu base address
+     * k1: Paddr extension depending on cluster_id
      */
 
@@ -200,5 +196,10 @@
     wait
 
-    lw      k0,     0(t5)           /* k0 <= XICU[WTI_REG][local_id]  */
+    /* read the address to jump with a physical read */
+
+    mtc2    k1,     CP2_PADDR_EXT   /* set PADDR extension                */
+    lw      k0,     0(t5)           /* k0 <= XICU[WTI_REG][local_id]      */
+    mtc2    zero,   CP2_PADDR_EXT   /* reset PADDR extension              */
+
     jr      k0
     nop