Index: /trunk/softs/tsar_boot/README.txt =================================================================== --- /trunk/softs/tsar_boot/README.txt (revision 567) +++ /trunk/softs/tsar_boot/README.txt (revision 568) @@ -15,6 +15,12 @@ This file is mandatory. This file defines the NB_PROCS per cluster, the NB_CLUSTERS and the base address of - the TTY, IOC and XICU devices. + the TTY, IOC, XICU and MEMC (config) devices. It defines also: + + -> USE_IOB + This constant is used by the boot_ioc_read function to know + if the buffer used to store the blocks from the + block_device must be invalidated in the memory cache after + the transfert has finished. -> CACHE_COHERENCE @@ -25,5 +31,5 @@ -> CACHE_LINE_SIZE - This constant is mandatory if CACHE_COHERENCE=0 + This constant is mandatory if CACHE_COHERENCE=0 or USE_IOB=1 This constant defines the size in bytes of a cache line. @@ -55,8 +61,8 @@ seg_stack_base: Base address of the stack used by processor 0 during the boot process. read-write data and bss will also - be there. + be there. seg_boot_base: Base address of the code and read-only data - defined for this loader + defined for this loader Makefile Makefile for compile the boot loader. Index: /trunk/softs/tsar_boot/conf/platform_fpga_de2-115/defs_platform.h =================================================================== --- /trunk/softs/tsar_boot/conf/platform_fpga_de2-115/defs_platform.h (revision 567) +++ /trunk/softs/tsar_boot/conf/platform_fpga_de2-115/defs_platform.h (revision 568) @@ -4,4 +4,5 @@ #define IRQ_PER_PROC 1 +#define USE_IOB 0 #define CACHE_COHERENCE 1 #define CACHE_LINE_SIZE 64//bytes @@ -13,4 +14,5 @@ #define TTY_BASE 0xFC000000 #define ICU_BASE 0xFD000000 +#define MCC_BASE 0xFFFFFFFF // not used /* Mandatory argument only for FPGA platforms */ Index: /trunk/softs/tsar_boot/conf/platform_tsarv4_mono_mmu_ioc/defs_platform.h =================================================================== --- /trunk/softs/tsar_boot/conf/platform_tsarv4_mono_mmu_ioc/defs_platform.h (revision 567) +++ /trunk/softs/tsar_boot/conf/platform_tsarv4_mono_mmu_ioc/defs_platform.h (revision 568) @@ -4,4 +4,5 @@ #define IRQ_PER_PROC 1 +#define USE_IOB 0 #define CACHE_COHERENCE 1 #define CACHE_LINE_SIZE 64 // bytes (ie 16 x 32-bit word) @@ -13,2 +14,3 @@ #define ICU_BASE 0x30000000 #define IOC_BASE 0x40000000 +#define MCC_BASE 0xFFFFFFFF // not used Index: /trunk/softs/tsar_boot/conf/platform_vgsb_xicu_mmu/defs_platform.h =================================================================== --- /trunk/softs/tsar_boot/conf/platform_vgsb_xicu_mmu/defs_platform.h (revision 567) +++ /trunk/softs/tsar_boot/conf/platform_vgsb_xicu_mmu/defs_platform.h (revision 568) @@ -4,4 +4,5 @@ #define IRQ_PER_PROC 1 +#define USE_IOB 0 #define CACHE_COHERENCE 0 #define CACHE_LINE_SIZE 16//bytes @@ -13,2 +14,3 @@ #define IOC_BASE 0x00F10000 #define TTY_BASE 0x00F20000 +#define MCC_BASE 0xFFFFFFFF //not used Index: /trunk/softs/tsar_boot/include/boot_ioc.h =================================================================== --- /trunk/softs/tsar_boot/include/boot_ioc.h (revision 567) +++ /trunk/softs/tsar_boot/include/boot_ioc.h (revision 568) @@ -7,4 +7,5 @@ #else #include +#include #endif Index: /trunk/softs/tsar_boot/include/mcc.h =================================================================== --- /trunk/softs/tsar_boot/include/mcc.h (revision 568) +++ /trunk/softs/tsar_boot/include/mcc.h (revision 568) @@ -0,0 +1,30 @@ +#ifndef MCC_H +#define MCC_H + +enum MccRegisters +{ + MCC_LOCK = 0, + MCC_ADDR_LO = 1, + MCC_ADDR_HI = 2, + MCC_LENGTH = 3, + MCC_CMD = 4 +}; + +enum MccConfigCmd +{ + MCC_CMD_NOP = 0, + MCC_CMD_INVAL = 1, + MCC_CMD_SYNC = 2 +}; + +#endif + +// Local Variables: +// tab-width: 4; +// c-basic-offset: 4; +// c-file-offsets:((innamespace . 0)(inline-open . 0)); +// indent-tabs-mode: nil; +// End: +// +// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 + Index: /trunk/softs/tsar_boot/src/boot_ioc.c =================================================================== --- /trunk/softs/tsar_boot/src/boot_ioc.c (revision 567) +++ /trunk/softs/tsar_boot/src/boot_ioc.c (revision 568) @@ -145,4 +145,13 @@ // SOCLIB version of the boot_ioc_read function +void boot_buf_invalidate ( + const void * buffer, + unsigned int line_size, + unsigned int size); + +void boot_mcc_invalidate ( + const void * buffer, + unsigned int size); + int boot_ioc_read(unsigned int lba, void* buffer, unsigned int count) { @@ -179,6 +188,10 @@ _boot_ioc_completed(); -#if (CACHE_COHERENCE == 0) - boot_dbuf_invalidate(buffer, CACHE_LINE_SIZE, count * 512); +#if (CACHE_COHERENCE == 0) || (USE_IOB == 1) + boot_buf_invalidate(buffer, CACHE_LINE_SIZE, count * 512); +#endif + +#if (USE_IOB == 1) + boot_mcc_invalidate(buffer, count * 512); #endif @@ -252,6 +265,6 @@ * buffer (identified by an address and a size). */ -#if (CACHE_COHERENCE == 0) -void boot_dbuf_invalidate ( +#if (CACHE_COHERENCE == 0) || (USE_IOB == 1) +void boot_buf_invalidate ( const void * buffer, unsigned int line_size, @@ -271,4 +284,33 @@ #endif +/** + * boot_mcc_inval() + * + * Invalidate all data cache lines corresponding to a memory + * buffer (identified by an address and a size). + */ +#if (USE_IOB == 1) +void boot_mcc_invalidate ( + const void * buffer, + unsigned int size) +{ + unsigned int * mcc_address = (unsigned int *)MCC_BASE; + + // get the hard lock assuring exclusive access to MEMC + while (ioread32(&mcc_address[MCC_LOCK])); + + // write invalidate paremeters on the memory cache + // this preloader use only the cluster 0 and then the HI bits are not used + + iowrite32(&mcc_address[MCC_ADDR_LO], (unsigned int) buffer); + iowrite32(&mcc_address[MCC_ADDR_HI], (unsigned int) 0); + iowrite32(&mcc_address[MCC_LENGTH] , (unsigned int) size); + iowrite32(&mcc_address[MCC_CMD] , (unsigned int) MCC_CMD_INVAL); + + // release the lock protecting MEMC + iowrite32(&mcc_address[MCC_LOCK], (unsigned int) 0); +} +#endif + /* * vim: tabstop=4 : shiftwidth=4 : expandtab