Changeset 57 for trunk/modules/vci_mem_cache_v4/caba/source/src
- Timestamp:
- Jun 18, 2010, 4:07:34 PM (15 years ago)
- File:
-
- 1 edited
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- Unmodified
- Added
- Removed
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trunk/modules/vci_mem_cache_v4/caba/source/src/vci_mem_cache_v4.cpp
r19 r57 32 32 //#define IDEBUG // Update tab debug 33 33 //#define DDEBUG // Directory debug 34 //#define LOCK_DEBUG // Lock debug 34 35 //#define DEBUG_VCI_MEM_CACHE 1 36 #define DEBUG_START_CYCLE 8750000 35 37 #define RANDOMIZE_SC 36 #define NCYCLES -137 38 namespace soclib { namespace caba { 38 39 … … 134 135 "XRAM_RSP_INVAL", 135 136 "XRAM_RSP_WRITE_DIRTY", 137 "XRAM_RSP_HEAP_ERASE", 138 "XRAM_RSP_HEAP_LAST", 136 139 }; 137 140 const char *ixr_cmd_fsm_str[] = { … … 581 584 582 585 #if DEBUG_VCI_MEM_CACHE 583 if(m_cpt_cycles > NCYCLES){586 if(m_cpt_cycles > DEBUG_START_CYCLE){ 584 587 std::cout << "---------------------------------------------" << std::dec << std::endl; 585 588 std::cout << "MEM_CACHE " << m_srcid_ini << " ; Time = " << m_cpt_cycles << std::endl … … 758 761 bool valid = m_update_tab.decrement(r_init_rsp_upt_index.read(), count); 759 762 #ifdef IDEBUG 763 if(m_cpt_cycles > DEBUG_START_CYCLE){ 760 764 std::cout << sc_time_stamp() << " " << name() << " INIT_RSP_UPT_LOCK update table : " << std::endl; 761 765 m_update_tab.print(); 766 } 762 767 #endif 768 while(!valid); 763 769 assert ( valid 764 770 && "VCI_MEM_CACHE Invalid UPT entry in VCI response paquet received by memory cache" ); … … 782 788 m_update_tab.clear(r_init_rsp_upt_index.read()); 783 789 #ifdef IDEBUG 790 if(m_cpt_cycles > DEBUG_START_CYCLE){ 784 791 std::cout << sc_time_stamp() << " " << name() << " INIT_RSP_UPT_CLEAR update table : " << std::endl; 785 792 m_update_tab.print(); 793 } 786 794 #endif 787 795 } … … 835 843 DirectoryEntry entry = m_cache_directory.read(m_cmd_read_addr_fifo.read(), way); 836 844 #ifdef DDEBUG 845 if(m_cpt_cycles > DEBUG_START_CYCLE){ 837 846 std::cout << "In READ_DIR_LOCK printing the entry of address is : " << std::hex << m_cmd_read_addr_fifo.read() << std::endl; 838 847 entry.print(); 839 848 std::cout << "done" << std::endl; 849 } 840 850 #endif 841 842 851 r_read_is_cnt = entry.is_cnt; 843 852 r_read_dirty = entry.dirty; … … 888 897 entry.tag = r_read_tag.read(); 889 898 entry.lock = r_read_lock.read(); 890 entry.ptr = 0;899 entry.ptr = r_read_ptr.read(); 891 900 if(cached_read){ // Cached read, we update the copy 892 901 if(!is_cnt){ // Not counter mode … … 905 914 } 906 915 #ifdef DDEBUG 916 if(m_cpt_cycles > DEBUG_START_CYCLE){ 907 917 std::cout << "In READ_DIR_HIT printing the entry of address is : " << std::endl; 908 918 entry.print(); 909 919 std::cout << "done" << std::endl; 920 } 910 921 #endif 911 922 … … 946 957 } 947 958 #ifdef DDEBUG 959 if(m_cpt_cycles > DEBUG_START_CYCLE){ 948 960 std::cout << "In READ_HEAP_LOCK printing the entry of address is : " << std::endl; 949 961 entry.print(); 950 962 std::cout << "done" << std::endl; 963 } 951 964 #endif 952 965 … … 1064 1077 if ( r_alloc_trt_fsm.read() == ALLOC_TRT_READ ) { 1065 1078 #ifdef TDEBUG 1079 if(m_cpt_cycles > DEBUG_START_CYCLE){ 1066 1080 std::cout << sc_time_stamp() << " " << name() << " READ_TRT_LOCK " << std::endl; 1081 } 1067 1082 #endif 1068 1083 size_t index = 0; … … 1095 1110 std::vector<data_t>(m_words,0)); 1096 1111 #ifdef TDEBUG 1112 if(m_cpt_cycles > DEBUG_START_CYCLE){ 1097 1113 std::cout << sc_time_stamp() << " " << name() << " READ_TRT_SET transaction table : " << std::endl; 1098 1114 for(size_t i = 0 ; i < m_transaction_tab.size() ; i++) 1099 1115 m_transaction_tab.print(i); 1116 } 1100 1117 #endif 1101 1118 … … 1336 1353 } 1337 1354 #ifdef IDEBUG 1355 if(m_cpt_cycles > DEBUG_START_CYCLE){ 1338 1356 if(wok){ 1339 1357 std::cout << sc_time_stamp() << " " << name() << " WRITE_UPT_LOCK update table : " << std::endl; 1340 1358 m_update_tab.print(); 1341 1359 } 1360 } 1342 1361 #endif 1343 1362 r_write_upt_index = index; … … 1456 1475 if ( r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE ) { 1457 1476 #ifdef TDEBUG 1477 if(m_cpt_cycles > DEBUG_START_CYCLE){ 1458 1478 std::cout << sc_time_stamp() << " " << name() << " READ_TRT_LOCK " << std::endl; 1479 } 1459 1480 #endif 1460 1481 size_t hit_index = 0; … … 1507 1528 data_vector); 1508 1529 #ifdef TDEBUG 1530 if(m_cpt_cycles > DEBUG_START_CYCLE){ 1509 1531 std::cout << sc_time_stamp() << " " << name() << " WRITE_TRT_SET transaction table : " << std::endl; 1510 1532 for(size_t i = 0 ; i < m_transaction_tab.size() ; i++) 1511 1533 m_transaction_tab.print(i); 1534 } 1512 1535 #endif 1513 1536 … … 1533 1556 r_write_fsm = WRITE_RSP; 1534 1557 #ifdef TDEBUG 1558 if(m_cpt_cycles > DEBUG_START_CYCLE){ 1535 1559 std::cout << sc_time_stamp() << " " << name() << " WRITE_TRT_DATA transaction table : " << std::endl; 1536 1560 for(size_t i = 0 ; i < m_transaction_tab.size() ; i++) 1537 1561 m_transaction_tab.print(i); 1562 } 1538 1563 #endif 1539 1564 … … 1592 1617 index); 1593 1618 #ifdef IDEBUG 1619 if(m_cpt_cycles > DEBUG_START_CYCLE){ 1594 1620 if(wok){ 1595 1621 std::cout << sc_time_stamp() << " " << name() << " WRITE_INVAL_LOCK update table : " << std::endl; 1596 1622 m_update_tab.print(); 1597 1623 } 1624 } 1598 1625 #endif 1599 1626 r_write_upt_index = index; … … 1624 1651 std::vector<data_t>(m_words,0)); 1625 1652 #ifdef TDEBUG 1653 if(m_cpt_cycles > DEBUG_START_CYCLE){ 1626 1654 std::cout << sc_time_stamp() << " " << name() << " WRITE_DIR_INVAL transaction table : " << std::endl; 1627 1655 for(size_t i = 0 ; i < m_transaction_tab.size() ; i++) 1628 1656 m_transaction_tab.print(i); 1657 } 1629 1658 #endif 1630 1659 … … 1830 1859 r_ixr_rsp_fsm = IXR_RSP_IDLE; 1831 1860 #ifdef TDEBUG 1861 if(m_cpt_cycles > DEBUG_START_CYCLE){ 1832 1862 std::cout << sc_time_stamp() << " " << name() << " IXR_RSP_TRT_ERASE transaction table : " << std::endl; 1833 1863 for(size_t i = 0 ; i < m_transaction_tab.size() ; i++) 1834 1864 m_transaction_tab.print(i); 1865 } 1835 1866 #endif 1836 1867 … … 1851 1882 if ( eop ) { 1852 1883 #ifdef TDEBUG 1884 if(m_cpt_cycles > DEBUG_START_CYCLE){ 1853 1885 std::cout << sc_time_stamp() << " " << name() << " IXR_RSP_TRT_READ transaction table : " << std::endl; 1854 1886 for(size_t i = 0 ; i < m_transaction_tab.size() ; i++) 1855 1887 m_transaction_tab.print(i); 1888 } 1856 1889 #endif 1857 1890 … … 1900 1933 break; 1901 1934 #ifdef TDEBUG 1935 if(m_cpt_cycles > DEBUG_START_CYCLE){ 1902 1936 std::cout << "XRAM_RSP FSM in XRAM_RSP_IDLE state" << std::endl; 1937 } 1903 1938 #endif 1904 1939 } … … 1912 1947 r_xram_rsp_fsm = XRAM_RSP_TRT_COPY; 1913 1948 #ifdef TDEBUG 1949 if(m_cpt_cycles > DEBUG_START_CYCLE){ 1914 1950 std::cout << "XRAM_RSP FSM in XRAM_RSP_DIR_LOCK state" << std::endl; 1951 } 1915 1952 #endif 1916 1953 } … … 1948 1985 r_xram_rsp_fsm = XRAM_RSP_INVAL_LOCK; 1949 1986 #ifdef TDEBUG 1987 if(m_cpt_cycles > DEBUG_START_CYCLE){ 1950 1988 std::cout << "XRAM_RSP FSM in XRAM_RSP_TRT_COPY state" << std::endl; 1951 1989 std::cout << "Victim way : " << std::hex << way << " set " << std::hex << set << std::endl; 1952 1990 victim.print(); 1991 } 1953 1992 #endif 1954 1993 } … … 1960 1999 if ( r_alloc_upt_fsm == ALLOC_UPT_XRAM_RSP ) { 1961 2000 #ifdef IDEBUG 2001 if(m_cpt_cycles > DEBUG_START_CYCLE){ 1962 2002 std::cout << "XRAM_RSP FSM in XRAM_RSP_INVAL_LOCK state" << std::endl; 2003 } 1963 2004 #endif 1964 2005 size_t index; … … 1966 2007 r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT; 1967 2008 #ifdef IDEBUG 2009 if(m_cpt_cycles > DEBUG_START_CYCLE){ 1968 2010 std::cout << "XRAM_RSP FSM in XRAM_RSP_INVAL_LOCK state to XRAM_RSP_INVAL_WAIT state" << std::endl; 1969 2011 std::cout << "A invalidation is already registered at this address" << std::endl; 1970 2012 m_update_tab.print(); 2013 } 1971 2014 #endif 1972 2015 … … 1975 2018 r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT; 1976 2019 #ifdef IDEBUG 2020 if(m_cpt_cycles > DEBUG_START_CYCLE){ 1977 2021 std::cout << "XRAM_RSP FSM in XRAM_RSP_INVAL_LOCK state to XRAM_RSP_INVAL_WAIT state" << std::endl; 1978 2022 std::cout << "The inval tab is full" << std::endl; 1979 2023 m_update_tab.print(); 2024 } 1980 2025 #endif 1981 2026 } … … 1983 2028 r_xram_rsp_fsm = XRAM_RSP_DIR_UPDT; 1984 2029 #ifdef IDEBUG 2030 if(m_cpt_cycles > DEBUG_START_CYCLE){ 1985 2031 std::cout << "XRAM_RSP FSM in XRAM_RSP_INVAL_LOCK state to XRAM_RSP_DIR_UPDT state" << std::endl; 1986 2032 m_update_tab.print(); 2033 } 1987 2034 #endif 1988 2035 } … … 1996 2043 break; 1997 2044 #ifdef IDEBUG 2045 if(m_cpt_cycles > DEBUG_START_CYCLE){ 1998 2046 std::cout << "XRAM_RSP FSM in XRAM_RSP_INVAL_WAIT state" << std::endl; 2047 } 1999 2048 #endif 2000 2049 } … … 2042 2091 m_cache_directory.write(set, way, entry); 2043 2092 #ifdef DDEBUG 2093 if(m_cpt_cycles > DEBUG_START_CYCLE){ 2044 2094 std::cout << "printing the entry : " << std::endl; 2045 2095 entry.print(); 2046 2096 std::cout << "done" << std::endl; 2097 } 2047 2098 #endif 2048 2099 2049 2100 #ifdef TDEBUG 2101 if(m_cpt_cycles > DEBUG_START_CYCLE){ 2050 2102 std::cout << sc_time_stamp() << " " << name() << " XRAM_RSP_DIR_UPDT transaction table : " << std::endl; 2051 2103 for(size_t i = 0 ; i < m_transaction_tab.size() ; i++) 2052 2104 m_transaction_tab.print(i); 2105 } 2053 2106 #endif 2054 2107 … … 2069 2122 2070 2123 #ifdef IDEBUG 2124 if(m_cpt_cycles > DEBUG_START_CYCLE){ 2071 2125 std::cout << "xram_rsp : record invalidation, time = " << std::dec << m_cpt_cycles << std::endl; 2072 2126 m_update_tab.print(); 2127 } 2073 2128 #endif 2074 2129 r_xram_rsp_upt_index = index; … … 2105 2160 std::vector<data_t>(m_words,0) ); 2106 2161 #ifdef TDEBUG 2162 if(m_cpt_cycles > DEBUG_START_CYCLE){ 2107 2163 std::cout << sc_time_stamp() << " " << name() << " XRAM_RSP_TRT_DIRTY transaction table : " << std::endl; 2108 2164 for(size_t i = 0 ; i < m_transaction_tab.size() ; i++) 2109 2165 m_transaction_tab.print(i); 2166 } 2110 2167 #endif 2111 2168 … … 2135 2192 2136 2193 #ifdef DDEBUG 2194 if(m_cpt_cycles > DEBUG_START_CYCLE){ 2137 2195 std::cout << "XRAM_RSP FSM in XRAM_RSP_DIR_RSP state" << std::endl; 2196 } 2138 2197 #endif 2139 2198 } … … 2164 2223 else r_xram_rsp_fsm = XRAM_RSP_IDLE; 2165 2224 #ifdef IDEBUG 2225 if(m_cpt_cycles > DEBUG_START_CYCLE){ 2166 2226 std::cout << "XRAM_RSP FSM in XRAM_RSP_INVAL state" << std::endl; 2227 } 2167 2228 #endif 2168 2229 } … … 2185 2246 else r_xram_rsp_fsm = XRAM_RSP_IDLE; 2186 2247 #ifdef TDEBUG 2248 if(m_cpt_cycles > DEBUG_START_CYCLE){ 2187 2249 std::cout << "XRAM_RSP FSM in XRAM_RSP_WRITE_DIRTY state" << std::endl; 2250 } 2188 2251 #endif 2189 2252 } … … 2286 2349 DirectoryEntry entry = m_cache_directory.read(cleanup_address , way); 2287 2350 #ifdef DDEBUG 2351 if(m_cpt_cycles > DEBUG_START_CYCLE){ 2288 2352 std::cout << "In CLEANUP_DIR_LOCK printing the entry of address is : " << std::hex << cleanup_address << std::endl; 2289 2353 entry.print(); 2290 2354 std::cout << "done" << std::endl; 2355 } 2291 2356 #endif 2292 2357 r_cleanup_is_cnt = entry.is_cnt; … … 2513 2578 if(!hit_inval) { 2514 2579 #ifdef DEBUG_VCI_MEM_CACHE 2515 if(m_cpt_ total_cycles > NCYCLES)2580 if(m_cpt_cycles > DEBUG_START_CYCLE) 2516 2581 std::cout << "MEM_CACHE WARNING: cleanup with no corresponding entry at address : " << std::hex << (r_cleanup_nline.read()*4*m_words) << std::dec << std::endl; 2517 2582 #endif … … 2536 2601 m_update_tab.clear(r_cleanup_index.read()); 2537 2602 #ifdef IDEBUG 2603 if(m_cpt_cycles > DEBUG_START_CYCLE){ 2538 2604 std::cout << sc_time_stamp() << " " << name() << " CLEANUP_UPT_WRITE update table : " << std::endl; 2539 2605 m_update_tab.print(); 2606 } 2540 2607 #endif 2541 2608 … … 2605 2672 if( m_cmd_llsc_addr_fifo.rok() ) { 2606 2673 #ifdef LOCK_DEBUG 2674 if(m_cpt_cycles > DEBUG_START_CYCLE){ 2607 2675 std::cout << "SC data : " << m_cmd_llsc_wdata_fifo.read() << std::endl; 2608 2676 std::cout << "SC addr : " << std::hex << m_cmd_llsc_addr_fifo.read() << std::dec << std::endl; 2609 2677 std::cout << "SC cpt : " << r_llsc_cpt.read() << std::endl; 2678 } 2610 2679 #endif 2611 2680 if(m_cmd_llsc_eop_fifo.read()){ … … 2613 2682 r_llsc_fsm = SC_DIR_LOCK; 2614 2683 #ifdef LOCK_DEBUG 2684 if(m_cpt_cycles > DEBUG_START_CYCLE){ 2615 2685 std::cout << "SC eop" << std::endl; 2686 } 2616 2687 #endif 2617 2688 } else { // we keep the last word … … 2681 2752 2682 2753 #ifdef LOCK_DEBUG 2754 if(m_cpt_cycles > DEBUG_START_CYCLE){ 2683 2755 std::cout << "SC_DIR_HIT_READ ok ? " << ok << std::endl; 2684 2756 if(!ok){ … … 2693 2765 std::cout << "SC_DIR_HIT_READ wdata 1 : " << m_cmd_llsc_wdata_fifo.read() << std::endl; 2694 2766 } 2767 } 2695 2768 #endif 2696 2769 if(ok){ … … 2770 2843 } 2771 2844 #ifdef IDEBUG 2845 if(m_cpt_cycles > DEBUG_START_CYCLE){ 2772 2846 if(wok){ 2773 2847 std::cout << sc_time_stamp() << " " << name() << " SC_UPT_LOCK update table : " << std::endl; 2774 2848 m_update_tab.print(); 2775 2849 } 2850 } 2776 2851 #endif 2777 2852 r_llsc_upt_index = index; … … 2822 2897 if(r_llsc_count.read() == 1){ 2823 2898 #ifdef LOCK_DEBUG 2899 if(m_cpt_cycles > DEBUG_START_CYCLE){ 2824 2900 std::cout << "SC_UPT_REQ, only one owner : " << r_llsc_copy.read() << std::endl; 2901 } 2825 2902 #endif 2826 2903 r_llsc_fsm = LLSC_IDLE; … … 2916 2993 index); 2917 2994 #ifdef IDEBUG 2995 if(m_cpt_cycles > DEBUG_START_CYCLE){ 2918 2996 if(wok){ 2919 2997 std::cout << sc_time_stamp() << " " << name() << " LLSC_INVAL_LOCK update table : " << std::endl; 2920 2998 m_update_tab.print(); 2921 2999 } 3000 } 2922 3001 #endif 2923 3002 r_llsc_upt_index = index; … … 2947 3026 std::vector<data_t>(m_words,0)); 2948 3027 #ifdef TDEBUG 3028 if(m_cpt_cycles > DEBUG_START_CYCLE){ 2949 3029 std::cout << sc_time_stamp() << " " << name() << " SC_DIR_INVAL transaction table : " << std::endl; 2950 3030 for(size_t i = 0 ; i < m_transaction_tab.size() ; i++) 2951 3031 m_transaction_tab.print(i); 3032 } 2952 3033 #endif 2953 3034 … … 3083 3164 data_vector); 3084 3165 #ifdef TDEBUG 3166 if(m_cpt_cycles > DEBUG_START_CYCLE){ 3085 3167 std::cout << sc_time_stamp() << " " << name() << " LLSC_TRT_SET transaction table : " << std::endl; 3086 3168 for(size_t i = 0 ; i < m_transaction_tab.size() ; i++) 3087 3169 m_transaction_tab.print(i); 3170 } 3088 3171 #endif 3089 3172
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